Pixel driving circuit and display substrate

Abstract

This disclosure provides a pixel driving circuit, including a driving sub-circuit, a data writing sub-circuit, and a threshold compensation sub-circuit. The data writing sub-circuit is configured to transmit a data voltage signal to a first terminal of the driving sub-circuit under the control of a first control signal. The threshold compensation sub-circuit is configured to compensate the threshold voltage of the driving sub-circuit under the control of a second control signal. The driving sub-circuit is configured to provide a driving current to a light-emitting device to be driven based on the voltage at its first terminal and the control terminal. The circuit also includes an auxiliary compensation sub-circuit electrically connected to the driving sub-circuit. The auxiliary compensation sub-circuit is configured to transmit an auxiliary compensation signal to either the first or second terminal of the driving sub-circuit under the control of a third control signal when the threshold compensation sub-circuit compensates the driving sub-circuit. The auxiliary compensation signal has the same polarity as the data voltage signal, and the absolute value of the auxiliary compensation signal is less than the absolute value of the data voltage signal.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a pixel driving circuit and a display substrate. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are a new type of current-driven semiconductor light-emitting device. They emit light by controlling the injection and recombination of charge carriers to excite organic materials, representing a self-emissive technology. Compared to passively emitting liquid crystal displays (LCDs), self-emissive OLEDs offer advantages such as faster response times, higher contrast ratios, and wider viewing angles. They are also easier to implement in flexible displays, making them widely favored in the industry. There is a consensus that OLED displays are highly likely to become the mainstream product of the next generation of display technology. However, traditional OLED circuits and driving architectures always have some unresolved problems, such as low brightness uniformity, image retention, flicker, and low-brightness color shift, especially with the application of LTPO technology at high refresh rates, these problems have become even more pronounced. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art, and provides a pixel driving circuit, including a driving sub-circuit, a data writing sub-circuit, and a threshold compensation sub-circuit; wherein,

[0004] The data writing sub-circuit is configured to transmit the data voltage signal to the first terminal of the driving sub-circuit under the control of the first control signal;

[0005] The threshold compensation sub-circuit is configured to compensate the threshold voltage of the driving sub-circuit under the control of the second control signal.

[0006] The driving sub-circuit is configured to provide a driving current to the light-emitting device to be driven based on the voltage of its first terminal and control terminal;

[0007] The pixel driving circuit further includes an auxiliary compensation sub-circuit electrically connected to the driving sub-circuit; the auxiliary compensation sub-circuit is configured to transmit an auxiliary compensation signal to a first or second terminal of the driving sub-circuit under the control of a third control signal when the threshold compensation sub-circuit compensates the driving sub-circuit; the polarity of the auxiliary compensation signal is the same as the polarity of the data voltage signal, and the absolute value of the auxiliary compensation signal is less than the absolute value of the data voltage signal.

[0008] In some embodiments, the auxiliary compensation sub-circuit includes a ninth transistor; the control electrode of the ninth transistor is connected to a third control signal terminal, the first electrode is connected to a first or second terminal of the driving sub-circuit, and the second electrode is connected to an auxiliary compensation signal terminal.

[0009] In some embodiments, the pixel driving circuit further includes a first reset circuit and a second reset circuit;

[0010] The first reset sub-circuit is configured to reset the control terminal of the drive sub-circuit via a first initialization signal under the control of a fourth control signal.

[0011] The second reset sub-circuit is configured to reset the first terminal of the drive sub-circuit via a second initialization signal under the control of a fifth control signal.

[0012] In some embodiments, the first reset sub-circuit includes a fourth transistor; the control terminal of the fourth transistor is connected to a fourth control signal terminal, the first terminal is connected to the control terminal of the drive sub-circuit, and the second terminal is connected to a first initialization signal terminal.

[0013] The second reset sub-circuit includes an eighth transistor; the control electrode of the eighth transistor is connected to the fifth control signal terminal, the first electrode is connected to the first terminal of the drive sub-circuit, and the second electrode is connected to the second initialization signal terminal.

[0014] In some embodiments, the pixel driving circuit further includes a first light emission control sub-circuit and a second light emission control sub-circuit;

[0015] The first light-emitting control sub-circuit is configured to transmit a first level signal to the first terminal of the driving sub-circuit under the control of a first light-emitting control signal; the second light-emitting control sub-circuit is configured to transmit the driving current to the light-emitting device to be driven under the control of a second light-emitting control signal.

[0016] In some embodiments, the first light-emitting control sub-circuit includes a fifth transistor; the control electrode of the fifth transistor is connected to a first light-emitting control signal terminal, the first electrode is connected to a first level signal terminal, and the second electrode is connected to a first terminal of the driving sub-circuit.

[0017] The second light-emitting control sub-circuit includes a sixth transistor; the control electrode of the sixth transistor is connected to the second light-emitting control signal terminal, the first electrode is connected to the second terminal of the driving sub-circuit, and the second electrode is connected to the first electrode of the light-emitting device.

[0018] In some embodiments, the pixel driving circuit further includes a third reset sub-circuit; the third reset sub-circuit is configured to reset the first electrode of the light-emitting device by a third initialization signal under the control of a sixth control signal.

[0019] In some embodiments, the third reset circuit includes a seventh transistor; the control electrode of the seventh transistor is connected to a sixth control signal terminal, the first electrode is connected to the first electrode of the light-emitting device, and the second electrode is connected to a third initialization signal terminal.

[0020] In some embodiments, the data writing sub-circuit includes a first transistor; the control electrode of the first transistor is connected to a first control signal terminal, the first electrode is connected to a first terminal of the driving sub-circuit, and the second electrode is connected to a data voltage signal line.

[0021] In some embodiments, the threshold compensation sub-circuit includes a third transistor; the control electrode of the third transistor is connected to a second control signal terminal, the first electrode is connected to the control terminal of the driving sub-circuit, and the second electrode is connected to the second terminal of the driving sub-circuit.

[0022] In some embodiments, the driving sub-circuit includes a second transistor; the control electrode of the second transistor is multiplexed as the control terminal of the driving sub-circuit; the first electrode of the second transistor is multiplexed as the first terminal of the driving sub-circuit; and the second electrode of the second transistor is multiplexed as the second terminal of the driving sub-circuit.

[0023] This disclosure also provides a display substrate including the pixel driving circuit described above.

[0024] In some embodiments, the display substrate includes a substrate and a plurality of pixel units arranged in an array on the substrate; the pixel unit includes the pixel driving circuit and a light-emitting device disposed on the side of the pixel driving circuit facing away from the substrate. Attached Figure Description

[0025] Figure 1a This is a structural block diagram of a pixel driving circuit provided in an embodiment of the present disclosure.

[0026] Figure 1b This is a structural block diagram of another pixel driving circuit provided in an embodiment of the present disclosure.

[0027] Figure 2a To and Figure 1a A schematic diagram of the corresponding pixel driving circuit.

[0028] Figure 2b To and Figure 1b A schematic diagram of the corresponding pixel driving circuit.

[0029] Figure 3a This is a structural block diagram of another pixel driving circuit provided in an embodiment of the present disclosure.

[0030] Figure 3bThis is a structural block diagram of another pixel driving circuit provided in an embodiment of the present disclosure.

[0031] Figure 4a To and Figure 3a A schematic diagram of the corresponding pixel driving circuit.

[0032] Figure 4b To and Figure 3b A schematic diagram of the corresponding pixel driving circuit.

[0033] Figure 5 for Figure 4a Timing diagram of the mid-pixel driving circuit.

[0034] Figure 6 The image shows the simulated image retention test results of the pixel driving circuit provided in the embodiments of this disclosure.

[0035] Figure 7 The diagram shows the uniformity test results of the pixel driving circuit provided in the embodiments of this disclosure. Detailed Implementation

[0036] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of objects. "Above," "below," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0039] The transistors used in these embodiments can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Since the source and drain of the transistors are symmetrical, there is no distinction between them. In these embodiments, to distinguish the source and drain of the transistor, one is called the first electrode, the other the second electrode, and the gate is called the control electrode. Furthermore, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When using a P-type transistor, the control electrode is the gate, the first electrode is the source, and the second electrode is the drain. The transistor turns on when a low-level signal is input to the gate; therefore, for a P-type transistor, the operating level signal is a low-level signal, and the non-operating level signal is a high-level signal. When using an N-type transistor, the control electrode is the gate, the first electrode is the source, and the second electrode is the drain. The transistor turns on when a high-level signal is input to the gate; therefore, for an N-type transistor, the operating level signal is a high-level signal, and the non-operating level signal is a low-level signal.

[0040] Meanwhile, in some embodiments, the light-emitting device to be driven can be a micro inorganic light-emitting diode, or more specifically, a current-driven light-emitting diode, such as a micro LED or a mini LED. Of course, in the embodiments of this disclosure, the light-emitting device can also be an organic light-emitting diode (OLED). One of the first and second electrodes of the light-emitting device is the anode, and the other is the cathode. In the embodiments of this disclosure, only an OLED is used as an example, with the first electrode being the anode and the second electrode being the cathode.

[0041] Firstly, such as Figures 1a-1bAs shown, this disclosure provides a pixel driving circuit, comprising: a driving sub-circuit 2, a data writing sub-circuit 1, a threshold compensation sub-circuit 3, and an auxiliary compensation sub-circuit 5. The data writing sub-circuit 1 is configured to transmit a data voltage signal Vdata to the first terminal of the driving sub-circuit 2 under the control of a first control signal S1. Here, the first control signal S1 can be a gate driving signal. The threshold compensation sub-circuit 3 is configured to compensate the threshold voltage of the driving sub-circuit 2 under the control of a second control signal S2. The driving sub-circuit 2 is configured to provide a driving current to the light-emitting device D to be driven based on the voltages at its first terminal and control terminal. The auxiliary compensation sub-circuit 5 is configured to, when the threshold compensation sub-circuit 3 performs threshold compensation on the driving sub-circuit 2, transmit an auxiliary compensation signal Vcomp to the first or second terminal of the driving sub-circuit 2 under the control of a third control signal S3. This auxiliary compensation signal Vcomp is used to pre-write data to the pixel driving circuit, thereby increasing the data writing time and ensuring that the driving sub-circuit 2 achieves the expected performance under various conditions, extending the lifespan of the device. It should be noted that the auxiliary compensation signal Vcomp and the data voltage signal Vdata have the same polarity, and the absolute value of the auxiliary compensation signal Vcomp is less than the absolute value of the data voltage signal Vdata. This setting ensures the normal turn-on of the driving transistor. For example, the auxiliary compensation signal Vcomp can be half of the data voltage signal Vdata.

[0042] In the embodiments disclosed herein, such as Figure 1a As shown, the control terminal of the data writing sub-circuit 1 is connected to the first control signal terminal, the first terminal of the data writing sub-circuit 1 is connected to the first terminal of the driving sub-circuit 2, and the second terminal of the data writing sub-circuit 1 is connected to the data voltage signal terminal. During the data writing stage of the pixel driving circuit, the first control signal S1 provided by the first control signal terminal is a working level signal, the data writing sub-circuit 1 is turned on, and the data voltage signal Vdata provided by the data voltage signal line is written to the first terminal of the driving sub-circuit 2 to realize the writing of the data voltage signal Vdata into the pixel driving circuit. The control terminal of the driving sub-circuit 2 is connected to the first terminal of the threshold compensation sub-circuit 3, the first terminal of the driving sub-circuit 2 is connected to the first terminal of the data writing sub-circuit 1, and the second terminal of the driving sub-circuit 2 is connected to the second terminal of the threshold compensation sub-circuit 3. Simultaneously, as shown... Figure 1a As shown, the control terminal of the threshold compensation sub-circuit 3 is connected to the second control signal terminal. (Continue referring to...) Figure 1aThe pixel driving circuit also includes a storage sub-circuit 4. The first terminal of the storage sub-circuit 4 is connected to a first-level signal terminal, and the second terminal is connected to the control terminal of the driving sub-circuit 2. During the data writing phase of the pixel driving circuit, the second control signal S2 provided on the second control signal terminal is a working-level signal. The threshold compensation sub-circuit 3 is turned on and connects the second terminal of the driving sub-circuit 2 to the control terminal to compensate for the threshold voltage of the driving sub-circuit 2. Furthermore, during the data writing phase, both the data writing sub-circuit 1 and the threshold compensation sub-circuit 3 are turned on. The data voltage signal Vdata is written to the control terminal of the driving sub-circuit 2 via the data writing sub-circuit 1, the first terminal of the driving sub-circuit 2, and the second terminal of the driving sub-circuit 2. Simultaneously, the storage sub-circuit 4 stores the data voltage signal Vdata. In this way, the threshold voltage of the driving sub-circuit 2 is compensated simultaneously with data writing.

[0043] Continue to refer to Figure 1a The control terminal of the auxiliary compensation sub-circuit 5 is connected to the third control signal terminal, the first terminal of the auxiliary compensation sub-circuit 5 is connected to the first terminal of the driving sub-circuit 2, and the second terminal of the auxiliary compensation sub-circuit 5 is connected to the auxiliary compensation signal terminal. Before the data writing stage of the pixel driving circuit, the pixel driving circuit also includes a pre-writing stage. In the pre-writing stage of the pixel driving circuit, the third control signal S3 provided by the third control signal terminal is a working level signal, the auxiliary compensation sub-circuit 5 is turned on, and the auxiliary compensation signal Vcomp provided by the auxiliary compensation signal terminal is written to the first terminal of the driving sub-circuit 2 to realize the writing of the auxiliary compensation signal Vcomp into the pixel driving circuit. At the same time, in the pre-writing stage, the first control signal S1 provided by the first control signal terminal is a working level signal, so the threshold compensation sub-circuit 3 is also in the turned-on state, and the threshold compensation sub-circuit 3 connects the second terminal of the driving sub-circuit 2 and the control terminal to realize the compensation of the threshold voltage of the driving sub-circuit 2. Therefore, in the pre-writing stage, the auxiliary compensation signal Vcomp is written to the control terminal of the driving sub-circuit 2 via the auxiliary compensation sub-circuit 5, the first terminal of the driving sub-circuit 2, the second terminal of the driving sub-circuit 2, and the threshold compensation sub-circuit 3, while the storage sub-circuit 4 stores the auxiliary compensation signal Vcomp. This method allows for simultaneous compensation of the threshold voltage of the driver sub-circuit 2 while the auxiliary compensation signal is being written. Since the auxiliary compensation signal Vcomp is less than the data voltage signal Vdata, the driver transistor can remain on from the pre-write stage to the data write stage, facilitating the writing of the data voltage signal Vdata. Furthermore, the added pre-write stage increases the data write time of the pixel driver circuit, thus improving its reliability.

[0044] Figure 1b This is a structural block diagram of another pixel driving circuit provided in an embodiment of the present disclosure, which is related to... Figure 1aThe only difference in the pixel driving circuit is that the first terminal of the auxiliary compensation sub-circuit 5 is connected to the second terminal of the driving sub-circuit 2. Therefore, during the pre-writing stage, the auxiliary compensation signal is written to the control terminal of the driving sub-circuit 2 via the auxiliary compensation sub-circuit 5, the second terminal of the driving sub-circuit 2, and the threshold compensation sub-circuit 3. The specific driving process is the same as... Figure 1a The driving process of the pixel driving circuit is similar and will not be described in detail here.

[0045] In this embodiment, during actual operation, the data voltage signal Vdata written to the pixel driving circuit changes according to the grayscale variation of the light-emitting device D during imaging. At this stage, the threshold compensation sub-circuit 3 is in the ON state. The data voltage signal Vdata is written to the control terminal of the driving sub-circuit 2 via the first and second terminals. Therefore, the potential of the control terminal of the driving sub-circuit 2 changes with the data voltage signal Vdata written to the pixel driving circuit. Correspondingly, the auxiliary compensation signal Vcomp is also a dynamically changing voltage, changing with the data voltage Vdata signal. This avoids affecting the ON of the driving sub-circuit 2 and the operation of the light-emitting device D.

[0046] Specifically, refer to Figures 2a-2b , Figure 2a To and Figure 1a A schematic diagram of the corresponding pixel driving circuit. Figure 2b To and Figure 1b A schematic diagram of the corresponding pixel driving circuit. (Refer to...) Figure 2a The data writing sub-circuit 1 includes a first transistor T1, wherein the gate of the first transistor T1 is multiplexed as the control terminal of the data writing sub-circuit 1, the source is multiplexed as the first terminal of the data writing sub-circuit 1, and the drain is multiplexed as the second terminal of the data writing sub-circuit 1. The driving sub-circuit 2 includes a second transistor T2, wherein the gate of the second transistor T2 is multiplexed as the control terminal of the driving sub-circuit 2, the source is multiplexed as the first terminal of the driving sub-circuit 2, and the drain is multiplexed as the second terminal of the driving sub-circuit 2. The threshold compensation sub-circuit 3 includes a third transistor T3, wherein the gate of the third transistor T3 is multiplexed as the control terminal of the threshold compensation sub-circuit 3, the source is multiplexed as the first terminal of the threshold compensation sub-circuit 3, and the drain is multiplexed as the second terminal of the threshold compensation sub-circuit 3. The storage sub-circuit 4 includes a first capacitor C1, wherein the first terminal of the first capacitor C1 is multiplexed as the first terminal of the storage sub-circuit 4, and the second terminal is multiplexed as the second terminal of the storage sub-circuit 4. The auxiliary compensator circuit 5 includes a ninth transistor T9, wherein the gate of the ninth transistor T9 is multiplexed as the control terminal of the auxiliary compensator circuit 5, the source is multiplexed as the first terminal of the auxiliary compensator circuit 5, and the drain is multiplexed as the second terminal of the auxiliary compensator circuit 5.

[0047] exist Figure 2a In the pixel driving circuit shown, the drain of the first transistor T1 is connected to the first control signal terminal, its source is connected to the source of the second transistor T2, and its drain is connected to the data voltage signal line. The gate of the second transistor T2 is connected to the second terminal of the first capacitor C1 and the source of the third transistor T3, its source is connected to the source of the first transistor T1, and its drain is connected to the drain of the third transistor T3. The gate of the third transistor T3 is connected to the second control signal terminal, its source is connected to the gate of the second transistor T2, and its drain is connected to the drain of the second transistor T2. The first terminal of the first capacitor C1 is connected to the first level signal terminal, and its second terminal is connected to the gate of the second transistor T2. The gate of the ninth transistor T9 is connected to the third control signal terminal, its source is connected to the source of the second transistor T2, and its drain is connected to the auxiliary compensation signal terminal. During the pre-write phase of the pixel driving circuit, the second transistor T2, the third transistor T3, and the ninth transistor T9 are turned on. The auxiliary compensation signal is sequentially written to the gate of the second transistor T2 and the first capacitor C1 through the drain and source of the ninth transistor T9, the source and drain of the second transistor T2, and the drain and source of the third transistor T3, and is stored by the first capacitor C1. During the data writing phase of the pixel driving circuit, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on. The data voltage signal is sequentially written to the gate of the second transistor T2 and the first capacitor C1 through the drain and source of the first transistor T1, the source and drain of the second transistor T2, and the drain and source of the third transistor T3, and is stored by the first capacitor C1.

[0048] exist Figure 2bIn the pixel driving circuit shown, the drain of the first transistor T1 is connected to the first control signal terminal, its source is connected to the source of the second transistor T2, and its drain is connected to the data voltage signal line. The gate of the second transistor T2 is connected to the second terminal of the first capacitor C1 and the source of the third transistor T3, its source is connected to the source of the first transistor T1, and its drain is connected to the drain of the third transistor T3. The gate of the third transistor T3 is connected to the second control signal terminal, its source is connected to the gate of the second transistor T2, and its drain is connected to the drain of the second transistor T2. The first terminal of the first capacitor C1 is connected to the first level signal terminal, and its second terminal is connected to the gate of the second transistor T2. The gate of the ninth transistor T9 is connected to the third control signal terminal, its source is connected to the drain of the second transistor T2, and its drain is connected to the auxiliary compensation signal terminal. During the pre-write phase of the pixel driving circuit, the second transistor T2, the third transistor T3, and the ninth transistor T9 are turned on. The auxiliary compensation signal is sequentially written to the gate of the second transistor T2 and the first capacitor C1 through the drain and source of the ninth transistor T9, the drain of the second transistor T2, and the drain and source of the third transistor T3, and is stored by the first capacitor C1. During the data writing phase of the pixel driving circuit, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on. The data voltage signal is sequentially written to the gate of the second transistor T2 and the first capacitor C1 through the drain and source of the first transistor T1, the source and drain of the second transistor T2, and the drain and source of the third transistor T3, and is stored by the first capacitor C1.

[0049] In some embodiments, such as Figures 3a-3b As shown, the pixel driving circuit further includes a first reset sub-circuit 6 and a second reset sub-circuit 7. The first reset sub-circuit 6 is configured to reset the control terminal of the driving sub-circuit 2 via a first initialization signal Vinit1 under the control of a fourth control signal S4. The second reset sub-circuit 7 is configured to reset the first terminal of the driving sub-circuit 2 via a second initialization signal Vinit2 under the control of a fifth control signal S5. In this embodiment, since the data voltage signal Vdata changes, the control terminal and the first terminal of the driving sub-circuit 2 need to be reset via the first reset sub-circuit 6 and the second reset circuit 7 before each data writing stage of the pixel driving circuit to avoid affecting the operation of the light-emitting device D to be driven. It should be noted that the first initialization signal Vinit1 and the second initialization signal Vinit2 also change dynamically with the data voltage signal Vdata to ensure the normal operation of the pixel driving circuit.

[0050] Reference Figures 4a-4bThe first reset circuit 6 includes a fourth transistor T4, wherein the gate of the fourth transistor T4 is multiplexed as the control terminal of the first reset circuit 6, the source is multiplexed as the first terminal of the first reset circuit 6, and the drain is multiplexed as the second terminal of the first reset circuit 6. The second reset circuit 7 includes an eighth transistor T8, wherein the gate of the eighth transistor T8 is multiplexed as the control terminal of the second reset circuit 7, the source is multiplexed as the first terminal of the second reset circuit 7, and the drain is multiplexed as the second terminal of the second reset circuit 7. Specifically, the gate of the fourth transistor T4 is connected to the fourth control signal terminal, the source is connected to the gate of the second transistor T2, and the drain is connected to the first initialization signal terminal. The gate of the eighth transistor T8 is connected to the fifth control signal terminal, the source is connected to the source of the second transistor T2, and the drain is connected to the second initialization signal terminal. During the reset phase of the pixel driving circuit, the first initialization signal resets the gate of the second transistor T2 through the fourth transistor T4, and the second initialization signal resets the source of the second transistor T2 through the eighth transistor T8.

[0051] In some embodiments, continue to refer to Figures 3a-3b The pixel driving circuit further includes a first light-emitting control sub-circuit 8 and a second light-emitting control sub-circuit 9. The first light-emitting control sub-circuit 8 is configured to transmit a first level signal Vdd to the first terminal of the driving sub-circuit 2 under the control of a first light-emitting control signal EM1. The second light-emitting control sub-circuit 9 is configured to transmit the driving current output by the driving sub-circuit 2 to the light-emitting device D to be driven under the control of a second light-emitting control signal EM2. In this embodiment, by setting the first light-emitting control sub-circuit 8 and the second light-emitting control sub-circuit 9, the driving current output by the driving sub-circuit 2 is controlled to be output to the light-emitting device D to be driven during the light-emitting driving stage of the pixel driving circuit, thereby driving the light-emitting device D to emit light.

[0052] Continue to refer to Figures 4a-4bThe first light-emitting control sub-circuit 8 includes a fifth transistor T5, wherein the gate of the fifth transistor T5 is multiplexed as the control terminal of the first light-emitting control sub-circuit 8, the source is multiplexed as the first terminal of the first light-emitting control sub-circuit 8, and the drain is multiplexed as the second terminal of the first light-emitting control sub-circuit 8. The second light-emitting control sub-circuit 9 includes a sixth transistor T6, wherein the gate of the sixth transistor T6 is multiplexed as the control terminal of the second light-emitting control sub-circuit 9, the source is multiplexed as the first terminal of the second light-emitting control sub-circuit 9, and the drain is multiplexed as the second terminal of the second light-emitting control sub-circuit 9. Specifically, the gate of the fifth transistor T5 is connected to the first light-emitting control signal terminal, the source is connected to the first level signal terminal, and the drain is connected to the source of the second transistor T2. The gate of the sixth transistor T6 is connected to the second light-emitting control signal terminal, the source is connected to the drain of the second transistor T2, and the drain is connected to the anode of the light-emitting device. Here, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 can be two signals with completely identical timing. During the light-emitting stage of the pixel driving circuit, both the fifth transistor T5 and the sixth transistor T6 are turned on. The first level signal Vdd is written into the anode of the light-emitting device D through the fifth transistor T5, the second transistor T2 and the sixth transistor T6 in sequence, driving the light-emitting device D to emit light.

[0053] In some embodiments, continue to refer to Figures 3a-3b The pixel driving circuit also includes a third reset sub-circuit 10. The third reset sub-circuit 10 is configured to reset the anode of the light-emitting device via a third initialization signal Vinit3 under the control of a sixth control signal S6. Here, the sixth control signal S6 can be a signal with the same timing as the first light-emitting control signal EM1 and the second light-emitting control signal EM2. Alternatively, the sixth control signal S6 can have a different duty cycle than the first and second light-emitting control signals EM1 and EM2, facilitating control of different loads and different operations. It should also be noted that the third initialization signal Vinit3 changes with the data voltage signal Vdata to ensure that the light-emitting device D is not accidentally turned on, thus avoiding affecting the display effect.

[0054] Specifically, the third reset sub-circuit 10 includes a seventh transistor T7, wherein the gate of the seventh transistor T7 is connected to the sixth control signal terminal, the source is connected to the drain of the sixth transistor T6 and the anode of the light-emitting device D, and the drain is connected to the third initialization signal terminal. During the reset phase, pre-write phase, and data write phase of the pixel driving circuit, the sixth control signal S6 written to the sixth control signal terminal is a working level signal, therefore the seventh transistor T7 is turned on. The third initialization signal is written to the anode of the light-emitting device D through the seventh transistor T7, preventing the light-emitting device D from emitting light. During the light-emitting driving phase of the pixel driving circuit, a non-working level signal is written to the sixth control signal terminal, therefore the seventh transistor T7 is turned off, and the driving current output by the driving sub-circuit 2 can be transmitted to the light-emitting device D, driving the light-emitting device D to emit light.

[0055] To more specifically illustrate the specific structure of the pixel driving circuit in the embodiments of this disclosure, the following pixel driving circuit includes: a data writing sub-circuit 1, a driving sub-circuit 2, a threshold compensation sub-circuit 3, a storage sub-circuit 4, an auxiliary compensation sub-circuit 5, a first reset sub-circuit 6, a second reset sub-circuit 7, a first light emission control sub-circuit 8, a second light emission control sub-circuit 9, and a third reset sub-circuit 10, as described below. It should be noted that, in one example, the first terminal of the auxiliary compensation sub-circuit 5 is connected to the first terminal of the driving sub-circuit 2, such as... Figure 4a As shown. In another example, the first terminal of the auxiliary compensation sub-circuit 5 is connected to the second terminal of the drive sub-circuit 2, as shown. Figure 4b As shown. The driving process of the pixel driving circuit in the two examples is basically the same. The only difference is that in the first example, the auxiliary compensation signal Vcomp needs to be written to the control terminal of the driving sub-circuit 2 through the first and second terminals of the driving sub-circuit 2, while in the second example, the auxiliary compensation signal Vcomp is directly written to the control terminal of the driving sub-circuit 2 through the second terminal of the driving sub-circuit 2. The other driving processes are exactly the same. Therefore, the following description only uses the example of the first terminal of the auxiliary compensation sub-circuit 5 being connected to the first terminal of the driving sub-circuit 2 to explain the specific driving process of the pixel driving circuit.

[0056] Specifically, referring to Figure 4, the data writing sub-circuit 1 includes a first transistor T1. The gate of the first transistor T1 is connected to the first control signal terminal. The source of the first transistor T1 is connected to the source of the second transistor T2, the drain of the fifth transistor T5, the source of the eighth transistor T8, and the source of the ninth transistor T9. The drain of the first transistor T1 is connected to the data voltage signal line. The driving sub-circuit 2 includes a second transistor T2. The control terminal of the second transistor T2 is connected to the second terminal of the first capacitor C1 and the source of the third transistor T3. The source of the second transistor T2 is connected to the source of the first transistor T1, the drain of the fifth transistor T5, the source of the eighth transistor T8, and the source of the ninth transistor T9. The drain of the second transistor T2 is connected to the drain of the third transistor T3 and the source of the sixth transistor T6. The threshold compensation sub-circuit 3 includes a third transistor T3. The gate of the third transistor T3 is connected to the second control signal terminal. The source of the third transistor T3 is connected to the source of the fourth transistor T4, the gate of the second transistor T2, and the second terminal of the first capacitor C1. The drain of the third transistor T3 is connected to the drain of the second transistor T2 and the source of the sixth transistor T6. The storage sub-circuit 4 includes a first capacitor C1. The first terminal of the first capacitor C1 is connected to the source of the fifth transistor T5 and the first level signal terminal. The second terminal of the first capacitor C1 is connected to the gate of the second transistor T2, the source of the third transistor T3, and the source of the fourth transistor T4. The auxiliary compensation sub-circuit 5 includes a ninth transistor T9. The gate of the ninth transistor T9 is connected to the third control signal terminal. The source of the ninth transistor T9 is connected to the source of the first transistor T1, the source of the second transistor T2, the drain of the fifth transistor T5, and the source of the eighth transistor T8. The drain of the ninth transistor T9 is connected to the auxiliary compensation signal terminal. The first reset sub-circuit 6 includes a fourth transistor T4. The gate of the fourth transistor T4 is connected to a fourth control signal terminal. The source of the fourth transistor T4 is connected to the gate of the second transistor T2, the source of the third transistor T3, and the second terminal of the first capacitor C1. The drain of the fourth transistor T4 is connected to a first initialization signal terminal. The second reset sub-circuit 7 includes an eighth transistor T8. The gate of the eighth transistor T8 is connected to a fifth control signal terminal. The source of the eighth transistor T8 is connected to the source of the first transistor T1, the source of the second transistor T2, the drain of the fifth transistor T5, and the source of the ninth transistor T9. The drain of the eighth transistor T8 is connected to a second initialization signal terminal. The first light-emitting control sub-circuit 8 includes a fifth transistor T5. The gate of the fifth transistor T5 is connected to a first light-emitting control signal terminal. The source of the fifth transistor T5 is connected to a first level signal terminal. The drain of the fifth transistor T5 is connected to the source of the first transistor T1, the source of the second transistor T2, the source of the eighth transistor T8, and the source of the ninth transistor T9.The second light-emitting control sub-circuit 9 includes a sixth transistor T6. The gate of the sixth transistor T6 is connected to the second light-emitting control signal terminal. The source of the sixth transistor T6 is connected to the drain of the second transistor T2 and the drain of the third transistor T3. The drain of the sixth transistor T6 is connected to the source of the seventh transistor T7 and the anode of the light-emitting device D. The third reset sub-circuit 10 includes a seventh transistor T7. The gate of the seventh transistor T7 is connected to the sixth control signal terminal. The source of the seventh transistor T7 is connected to the drain of the sixth transistor T6 and the anode of the light-emitting device D. The drain of the seventh transistor T7 is connected to the third initialization signal terminal.

[0057] It should be noted that in this embodiment, only N-type oxide thin-film transistors (OTCs) are used for the third transistor T3, the fourth transistor T4, and the seventh transistor T7, while P-type low-temperature polysilicon transistors (LTPSs) are used for the illustration. LTCs have higher electron mobility, thus exhibiting better switching and response speeds, while OTCs have lower electron mobility and lower leakage current. Using OTCs as transistors with low leakage current (e.g., the third transistor T3 (for threshold compensation), the fourth transistor T4 (for resetting the driver sub-circuit 2), and the seventh transistor T7 (for resetting the light-emitting device) can improve circuit reliability. Of course, the types of transistors in the pixel driving circuit of this disclosure are not limited to this, and different designs can be implemented as needed.

[0058] Figure 5 To and Figure 4a The timing diagram of the pixel driving circuit is shown in the image. (Refer to...) Figure 5 The driving phases of the pixel driving circuit include: reset phase t1, threshold compensation phase t2, pre-write phase t3, data write phase t4, and light emission driving phase t5. The pre-write phase t3 and the data write phase t4 are both located within the threshold compensation phase t2. That is, when the pixel driving circuit writes the auxiliary compensation signal Vcomp in the pre-write phase t3, it simultaneously performs threshold voltage compensation. Similarly, when the pixel driving circuit writes the data voltage signal Vdata in the data write phase t4, it simultaneously performs threshold voltage compensation. Furthermore, the reset phase t1 includes a first reset sub-phase t1-1 and a second reset sub-phase t1-2. The first reset sub-phase t1-1 is located before the pre-write phase t2 and the data write phase t3, and the second reset phase t1-2 is located after the pre-write phase t2 and the data write phase t3. The working process of each phase is as follows:

[0059] In the first reset stage t1: a high-level signal is written to the fourth control signal terminal, a low-level signal is written to the fifth control signal terminal, and a high-level signal is written to the sixth control signal terminal. The fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are all turned on. The first initialization signal Vinit1 resets the gate of the second transistor T2 through the fourth transistor T4, and the second initialization signal Vinit2 resets the source of the second transistor T2 through the eighth transistor T8, preparing for the writing of the data voltage signal Vdata. The third initialization signal Vinit3 resets the anode of the light-emitting device D through the seventh transistor T7, causing the light-emitting device D to no longer be in the forward conduction state. This gradually eliminates the internal electric field formed by the directional movement of impurity ions within the light-emitting device D, thereby restoring the characteristics of the light-emitting device. Simultaneously, in this stage, the second control signal S2 is an alternating high and low level signal. When a high-level signal is written to the second control signal terminal, the third transistor T3 turns on, along with the gate and drain of the second transistor T2. This ensures that the gate, source, and drain of the second transistor T2 are all low-level signals, preparing for signal writing.

[0060] Pre-writing stage t3 (threshold compensation is performed simultaneously): A high-level signal is written to the second control signal terminal, and a low-level signal is written to the third control signal terminal. Both the third transistor T3 and the ninth transistor T9 are turned on. The gate and drain of the second transistor T2 are turned on through the third transistor T3. The auxiliary compensation signal Vcomp written to the auxiliary compensation signal terminal is written to the gate of the second transistor T2 through the ninth transistor T9, the source and drain of the second transistor T2, and the third transistor T3 in sequence, until the gate voltage of the second transistor T2 is Vcomp+Vth (Vth<0, Vth is the threshold voltage of the second transistor T2), and stored in the first capacitor C1. The voltages of the first terminal and the second terminal of the first capacitor C1 are VDD and Vcomp+Vth, respectively.

[0061] Data writing stage t4 (with simultaneous threshold compensation): A low-level signal is written to the first control signal terminal, and a high-level signal is written to the second control signal terminal. Both the first transistor T1 and the third transistor T3 are turned on. The gate and drain of the second transistor T2 are turned on through the third transistor T3. The data voltage signal Vdata written by the data voltage signal line is written to the source of the second transistor T2 through the ninth transistor T9. Since Vcomp + Vth < Vdata, the second transistor T2 is turned on. The data voltage signal Vdata is written to the gate of the second transistor T2 through the source and drain of the second transistor T2 and the third transistor T3 until the gate voltage of the second transistor T2 is Vdata + Vth (Vth < 0, Vth is the threshold voltage of the second transistor T2) and stored in the first capacitor C1. The voltages of the first terminal and the second terminal of the first capacitor C1 are VDD and Vdata + Vth, respectively.

[0062] Second reset stage t1-2: A low-level signal is written to the fifth control signal terminal, the eighth transistor T8 is turned on, and the second initialization signal Vinit2 is written to the source of the second transistor T2 through the eighth transistor T8, in preparation for writing the first level signal Vdd.

[0063] During the light-emitting driving stage t5: Low-level signals are written to the first, second, and sixth light-emitting control signal terminals. Transistors T5 and T6 are both turned on, while transistor T7 is turned off, stopping the reset of the light-emitting device D. The first-level signal Vdd is written to the source of transistor T2 through transistor T5. Therefore, the gate-source voltage of transistor T2 is: Vgs = (Vdata + Vth) - Vdd. The light-emitting current I of the light-emitting device is equal to the current flowing through transistor T2, expressed as:

[0064] I = β*(Vgs - Vth) 2

[0065] =β*(Vdata+Vth-Vdd-Vth) 2

[0066] =β*(Vdata-Vdd) 2

[0067] Where β = 1 / 2 * μ n *C ox *(W / L), μ n C is the electron mobility of the second transistor T2. ox It is the insulation capacitance per unit area, and W / L is the width-to-length ratio of the second transistor T2.

[0068] This concludes the process. Figure 4a The pixel driving circuit shown is driven by adding an auxiliary compensation sub-circuit 5 to increase the data writing time, which can improve the overall compensation effect of the circuit and solve problems such as uneven image display and afterimage aberration.

[0069] Figure 6 The diagram shows the image retention simulation test results of a conventional pixel driving circuit (8T1C, excluding the ninth transistor T9) and the pixel driving circuit of this disclosure, as provided in the embodiments of this disclosure. It should be noted that, in performing the image retention simulation test and the following uniformity test, to demonstrate the impact of the added ninth transistor T9 on the performance of the pixel driving circuit, the seventh transistor in the pixel driving circuit is an LTPS transistor (the same as in the conventional pixel driving circuit). (Refer to...) Figure 6The horizontal axis of the image stick simulation test result graph represents time in minutes; the vertical axis represents the image stick score, with a lower score indicating better circuit performance. The POR line represents the test results of a traditional pixel driving circuit, while the DOE line represents the test results of the pixel driving circuit of this embodiment. As can be seen from the graph, the pixel driving circuit of this embodiment has a lower image stick score, indicating better stability, stronger anti-interference capability, higher signal transmission quality, and higher reliability.

[0070] Figure 7 This paper presents a test of the uniformity of a display panel under the same refresh rate and low brightness conditions using a conventional pixel driving circuit (8T1C, excluding the ninth transistor T9) and the pixel driving circuit of this disclosure. Uniformity refers to the consistency of performance indicators such as brightness and color among the various pixel units on the display panel. This consistency can be measured by comparing with standard values. For example, a uniformity of 90% for the display panel means that the performance of most pixel units is very close to the standard value, and the display effect is relatively consistent. The column containing POR data represents the test parameters for uniformity when the display panel uses the conventional pixel driving circuit, and the column containing DOE data represents the test parameters for uniformity when the display panel uses the pixel driving circuit of this disclosure. As can be seen from the figure, when the refresh rate of the display panel is 120Hz and the display brightness is 0.01nit, the uniformity parameter of the display panel using the conventional pixel driving circuit is 1.6%, while the uniformity parameter of the display panel using the pixel driving circuit of this disclosure is 10.7%, which is 9.1% higher than that of the display panel using the pixel driving circuit. When the refresh rate of the display panel is 120Hz and the display brightness is 0.05nit, the uniformity parameter of the display panel using a conventional pixel driving circuit is 5.1%, while the uniformity parameter of the display panel using the pixel driving circuit of this disclosure is 26.8%, which is 21.7% higher than that of the display panel using a conventional pixel driving circuit. When the refresh rate of the display panel is 120Hz and the display brightness is 0.1nit, the uniformity parameter of the display panel using a conventional pixel driving circuit is 12.7%, while the uniformity parameter of the display panel using the pixel driving circuit of this disclosure is 32.7%, which is 20.0% higher than that of the display panel using a conventional pixel driving circuit. This means that the pixel driving circuit of this disclosure has good stability and reliability, and can improve the display quality of the display panel.

[0071] Secondly, this disclosure also provides a display substrate, which includes the pixel driving circuit of the preceding embodiments. Specifically, the display substrate includes a substrate and a plurality of pixel units arranged in an array on the substrate. Each pixel unit includes the pixel driving circuit of the above embodiments and a light-emitting device disposed on the side of the pixel driving circuit facing away from the substrate.

[0072] The aforementioned display substrate can be used in display panels, which may include: flexible wearable devices, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and any other products or components with display functions. Other essential components of this display are understood by those skilled in the art and will not be elaborated upon here, nor should they be construed as limiting the invention.

[0073] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A pixel driving circuit, comprising a driving sub-circuit, a data writing sub-circuit, and a threshold compensation sub-circuit; wherein, The data writing sub-circuit is configured to transmit the data voltage signal to the first terminal of the driving sub-circuit under the control of the first control signal; The threshold compensation sub-circuit is configured to compensate the threshold voltage of the driving sub-circuit under the control of the second control signal. The driving sub-circuit is configured to provide a driving current to the light-emitting device to be driven based on the voltage of its first terminal and control terminal; The pixel driving circuit further includes an auxiliary compensation sub-circuit electrically connected to the driving sub-circuit; the auxiliary compensation sub-circuit is configured to, when the threshold compensation sub-circuit compensates the driving sub-circuit, transmit an auxiliary compensation signal to a first terminal or a second terminal of the driving sub-circuit under the control of a third control signal; the polarity of the auxiliary compensation signal is the same as the polarity of the data voltage signal, and the absolute value of the auxiliary compensation signal is less than the absolute value of the data voltage signal; The auxiliary compensation signal is half of the data voltage signal; The auxiliary compensation signal is a dynamically changing voltage that changes with the data voltage signal.

2. The pixel driving circuit according to claim 1, wherein, The auxiliary compensation sub-circuit includes a ninth transistor; the control electrode of the ninth transistor is connected to the third control signal terminal, the first electrode is connected to the first or second terminal of the driving sub-circuit, and the second electrode is connected to the auxiliary compensation signal terminal.

3. The pixel driving circuit according to claim 1, wherein the pixel driving circuit further includes a first reset sub-circuit and a second reset sub-circuit; The first reset sub-circuit is configured to reset the control terminal of the drive sub-circuit via a first initialization signal under the control of a fourth control signal. The second reset sub-circuit is configured to reset the first terminal of the drive sub-circuit via a second initialization signal under the control of a fifth control signal.

4. The pixel driving circuit according to claim 3, wherein, The first reset sub-circuit includes a fourth transistor; the control terminal of the fourth transistor is connected to a fourth control signal terminal, the first terminal is connected to the control terminal of the drive sub-circuit, and the second terminal is connected to a first initialization signal terminal. The second reset sub-circuit includes an eighth transistor; the control electrode of the eighth transistor is connected to the fifth control signal terminal, the first electrode is connected to the first terminal of the drive sub-circuit, and the second electrode is connected to the second initialization signal terminal.

5. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit further includes a first light emission control sub-circuit and a second light emission control sub-circuit; The first light-emitting control sub-circuit is configured to transmit a first level signal to the first terminal of the driving sub-circuit under the control of the first light-emitting control signal; The second light-emitting control sub-circuit is configured to transmit the driving current to the light-emitting device to be driven under the control of the second light-emitting control signal.

6. The pixel driving circuit according to claim 5, wherein, The first light-emitting control sub-circuit includes a fifth transistor; the control electrode of the fifth transistor is connected to the first light-emitting control signal terminal, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first terminal of the driving sub-circuit. The second light-emitting control sub-circuit includes a sixth transistor; the control electrode of the sixth transistor is connected to the second light-emitting control signal terminal, the first electrode is connected to the second terminal of the driving sub-circuit, and the second electrode is connected to the first electrode of the light-emitting device.

7. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit further includes a third reset sub-circuit; the third reset sub-circuit is configured to reset the first electrode of the light-emitting device by a third initialization signal under the control of a sixth control signal.

8. The pixel driving circuit according to claim 7, wherein, The third reset circuit includes a seventh transistor; the control electrode of the seventh transistor is connected to the sixth control signal terminal, the first electrode is connected to the first electrode of the light-emitting device, and the second electrode is connected to the third initialization signal terminal.

9. The pixel driving circuit according to claim 1, wherein, The data writing sub-circuit includes a first transistor; the control electrode of the first transistor is connected to a first control signal terminal, the first electrode is connected to the first terminal of the driving sub-circuit, and the second electrode is connected to a data voltage signal line.

10. The pixel driving circuit according to claim 1, wherein, The threshold compensation sub-circuit includes a third transistor; the control electrode of the third transistor is connected to the second control signal terminal, the first electrode is connected to the control terminal of the driving sub-circuit, and the second electrode is connected to the second terminal of the driving sub-circuit.

11. The pixel driving circuit according to claim 1, wherein, The driving sub-circuit includes a second transistor; the control electrode of the second transistor is multiplexed as the control terminal of the driving sub-circuit; the first electrode of the second transistor is multiplexed as the first terminal of the driving sub-circuit; and the second electrode of the second transistor is multiplexed as the second terminal of the driving sub-circuit.

12. A display substrate comprising a pixel driving circuit as claimed in any one of claims 1-11.

13. The display substrate according to claim 12, wherein, The display substrate includes a substrate and a plurality of pixel units arranged in an array on the substrate; the pixel unit includes the pixel driving circuit and a light-emitting device disposed on the side of the pixel driving circuit away from the substrate.

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