Solar cell, photovoltaic module and preparation method of doped polycrystalline silicon layer

Abstract

The invention provides a solar cell, a photovoltaic module and a preparation method of a doped polycrystalline silicon layer, and relates to the technical field of photovoltaics. The solar cell includes: a silicon substrate; the doped polycrystalline silicon layer is located on the silicon substrate; in the direction perpendicular to the thickness direction of the solar cell, the doped polycrystalline silicon layer comprises a lightly doped polycrystalline silicon part and a heavily doped polycrystalline silicon part. The doping type of the lightly-doped polycrystalline silicon part is the same as that of the heavily-doped polycrystalline silicon part, and the doping concentration of the lightly-doped polycrystalline silicon part is smaller than that of the heavily-doped polycrystalline silicon part; the first transparent conductive layer is located on the doped polycrystalline silicon layer; and the first electrode is located at a position corresponding to the heavily doped polycrystalline silicon part on the first transparent conductive layer. Collection of current carriers is increased, low contact resistance and good passivation performance are achieved, auger recombination of the non-metal area can be reduced, long-wave light parasitic absorption of the non-metal area is reduced, filling factors are improved, and the performance of the solar cell is improved.

Description

Technical Field

[0001] The invention relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell, a photovoltaic module and a doped polysilicon layer. Background Art

[0002] Solar cells can convert solar energy into electrical energy. They utilize clean energy and therefore have broad application prospects.

[0003] Doped polysilicon has good electrical and optical properties, etc., and is therefore widely used in solar cells.

[0004] However, in solar cells containing doped polysilicon and a transparent conductive layer, due to the poor conductivity of the transparent conductive layer, there is usually a large transmission resistance, which affects the further improvement of the battery performance. Summary of the invention

[0005] The present invention provides a solar cell, a photovoltaic module and a method for preparing a doped polysilicon layer, aiming to solve the problems of poor conductivity and large transmission resistance in existing solar cells containing doped polysilicon and a transparent conductive layer.

[0006] A first aspect of the present invention provides a solar cell, comprising:

[0007] Silicon substrate;

[0008] A doped polysilicon layer is located on the silicon substrate; in a direction perpendicular to the thickness direction of the solar cell, the doped polysilicon layer includes: a lightly doped polysilicon portion and a heavily doped polysilicon portion; the lightly doped polysilicon portion and the heavily doped polysilicon portion have the same doping type, and the doping concentration of the lightly doped polysilicon portion is less than the doping concentration of the heavily doped polysilicon portion;

[0009] A first transparent conductive layer, located on the doped polysilicon layer;

[0010] The first electrode is located at a position corresponding to the heavily doped polysilicon portion on the first transparent conductive layer.

[0011] In the embodiment of the present invention, in the direction perpendicular to the thickness direction of the solar cell, the doped polysilicon layer includes: a lightly doped polysilicon portion and a heavily doped polysilicon portion, the lightly doped polysilicon portion and the heavily doped polysilicon portion have the same doping type, and the doping concentration of the lightly doped polysilicon portion is less than the doping concentration of the heavily doped polysilicon portion, the first electrode is located at a position corresponding to the heavily doped polysilicon portion on the first transparent conductive layer, that is, the region corresponding to the first electrode in the doped polysilicon is heavily doped, and the remaining region is lightly doped to form a structure similar to a high-low junction, under the action of the high-low junction, a part of the carriers move laterally from the lightly doped polysilicon portion to the heavily doped polysilicon portion in the doped polysilicon layer, and then pass through the first transparent conductive layer longitudinally, and are then collected by the first electrode, which can play a shunting role, and can generally increase the collection effect of the carriers. In addition, the position where the first electrode is not set on the first transparent conductive layer corresponds to the position of the lightly doped polysilicon portion, which can reduce the Auger recombination in the non-metallic region on the one hand, and reduce the parasitic absorption of long-wave light in the non-metallic region on the other hand. Thirdly, for BC hybrid cells, the non-metallic region is lightly doped and its conductivity is relatively weak, the risk of leakage in local areas is reduced, and the passivation performance of the N / P junction area can be improved. At the same time, the first transparent conductive layer located between the doped polysilicon layer and the first electrode can further reduce the contact resistance between the doped polysilicon layer and the first electrode, and increase the lateral transmission capacity of the doped polysilicon, improve the fill factor, and further improve the performance of the solar cell.

[0012] Optionally, a ratio of the doping concentration of the heavily doped polysilicon portion to the doping concentration of the lightly doped polysilicon portion is 1.25 to 25.

[0013] Optionally, the square resistance of the heavily doped polysilicon portion is 20 ohm / □ to 200 ohm / □.

[0014] Optionally, the doping depth of the heavily doped polysilicon portion is 50 nm to 200 nm.

[0015] Optionally, the crystallization rate of the heavily doped polysilicon portion is greater than or equal to 75%, and / or the crystallization rate of the lightly doped polysilicon portion is less than or equal to 71%.

[0016] Optionally, the roughness of a surface of the heavily doped polysilicon portion that is away from the silicon substrate is less than or equal to 40 nm.

[0017] Optionally, the thickness of the first transparent conductive layer is 20 nm to 200 nm.

[0018] Optionally, the heavily doped polysilicon portion has a width of 20 μm to 100 μm; and the width direction is perpendicular to the thickness direction of the solar cell.

[0019] Optionally, the solar cell further comprises:

[0020] A second semiconductor layer is located on the same side of the silicon substrate as the doped polysilicon layer and is alternately distributed with the doped polysilicon layer;

[0021] a second transparent conductive layer, covering the second semiconductor layer;

[0022] and a second electrode, located on the second transparent conductive layer.

[0023] Optionally, the solar cell further comprises:

[0024] The tunnel oxide layer is stacked with the doped polysilicon layer and is located between the silicon substrate and the doped polysilicon layer. In a second aspect of the present invention, a photovoltaic module is provided, comprising: a plurality of any of the aforementioned solar cells.

[0025] The above-mentioned solar cells and photovoltaic modules have the same or similar beneficial effects, which will not be described again here to avoid repetition.

[0026] A third aspect of the present invention provides a method for preparing a doped polysilicon layer, comprising:

[0027] A battery precursor is provided, wherein the battery precursor comprises a silicon substrate, a lightly doped polysilicon layer formed on the silicon substrate, and a doping source layer formed on the lightly doped polysilicon layer; a doping element in the doping source layer in the battery precursor is doped into a local area of ​​the lightly doped polysilicon layer by using a local laser doping method;

[0028] The lightly doped polysilicon layer partially doped with the doping element is annealed in an atmosphere containing the doping element to obtain the doped polysilicon layer.

[0029] Optionally, during the annealing process, the pressure is from 100 Pa to normal pressure, the annealing temperature is from 500° C. to 900° C., and the annealing time is from 20 min to 90 min.

[0030] Optionally, the atmosphere containing the doping element includes: a phosphorus source gas or a boron source gas, the phosphorus source gas includes phosphorus oxychloride, the boron source gas includes boron trichloride and boron tribromide, and the flow rate of the atmosphere containing the doping element is 50 sccm to 200 sccm.

[0031] In the preparation method of the doped polysilicon layer of the present application, annealing is performed in an atmosphere containing doping elements. The doping elements in the atmosphere are similar to a supplementary source. On the one hand, the doping elements can be supplemented to further enhance the effect of re-doping. On the other hand, the internal diffusion concentration of the doping elements is increased, thereby reducing the contact resistance. Annealing in an atmosphere containing doping elements further reduces the surface concentration of the non-laser region. In solar cells, surface recombination can be reduced, the open circuit voltage can be increased, and the doping atoms in the laser region can be further supplemented, promoted, and activated, thereby achieving a better repair effect on the internal lattice damage caused by laser doping. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0033] Figure 1 A partial structural schematic diagram of a second solar cell in an embodiment of the present invention is shown;

[0034] Figures 2 to 10 A schematic diagram showing the steps of preparing a solar cell in an embodiment of the present invention is shown;

[0035] Fig.11 A schematic diagram comparing the contact resistance of a doped amorphous silicon layer obtained by annealing in an atmosphere containing doping elements and annealing in an atmosphere not containing doping elements is shown.

[0036] Description of the accompanying drawings:

[0037] 0-contact opening, 1-silicon substrate, 2-tunneling oxide layer, 3-lightly doped polysilicon portion, 3'-intrinsic polysilicon layer, 4-intrinsic amorphous silicon layer, 5-doped amorphous silicon layer, 6-first transparent conductive layer, 7-heavily doped polysilicon portion, 8-first electrode, 9-doped source layer. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] The present invention provides a solar cell, referring to Figure 1The solar cell includes: a silicon substrate 1 , a doped polysilicon layer, a first transparent conductive layer 6 and a first electrode 8 .

[0040] The present invention does not specifically limit the doping type of the silicon substrate 1. The doped polysilicon layer is located on the silicon substrate 1. Figure 1 In the figure, the thickness direction of the solar cell is the up-down direction. In the direction perpendicular to the thickness direction of the solar cell (i.e., the horizontal direction in the figure), the doped polysilicon layer includes: a lightly doped polysilicon portion 3 and a heavily doped polysilicon portion 7. The lightly doped polysilicon portion 3 and the heavily doped polysilicon portion 7 have the same doping type, and the doping concentration of the lightly doped polysilicon portion 3 is less than the doping concentration of the heavily doped polysilicon portion 7.

[0041] It should be noted that the "light" and "heavy" in the lightly doped polysilicon part 3 and the heavily doped polysilicon part 7 do not limit the doping concentration of each part. "Light" and "heavy" are only used to distinguish the two parts and indicate the relationship between the doping concentrations of the two parts.

[0042] Reference Figure 1 The first transparent conductive layer 6 is located on the doped polysilicon layer. The first electrode 8 is located at a position corresponding to the heavily doped polysilicon portion 7 on the first transparent conductive layer 6. That is, the region corresponding to the first electrode 8 in the doped polysilicon is heavily doped, and the remaining region is lightly doped.

[0043] If the doping concentration in the horizontal direction of the doped polysilicon is consistent, that is, there is no heavily doped polysilicon part and lightly doped polysilicon part, the carrier transmission path is basically: the carrier is transmitted longitudinally through the doped polysilicon layer to the first transparent conductive layer, and then transmitted laterally in the first transparent conductive layer, and then collected by the first electrode. Due to the limited lateral transmission capacity of the first transparent conductive layer, the carrier collection efficiency is low, and in this application, the polysilicon area corresponding to the first electrode is heavily doped, and a structure similar to a high-low junction is formed with the surrounding lightly doped polysilicon part. Under the action of the high-low junction, a part of the carriers moves laterally from the lightly doped polysilicon part to the heavily doped polysilicon part in the doped polysilicon layer, and then passes longitudinally through the first transparent conductive layer, and then is collected by the first electrode, which can play a shunting role and can generally increase the carrier collection effect.

[0044] In addition, the position where the first electrode 8 is not provided on the first transparent conductive layer 6 corresponds to the position of the lightly doped polysilicon portion 3, which can reduce Auger recombination in the non-metallic region on the one hand, and reduce parasitic absorption of long-wave light in the non-metallic region on the other hand. Therefore, the structure of the present invention can achieve lower contact resistance and better passivation performance and optical performance.

[0045] It should be noted that the first electrode 8 is located at a position corresponding to the heavily doped polysilicon portion 7 on the first transparent conductive layer 6, which does not result in a strict limitation on the relative size of the first electrode 8 and the heavily doped polysilicon portion 7. The width of the first electrode 8 and the width of the heavily doped polysilicon portion 7 can be set according to limiting factors such as the actual production process and alignment accuracy. For example, the first electrode 8 can extend outside the heavily doped polysilicon portion 7, that is, the width of the first electrode is greater than the width of the heavily doped polysilicon portion. For another example, Figure 1 In the embodiment, the first electrode 8 does not extend beyond the heavily doped polysilicon portion 7, that is, the width of the first electrode is smaller than the width of the heavily doped polysilicon portion.

[0046] Optionally, the ratio of the doping concentration of the heavily doped polysilicon portion 7 to the doping concentration of the lightly doped polysilicon portion 3 is 1.25 to 25. In this way, the relative size of the doping concentrations of the two has a good effect on reducing contact resistance, improving passivation performance, reducing Auger recombination in non-metallic areas, and reducing parasitic absorption of long-wave light in non-metallic areas. It should be noted that the doping concentration of the heavily doped polysilicon portion 7 refers to the number of doped atoms per unit volume in the heavily doped polysilicon portion 7, and the doping concentration of the lightly doped polysilicon portion 3 refers to the number of doped atoms per unit volume in the lightly doped polysilicon portion 3.

[0047] More specifically, the ratio of the doping concentration of the heavily doped polysilicon portion 7 to the doping concentration of the lightly doped polysilicon portion 3 may be 1.25, 2.5, 5, 10, 15, 25, 16.25, 20, 23.5, 14, 18, and the like.

[0048] In a specific embodiment, the doping concentration of the heavily doped polysilicon portion 7 is greater than or equal to 1E20 atoms / cm 3 (The number of doping atoms or ions per cubic centimeter). The doping concentration of the lightly doped polysilicon portion 3 is less than or equal to 8E19 atoms / cm 3 .

[0049] For another example, the doping concentration of the heavily doped polysilicon portion 7 is 1E20 atoms / cm 3 Up to 5E20atoms / cm 3 , the doping concentration of the lightly doped polysilicon portion 3 is 2E19atoms / cm 3 To 8E19atoms / cm 3 .

[0050] In a specific embodiment, the square resistance of the heavily doped polysilicon portion 7 is 20 ohm / □ to 200 ohm / □. The square resistance range of the heavily doped polysilicon portion 7 can further increase the collection of carriers, and can achieve lower contact resistance and better passivation performance.

[0051] For example, the square resistance of the heavily doped polysilicon part 7 can be 20ohm / □, 30ohm / □, 50ohm / □, 53ohm / □, 60ohm / □, 72ohm / □, 80ohm / □, 85ohm / □, 92ohm / □, 100ohm / □, 110ohm / □, 105ohm / □, 113ohm / □, 120ohm / □, 150ohm / □, 180ohm / □, 175ohm / □, 200ohm / □.

[0052] Optionally, the doping depth of the heavily doped polysilicon portion 7 is 50nm to 200nm. It should be noted that the doping depth of the heavily doped polysilicon portion 7 refers to the depth of diffusion of doped atoms or doped ions in the heavily doped polysilicon portion 7, that is, the distance from the doping source to a certain position inside the heavily doped polysilicon portion 7, which can be obtained based on the inflection point of the ECV (Electrochemical Capacitance-Voltage profiler, electrochemical differential capacitance voltage) curve. The doping depth of the heavily doped polysilicon portion 7 is 50nm to 200nm, and the doping depth of the heavily doped polysilicon portion 7 can further increase the collection of carriers, and can achieve lower contact resistance and better passivation performance.

[0053] For example, the doping depth of the heavily doped polysilicon portion 7 may be 50nm, 60nm, 70nm, 75nm, 80nm, 85nm, 90nm, 100nm, 110nm, 105nm, 120nm, 106nm, 150nm, 180nm, 185nm, or 200nm.

[0054] Optionally, the crystallization rate of the heavily doped polysilicon part 7 is greater than or equal to 75%, and / or the crystallization rate of the lightly doped polysilicon part 3 is less than or equal to 71%. The heavily doped polysilicon part 7 has a higher crystallization rate and stronger conductivity, which can further reduce the contact resistance.

[0055] For example, the crystallization rate of the heavily doped polysilicon portion 7 may be 75%, 76%, 77%, 78%, 79%, 80%, 80.3%, 81%, 82%, 84%. For example, the crystallization rate of the lightly doped polysilicon portion 3 may be 71%, 70%, 68%, 65%, 60%, 59%, 55%, 50%, 52%, 54%.

[0056] Optionally, the roughness of the surface of the heavily doped polysilicon portion 7 away from the silicon substrate 1 is less than or equal to 40 nm, that is, the surface of the heavily doped polysilicon portion 7 away from the silicon substrate 1 is relatively flat, and heavy doping such as laser heavy doping has basically no adverse effect on the passivation performance, and the heavily doped polysilicon portion 7 still has good passivation performance. The roughness here refers to: the difference between the highest point and the lowest point of the surface of the heavily doped polysilicon portion 7 away from the silicon substrate 1 is the Ra roughness.

[0057] For example, the roughness of the surface of the heavily doped polysilicon portion 7 facing away from the silicon substrate 1 is 1 nm, 3 nm, 5 nm, 8 nm, 10 nm, 15 nm, 20 nm, 24 nm, 27 nm, 30 nm, 35 nm, 38 nm, or 40 nm.

[0058] Optional, see Fig. 9 The width W1 of the heavily doped polysilicon part 7 is 20μm (micrometer) to 100μm, and the width direction is perpendicular to the thickness direction of the solar cell. The width range of the heavily doped polysilicon part 7 is relatively matched with the common size of the first electrode, and the collection of carriers is more obviously promoted.

[0059] For example, the width of the heavily doped polysilicon portion 7 can be 20μm, 30μm, 50μm, 80μm, 100μm, 150μm, 180μm, 200μm, 225μm, 250μm, 300μm, 350μm, 320μm, 400μm, 500μm, 510μm, 600μm, 700μm, 800μm, 900μm, 1000μm. Optionally, the solar cell may also include: a tunneling oxide layer 2 stacked with the aforementioned doped polysilicon layer, that is, the tunneling oxide layer 2 is located between the doped polysilicon layer and the silicon substrate 1, and the tunneling oxide layer 2 is closer to the silicon substrate 1. The surface passivation effect is improved through the tunneling oxide layer 2, and recombination can also be reduced, thereby further improving the battery performance.

[0060] Optionally, the thickness of the first transparent conductive layer 6 is 20 nm to 200 nm. The thickness range of the first transparent conductive layer 6 has a more obvious effect on reducing the contact resistance.

[0061] For example, the thickness of the first transparent conductive layer 6 can be 20nm, 30nm, 40nm, 50nm, 55nm, 60nm, 70nm, 80nm, 72nm, 83nm, 90nm, 94nm, 75nm, 100nm, 120nm, 110nm, 150nm, 170nm, or 200nm.

[0062] Optionally, the solar cell may include: a second semiconductor layer, a second transparent conductive layer, and a second electrode. The second semiconductor layer and the aforementioned doped polysilicon layer are located on the same side of the silicon substrate 1, and are alternately distributed with the aforementioned doped polysilicon layer. Specifically, the second semiconductor layer and the doped polysilicon layer are both located on the backlight side of the silicon substrate 1. During the normal operation of the solar cell, the side of the silicon substrate 1 that mainly absorbs light is the light-facing side of the silicon substrate 1. The backlight side is opposite to the light-facing side, that is, the solar cell is a back-contact solar cell. The second transparent conductive layer covers the second semiconductor layer. The second electrode is located on the second transparent conductive layer.

[0063] The solar cell may also include: a tunneling oxide layer 2 stacked with the aforementioned doped polysilicon layer, the tunneling oxide layer 2 being closer to the silicon substrate 1. The second semiconductor layer may include: an intrinsic amorphous silicon layer 4 and a doped amorphous silicon layer 5 stacked, wherein the intrinsic amorphous silicon layer is closer to the silicon substrate 1. The doping types of the doped amorphous silicon layer and the doped polysilicon layer are different, one of which is N-type doping and the other is P-type doping. The solar cell is a back contact hybrid cell, and the above-mentioned doped polysilicon layer, tunneling oxide layer, intrinsic amorphous silicon layer and doped amorphous silicon layer are all located on the back side of the silicon substrate. For the back contact hybrid cell, the non-metallic region is lightly doped and its conductivity is relatively weak, the risk of leakage in the local area is reduced, and the passivation performance of the n / p junction area can be improved. At the same time, the first transparent conductive layer 6 located between the doped polysilicon layer and the first electrode 8 can further reduce the contact resistance between the doped polysilicon layer and the first electrode 8, and increase the lateral transmission capacity of the doped polysilicon, improve the fill factor, and further improve the performance of the solar cell.

[0064] The present application also provides a photovoltaic module, which includes: a plurality of any of the aforementioned solar cells, and the photovoltaic module has the same or similar beneficial effects as any of the aforementioned solar cells, which will not be described again here to avoid repetition.

[0065] The present application also provides a method for preparing a doped polysilicon layer, which can prepare a doped polysilicon layer in any of the aforementioned solar cells. The preparation method can include the following steps.

[0066] Step 101 : providing a battery precursor, wherein the battery precursor comprises a silicon substrate, a lightly doped polysilicon layer formed on the silicon substrate, and a doping source layer formed on the lightly doped polysilicon layer.

[0067] The preparation of the lightly doped polysilicon layer can be as follows: Figure 3 , 4First, an intrinsic polysilicon layer 3' is prepared, and a diffusion process is performed on it to form a lightly doped polysilicon layer 3 and a doping source layer 9 formed on the lightly doped polysilicon layer 3. When an N-type doped polysilicon layer is to be formed, the doping source layer 9 can be a PSG (phosphorus silicon glass) layer, and when a P-type doped polysilicon layer is to be formed, the doping source layer 9 can be a BSG (borosilicate glass) layer.

[0068] Generally, in order to improve the efficiency of the battery, before preparing the intrinsic polysilicon, a tunneling oxide layer 2 is prepared to form a passivation contact structure with the doped polysilicon layer formed after diffusion to improve the passivation effect. Specifically, if LPCVD is used to prepare intrinsic polysilicon, the tunneling oxide layer and the intrinsic polysilicon layer can be integrated into one process. Other methods for preparing intrinsic polysilicon are not described here.

[0069] Step 102: local laser doping is used to dope the doping elements in the doping source layer in the battery precursor into the local area of ​​the lightly doped polysilicon layer.

[0070] Specifically, phosphorus atoms / boron atoms can be selectively doped into silicon in a patterned manner by laser doping after pre-deposition.

[0071] Step 103 , annealing the lightly doped polysilicon layer partially doped with the doping element in an atmosphere containing the doping element to obtain the doped polysilicon layer.

[0072] In order to compare the difference between annealing and annealing in an atmosphere containing doping elements, we tested the contact resistance of multiple samples. Fig.11 . Fig.11 In the figure, the left side refers to the contact resistance data of annealing in an atmosphere without doping elements; the right side refers to the contact resistance data of annealing in an atmosphere containing doping elements in this application. The white dot in each dotted box represents the mean value, and the horizontal line represents the median. Fig.11 It can be concluded that the contact resistance after annealing in an atmosphere containing doping elements in the present application is significantly reduced. This is because the doping elements in the annealing atmosphere are similar to a supplementary source. On the one hand, they can supplement the doping elements and further enhance the effect of re-doping. On the other hand, they increase the internal expansion in the silicon substrate and reduce the contact resistance.

[0073] Optionally, during the annealing process in step 103, the pressure is 100 Pa (Pascal) to normal pressure, the annealing temperature is 500 to 900°C, and the annealing time is 20 to 90 minutes. The re-doping effect after annealing within the above parameter range is better, and the internal lattice damage caused by laser doping can be basically completely repaired.

[0074] Optionally, during the annealing process of step 103, the atmosphere containing doping elements may include: phosphorus source gas or boron source gas, the phosphorus source gas includes phosphorus oxychloride, the boron source gas includes boron trichloride, boron tribromide, etc., and the flow rate of the atmosphere containing doping elements is 50sccm to 200sccm. It can be understood that the atmosphere of the doping elements matches the elements to be heavily doped. In the case of forming an N-type doped polysilicon layer, the element to be heavily doped is phosphorus, and the atmosphere containing doping elements is a phosphorus source gas; in the case of forming a P-type doped polysilicon layer, the element to be heavily doped is boron, and the atmosphere containing doping elements is a boron source gas. The flow rate of the atmosphere containing doping elements is 50sccm to 200sccm, and the heavy doping effect after annealing is better, and the contact resistance is smaller.

[0075] For example, the flow rate of the atmosphere containing the doping element may be 50 sccm, 60 sccm, 70 sccm, 90 sccm, 100 sccm, 125 sccm, 150 sccm, 175 sccm, or 200 sccm.

[0076] The present application is further explained below with reference to specific embodiments.

[0077] Example 1

[0078] The first step is to refer to Figure 2 , polishing treatment, a texturing process is performed on an N-type silicon substrate 1 with a resistivity of 0.1Ω.cm to 10Ω.cm, a thickness of 50μm-400μm, and doped elements such as P (phosphorus) and other VA group elements to obtain a polished silicon substrate surface.

[0079] Step 2: Refer to Figure 3 , prepare tunnel oxide layer 2, the main material is SiO x , and can also be doped with inorganic elements such as N and P. Including but not limited to thermal oxidation (temperature 200℃-800℃), wet oxidation (oxidant HNO3 / O3 / H2O2, etc.), PECVD (SiH4 and N2O / CO2), ALD (TMS, tetramethylsilane and H2O / O3, etc.) and other processes.

[0080] Step 3: Reference Figure 3 , prepare the intrinsic polysilicon layer 3', the main material of the intrinsic polysilicon layer 3' is Si. The preparation methods of the intrinsic polysilicon layer 3' include but are not limited to APCVD, LPCVD (temperature 400-700℃, SiH4), PECVD (SiH4), PVD and other processes. If LPCVD is used to prepare intrinsic polysilicon, the preparation is directly carried out after the tunneling silicon oxide is prepared above, and the second step and the third step can be integrated into one process.

[0081] Step 4: Reference Figure 4, pre-deposit doping source layer 9 and advance, doping source layer 9 can be PSG. The main material is P-doped SiO x Including but not limited to APCVD, LPCVD, PECVD (SiH4), PVD and other processes. Specifically, such as depositing PSG, the structure after the intrinsic polysilicon layer is prepared is placed in a high-temperature diffusion device for direct preparation. At a temperature of 400-900°C, the reaction gases POCl3 and O2 are introduced, and the flow rates are 50-1000sccm and 0.1-20slm respectively. The deposition pressure is 100-400Pa, and the duration is 5-120min. Under this condition, the crystallinity of polysilicon is improved and light doping (doping concentration C P,surface <2E19atoms / cm 3 ), and a layer of PSG is pre-deposited on its surface for the phosphorus source of subsequent laser doping.

[0082] Step 5: Reference Figure 5 , laser doping is used to prepare the heavily doped polysilicon portion 7, and the silicon substrate 1 is laser treated, and selective laser doping is used to form a heavily doped contact area. Specifically, in the first electrode contact area of ​​the above structure, a laser is used, the laser wavelength is 100-1200nm, the pulse width is 1ps-500ns, the frequency is 100kHz to 100MHz (Note: it can also be a continuous laser), the laser spot shape is square or circular, the spot diameter is 50-150μm, the output power is 1-1000W, and the scanning speed is 5-70m / s to dope the local contact area.

[0083] Step 6: Reference Figure 6 , clean PSG, wet clean both the N-type polysilicon laser processing area and the non-processing area to remove PSG on the surface. Specifically, the formed structure is placed in a tank or chain cleaning machine, and the silicon substrate 1 is cleaned on one side or both sides with HF (or NH4HF2) solution (or a mixed solution thereof with HCl), and the concentration of the solution is 0.5-10%.

[0084] In the sixth step, the depth of the PSG removal etching is slightly different from the depth of the laser doping / modification damage, and the polysilicon surface can be flattened after the PSG removal, and the passivation effect of the passivation film is guaranteed. The laser modification mentioned in the entire application mainly refers to improving the crystallization rate by laser.

[0085] The seventh step is annealing. The cleaned silicon substrate 1 is placed in a tubular annealing furnace for annealing. During the annealing process, a phosphorus source is introduced (the flow rate of the phosphorus source is 50-200sccm). The pressure can be from 100Pa to normal pressure. The annealing temperature is 500-900℃ and the annealing time is 20-90min. After annealing, the damage caused by laser doping is eliminated, and the doping concentration distribution of the laser doped area is more uniform. After this step, a surface contact structure with a high and low concentration difference is formed on the surface of the polysilicon. Fig.11 It can be concluded that the contact resistance after annealing in an atmosphere containing doping elements in the present application is significantly reduced. This is because the doping elements in the annealing atmosphere are similar to a supplementary source. On the one hand, they can supplement the doping elements, further enhance the effect of heavy doping, increase the internal expansion in the silicon substrate, and reduce the contact resistance.

[0086] Step 8. Reference Figure 7 , prepare the intrinsic amorphous silicon layer 4, and deposit an intrinsic amorphous silicon film on the back, including but not limited to PECVD (temperature 100-300°C, SiH4, H2, etc.), HWCVD (or Cat-CVD), PVD, ALD or solution method. Specifically, if a 2-16nm intrinsic amorphous silicon layer is deposited by PECVD method, the reaction gas is SiH4 and H2, the volume ratio of SiH4 and H2 in the mixed gas is 1:1-1:50, and the power density of the power supply is 0.01-0.5W / cm 2 , pressure is 20-200Pa, and reaction temperature is 100-250℃.

[0087] Step 9: Reference Figure 8 , prepare P-type amorphous / microcrystalline / nanocrystalline silicon, the main doping elements are IIIA group elements such as B, and inorganic elements such as O and C can also be additionally doped in this basic structure. Phosphorus-doped amorphous / microcrystalline / nanocrystalline silicon film is deposited on the back, including but not limited to PECVD (temperature 100-300°C, SiH4, H2, etc.), HWCVD (or Cat-CVD), PVD, ALD or solution method. Specifically, a 10-40nm P-type amorphous / microcrystalline doped layer is continuously deposited on the surface of intrinsic amorphous silicon, the reaction gases are SiH4, H2 and B2H6, the volume ratio of SiH4 and H2 in the mixed gas is 1:1-1:50, the volume ratio of SiH4 and B2H6 is 5:1-100:1, and the power density of the power supply is 0.01-0.2W / cm 2 , pressure is 20-200Pa, and reaction temperature is 100-250℃.

[0088] Step 10: Reference Fig. 9, forming a contact opening 0, using laser processing (laser wavelength 100-800nm, pulse width 100fs-1ms), printing or spraying etching slurry, etc., to remove the intrinsic amorphous silicon and P-type amorphous / microcrystalline / nanocrystalline silicon in the contact area (this process may involve additional post-cleaning processes). Specifically, such as laser processing, in the local contact area on the front side of the above structure, a laser wavelength of 355nm or 532nm, a pulse width of 1ps-500ns, a frequency of 100kHz-100MHz, a laser spot shape of square or circular, a spot diameter of 0.5-120μm, an output power of 1-20W, a linear speed of 1-100m / s, is used to open the surface passivation layer of the local contact area, and the opening width W2 is 1-300μm. Other methods of preparing contact openings are not described here.

[0089] Step 11. Reference Fig.10 , prepare the first transparent conductive layer 6, deposit ITO, IWO, FTO, AZO and other metal oxides or their mixtures (or other materials with work functions between P-type amorphous / microcrystalline / nanocrystalline silicon and the first electrode 8) on the surface of the above structure, including but not limited to Magnetron Sputtering, RPD (Reactive Plasma Deposition, reactive plasma deposition), Vacuum Evaporation, PECVD, ALD and other preparation methods. Specifically, for example, a 40-100nm ITO (In: Sn = 1: 1-20: 1) transparent conductive film is deposited by PVD method, filled with Ar and O2, O2 / Ar = 0.01-0.2, pressure 0.1-5Pa, and the temperature of the silicon substrate 1 is room temperature.

[0090] It is also possible not to prepare intrinsic amorphous silicon 4, P-type amorphous / microcrystalline / nanocrystalline silicon, and the aforementioned eighth to tenth steps can be reduced.

[0091] Step 12: Prepare the first electrode 8, which can be a metal material such as Au, Pt, Ti, Pd, Ag, Cu, Ni, Al, or a mixture synthesized with other materials, or a related laminated material. Including but not limited to screen printing, laser transfer printing, electroplating, evaporation (can be combined with other graphical means, such as photolithography, etc.), the subsequent processing of the finished battery includes but is not limited to solidification, sintering, light injection, electric injection, or dark annealing. Specifically, if screen printing is used, silver paste is printed in the localized contact opening area of ​​the above structure to form a complete electrode structure, the gate line width is 1-500μm, and the electrode can be smaller than the heavily doped polysilicon part, or the same width as the heavily doped polysilicon part, or wider than the heavily doped polysilicon part. Other preparation methods of the first electrode 8 are not described here.

[0092] Example 2

[0093] The first step, the second step, and the third step in this embodiment 2 correspond to the first step, the second step, and the third step in embodiment 1, and the difference starts from the fourth step.

[0094] The fourth step is laser modification. The silicon substrate 1 is treated with laser and the electrode contact area is selectively laser scanned. Specifically, in the gate line contact area of ​​the above structure, a laser is used with a laser wavelength of 100-1200nm, a pulse width of 1ps-1000ns, a frequency of 100kHz-100MHz (Note: it can also be a continuous laser), a laser spot shape of square or circular, a spot diameter of 20-200μm, an output power of 1-1000W, and a scanning speed of 5-70m / s. The properties of the laser area change, and the distribution of silicon atoms in the polycrystalline silicon with a low crystallization rate changes under the action of the laser, and the originally intertwined crystal planes become ordered crystal planes. That is to say, the laser modification mentioned in the full text of this application mainly refers to laser crystallization or laser enhancement of the crystallization rate. In this step, the laser transforms the originally messy crystal planes into ordered crystal planes, and the number of grains in the polycrystalline silicon is large, so it has more grain boundaries. Grain boundaries can serve as diffusion channels for doping elements. The more grain boundaries there are, the more doping elements diffuse. In the subsequent deposition process, the concentration of doping elements in the laser area is greater than that in the non-laser area, forming a high-concentration heavily doped polysilicon part, which forms a high-low concentration difference with the non-laser area, thereby improving the carrier transmission capacity.

[0095] The fifth step is phosphorus source deposition and annealing, including but not limited to APCVD, LPCVD, PECVD (SiH4), PVD and other processes. Specifically, for example, to deposit PSG, the intrinsic polysilicon prepared above is placed in a high-temperature diffusion device for direct preparation. At a temperature of 400-900°C, the reaction gases POCl3 and O2 are introduced, with flow rates of 50-1000sccm and 0.1-20slm respectively, and the deposition pressure is 100-400Pa for 5-120min. Under this condition, the crystallinity of the polysilicon is improved, and the laser modified area forms a heavily doped area (doping concentration C P,surface >1E20atoms / cm 3 ), the non-laser area forms a lightly doped area, and the doping concentration (doping concentration C P,surface <8E19atoms / cm 3 ) and pre-deposit a layer of PSG on its surface, and the phosphorus atoms doped into the polysilicon film layer can be activated.

[0096] The sixth step, the seventh step, the eighth step, the ninth step, and the tenth step in this embodiment 2 correspond to the eighth step, the ninth step, the tenth step, the eleventh step, and the twelfth step in embodiment 1.

[0097] With respect to the processes of forming the heavily doped polysilicon portion corresponding to Embodiment 1 and Embodiment 2, in the formed solar cell, the passivation effects of the heavily doped polysilicon portion and the lightly doped polysilicon portion are substantially the same.

[0098] Through the improvements of the present application, the cell efficiency of the solar cells obtained by testing Example 1 and Example 2 can be increased by more than 0.2%, and only one laser doping process needs to be added, without the need for additional high-temperature oxidation equipment, to achieve local differentiation of polysilicon doping concentration, and the process flow is simple.

[0099] It should be noted that, for the method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the described order of actions, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0100] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0101] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0102] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A solar cell, characterized in that: include: Silicon substrate; A doped polysilicon layer, located on the silicon substrate; In a direction perpendicular to the thickness direction of the solar cell, the doped polysilicon layer includes: a lightly doped polysilicon portion and a heavily doped polysilicon portion; the lightly doped polysilicon portion and the heavily doped polysilicon portion have the same doping type, and the doping concentration of the lightly doped polysilicon portion is less than the doping concentration of the heavily doped polysilicon portion; A first transparent conductive layer, located on the doped polysilicon layer; The first electrode is located at a position corresponding to the heavily doped polysilicon portion on the first transparent conductive layer.

2. The solar cell according to claim 1, characterized in that: The ratio of the doping concentration of the heavily doped polysilicon portion to the doping concentration of the lightly doped polysilicon portion is 1.25 to 25.

3. The solar cell according to claim 1, characterized in that The sheet resistance of the heavily doped polysilicon portion is 20 ohm / □ to 200 ohm / □.

4. The solar cell according to claim 1, characterized in that The doping depth of the heavily doped polysilicon portion is 50 nm to 200 nm.

5. The solar cell according to claim 1, characterized in that: The crystallization rate of the heavily doped polysilicon portion is greater than or equal to 75%, and / or the crystallization rate of the lightly doped polysilicon portion is less than or equal to 71%.

6. The solar cell according to claim 1, characterized in that The roughness of the surface of the heavily doped polysilicon portion facing away from the silicon substrate is less than or equal to 40 nm.

7. The solar cell according to claim 1, characterized in that The thickness of the first transparent conductive layer is 20 nm to 200 nm.

8. The solar cell according to claim 1, characterized in that The heavily doped polysilicon portion has a width of 20 μm to 100 μm; the width direction is perpendicular to the thickness direction of the solar cell.

9. The solar cell according to any one of claims 1 to 8, characterized in that: Also includes: A second semiconductor layer is located on the same side of the silicon substrate as the doped polysilicon layer and is alternately distributed with the doped polysilicon layer; a second transparent conductive layer, covering the second semiconductor layer; and a second electrode, located on the second transparent conductive layer.

10. The solar cell according to any one of claims 1 to 8, characterized in that: Also includes: The tunneling oxide layer is stacked with the doped polysilicon layer and is located between the silicon substrate and the doped polysilicon layer.

11. A photovoltaic module, characterized in that: include: A solar cell as claimed in any one of claims 1 to 10.

12. A method for preparing a doped polysilicon layer, characterized in that: include: Providing a battery precursor, the battery precursor comprising a silicon substrate, a lightly doped polysilicon layer formed on the silicon substrate, and a doping source layer formed on the lightly doped polysilicon layer; Using local laser doping to dope the doping elements in the doping source layer in the battery precursor into the local area of ​​the lightly doped polysilicon layer; The lightly doped polysilicon layer partially doped with the doping element is annealed in an atmosphere containing the doping element to obtain the doped polysilicon layer.

13. The method for preparing a doped polysilicon layer according to claim 12, characterized in that: During the annealing process, the pressure is from 100 Pa to normal pressure, the annealing temperature is from 500° C. to 900° C., and the annealing time is from 20 min to 90 min.

14. The method for preparing a doped polysilicon layer according to claim 12 or 13, characterized in that: The atmosphere containing the doping element includes: a phosphorus source gas or a boron source gas, the phosphorus source gas includes phosphorus oxychloride, the boron source gas includes boron trichloride and boron tribromide, and the flow rate of the atmosphere containing the doping element is 50 sccm to 200 sccm.

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