Semiconductor chip testing device and testing method

Abstract

The invention provides a semiconductor chip testing device and a testing method. The testing device comprises a platform, a needle seat substrate arranged on the platform and a plurality of probe assemblies, the probe assembly includes a pressure sensor having at least one pressure-sensitive surface, the pressure sensor configured to generate an electrical signal in response to a pressure having a directional component perpendicular to the pressure-sensitive surface; the needle seat substrate is provided with a plurality of needle seats, and each needle seat is electrically connected with one probe assembly; the needle seat is configured to detect an electric signal of the probe assembly electrically connected with the needle seat. According to the testing device, the contact state of each probe and the chip pin can be detected before a plurality of chips are synchronously tested, so that the situation that the test cannot be completed or the test time is greatly prolonged due to the abnormity of uncertain point positions in the synchronous test of the plurality of chips is reduced, and the synchronous test efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field related to testing methods, and in particular to a semiconductor chip testing device and a testing method. Background Art

[0002] CP (Chip Probe) test and FT (Final Test) test are two modules in chip testing. CP test refers to the performance and function test of the chip by piercing the chip pins with probes at the wafer stage. It refers to the final test of the chip after the packaging is completed. Only the chips that pass the test will be shipped. The existing CP test / FT test generally adopts parallel testing (Multi-Site) to improve the test efficiency. For example, FT 64site 128 / 256DUT (device under test) is tested at the same time, and all sites can be tested in parallel. When the tests of all sites are completed, the test of the whole batch of chips is completed normally. The test equipment can classify them according to the functional components, stable clock frequency, required voltage and thermal output of the chip (this sorting procedure is called chip binning) and generate a test log (log).

[0003] However, the existing Multi-Site simultaneous testing has certain limitations. That is, if a test timeout occurs at a certain point and cannot be completed normally, due to the current Multi-Site process mechanism of waiting for each other indefinitely, the tests at other points cannot be completed, resulting in a hangup in the test of the entire batch of 128 / 256 DUT chips. Since the test equipment cannot complete the test normally, if the test equipment is shut down or reset at this time, the current test results of all points will not be available, resulting in delays in test costs and cycle time. The entire batch of chips can only be retested. If the same phenomenon occurs again during the retest, the entire batch of chips will be scrapped because there is only one retest opportunity, resulting in a decrease in the yield rate.

[0004] There are many reasons for the timeout of a certain point test, and weak contact is a common reason. During the test process, for a device-specific adapter substrate with weak contact, when the chip is placed on the device-specific adapter for testing, a simple open / short test will not cause any problems. However, when performing certain functional tests (large current and long time, such as flash programming), poor contact may occur, causing the chip at a certain point to time out due to the lack of signal stimulation or feedback from the test equipment, resulting in the entire batch of chips being unable to end the test normally, and the test equipment being in an idle state.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0006] In view of the problems in the prior art, an object of the present invention is to provide a semiconductor chip testing device and a testing method, which can improve the efficiency of synchronous testing of multiple chips.

[0007] A first aspect of the present invention provides a semiconductor chip testing device, the testing device comprising a platform, a needle seat substrate disposed on the platform, and a plurality of probe assemblies;

[0008] The probe assembly includes a pressure sensor having at least one pressure-sensitive surface, the pressure sensor being configured to generate an electrical signal in response to a pressure having a directional component perpendicular to the pressure-sensitive surface;

[0009] The needle seat substrate is provided with a plurality of needle seats, and each of the needle seats is electrically connected to one of the probe assemblies;

[0010] The needle hub is configured to detect an electrical signal of the probe assembly electrically connected thereto.

[0011] According to the first aspect of the present invention, the probe assembly is a spring-type probe.

[0012] According to a first aspect of the present invention, the probe assembly comprises a needle head, the pressure sensor, a spring and a needle tail which are electrically connected in sequence;

[0013] The needle is used to electrically contact the pins of the chip to be tested;

[0014] The needle tail is electrically connected to the needle seat.

[0015] According to the first aspect of the present invention, the probe assembly further comprises a shaft tube;

[0016] The pressure sensor and the spring are arranged in the shaft tube;

[0017] The needle head and the needle tail respectively penetrate through the two ends of the shaft tube and can move relative to the two ends of the shaft tube respectively.

[0018] According to the first aspect of the present invention, the pressure sensor is a capacitive pressure sensor.

[0019] A second aspect of the present invention provides a semiconductor chip testing method, which is applicable to the semiconductor chip testing device, and the testing method comprises the following steps:

[0020] Placing a wafer to be tested on the semiconductor chip testing device, wherein the wafer includes a plurality of chips to be tested, and each of the probe assemblies corresponds to a pin of the chip;

[0021] Applying pressure to make the probe assembly contact with the pins on the chip;

[0022] Reading the electrical signal of each of the probe assemblies and determining whether the electrical signal of each of the probe assemblies is greater than a first set threshold;

[0023] If the electrical signal of the probe assembly is not greater than the first set threshold, the probe assembly is a first weak contact probe assembly, and the position of the first weak contact probe assembly is obtained;

[0024] Configuring a wafer test program, removing the test of the chips in the area corresponding to the position of the first weak contact probe assembly in the test program;

[0025] Execute the test procedure.

[0026] According to a second aspect of the present invention, if the electrical signal of one of the probe assemblies is greater than a first set threshold, it is determined whether the electrical signal of each of the probe assemblies is greater than a second set threshold, and the second set threshold is greater than the first set threshold;

[0027] If the electrical signal of the probe assembly is not greater than the second set threshold, the probe assembly is a second weak contact probe assembly, and the position of the second weak contact probe assembly is obtained;

[0028] Configuring a wafer test program, configuring the test of the chips in the corresponding area at the position of the second weak contact probe assembly to perform a partial test in the test program;

[0029] Execute the test procedure.

[0030] According to a second aspect of the present invention, the pressure sensor is a capacitive pressure sensor;

[0031] The electrical signal read from each of the probe components is a voltage;

[0032] The first set threshold is 40% of the maximum output voltage of the capacitive pressure sensor.

[0033] According to a second aspect of the present invention, the second set threshold is between 40% and 60% of the maximum output voltage of the capacitive pressure sensor.

[0034] Compared with the prior art, the present invention provides a semiconductor chip testing device and a testing method, wherein the testing device comprises a platform, a needle seat substrate disposed on the platform, and a plurality of probe assemblies; the probe assembly comprises a pressure sensor, the pressure sensor has at least one pressure-sensitive surface, and the pressure sensor is configured to generate an electrical signal in response to a pressure having a directional component perpendicular to the pressure-sensitive surface; the needle seat substrate is provided with a plurality of needle seats, each of which is electrically connected to a probe assembly; the needle seat is configured to detect the electrical signal of the probe assembly electrically connected thereto. The testing device of the present invention can detect the contact state between each probe and the chip pin before the synchronous testing of multiple chips, thereby reducing the situation in which the test cannot be completed or the test time is greatly extended due to the abnormality of the uncertain point position during the synchronous testing of multiple chips, and improving the efficiency of the synchronous testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more apparent. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same figure numbers in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0036] Figure 1 A schematic diagram of the structure of a semiconductor chip testing device according to an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of the structure of a probe assembly according to an embodiment of the present invention; and

[0038] Figure 3 The figure is a flow chart of a semiconductor chip testing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the details in the present invention can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0040] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0041] In the representation of the present invention, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present invention and the features of different embodiments or examples, unless they are contradictory.

[0042] In order to clearly describe the present invention, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0043] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0044] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.

[0045] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0046] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present invention. The singular form used herein also includes the plural form as long as the sentence does not clearly indicate the opposite meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0047] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the content of relevant technical literature and current disclosures, and unless defined, shall not be overly interpreted as ideal or very formal meanings.

[0048] In order to overcome the above technical problems, the present invention provides a semiconductor chip testing device and a testing method, wherein the testing device includes a platform, a needle seat substrate disposed on the platform, and a plurality of probe assemblies; the probe assembly includes a pressure sensor, the pressure sensor has at least one pressure-sensitive surface, and the pressure sensor is configured to generate an electrical signal in response to a pressure having a directional component perpendicular to the pressure-sensitive surface; the needle seat substrate is provided with a plurality of needle seats, each of which is electrically connected to a probe assembly; the needle seat is configured to detect the electrical signal of the probe assembly electrically connected thereto. The testing device of the present invention can detect the contact state between each probe and the chip pin before the synchronous testing of multiple chips, thereby reducing the situation in which the test cannot be completed or the test time is greatly extended due to the abnormality of the uncertain point position during the synchronous testing of multiple chips, and improving the efficiency of the synchronous testing.

[0049] The semiconductor chip testing device and testing method of the present invention are further described below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the various specific embodiments are not intended to limit the protection scope of the present invention.

[0050] Figure 1 This is a schematic diagram of the structure of a semiconductor chip testing device according to an embodiment of the present invention. Specifically, the testing device includes a platform 1, a needle holder substrate 2 disposed on the platform 1, and a plurality of probe assemblies 3. Usually, there are several chips 9 on the wafer to be tested, and a plurality of probe assemblies constitute a probe array. The structure of the probe array usually corresponds to the structure of the chip array on the wafer to be tested. During the test, each probe assembly contacts a pin of the chip. It should be noted that a single chip to be tested includes pins of different numbers and positions due to different structures or functions, and each testing device is suitable for performance testing of wafers including different chips. The multiple probe assemblies provided in the testing device can test multiple chips 9 on the wafer at the same time, which greatly improves the chip testing efficiency and reduces the testing time and cost.

[0051] The probe assembly 3 of the present invention includes a pressure sensor having at least one pressure-sensitive surface, and the pressure sensor is configured to generate an electrical signal in response to a pressure having a directional component perpendicular to the pressure-sensitive surface; the needle seat substrate 2 is provided with a plurality of needle seats, each of which is electrically connected to one of the probe assemblies 3; the needle seat is configured to detect an electrical signal of the probe assembly 3 electrically connected thereto. The needle seat can be regarded as a conductor connecting the probe assembly to a circuit board (PCB) or a wire.

[0052] In some embodiments, the probe assembly 3 may be a spring-type probe. More specifically, Figure 2The schematic diagram of the structure of the probe assembly of an embodiment of the present invention includes a needle head 31, a pressure sensor 32, a spring 33 and a needle tail 34 which are electrically connected in sequence; the needle head 31 is used to electrically contact the pin of the chip to be tested; the needle tail 34 is electrically connected to the needle seat. The spring provides the necessary contact force, and the needle head 31 of the probe assembly is in close contact with the pin to be tested through the elastic force applied by the spring 33, forming a channel for current transmission, ensuring that the electrical signal or current is transmitted from the needle head contact end to the needle tail 34 and the needle seat, and then flows to the circuit board (PCB) or line.

[0053] In the present invention, the pressure sensor 32 is used to detect the contact state between the probe assembly and the pins of the chip to be tested. Preferably, the entire probe assembly is perpendicular to the contact surface. Accordingly, the pressure-sensitive surface of the pressure sensor 32 that senses pressure is perpendicular to the pressure direction, that is, perpendicular to the probe assembly.

[0054] In some other embodiments, the probe assembly further includes a shaft tube 35; the pressure sensor 32 and the spring 33 are disposed in the shaft tube 35; the needle head 31 and the needle tail 34 respectively penetrate the two ends of the shaft tube 35 and can move relative to the two ends of the shaft tube 35. The above structure can ensure that the needle head 31 moves along the direction from the pin to the needle seat. At the same time, the resistance of the entire probe assembly itself needs to be small so that a stable test electrical signal or current can be transmitted.

[0055] The pressure sensor 32 can be a capacitive pressure sensor, such as a pressure capacitor. Usually, due to the difference in pressure (axial load), the voltage generated by the pressure capacitor is between 0 and 30mV, that is, the contact between each probe assembly on the needle seat substrate and the chip pin can be characterized by detecting the voltage value. The pressure of each probe assembly on the needle seat substrate is between 8 and 20g (the industry requires the needle pressure working range). For example, if the pressure of the probe assembly is less than 8g, it is considered that the contact is poor. At this time, the voltage of the piezoelectric capacitor under 8g pressure is about ~8mV, that is, when the chip to be tested is placed in the test device and a certain pressure is applied, only when the voltage of the probe assembly under pressure is detected to be greater than 8mV, the contact is considered to be effective. The voltage of each probe assembly that abuts against multiple pins of the chip to be tested under pressure reaches the threshold, and then it is considered that the chip to be tested can be tested. In addition, the CP test is to test the basic device parameters of each chip (Die) on the whole wafer, including simple open / short tests, such as Vt (threshold voltage), Rdson (on-resistance), BVdss (source-drain breakdown voltage), Igss (gate-source leakage current), Idss (drain-source leakage current), and some functional tests, such as logic function, data processing function, communication function, etc., among which the functional test has higher requirements for contact resistance. The contact between the probe assembly and the chip pin is an effective contact, and there will be no problems in a simple open / short test. However, when performing certain functional tests, problems such as large current and long time will occur, and poor contact may occur. The pressure value corresponding to this interval can be determined based on experience.

[0056] The present invention also provides a semiconductor chip testing method, which is applicable to the semiconductor chip testing device. Figure 3 This is a flow chart of a semiconductor chip testing method according to an embodiment of the present invention. The testing method comprises the following steps:

[0057] Step S100: placing a wafer to be tested on the semiconductor chip testing device, wherein the wafer includes a plurality of chips to be tested, and each of the probe assemblies corresponds to a pin of the chip;

[0058] Step S200: applying pressure to make the probe assembly contact with the pins on the chip;

[0059] Step S300: reading the electrical signal of each of the probe assemblies and determining whether the electrical signal of each of the probe assemblies is greater than a first set threshold;

[0060] Step S400: If the electrical signal of a probe assembly is not greater than the first set threshold, the probe assembly is a first weak contact probe assembly, and the position of the first weak contact probe assembly is obtained; when the pressure sensor is a capacitive pressure sensor, the capacitive pressure sensor is an analog voltage output type. For example, if the output voltage of a capacitive pressure sensor is 0-10mV, that is, the maximum output voltage is 10mV, if its sensitivity is designed to produce a certain voltage change per Newton (such as 0.1V / N), taking 10 grams of pressure (about 0.0981N) as an example, it will produce an output voltage of about 0.0981×0.1=0.00981V, then the output voltage of 10 grams of pressure is 10mV. The electrical signal of each probe assembly is read as a voltage, and the first set threshold can be about 40% of the maximum output voltage, that is, the first set threshold can be set to about 4mV. If the pressure sensor between a probe assembly and a pin is less than or equal to the first set threshold (~4Mv), it is considered that the probe assembly and the pin are not in effective contact (such as Figure 1 The actual first set threshold value can be further determined according to the specific type and specification of the pressure sensor, the specification of the needle card, etc.

[0061] Step S500: configure the wafer test program, remove the test of the chip in the corresponding area of ​​the position of the first weak contact probe assembly in the test program; this step is to remove or shield the problematic points between the pin and the probe assembly in the test program; specifically, in the synchronous test of multiple chips, different test points are numbered, and the corresponding test point numbers are determined according to the position of the first weak contact probe assembly obtained in step S400, and the numbers of these test points are removed in the test program of step S500. Step 500 can be implemented by these C / C++ codes.

[0062] Step S600: executing the test program, that is, supplying power to the chip synchronization test device through the power supply circuit, measuring the required voltage / current of the pin input of each chip according to the nature of the test, and reading the voltage / current output by some pins at the same time.

[0063] In some other embodiments, as shown above, some functional tests have higher requirements for contact status. Therefore, in actual use, some contacts can meet simple test requirements but cannot perform some functional tests. Then, after step S400, the test method further includes:

[0064] If the electrical signal of one of the probe assemblies is greater than the first set threshold, execute S410: determine whether the electrical signal of each of the probe assemblies is greater than a second set threshold, and the second set threshold is greater than the first set threshold; if the electrical signal of one of the probe assemblies is not greater than the second set threshold, the probe assembly is a second weak contact probe assembly, and the position of the second weak contact probe assembly is obtained; the second set threshold can be set according to an empirical value, and the second set threshold can be about 40% to 60% of the maximum output voltage. Still taking the above-mentioned capacitive pressure sensor as an example, the second set threshold can be between 4mV and 6mV. At this time, the contact between the probe assembly and the pin of the chip is defined as weak contact. Similarly, the actual second set threshold can be further determined according to the specific type and specification of the pressure sensor, the specification of the pin card, etc.

[0065] S510: Configure the wafer test program, in which the test of the chips in the corresponding area at the position of the second weak contact probe assembly is configured to perform partial tests; that is, while removing the test of the chips that are not effectively contacted in step S500, some test points are configured to perform only simple tests without performing complex functional tests. Finally, the execution test program of step S600 is performed.

[0066] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

[0067] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A semiconductor chip testing device, characterized in that: The testing device comprises a platform, a needle seat substrate arranged on the platform, and a plurality of probe assemblies; The probe assembly includes a pressure sensor having at least one pressure-sensitive surface, the pressure sensor being configured to generate an electrical signal in response to a pressure having a directional component perpendicular to the pressure-sensitive surface; The needle seat substrate is provided with a plurality of needle seats, and each of the needle seats is electrically connected to one of the probe assemblies; The needle hub is configured to detect an electrical signal of the probe assembly electrically connected thereto.

2. The semiconductor chip testing device according to claim 1, characterized in that: The probe assembly is a spring-type probe.

3. The semiconductor chip testing device according to claim 1, characterized in that: The probe assembly includes a needle head, the pressure sensor, a spring and a needle tail which are electrically connected in sequence; The needle is used to electrically contact the pins of the chip to be tested; The needle tail is electrically connected to the needle seat.

4. The semiconductor chip testing device according to claim 3, characterized in that: The probe assembly also includes an axle tube; The pressure sensor and the spring are arranged in the shaft tube; The needle head and the needle tail respectively penetrate through the two ends of the shaft tube and can move relative to the two ends of the shaft tube respectively.

5. The semiconductor chip testing device according to claim 1, characterized in that: The pressure sensor is a capacitive pressure sensor.

6. A semiconductor chip testing method, characterized in that: Applicable to the semiconductor chip testing device according to any one of claims 1 to 4, the testing method comprising the following steps: Placing a wafer to be tested on the semiconductor chip testing device, wherein the wafer includes a plurality of chips to be tested, and each of the probe assemblies corresponds to a pin of the chip; Applying pressure to make the probe assembly contact with the pins on the chip; Reading the electrical signal of each of the probe assemblies and determining whether the electrical signal of each of the probe assemblies is greater than a first set threshold; If the electrical signal of the probe assembly is not greater than the first set threshold, the probe assembly is a first weak contact probe assembly, and the position of the first weak contact probe assembly is obtained; Configuring a wafer test program, removing the test of the chips in the area corresponding to the position of the first weak contact probe assembly in the test program; Execute the test procedure.

7. The semiconductor chip testing method according to claim 6, characterized in that: If the electrical signal of one of the probe assemblies is greater than a first set threshold, determining whether the electrical signal of each of the probe assemblies is greater than a second set threshold, the second set threshold being greater than the first set threshold; If the electrical signal of the probe assembly is not greater than the second set threshold, the probe assembly is a second weak contact probe assembly, and the position of the second weak contact probe assembly is obtained; Configuring a wafer test program, configuring the test of the chips in the corresponding area at the position of the second weak contact probe assembly to perform a partial test in the test program; Execute the test procedure.

8. The semiconductor chip testing method according to claim 7, characterized in that: The pressure sensor is a capacitive pressure sensor; The electrical signal read from each of the probe components is a voltage; The first set threshold is 40% of the maximum output voltage of the capacitive pressure sensor.

9. The semiconductor chip testing method according to claim 8, characterized in that: The second set threshold is between 40% and 60% of the maximum output voltage of the capacitive pressure sensor.

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