System downtime repair method and device, equipment, medium and program product

Abstract

The invention provides a system crash repair method and device, equipment, a medium and a program product. The method comprises the steps that a system downtime signal is obtained, the system downtime signal is a signal sent by a mainboard management controller to a complex programmable logic device according to a control loss signal, and the control loss signal is a signal sent by a CPU to the mainboard management controller when a voltage value meets a preset critical voltage value; according to the system downtime signal, backup flash memory connection information is obtained; according to the power-on signal, the CPU connection information and the backup flash memory connection information, a resynchronization signal is sent to the voltage regulation bus controller through the CPU, and the resynchronization signal is used for controlling the voltage regulation bus controller to restore to an initial state; and the bus controller is adjusted according to the voltage in the initial state, so that the system recovers the capability of adjusting the voltage. According to the method provided by the invention, the stability and safety of repairing the downtime system are improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a system downtime repair method, device, equipment, medium and program product. Background Art

[0002] With the continuous advancement of Internet technology, various applications and services have become more and more complex, and the degree of dependence on technology has also increased. This complexity is not only reflected in the software architecture, but also involves multiple levels such as hardware, network, and data. Once a problem occurs in a certain link, it may trigger a chain reaction and cause the system to crash. For example, when an abnormality occurs in the line between the CPU (Central Processing Unit) and the power controller, it will cause the CPU to crash. Therefore, how to recover a system in a crashed state is particularly important.

[0003] At present, in the prior art, a common method for handling a system downtime caused by an abnormality in a line between a CPU and a power controller is to manually restart the system in a downtime state.

[0004] However, the existing system downtime repair method has the problem of poor repair effect. Summary of the invention

[0005] The present application provides a system downtime repair method, device, equipment, medium and program product to solve the problem that the existing system downtime repair method has poor repair effect.

[0006] In a first aspect, the present application provides a system downtime repair method, comprising:

[0007] Obtaining a system downtime signal, where the system downtime signal is a signal sent by the mainboard management controller to the complex programmable logic device according to a control loss signal, where the control loss signal is a signal sent by the CPU to the mainboard management controller when the voltage value meets a preset critical voltage value;

[0008] According to the system downtime signal, the backup flash memory connection information is obtained;

[0009] According to the power-on signal, the CPU connection information and the backup flash memory connection information, a resynchronization signal is sent to the voltage regulation bus controller through the CPU, and the resynchronization signal is used to control the voltage regulation bus controller to recover to an initial state;

[0010] The bus controller is adjusted according to the voltage of the initial state, so that the system recovers the ability to regulate the voltage.

[0011] In the embodiment of the present application, before obtaining the system downtime signal, the method further includes:

[0012] Get CPU voltage status information;

[0013] When the CPU voltage status information meets the preset stability rules, a low voltage signal is sent to the main data bus in the voltage regulation bus controller. The low voltage signal is used by the main data bus to send a low voltage main data signal to the power controller. The low voltage main data signal is used by the power controller to send a low voltage slave data signal to the slave data bus in the voltage regulation bus controller. The low voltage slave data signal is used to control the slave data bus to adjust the voltage value of the CPU, so as to obtain the downtime CPU and the system downtime signal of the downtime CPU.

[0014] In an embodiment of the present application, when the CPU voltage state information satisfies a preset stability rule, sending a voltage-lowering signal to a main data bus in a voltage regulation bus controller includes:

[0015] When the voltage level information in the CPU voltage status information is at a high level, high level time information is obtained by timing;

[0016] When the high-level time information meets the preset time information, a first stable voltage signal is obtained;

[0017] According to the first stable voltage signal, a pull-down voltage signal is sent to a main data bus in a voltage regulation bus controller.

[0018] In the embodiment of the present application, after obtaining the first stable voltage signal, the method further includes:

[0019] Obtaining voltage change quantity information according to the first stable voltage signal and the voltage change information in the CPU voltage state information;

[0020] When the voltage change quantity information satisfies the preset change quantity information, a second stable voltage signal is obtained;

[0021] According to the second stable voltage signal, a pull-down voltage signal is sent to a main data bus in a voltage regulation bus controller.

[0022] In the embodiment of the present application, after the system recovers the ability to regulate voltage according to the voltage regulating bus controller in the initial state, the method further includes:

[0023] Get the voltage value of the CPU;

[0024] When the voltage value of the CPU meets the preset stable voltage value, the main flash memory connection information is obtained according to the recovery signal, wherein the recovery signal is a signal sent by the mainboard management controller;

[0025] The system is restored to a normal operating state according to the power-on signal, the CPU connection information and the main flash memory connection information.

[0026] In the embodiment of the present application, the main flash memory connection information is obtained according to the recovery signal, including:

[0027] According to the power-off signal in the recovery signal, converting to the power-off state;

[0028] In the power-off state, the main flash memory connection information is obtained according to the switching signal in the recovery signal.

[0029] In a second aspect, the present application provides a system downtime repair device, comprising:

[0030] An acquisition module, used for acquiring a system downtime signal, wherein the system downtime signal is a signal sent by the mainboard management controller to the complex programmable logic device according to a control loss signal, and the control loss signal is a signal sent by the CPU to the mainboard management controller when the voltage value meets a preset critical voltage value;

[0031] The obtaining module is used to obtain the backup flash memory connection information according to the system downtime signal;

[0032] A sending module, used for sending a resynchronization signal to the voltage regulation bus controller through the CPU according to the power-on signal, the CPU connection information and the backup flash memory connection information, wherein the resynchronization signal is used for controlling the voltage regulation bus controller to recover to an initial state;

[0033] The recovery module is used to adjust the bus controller according to the voltage of the initial state so that the system can recover the ability to adjust the voltage.

[0034] In a third aspect, the present application provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor;

[0035] Memory stores computer-executable instructions;

[0036] The processor executes the computer execution instructions stored in the memory to implement the system downtime repair method of the embodiment of the present application.

[0037] In a fourth aspect, a computer-readable storage medium stores computer execution instructions, which, when executed by a processor, are used to implement the system downtime repair method of an embodiment of the present application.

[0038] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the above first aspect and / or various possible implementation methods of the first aspect.

[0039] The system downtime repair method, apparatus, equipment, medium and program product provided by the present application obtain a system downtime signal, which is a signal sent by the mainboard management controller to the complex programmable logic device according to a control loss signal, and the control loss signal is a signal sent by the CPU to the mainboard management controller when the voltage value meets the preset critical voltage value; according to the system downtime signal, the backup flash memory connection information is obtained; according to the power-on signal, the CPU connection information and the backup flash memory connection information, the resynchronization signal is sent to the voltage regulation bus controller through the CPU, and the resynchronization signal is used to control the voltage regulation bus controller to return to the initial state; according to the voltage regulation bus controller in the initial state, the means for restoring the system's ability to regulate voltage is used, so that after the system downtime, the CPU reads the resynchronization signal in the backup flash memory through the complex programmable logic device, and the CPU then sends the resynchronization signal to the voltage regulation bus controller to restore it to the initial state, thereby achieving the effect of safely and stably repairing the downtime system. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0041] Figure 1 A flowchart of a method for repairing a system downtime provided in an embodiment of the present application;

[0042] Figure 2 A flowchart of another method for repairing a system downtime provided in an embodiment of the present application;

[0043] Figure 3 A schematic diagram of the structure of a system downtime repair device provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0045] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0046] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0047] First, the terms involved in this application are explained:

[0048] Baseboard Management Controller: BMC, short for Baseboard Management Controller, is a dedicated microcontroller that is independent of the server operating system and main processor and can be built into the motherboard of servers, network equipment, and other complex electronic systems.

[0049] CPU: refers to the central processing unit, the core hardware component of the computer, and also the computing core and control core of the computer;

[0050] Complex Programmable Logic Device: CPLD (Complex Programmable Logic Device) is a high-performance programmable logic device and a type of programmable logic device.

[0051] In the prior art, manually restarting a system in a downtime state may cause further failures or data corruption due to improper operation or misjudgment.

[0052] The system downtime repair method, device, equipment, medium and program product provided in the present application solve the technical problem of unsafe and unstable manual restart of a downtime system by using a complex programmable logic device to enable the CPU to read a resynchronization signal in a backup flash memory after receiving a system downtime signal, and the CPU then sends the resynchronization signal to the voltage regulation bus controller to restore it to its initial state.

[0053] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0054] Figure 1 The flowchart of the system downtime repair method provided in the embodiment of the present application is shown in FIG. The execution subject of the present method can be a server or other servers, and this embodiment is not particularly limited here. Figure 1 As shown, the method may include:

[0055] S101. Obtain a system downtime signal, where the system downtime signal is a signal sent by a mainboard management controller to a complex programmable logic device according to a control loss signal, and the control loss signal is a signal sent by a CPU to a mainboard management controller when a voltage value meets a preset critical voltage value.

[0056] Among them, the system downtime signal may refer to a signal used to notify a complex programmable logic device that the system has crashed and that a corresponding operation needs to be performed. In an embodiment of the present application, the corresponding operation may refer to disconnecting the complex programmable logic device from the main flash memory and establishing a connection with the backup flash memory.

[0057] The baseboard management controller can refer to BMC (Baseboard Management Controller), which is usually used for remote management of servers. It can monitor various hardware status of the server, such as temperature, voltage, fan speed, etc., and take corresponding measures when abnormalities are found.

[0058] The control loss signal may refer to a signal sent by the CPU to the motherboard management controller indicating that the system has lost control. The judgment criterion for loss of control may be that the voltage value of the CPU satisfies a preset critical voltage value. In an embodiment of the present application, the preset critical voltage value may be 0, that is, when the voltage value of the CPU is 0, a control loss signal is sent to the motherboard management controller.

[0059] In the embodiment of the present application, before obtaining the system downtime signal, the method may further include:

[0060] Get CPU voltage status information;

[0061] When the CPU voltage status information meets the preset stability rules, a low voltage signal is sent to the main data bus in the voltage regulation bus controller. The low voltage signal is used by the main data bus to send a low voltage main data signal to the power controller. The low voltage main data signal is used by the power controller to send a low voltage slave data signal to the slave data bus in the voltage regulation bus controller. The low voltage slave data signal is used to control the slave data bus to adjust the voltage value of the CPU, so as to obtain the downtime CPU and the system downtime signal of the downtime CPU.

[0062] Among them, the CPU voltage status information may refer to the voltage-related status information of the CPU running in the current working state, such as the real-time voltage value, voltage deviation value and voltage change rate, etc. In the embodiment of the present application, it may include voltage level information and voltage change information. The voltage level information can be divided into high level and low level, and the distinction standard can be set by the user according to the actual situation. The voltage change information may refer to the information of voltage fluctuations, which can be obtained by sampling the falling edge or rising edge of the clock signal used by the CPU to send a synchronization signal to the power controller.

[0063] The stability rule may refer to a rule for determining whether the current voltage is in a stable state, and may include a sensitivity index, a singular value and an eigenvalue index, and the like.

[0064] The voltage regulation bus controller may refer to a controller used to control the bus connecting the CPU and the power controller, and may include a master data bus and a slave data bus. The master data bus is used for the CPU to send signals to the power controller, and the slave data bus is used for the power controller to send signals to the CPU.

[0065] A method for a complex programmable logic device to send a low-voltage signal to a main data bus in a voltage regulation bus controller may include the complex programmable logic device outputting a signal PULL_LOW_MDATA=0 to the main data bus through a signal line, so that the main data bus is continuously pulled down until it is pulled down to 0, and the main data bus sends a low-voltage main data signal to the power controller, representing the voltage signal on the main data bus after being pulled down.

[0066] After receiving the low-voltage main data signal, the power controller adjusts the voltage according to the low-voltage main data signal, and sends the low-voltage slave data signal representing the voltage adjustment result to the CPU through the slave data bus to adjust the voltage value of the CPU. Since the voltage is lowered at this time, the CPU cannot obtain enough energy to execute its internal logic and computing tasks, which will cause the CPU to fail to work normally, and then cause the system to crash or shut down, thereby resulting in a shut-down CPU.

[0067] Among them, in the embodiment of the present application, when the CPU voltage state information satisfies the preset stability rule, sending a voltage-lowering signal to the main data bus in the voltage regulation bus controller, the method may include:

[0068] When the voltage level information in the CPU voltage status information is at a high level, high level time information is obtained by timing;

[0069] When the high-level time information meets the preset time information, a first stable voltage signal is obtained;

[0070] According to the first stable voltage signal, a pull-down voltage signal is sent to a main data bus in a voltage regulation bus controller.

[0071] Among them, the method for obtaining high-level time information may include determining whether the voltage level information is a high level. If it is not a high level, continue to obtain new voltage level information until it is a high level, then the timer in the complex programmable logic device starts timing to obtain high-level time information; when the high-level time information meets the preset time information, for example, it reaches 200 seconds, it means that the voltage has been initially stabilized, and the first stable voltage signal is obtained.

[0072] In the embodiment of the present application, after obtaining the first stable voltage signal, the method may further include:

[0073] Obtaining voltage change quantity information according to the first stable voltage signal and the voltage change information in the CPU voltage state information;

[0074] When the voltage change quantity information satisfies the preset change quantity information, a second stable voltage signal is obtained;

[0075] According to the second stable voltage signal, a pull-down voltage signal is sent to a main data bus in a voltage regulation bus controller.

[0076] Among them, after the voltage is initially stabilized, the stability of the voltage can be further determined. Whenever the voltage changes from high to low or from low to high, the voltage change information is obtained. The number of changes is recorded by a counter to obtain the voltage change quantity information. When the voltage change quantity information meets the preset change quantity information, for example 9 times, it means that the voltage has been further stabilized, and a second stable signal is obtained, and subsequent operations can be performed on this basis.

[0077] In an embodiment of the present application, after the voltage stabilizes, according to user needs, the voltage value can be lowered through a complex programmable logic device to trigger an abnormal phenomenon, causing the CPU to crash, so as to test a method for repairing a crashed system. This method of creating a crashed CPU can accurately control the voltage reduction range and timing, making the test environment closer to the actual application scenario, thereby simulating a specific type of crash. At the same time, compared with other crash triggering methods that may directly damage hardware, the method of lowering the voltage value, when properly controlled, causes less damage to the CPU, helps protect test equipment, and reduces testing costs.

[0078] S102: Obtain backup flash memory connection information according to the system downtime signal.

[0079] The method for obtaining the backup flash memory connection information may be to first disconnect the connection with the main flash memory and then establish the connection with the backup flash memory.

[0080] The primary flash memory may refer to the area primarily responsible for storage, used to store firmware code and settings, and the backup flash memory may refer to an additional storage area used to provide a recovery option in case of problems with the primary flash memory.

[0081] The backup flash memory connection information may refer to information about a connection relationship between a complex programmable logic device and the backup flash memory.

[0082] S103, sending a resynchronization signal to the voltage regulation bus controller through the CPU according to the power-on signal, the CPU connection information and the backup flash memory connection information, wherein the resynchronization signal is used to control the voltage regulation bus controller to recover to an initial state.

[0083] The power-on signal may refer to a signal for powering on that is sent from a motherboard management controller to a complex programmable logic device.

[0084] The CPU connection information may refer to a connection relationship between the CPU and a complex programmable logic device.

[0085] The resynchronization signal may refer to a synchronization signal sent by a BIOS (Basic Input Output System) with a resynchronization function in the backup flash memory.

[0086] The method for sending a resynchronization signal to a voltage regulation bus controller through a CPU may include enabling the CPU to establish a connection with a backup flash memory through a complex programmable logic device according to CPU connection information and backup flash memory connection information; after the connection is established, the complex programmable logic device is powered on according to a power-on signal sent by a motherboard management controller; and the CPU and the backup flash memory are then powered on through the CPU connection information and the backup flash memory connection information; a connection circuit through which current flows is formed between the CPU, the complex programmable logic device and the backup flash memory; thereby, the backup flash memory sends the resynchronization signal to the complex programmable logic device through the backup flash memory connection information, the complex programmable logic device sends the resynchronization signal to the CPU through the CPU connection information, and the CPU then sends the resynchronization signal to the voltage regulation bus controller.

[0087] The method for restoring the voltage regulation bus controller to the initial state may refer to the CPU sending a resynchronization signal to the main data bus, so that the main data bus clears the previous signal and restores to the initial state, thereby obtaining an initial state voltage regulation bus controller. The initial state may refer to the factory default setting or preset initial state.

[0088] S104: Adjust the bus controller according to the voltage in the initial state, so that the system can recover the ability to adjust the voltage.

[0089] Among them, according to the voltage regulation bus controller in the initial state, the CPU can normally send a voltage regulation signal to the power controller, and then the power controller adjusts the voltage and sends the voltage adjustment result back to the CPU, so that the system can restore the ability to regulate voltage.

[0090] In the embodiment of the present application, after the system recovers the ability to regulate voltage according to the voltage regulating bus controller in the initial state, the method may further include:

[0091] Get the voltage value of the CPU;

[0092] When the voltage value of the CPU meets the preset stable voltage value, the main flash memory connection information is obtained according to the recovery signal, wherein the recovery signal is a signal sent by the mainboard management controller;

[0093] The system is restored to a normal operating state according to the power-on signal, the CPU connection information and the main flash memory connection information.

[0094] The stable voltage value may refer to a stable voltage value after the CPU is successfully powered on. When the voltage value of the CPU meets the preset stable voltage value, it indicates that the system has recovered the ability to regulate the voltage.

[0095] The recovery signal may refer to a signal sent by the mainboard management controller to the complex programmable logic device to restore the internal connection mode of the system after the downed system returns to normal. In the embodiment of the present application, the recovery signal may include a power-off signal and a switching signal.

[0096] The main flash memory connection information may refer to connection information between the complex programmable logic device and the main flash memory.

[0097] The method for restoring the system to a normal operating state may include enabling the CPU to establish a connection with the main flash memory through a complex programmable logic device according to CPU connection information and main flash memory connection information; after the connection is established, the complex programmable logic device is powered on again according to a power-on signal sent by a motherboard management controller; and the CPU and the main flash memory are powered on through the CPU connection information and the main flash memory connection information, so that a connection circuit through which current flows is formed between the CPU, the complex programmable logic device and the main flash memory.

[0098] In the embodiment of the present application, the method for obtaining the main flash memory connection information according to the recovery signal may include:

[0099] According to the power-off signal in the recovery signal, converting to the power-off state;

[0100] In the power-off state, the main flash memory connection information is obtained according to the switching signal in the recovery signal.

[0101] The power-off signal may refer to a signal that causes no current to flow through the complex programmable logic device.

[0102] The switching signal may refer to a signal that disconnects the complex programmable logic device from the backup flash memory and establishes a connection between the complex programmable logic device and the main flash memory.

[0103] In this way, the CPU can be restored from the backup flash memory to the main flash memory through the flash memory connected to the complex programmable logic device. When switching the flash memory, you can switch the connection first and then power off, or you can power off first and then switch the link, and then power on again after completion. The main flash memory can be read during the power-on process.

[0104] The system downtime repair method provided in the embodiment of the present application can, after receiving the system downtime signal, enable the CPU to read the resynchronization signal in the backup flash memory through a complex programmable logic device, and the CPU then sends the resynchronization signal to the voltage regulation bus controller to restore it to its initial state. This technical means solves the technical problem of manual restart of the downtime system being unsafe and unstable.

[0105] Figure 2 A flowchart of another method for repairing a system downtime provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the method includes:

[0106] The CPU is used to send a control loss signal CONTROL_LOSS to the BMC (Baseboard Management Controller) when the voltage value is 0; connect to the CPLD (Complex Programmable logic device) through the SPI (serial peripheral interface), and the CPLD is connected to the backup flash memory through the SPI to read the BIOS with a resynchronization function in the backup flash memory; send a resynchronization instruction to the AVSBUS controller in the VR to restore the AVSBUS bus.

[0107] BMC is used to receive the control loss signal sent by the CPU and send the BIOS SEL (System Event Log) signal to the CPLD; send a power-on command to the CPLD through the IIC (Inter-Integrated Circuit); obtain the voltage value of the CPU, and when the voltage value of the CPU is normal, send a switching signal and a power-off command to the CPLD; after the CPLD completes the switching signal and power-off, send a power-on command to the CPLD.

[0108] The CPLD is used to receive the BIOS SEL signal sent by the BMC, thereby disconnecting the SPI connected to the main flash memory and connecting to the backup flash memory through the SPI; receive the power-on instruction sent by the BMC, and power on according to the power-on instruction; receive the resynchronization instruction in the backup flash memory and send it to the CPU; receive the switching signal and power-off instruction sent by the BMC, thereby disconnecting the SPI connected to the backup flash memory, connecting to the main flash memory through the SPI, and powering off at the same time; receive the re-power-on instruction sent by the BMC, and re-power on.

[0109] VR is used to receive a resynchronization instruction sent by the CPU and resynchronize the AVS BUS controller according to the resynchronization instruction.

[0110] Another system crash repair method provided by an embodiment of the present application can add a backup flash memory to the hardware design, so that the CPLD can switch the SPI link and allow the CPU to read the resynchronization instructions in the backup flash memory. After the synchronization is completed, the CPLD can also switch the SPI link to allow the CPU to restore the connection with the main flash memory, so as to achieve the effect of self-recovery of the crashed system.

[0111] Figure 3 This is a schematic diagram of the structure of the system downtime repair device provided in the embodiment of the present application. Figure 3 As shown, the system downtime repair device 30 includes: an acquisition module 301, a obtaining module 302, a sending module 303, and a recovery module 304. Among them:

[0112] An acquisition module 301 is used to acquire a system downtime signal, where the system downtime signal is a signal sent by the mainboard management controller to the complex programmable logic device according to a control loss signal, where the control loss signal is a signal sent by the CPU to the mainboard management controller when the voltage value meets a preset critical voltage value;

[0113] Obtaining module 302, for obtaining backup flash memory connection information according to the system downtime signal;

[0114] The sending module 303 is used to send a resynchronization signal to the voltage regulation bus controller through the CPU according to the power-on signal, the CPU connection information and the backup flash memory connection information, and the resynchronization signal is used to control the voltage regulation bus controller to recover to an initial state;

[0115] The recovery module 304 is used to adjust the bus controller according to the voltage in the initial state so that the system can recover the ability to adjust the voltage.

[0116] In the embodiment of the present application, the acquisition module 301 may also be used for:

[0117] Get CPU voltage status information;

[0118] When the CPU voltage status information meets the preset stability rules, a low voltage signal is sent to the main data bus in the voltage regulation bus controller. The low voltage signal is used by the main data bus to send a low voltage main data signal to the power controller. The low voltage main data signal is used by the power controller to send a low voltage slave data signal to the slave data bus in the voltage regulation bus controller. The low voltage slave data signal is used to control the slave data bus to adjust the voltage value of the CPU, so as to obtain the downtime CPU and the system downtime signal of the downtime CPU.

[0119] In the embodiment of the present application, the acquisition module 301 may also be used for:

[0120] When the voltage level information in the CPU voltage status information is at a high level, high level time information is obtained by timing;

[0121] When the high-level time information meets the preset time information, a first stable voltage signal is obtained;

[0122] According to the first stable voltage signal, a pull-down voltage signal is sent to a main data bus in a voltage regulation bus controller.

[0123] In the embodiment of the present application, the acquisition module 301 may also be used for:

[0124] Obtaining voltage change quantity information according to the first stable voltage signal and the voltage change information in the CPU voltage state information;

[0125] When the voltage change quantity information satisfies the preset change quantity information, a second stable voltage signal is obtained;

[0126] According to the second stable voltage signal, a pull-down voltage signal is sent to a main data bus in a voltage regulation bus controller.

[0127] In the embodiment of the present application, the recovery module 304 may also be used to:

[0128] Get the voltage value of the CPU;

[0129] When the voltage value of the CPU meets the preset stable voltage value, the main flash memory connection information is obtained according to the recovery signal, wherein the recovery signal is a signal sent by the mainboard management controller;

[0130] The system is restored to a normal operating state according to the power-on signal, the CPU connection information and the main flash memory connection information.

[0131] In the embodiment of the present application, the recovery module 304 may also be used to:

[0132] According to the power-off signal in the recovery signal, converting to the power-off state;

[0133] In the power-off state, the main flash memory connection information is obtained according to the switching signal in the recovery signal.

[0134] As can be seen from the above, the system downtime repair device of the embodiment of the present application is composed of an acquisition module 301, which is used to acquire a system downtime signal, the system downtime signal is a signal sent by the mainboard management controller to the complex programmable logic device according to the control loss signal, and the control loss signal is a signal sent by the CPU to the mainboard management controller when the voltage value meets the preset critical voltage value; an acquisition module 302, which is used to obtain the backup flash memory connection information according to the system downtime signal; a sending module 303, which is used to send a resynchronization signal to the voltage regulation bus controller through the CPU according to the power-on signal, the CPU connection information and the backup flash memory connection information, and the resynchronization signal is used to control the voltage regulation bus controller to restore to the initial state; a recovery module 304, which is used to restore the system's ability to regulate voltage according to the voltage regulation bus controller in the initial state. Therefore, the embodiment of the present application can, after receiving the system downtime signal, enable the CPU to read the resynchronization signal in the backup flash memory through the complex programmable logic device, and the CPU then sends the resynchronization signal to the voltage regulation bus controller to restore it to the initial state, solving the technical problem of manual restart of the downtime system being unsafe and unstable.

[0135] Figure 4 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 4 As shown, the electronic device 40 provided in this embodiment includes: at least one processor 401 and a memory 402. Optionally, the device 40 also includes a communication component 403. The processor 401, the memory 402 and the communication component 403 are connected via a bus 404.

[0136] In a specific implementation process, at least one processor 401 executes the computer-executable instructions stored in the memory 402, so that at least one processor 401 executes the above method.

[0137] The specific implementation process of the processor 401 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0138] In the above embodiments, it should be understood that the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the invention can be directly implemented as a hardware processor, or can be implemented by a combination of hardware and software modules in the processor.

[0139] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk storage.

[0140] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0141] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0142] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0143] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0144] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0145] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0146] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0147] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0148] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0149] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0150] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A method for repairing system downtime, It is characterized in that Applied to a complex programmable logic device, the method comprises: Acquire a system downtime signal, wherein the system downtime signal is a signal sent by a mainboard management controller to the complex programmable logic device according to a control loss signal, wherein the control loss signal is a signal sent by a CPU to the mainboard management controller when a voltage value meets a preset critical voltage value; Obtaining backup flash memory connection information according to the system downtime signal; According to the power-on signal, the CPU connection information and the backup flash memory connection information, a resynchronization signal is sent to the voltage regulation bus controller through the CPU, wherein the resynchronization signal is used to control the voltage regulation bus controller to return to an initial state; The bus controller is adjusted according to the voltage of the initial state, so that the system recovers the ability to regulate the voltage.

2. The method according to claim 1, It is characterized in that Before obtaining the system downtime signal, the method further includes: Obtaining the CPU voltage status information; When the CPU voltage status information meets the preset stability rule, a low voltage signal is sent to the main data bus in the voltage regulation bus controller. The low voltage signal is used for the main data bus to send a low voltage main data signal to the power controller. The low voltage main data signal is used for the power controller to send a low voltage slave data signal to the slave data bus in the voltage regulation bus controller. The low voltage slave data signal is used to control the slave data bus to adjust the voltage value of the CPU, so as to obtain a down CPU and a system down signal of the down CPU.

3. The method according to claim 2, It is characterized in that When the CPU voltage status information satisfies a preset stability rule, sending a voltage-lowering signal to a main data bus in the voltage regulation bus controller comprises: When the voltage level information in the CPU voltage state information is at a high level, obtaining high level time information by timing; When the high-level time information meets the preset time information, a first stable voltage signal is obtained; The pull-down voltage signal is sent to a main data bus in the voltage regulation bus controller according to the first stable voltage signal.

4. The method according to claim 3, It is characterized in that After obtaining the first stable voltage signal, the method further includes: Obtaining voltage change quantity information according to the first stable voltage signal and the voltage change information in the CPU voltage state information; When the voltage change quantity information satisfies the preset change quantity information, a second stable voltage signal is obtained; The pull-down voltage signal is sent to a main data bus in the voltage regulation bus controller according to the second stable voltage signal.

5. The method according to claim 1, It is characterized in that After the bus controller is adjusted according to the voltage in the initial state to restore the system's ability to adjust the voltage, the method further includes: Obtaining a voltage value of the CPU; When the voltage value of the CPU meets the preset stable voltage value, the main flash memory connection information is obtained according to the recovery signal, wherein the recovery signal is a signal sent by the motherboard management controller; The system is restored to a normal operating state according to the power-on signal, the CPU connection information and the main flash memory connection information.

6. The method according to claim 5, It is characterized in that The method of obtaining the main flash memory connection information according to the recovery signal includes: Converting to a power-off state according to a power-off signal in the recovery signal; In a power-off state, the main flash memory connection information is obtained according to the switching signal in the recovery signal.

7. A system downtime repair device, It is characterized in that include: an acquisition module, used for acquiring a system downtime signal, wherein the system downtime signal is a signal sent by the mainboard management controller to the complex programmable logic device according to a control loss signal, wherein the control loss signal is a signal sent by the CPU to the mainboard management controller when the voltage value meets a preset critical voltage value; An obtaining module, used for obtaining backup flash memory connection information according to the system downtime signal; a sending module, configured to send a resynchronization signal to a voltage regulation bus controller through the CPU according to a power-on signal, CPU connection information and the backup flash memory connection information, wherein the resynchronization signal is used to control the voltage regulation bus controller to return to an initial state; The recovery module is used to adjust the bus controller according to the voltage of the initial state so that the system can recover the ability to adjust the voltage.

8. An electronic device, It is characterized in that include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 6 when executed by a processor.

10. A computer program product, It is characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 6 when being executed by a processor.

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