A power device driving circuit, a control method and a power device driving unit

Abstract

A power device driving circuit, a control method and a power device driving unit provided by an embodiment of the present application can take into account the requirements of the power device driving circuit for low conduction loss and low switching loss, improve the switching quality of the power device driving circuit, and further improve the practicability of the power device driving circuit. The power device driving circuit includes: a first half-bridge circuit including two first switching circuits connected in series, the first switching circuit including a first transistor; a second half-bridge circuit including two second switching circuits connected in series, the second switching circuit including a second transistor, the first half-bridge circuit and the second half-bridge circuit being connected to the same DC bus, wherein the parasitic capacitance of the second transistor is less than the parasitic capacitance of the first transistor; a first inductor, one end of the first inductor being connected between the two first transistors of the first half-bridge circuit, and the other end of the first inductor being connected between the two second transistors of the second half-bridge circuit.

Description

Technical Field

[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a power device drive circuit, a control method, and a power device drive unit. Background Art

[0002] Power semiconductor devices are semiconductor devices that can perform power processing and have the ability to handle high voltages and large currents. With the wide application of power semiconductor devices, the requirements for the on-state performance such as the switching speed and switching loss of power semiconductor devices are gradually increasing.

[0003] Due to the minority carrier modulation effect, silicon-based semiconductor devices, especially IGBT devices (Insulate-Gate Bipolar Transistor), can conduct higher currents with lower on-state losses, but the switching losses of silicon-based semiconductor devices are relatively high. Therefore, in the power device drive circuit formed by silicon-based semiconductor devices, it is difficult to better meet the requirements of low on-state loss and low switching loss, which will affect the switching quality of the power device drive circuit and further affect the practicality of the power device drive circuit. Summary of the Invention

[0004] A power device drive circuit, a control method, and a power device drive unit provided by an embodiment of the present application can take into account the requirements of the power device drive circuit for low on-state loss and low switching loss, improve the switching quality of the power device drive circuit, and further improve the practicality of the power device drive circuit.

[0005] In a first aspect of an embodiment of the present application, a power device drive circuit is provided, including:

[0006] A first half-bridge circuit, including two first switching circuits connected in series, and the first switching circuit includes a first transistor;

[0007] A second half-bridge circuit, including two second switching circuits connected in series, the second switching circuit does not include a second transistor, and the first half-bridge circuit and the second half-bridge circuit are connected to the same DC bus, wherein the parasitic capacitance of the second transistor is less than the parasitic capacitance of the first transistor;

[0008] A first inductor, one end of the first inductor is connected between the two first transistors of the first half-bridge circuit, and the other end of the first inductor is connected between the two second transistors of the second half-bridge circuit.

[0009] In some embodiments, the first transistor includes a silicon transistor; and / or,

[0010] The second transistor includes a wide bandgap semiconductor transistor.

[0011] In some embodiments, the first switching circuit further includes a first unidirectional conduction unit, which is connected in parallel with the first transistor, and the conduction direction of the first unidirectional conduction unit is opposite to that of the first transistor;

[0012] The second switching circuit further includes a second unidirectional conduction unit, which is connected in parallel with the second transistor, and the conduction direction of the second unidirectional conduction unit is opposite to that of the second transistor.

[0013] In some embodiments, the power device driving circuit further includes:

[0014] A second inductor, one end of which is connected between the two first transistors of the first half-bridge circuit.

[0015] In a second aspect of the embodiments of the present application, a control method for a power device driving circuit is provided, which is used to control the power device driving circuit according to any one of the first aspects above. The control method includes:

[0016] Obtain a conduction signal of a target transistor, and detect a first drain-source voltage of the target transistor. The conduction signal is used to control the conduction of the target transistor, and the target transistor is the first transistor;

[0017] When the first drain-source voltage is greater than a preset reference voltage, control a second transistor on the same side as the target transistor to conduct;

[0018] Dynamically detect a second drain-source voltage of the target transistor until the second drain-source voltage is less than or equal to the preset reference voltage, and then control the target transistor to conduct.

[0019] In some embodiments, the control method of the power device driving circuit further includes:

[0020] When the first drain-source voltage is equal to the preset reference voltage, control the target transistor to conduct and control a second transistor on the same side as the target transistor to turn off.

[0021] In some embodiments, the control method of the power device driving circuit further includes:

[0022] Within a preset time after the target transistor conducts, control a second transistor on the same side as the target transistor to turn off.

[0023] In a third aspect of the embodiments of the present application, a power device driving unit is provided, which is used to implement the control method of the power device driving circuit according to any one of the second aspects above. The power device driving unit includes:

[0024] A clamping unit, the input end of the clamping unit is electrically connected to the source and drain of the first transistor of the power device driving circuit, and the clamping unit is used to obtain the drain-source voltage of the first transistor;

[0025] A control unit, the clamping signal input end of the control unit is electrically connected to the output end of the clamping unit, the conduction signal input end of the control unit is used to obtain the conduction signal of the first transistor, and the output end of the control unit is connected to the gate of the first transistor and the gate of the second transistor of the power device driving circuit. The control unit is used to control the on and off of the first transistor and the second transistor according to the magnitude relationship between the drain-source voltage of the first transistor and a preset reference voltage and the conduction signal.

[0026] In some embodiments, the control unit includes a comparison circuit, a first AND gate circuit, and a second AND gate circuit;

[0027] Among them, the comparison circuit includes a first input end, a second input end, a non-inverting output end, and an inverting output end. The first input end is electrically connected to the output end of the clamping unit, the second input end is used to connect to the preset reference voltage, and the comparison circuit is used to generate a first control signal and a second control signal according to the magnitude relationship between the drain-source voltage of the first transistor and the preset reference voltage. The inverting output end is electrically connected to the first input end of the first AND gate circuit to output the first control signal, and the non-inverting output end is electrically connected to the first input end of the second AND gate circuit to output the second control signal. The first control signal and the second control signal are complementary level signals;

[0028] The second input end of the first AND gate circuit is electrically connected to the conduction signal input end of the control unit, and the output end of the first AND gate circuit is electrically connected to the gate of the first transistor. The first AND gate circuit is used to generate a first gate driving signal according to the first control signal and the conduction signal to drive the conduction or turn-off of the first transistor;

[0029] The second input end of the second AND gate circuit is electrically connected to the conduction signal input end of the control unit, and the output end of the second AND gate circuit is electrically connected to the gate of the second transistor. The second AND gate circuit is used to generate a second gate driving signal according to the second control signal and the conduction signal to drive the conduction or turn-off of the second transistor.

[0030] In some embodiments, the control unit further includes a delay circuit, which is configured to control the transistor connected in parallel with the target transistor to turn off within a preset time after the target transistor is turned on. The delay circuit is electrically connected between the positive-phase output port and the first input terminal of the second AND gate circuit. The delay circuit includes a resistor and a capacitor. One end of the capacitor is grounded, and the other end of the capacitor is connected between the resistor and the first input terminal of the second AND gate circuit. One end of the resistor is electrically connected to the positive-phase output port, and the other end of the resistor is electrically connected to the capacitor.

[0031] The embodiments of the present application provide a power device drive circuit, a control method, and a power device drive unit. By forming a first half-bridge circuit with a first transistor having a large parasitic capacitance and a second half-bridge circuit with a second transistor having a small parasitic capacitance, and connecting the first half-bridge circuit and the second half-bridge circuit through a first inductor, the second transistor can assist the conduction of the first transistor, so that the first transistor with a large parasitic capacitance can achieve zero-voltage conduction, thereby reducing the switching loss of the first transistor. At the same time, the conduction performance of the first transistor can be retained, and thus the requirements of the power device drive circuit for low conduction loss and low switching loss can be taken into account, the switching quality of the power device drive circuit can be improved, and the practicability of the power device drive circuit can be enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for describing the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can be obtained based on these drawings.

[0033] Figure 1 It is a schematic diagram of a power device drive circuit provided by an embodiment of the present application;

[0034] Figure 2 It is a schematic flowchart of a control method for a power device drive circuit provided by an embodiment of the present application;

[0035] Figure 3 It is a schematic timing diagram of a control method for a power device drive circuit provided by an embodiment of the present application;

[0036] Figure 4 It is a schematic curve diagram of the conduction efficiency of the target transistor and the input power of a control method for a power device drive circuit provided by an embodiment of the present application;

[0037] Figure 5Schematic structural diagram of a power device driving unit provided by an embodiment of the present application;

[0038] Figure 6 Schematic circuit diagram of a control unit of a power device driving unit provided by an embodiment of the present application. Detailed implementation manners

[0039] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0041] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" or "having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0042] It should be noted that current power device certification experiments focus on environmental tests and experimental conditions of single electrical stress. The relevant tests can only test the reliability of power devices under a certain single stress, and usually only one test corresponds to one stress. Therefore, when performing other types of electrical stress tests, it is necessary to replace the test equipment, resulting in increased test difficulty, cumbersome test steps and low test efficiency. Therefore, it is crucial to invent a power device test circuit that can be used for various types of tests of power devices.

[0043] It should be noted that due to the minority carrier modulation effect, silicon-based semiconductor devices, especially IGBT devices, can conduct higher currents with lower conduction losses. However, on the other hand, the performance of silicon-based semiconductor devices in terms of switching speed and switching loss is poor. Wide bandgap power semiconductor devices represented by silicon carbide devices and gallium nitride devices are superior to silicon-based semiconductor devices in terms of low switching loss and high switching speed.

[0044] Therefore, it is an urgent problem to be solved at present to propose a power device drive circuit with high-quality switching performance and conduction performance.

[0045] As Figure 1 shown, in the first aspect of the embodiment of the present application, a power device drive circuit is provided, including: a first terminal V1, a second terminal V2, a first half-bridge circuit, a second half-bridge circuit, and a first inductor L. Among them, the first half-bridge circuit includes two first switching circuits connected in series, and the first switching circuit includes a first transistor; the second half-bridge circuit includes two second switching circuits connected in series, and the second switching circuit includes a second transistor. The first half-bridge circuit and the second half-bridge circuit are connected to the same DC bus. Among them, the parasitic capacitance of the second transistor is smaller than that of the first transistor; one end of the first inductor L is connected between the two first transistors of the first half-bridge circuit, and the other end of the first inductor Lr is connected between the two second transistors of the second half-bridge circuit. Among them, the first transistor includes a first transistor Sm1 in the upper half-bridge and a first transistor Sm2 in the lower half-bridge, and the second transistor includes a second transistor Sa2 in the upper half-bridge and a second transistor Sa1 in the lower half-bridge.

[0046] It should be noted that the first transistor with a higher parasitic capacitance has a larger resistance during the switching process. Therefore, the loss generated by the first transistor during the switching process is relatively large. Similarly, the second transistor with a lower parasitic capacitance generates less loss during the switching process. The second transistor can assist the first transistor in conduction to reduce the switching loss of the first transistor. For the first transistor, due to the large output parasitic capacitance of the first transistor and the tail current generated during the turn-off process, the switching of the first transistor usually has a higher switching loss. The large parasitic capacitance causes more charge to flow through the transistor during hard conduction, greatly increasing the conduction loss. However, in the case of zero-voltage conduction of the first transistor, the large parasitic capacitance will not generate a higher conduction loss, but can instead reduce the voltage rise rate during the turn-off process and reduce the turn-off loss. Therefore, when the switching loss of the first transistor is large, the turn-off loss can be reduced by connecting a capacitor in parallel.

[0047] Exemplarily, the materials included in the first transistor and the second transistor can be the same. By adopting first transistors and second transistors with different shapes, for example, different areas, etc., the parasitic capacitance of the first transistor can be made larger than that of the second transistor. The materials included in the first transistor and the second transistor can also be different. Materials with different parasitic capacitances can be used to form the first transistor and the second transistor, so that the parasitic capacitance of the first transistor is larger than that of the second transistor.

[0048] It should be noted that the inductance value of the first inductor Lr will directly affect the operating time and loss of the second transistor. For the low operating frequency of the IGBT, the slower rise time of Ir brought about by a larger inductance value has obviously little impact on the main operating state of the circuit. Instead, a lower current change rate is beneficial to the zero-current turn-on of the second transistor. When the second transistor Sa1 located in the lower half-bridge is turned off and the Ir flowing through the second transistor Sa2 located in the upper half-bridge drops to zero, an inverted Ir needs to be generated to charge the capacitor to complete the voltage balance between the two switching nodes. When the first transistor Sm2 located in the lower half-bridge is turned off, an additional Ir needs to be generated to charge Crau. And the remaining current can keep flowing in the circuit and cause conduction loss.

[0049] The power device drive circuit provided by the embodiment of the present application forms a first half-bridge circuit with the first transistor having a large parasitic capacitance and a second half-bridge circuit with the second transistor having a small parasitic capacitance. By connecting the first half-bridge circuit and the second half-bridge circuit through the first inductor Lr, the second transistor can assist the turn-on of the first transistor, so that the first transistor with a large parasitic capacitance can achieve zero-voltage turn-on, thereby reducing the switching loss of the first transistor. At the same time, the conduction performance of the first transistor can be retained, and further, the requirements of the power device drive circuit for low conduction loss and low switching loss can be taken into account, the switching quality of the power device drive circuit can be improved, and the practicability of the power device drive circuit can be enhanced.

[0050] In some feasible embodiments, the first transistor includes a silicon transistor; the second transistor includes a wide-bandgap semiconductor transistor.

[0051] Exemplarily, the wide-bandgap semiconductor transistor includes a silicon carbide transistor, a gallium nitride transistor, etc.

[0052] In some feasible embodiments, the first switching circuit further includes a first unidirectional conduction unit, the first unidirectional conduction unit is connected in parallel with the first transistor, and the conduction direction of the first unidirectional conduction unit is opposite to the conduction direction of the first transistor; the second switching circuit further includes a second unidirectional conduction unit, the second unidirectional conduction unit is connected in parallel with the second transistor, and the conduction direction of the second unidirectional conduction unit is opposite to the conduction direction of the second transistor.

[0053] Exemplarily, the first unidirectional conduction unit and the second unidirectional conduction unit may include diodes.

[0054] The power device drive circuit provided by the embodiment of the present application can protect other components in the power device drive circuit and avoid the components being broken down or burned by the induced voltage by setting the first unidirectional conduction unit and the second unidirectional conduction unit when the load current on the first inductor Lr changes, thereby further improving the safety and reliability of the power device drive circuit.

[0055] In some feasible embodiments, the power device driving circuit further includes: a second inductor L F , wherein one end of the second inductor L F is connected between two first transistors of the first half-bridge circuit.

[0056] Exemplarily, the second inductor L F is a boost inductor.

[0057] It should be noted that in the existing power device driving circuit, when the boost converter operates in the continuous conduction mode, the first transistor Sm2 located in the lower half-bridge is the main switch that causes conduction and turn-off losses. In the power device driving circuit provided in the embodiments of the present application, before the first transistor Sm2 located in the lower half-bridge conducts, the second transistor Sa1 located in the lower half-bridge is used as an auxiliary switch to conduct first, so that the load current on the first transistor Sm1 located in the upper half-bridge can slowly commutate to the second transistor Sa1 located in the lower half-bridge, thereby realizing zero-current turn-off of the first transistor Sm1 in the upper half-bridge and zero-current conduction of the second transistor Sa1 located in the lower half-bridge.

[0058] When the current Ir on the first inductor Lr is greater than the load current I F on the second inductor L F , the parasitic output capacitance of the first transistor Sm2 located in the lower half-bridge resonates with the first inductor Lr, and the first transistor Sm2 located in the lower half-bridge can be reduced to zero, thereby contributing to zero-voltage conduction of the first transistor Sm2 located in the lower half-bridge. The current Ir on the first inductor Lr is increased to be equal to the sum Imax of the load current I F on the second inductor L F and the resonant current generated by the output parasitic capacitance of the first transistor Sm2 located in the lower half-bridge, where the sum Imax of the resonant current can be determined by:

[0059] (1)

[0060] Determine the sum Imax of the above resonant current. It can be seen that a larger inductance of the first inductor Lr can effectively reduce the peak value of the resonant current and reduce the additional losses brought by the resonant current. Therefore, the factors restricting the inductance value of the first inductor Lr include inductance loss, saturation current of the inductor, and the volume required for integration. The current rise time of the first inductor Lr is divided into two parts, namely the linear rise time T1 of connecting the load current I F on the second inductor L F and a quarter of the resonant period, which can be determined by:

[0061] (2)

[0062] Determine the linear rise time T1, which can be achieved by:

[0063] (3)

[0064] Determine the quarter resonance period T2. Therefore, according to actual requirements, the inductance value of the first inductor Lr can be precisely designed to reduce losses and device size and improve the integration effect of the device.

[0065] Therefore, the power device drive circuit provided by the embodiments of the present application can achieve zero-voltage turn-on of the first transistor Sm2 located in the lower half-bridge and zero-current turn-on of the second transistor Sa1 located in the lower half-bridge. Similarly, the power device drive circuit provided by the embodiments of the present application can also achieve zero-voltage turn-on of the first transistor Sm1 located in the upper half-bridge and zero-current turn-on of the second transistor Sa2 located in the upper half-bridge.

[0066] As Figure 2 shown, in the second aspect of the embodiments of the present application, a control method for a power device drive circuit is provided, which is used to control the power device drive circuit as described in any one of the first aspects above. The control method includes:

[0067] Step S110: Obtain the turn-on signal of the target transistor and detect the first drain-source voltage of the target transistor. The turn-on signal is used to control the turn-on of the target transistor, and the target transistor is the first transistor.

[0068] Combined with Figure 1 , both the target transistor and the second transistor on the same side as the target transistor are located in the upper half-bridge or the lower half-bridge of the power device drive circuit. Taking the first transistor Sm2 located in the lower half-bridge as the target transistor as an example, the second transistor on the same side as the target transistor is the second transistor Sa1 located in the lower half-bridge.

[0069] Step S120: Control the second transistor on the same side as the target transistor to turn on when the first drain-source voltage is greater than the preset reference voltage.

[0070] As shown in FIG. 1, it can be understood that the first half-bridge circuit and the second half-bridge circuit are connected to the same DC bus. Therefore, the first transistor and the second transistor must not be on the same side in the DC bus transmission direction. So it can be clear that the above-mentioned second transistor on the same side as the target transistor refers to the second transistor that is located in the upper half-bridge or the lower half-bridge together with the target transistor, and the target transistor and the corresponding second transistor are on the same side in the direction from the DC bus to the ground wire.

[0071] Exemplarily, the preset reference voltage can be 0. The smaller the preset reference voltage, the lower the turn-on loss of the target transistor.

[0072] Step S130: Dynamically detect the second drain-source voltage of the target transistor until the second drain-source voltage is less than or equal to a preset reference voltage, and control the target transistor to conduct.

[0073] Exemplarily, the second drain-source voltage of the target transistor can be dynamically detected, and at the moment when the second drain-source voltage of the target transistor is less than or equal to the preset reference voltage, the target transistor is controlled to conduct.

[0074] As Figure 3 shown, t1 is the acquisition moment of the first drain-source voltage of the target transistor, and t2 is the conduction moment of the target transistor. It can be understood that the first drain-source voltage of the target transistor is acquired at the moment t1. At this time, the first drain-source voltage of the target transistor is higher than the preset reference voltage. Therefore, the target transistor is not conducted at this time, and only the second transistor on the same side as the target transistor is conducted. Continuously monitor the second drain-source voltage of the target transistor. At the moment t2, it is monitored that the second drain-source voltage drops to be equal to the preset reference voltage, and at this time, the target transistor is controlled to conduct.

[0075] As Figure 4 described, A1 is the curve obtained by driving the target transistor through the control method of the power device drive circuit provided in the embodiment of the present application in the power device drive circuit provided in the embodiment of the present application, and A2 is the curve obtained by driving the target transistor in the existing power device drive circuit. It can be seen that the conduction efficiency of driving the target transistor by using the power device drive circuit provided in the embodiment of the present application and the control method of the power device drive circuit provided in the embodiment of the present application is significantly higher than that of the existing drive circuit and drive method. Therefore, the power device drive circuit provided in the embodiment of the present application and the control method of the power device drive circuit provided in the embodiment of the present application can effectively reduce the switching loss generated during the driving process of the target transistor and improve the driving effect of the target transistor.

[0076] For the control method of the power device drive circuit provided in the embodiment of the present application, by detecting the first drain-source voltage of the target transistor when receiving the conduction signal of the target transistor, the switching mode of the target transistor in the current state can be determined. When the first drain-source voltage is greater than the preset reference voltage, it can be determined that the target transistor is in the hard switching mode in the current state. At this time, conducting the target transistor will cause an increase in the conduction loss of the target transistor. Therefore, by controlling the second transistor on the same side as the target transistor to conduct, the current Ir on the first inductor Lr can be made greater than the load current I F, enabling the output parasitic capacitance of the target transistor to resonate with the first inductor Lr, so that the voltage of the target transistor can be reduced. When the voltage of the target transistor drops to the preset reference voltage, controlling the target transistor to turn on can reduce the on-state loss of the target transistor, and at the same time, the on-state performance of the first transistor can be retained. Furthermore, the requirements of the power device drive circuit for low on-state loss and low switching loss can be taken into account, the switching quality of the power device drive circuit can be improved, and the practicability of the power device drive circuit can be enhanced.

[0077] In some feasible embodiments, the control method of the power device drive circuit further includes: when the first drain-source voltage is equal to the preset reference voltage, controlling the target transistor to turn on and controlling the second transistor on the same side as the target transistor to turn off.

[0078] It should be noted that when the first drain-source voltage is equal to the preset reference voltage, it can be determined that the current target transistor is already in the zero-voltage soft-switching state. Therefore, there is no need to turn on the second transistor on the same side as the target transistor, which can improve the driving efficiency of the power device drive circuit and further enhance the practicability of the power device drive circuit.

[0079] In some feasible embodiments, the control method of the power device drive circuit further includes: within a preset time after the target transistor turns on, controlling the second transistor on the same side as the target transistor to turn off.

[0080] It should be noted that the second transistor on the same side as the target transistor can be controlled to turn off while the target transistor turns on.

[0081] The control method of the power device drive circuit provided by the embodiments of the present application can avoid the influence of the second transistor on the subsequent conduction of the power device drive circuit by controlling the second transistor on the same side as the target transistor to turn off, and can further improve the reliability and stability of the power device drive circuit.

[0082] Such as Figure 5As shown in the figure, in the third aspect of the embodiments of the present application, a power device driving unit is provided, which is used to implement the control method of the power device driving circuit as described in any one of the above second aspects. The power device driving unit includes: a clamping unit 100 and a control unit 200. Among them, the input end of the clamping unit 100 is electrically connected to the source and drain of the first transistor of the power device driving circuit, and the clamping unit 100 is used to obtain the drain-source voltage of the first transistor; the clamping signal input end of the control unit 200 is electrically connected to the output end of the clamping unit 100, the conduction signal input end of the control unit 200 is used to obtain the conduction signal of the first transistor, and the output end of the control unit 200 is electrically connected to the gate of the first transistor and the gate of the second transistor of the power device driving circuit. The control unit 200 is used to control the on-off of the first transistor and the second transistor according to the magnitude relationship between the drain-source voltage of the first transistor and a preset reference voltage and the conduction signal.

[0083] Among them, the clamping unit (H) and the clamping unit (L) both belong to the clamping unit 100, the control unit (H) and the control unit (L) both belong to the control unit 200, and the first transistor and the second transistor are divided into the first transistor (H), the first transistor (L), the second transistor (H), and the second transistor (L) according to the conduction logic. The devices in Figure 5 can be divided into two groups of high-level conduction and low-level conduction according to the subscript, and the conduction logics of the above two groups of devices both conform to the conduction logic of the power device driving unit.

[0084] For the power device driving unit provided by the embodiments of the present application, the clamping unit 100 can obtain the drain-source voltage of the target transistor, and then the control unit 200 can compare the magnitude relationship between the drain-source voltage of the first transistor and the preset reference voltage, so as to implement the control method of the power device driving circuit as described in the above second aspect. When the voltage of the first transistor drops to the preset reference voltage, controlling the first transistor to conduct can reduce the conduction loss of the first transistor, and at the same time, the conduction performance of the first transistor can be retained. Furthermore, the requirements of the power device driving circuit for low conduction loss and low switching loss can be taken into account, the switching quality of the power device driving circuit can be improved, and the practicability of the power device driving circuit can be enhanced.

[0085] Such as Figure 6As shown, in some feasible embodiments, the control unit 200 includes a comparison circuit, a first AND gate circuit, and a second AND gate circuit. Among them, the comparison circuit includes a first input terminal, a second input terminal, a non-inverting output terminal, and an inverting output terminal. The first input terminal is electrically connected to the output terminal of the clamping unit 100, and the second input terminal is used to access a preset reference voltage. The comparison circuit is configured to generate a first control signal and a second control signal according to the magnitude relationship between the drain-source voltage of the first transistor and the preset reference voltage. The inverting output terminal is electrically connected to the first input terminal of the first AND gate circuit to output the first control signal, and the non-inverting output terminal is electrically connected to the first input terminal of the second AND gate circuit to output the second control signal. The first control signal and the second control signal are complementary level signals. The second input terminal of the first AND gate circuit is electrically connected to the conduction signal input terminal of the control unit 200, and the output terminal of the first AND gate circuit is electrically connected to the gate of the first transistor. The first AND gate circuit is configured to generate a first gate drive signal according to the first control signal and the conduction signal to drive the conduction or cutoff of the first transistor. The second input terminal of the second AND gate circuit is electrically connected to the conduction signal input terminal of the control unit 200, and the output terminal of the second AND gate circuit is electrically connected to the gate of the second transistor. The second AND gate circuit is configured to generate a second gate drive signal according to the second control signal and the conduction signal to drive the conduction or cutoff of the second transistor.

[0086] It should be noted that taking the gates of the first transistor and the second transistor conducting under a high-level signal as an example, when the drain-source voltage of the first transistor is greater than the preset reference voltage, the non-inverting output terminal of the comparison circuit outputs a second control signal in the same direction as the conduction signal, so that the second control signal and the conduction signal jointly pass through the second NOT gate circuit to output a high-level signal, controlling the second transistor to conduct. At this time, the inverting output terminal of the comparison circuit outputs a first control signal that is opposite to the conduction signal, so that the first control signal and the conduction signal jointly pass through the first NOT gate circuit to output a low-level signal, controlling the first transistor to cutoff.

[0087] When the drain-source voltage of the first transistor is equal to the preset reference voltage, the non-inverting output terminal of the comparison circuit outputs a second control signal that is opposite to the conduction signal, so that the second control signal and the conduction signal jointly pass through the second NOT gate circuit to output a low-level signal, controlling the second transistor to cutoff. At this time, the inverting output terminal of the comparison circuit outputs a first control signal in the same direction as the conduction signal, so that the first control signal and the conduction signal jointly pass through the first NOT gate circuit to output a high-level signal, controlling the first transistor to conduct.

[0088] The power device driving unit provided by the embodiment of the present application can compare the magnitude relationship between the drain-source voltage of the first transistor and a preset reference voltage through a comparison circuit, determine whether the drain-source voltage of the first transistor meets the soft-switching condition, and control the automatic conduction and automatic turn-off of the first transistor and the second transistor through the first AND gate circuit and the second AND gate circuit. Therefore, the second transistor can assist the first transistor to achieve zero-voltage conduction, reduce the conduction loss of the first transistor, and at the same time retain the conduction performance of the first transistor. Furthermore, the requirements of the power device driving circuit for low conduction loss and low switching loss can be taken into account, the switching quality of the power device driving circuit can be improved, and the practicability of the power device driving circuit can be enhanced.

[0089] As Figure 6 shown, in some feasible embodiments, the control unit 200 further includes a delay circuit. The delay circuit is used to control the turn-off of the transistor connected in parallel with the target transistor within a preset time after the target transistor is turned on. The delay circuit is electrically connected between the positive-phase output port and the first input terminal of the second AND gate circuit. The delay circuit includes a resistor R and a capacitor C. One end of the capacitor C is grounded, and the other end of the capacitor C is connected between the resistor R and the first input terminal of the second AND gate circuit. One end of the resistor R is electrically connected to the positive-phase output port, and the other end of the resistor R is electrically connected to the capacitor C.

[0090] It should be noted that, without setting the delay circuit, the turn-on of the target transistor and the turn-off of the second transistor connected in parallel will occur simultaneously. In actual applications, since the turn-on and turn-off of both the target transistor and the second transistor require time, it may cause the timing of the turn-on of the target transistor and the turn-off of the second transistor connected in parallel to be disordered, resulting in the voltage of the target transistor rising, the second transistor connected in parallel turning on again, the voltage of the target transistor dropping, the target transistor turning on, and the second transistor connected in parallel turning off in a non-harmonious mode. A cycle may also occur, damaging the stable operation of the power device driving circuit.

[0091] The power device driving unit provided by the embodiment of the present application can ensure that the turn-on of the target transistor occurs after the turn-off of the second transistor connected in parallel by setting a delay circuit between the positive-phase output port and the first input terminal of the second AND gate circuit, which can include the stability of the timing. At the same time, the state of the voltage rise of the target transistor corresponds to the state of the turn-off of the target transistor, and there is no all-on signal, so it will not affect the output, further improving the stability and reliability of the power device driving circuit.

[0092] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0093] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0094] The above-described embodiments only represent several implementation manners of this application. The descriptions are relatively specific and detailed, but should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of the patent of this application should be subject to the appended claims.

Claims

1. A control method for a power device driving circuit, characterized in that, For controlling a power device driving circuit, the power device driving circuit includes: a first half-bridge circuit including two first switching circuits connected in series, and the first switching circuit includes a first transistor; a second half-bridge circuit including two second switching circuits connected in series, and the second switching circuit includes a second transistor, and the first half-bridge circuit and the second half-bridge circuit are connected to the same DC bus, wherein the parasitic capacitance of the second transistor is less than that of the first transistor; a first inductor, one end of the first inductor is connected between the two first transistors of the first half-bridge circuit, and the other end of the first inductor is connected between the two second transistors of the second half-bridge circuit; the control method includes: Obtain a conduction signal of a target transistor, and detect a first drain-source voltage of the target transistor, where the conduction signal is used to control the target transistor to conduct, and the target transistor is a first transistor; When the first drain-source voltage is greater than a preset reference voltage, control a second transistor on the same side as the target transistor to conduct; Dynamically detect a second drain-source voltage of the target transistor until the second drain-source voltage is less than or equal to the preset reference voltage, and control the target transistor to conduct.

2. The control method of the power device driving circuit according to claim 1, characterized in that It further includes: When the first drain-source voltage is equal to the preset reference voltage, control the target transistor to conduct, and control the second transistor on the same side as the target transistor to turn off.

3. The control method of the power device drive circuit according to claim 1, wherein It further includes: Within a preset time after the target transistor conducts, control the second transistor on the same side as the target transistor to turn off.

4. The control method of the power device driving circuit according to claim 1, wherein The first transistor includes a silicon transistor; and / or The second transistor includes a wide-bandgap semiconductor transistor.

5. The control method of the power device driving circuit according to claim 1, wherein The first switching circuit further includes a first unidirectional conduction unit, the first unidirectional conduction unit is connected in parallel with the first transistor, and the conduction direction of the first unidirectional conduction unit is opposite to that of the first transistor; The second switching circuit further includes a second unidirectional conduction unit, the second unidirectional conduction unit is connected in parallel with the second transistor, and the conduction direction of the second unidirectional conduction unit is opposite to that of the second transistor.

6. The control method of the power device driving circuit according to claim 1, characterized in that It further includes: A second inductor, one end of the second inductor is connected between the two first transistors of the first half-bridge circuit.

7. A power device driving unit, characterized in that, For implementing the control method of the power device driving circuit according to any one of claims 1 to 6, the power device driving unit includes: A clamping unit, an input end of the clamping unit is electrically connected to the source and drain of the first transistor of the power device driving circuit, and the clamping unit is used to obtain the drain-source voltage of the first transistor; A control unit, the clamping signal input terminal of the control unit is electrically connected to the output terminal of the clamping unit, the conduction signal input terminal of the control unit is used to obtain the conduction signal of the first transistor, the output terminal of the control unit is electrically connected to the gates of the first transistor and the second transistor of the power device drive circuit, and the control unit is configured to control the on and off of the first transistor and the second transistor according to the magnitude relationship between the drain-source voltage of the first transistor and a preset reference voltage and the conduction signal.

8. The power device drive unit according to claim 7, wherein the control unit includes a comparison circuit, a first AND gate circuit, and a second AND gate circuit; wherein, the comparison circuit includes a first input terminal, a second input terminal, a non-inverting output terminal, and an inverting output terminal. The first input terminal is electrically connected to the output terminal of the clamping unit, the second input terminal is used to connect to the preset reference voltage. The comparison circuit is configured to generate a first control signal and a second control signal according to the magnitude relationship between the drain-source voltage of the first transistor and the preset reference voltage. The inverting output terminal is electrically connected to the first input terminal of the first AND gate circuit to output the first control signal, and the non-inverting output terminal is electrically connected to the first input terminal of the second AND gate circuit to output the second control signal. The first control signal and the second control signal are complementary level signals; the second input terminal of the first AND gate circuit is electrically connected to the conduction signal input terminal of the control unit, and the output terminal of the first AND gate circuit is electrically connected to the gate of the first transistor. The first AND gate circuit is configured to generate a first gate drive signal according to the first control signal and the conduction signal to drive the conduction or cutoff of the first transistor; the second input terminal of the second AND gate circuit is electrically connected to the conduction signal input terminal of the control unit, and the output terminal of the second AND gate circuit is electrically connected to the gate of the second transistor. The second AND gate circuit is configured to generate a second gate drive signal according to the second control signal and the conduction signal to drive the conduction or cutoff of the second transistor.

9. The power device drive unit according to claim 8, wherein the control unit further includes a delay circuit, the delay circuit is configured to control the transistor connected in parallel with the target transistor to turn off within a preset time after the target transistor is turned on. The delay circuit is electrically connected between the non-inverting output port and the first input terminal of the second AND gate circuit. The delay circuit includes a resistor and a capacitor. One end of the capacitor is grounded, and the other end of the capacitor is connected between the resistor and the first input terminal of the second AND gate circuit. One end of the resistor is electrically connected to the non-inverting output port, and the other end of the resistor is electrically connected to the capacitor.

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