Switched capacitor circuit, successive approximation analog-to-digital converter, chip and electronic equipment
By designing a switching capacitor circuit in a successive approximation analog-to-digital converter, the plate of the control capacitor is connected to different reference voltages, solving the problem of limited input range and realizing analog-to-digital conversion of a larger range of input voltages.
Patent Information
- Application Number
- CN202411130529.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-16
- Publication Date
- 2024-12-10
AI Technical Summary
The input range of the successive approximation analog-to-digital converter is limited by the reference voltage range connected to the digital-to-analog converter, and it is impossible to convert analog-to-digital input voltages to a larger range.
Design a switching capacitor circuit, by sampling the input voltage in the sampling stage, and using the first capacitor to perform analog-to-digital conversion during the conversion stage, controlling the plate of each capacitor to connect to a different reference voltage to expand the simulation. Range of voltage.
The input range of the successive approximation analog-to-digital converter is expanded so that it can perform analog-to-digital conversion on a larger input voltage, avoiding the problem of partial range being wasted and voltages exceeding the input range being unable to convert.
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Figure CN119109459A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a switched capacitor circuit, a successive approximation analog-to-digital converter, a chip, and an electronic device. Background Art
[0002] At present, a successive approximation register ADC (SAR ADC) is an analog-to-digital converter that changes a digital signal in a successive approximation manner and outputs an analog voltage according to the digital signal. During the conversion process of the successive approximation register ADC, the analog voltage will gradually approach the input voltage. When the analog voltage is equal to the input voltage, the digital signal corresponding to the analog voltage can be used as the converted digital signal of the input voltage.
[0003] However, the input range of the successive approximation analog-to-digital converter is limited by the reference voltage range to which its digital-to-analog converter is connected. For example, when the reference voltage range is 5V, the successive approximation analog-to-digital converter can only perform analog-to-digital conversion on input voltages of 0 to 5V, which leads to the problem of limited analog-to-digital conversion of the successive approximation analog-to-digital converter. Summary of the invention
[0004] In view of the above problems, embodiments of the present application provide a switched capacitor circuit, a successive approximation analog-to-digital converter, a chip, and an electronic device to solve the above technical problems.
[0005] In a first aspect, an embodiment of the present application provides a switched capacitor circuit, including:
[0006] A capacitor module, the capacitor module includes a plurality of first capacitors and at least one second capacitor, and the first plates of the first capacitors and the second capacitors are connected to each other;
[0007] A switch module, the switch module is used to control the voltage connected to the first plate and the second plate of each capacitor in the capacitor module;
[0008] The switch capacitor circuit has a sampling phase and a conversion phase. In the sampling phase, the switch module controls the first plate of each first capacitor and each second capacitor to access the common mode voltage, the second plate of each first capacitor to access the input voltage to access the first reference voltage or the second reference voltage, and the second plate of each second capacitor to access the input voltage;
[0009] In the conversion stage, the switch module controls the first plates of each first capacitor and each second capacitor to stop being connected to the common mode voltage, the second plates of some first capacitors are connected to the first reference voltage, and the second plates of the remaining first capacitors are connected to the second reference voltage, and the second plate of each second capacitor is connected to the input voltage to be connected to the first reference voltage or the second reference voltage;
[0010] The total capacitance of the plurality of first capacitors is greater than the total capacitance of the at least one second capacitor.
[0011] In a second aspect, the present application provides a successive approximation analog-to-digital converter, comprising:
[0012] The switched capacitor circuit as described in the first aspect, the switched capacitor circuit is used to sample the input voltage in the sampling phase and output the analog voltage in the conversion phase;
[0013] A comparison module, the comparison module is used to compare the analog voltage with the common mode voltage and output a comparison signal;
[0014] The successive approximation logic module is used to input a control signal to the switch capacitor circuit according to the comparison signal, so that the analog voltage approaches the common mode voltage in a successive manner.
[0015] In a third aspect, the present application provides a chip comprising the successive approximation analog-to-digital converter as described in the second aspect.
[0016] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising the chip as described in the third aspect.
[0017] In the sampling phase of the switch capacitor circuit of the present application, the switch module controls the first plate of each first capacitor and each second capacitor to access the common mode voltage, and the second plate of each second capacitor to access the input voltage; in the conversion phase, the switch module controls the first plate of each first capacitor and each second capacitor to stop accessing the common mode voltage, the second plates of some first capacitors are connected to the first reference voltage, and the second plates of the remaining first capacitors are connected to the second reference voltage. In other words, in the sampling phase of the present application, only the second capacitor samples the input voltage, and in the conversion phase, the first capacitor is used for analog-to-digital conversion. Compared with the solution in the related art that all capacitors sample the input voltage and perform analog-to-digital conversion, the present application is conducive to changing the range of the analog voltage output by the first plate of each first capacitor and each second capacitor, and finally expanding the input range of the switch capacitor circuit, so that the successive approximation analog-to-digital converter performs analog-to-digital conversion on input voltages with a larger voltage range.
[0018] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0020] Figure 1 A schematic diagram showing a circuit structure of a successive approximation analog-to-digital converter in conventional technology
[0021] Figure 2 A schematic diagram of a switched capacitor circuit in an embodiment of the present application is shown.
[0022] Figure 3 A schematic diagram showing the voltage connected to the capacitor module during the sampling phase in an embodiment of the present application.
[0023] Figure 4 A schematic diagram showing the voltage connected to the capacitor module during the conversion phase in an embodiment of the present application.
[0024] Figure 5 Another schematic diagram of the voltage connected to the capacitor module during the sampling phase in an embodiment of the present application is shown.
[0025] Figure 6 Another schematic diagram of the voltage connected to the capacitor module during the conversion phase in an embodiment of the present application is shown.
[0026] Figure 7 Another schematic diagram of the voltage connected to the capacitor module during the sampling phase in an embodiment of the present application is shown.
[0027] Figure 8 Another schematic diagram of the voltage connected to the capacitor module during the conversion phase in an embodiment of the present application is shown.
[0028] Fig. 9 Another schematic diagram of a switched capacitor circuit in an embodiment of the present application is shown.
[0029] Fig.10 Another schematic diagram of the voltage connected to the capacitor module during the sampling phase in an embodiment of the present application is shown.
[0030] Fig.11 Another schematic diagram of the voltage connected to the capacitor module during the conversion phase in an embodiment of the present application is shown.
[0031] Fig.12 Another schematic diagram of a switched capacitor circuit in an embodiment of the present application is shown.
[0032] Fig.13 Another schematic diagram of a switched capacitor circuit in an embodiment of the present application is shown.
[0033] Fig.14 Another schematic diagram of a switched capacitor circuit in an embodiment of the present application is shown.
[0034] Fig.15 Another schematic diagram of a switched capacitor circuit in an embodiment of the present application is shown.
[0035] Fig.16 Another schematic diagram of a switched capacitor circuit in an embodiment of the present application is shown.
[0036] Fig.17 Another schematic diagram of a switched capacitor circuit in an embodiment of the present application is shown.
[0037] Fig.18 Another schematic diagram of a switched capacitor circuit in an embodiment of the present application is shown.
[0038] Fig.19 A schematic diagram of a successive approximation analog-to-digital converter in an embodiment of the present application is shown.
[0039] Among them, 10 is a capacitor module, 20 is a switch module, 21 is a first switch unit, 22 is a second switch unit, and 23 is a third switch unit;
[0040] A first capacitor C1, a second capacitor C2, a third capacitor C3, a first reference voltage Vref1, a second reference voltage Vref2, a common mode voltage Vcm, an input voltage Vin, a sampling switch SW, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, and a sixth switch S6;
[0041] 100 switched capacitor circuit, 200 comparison module, 300 successive approximation logic module. DETAILED DESCRIPTION
[0042] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0043] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.
[0044] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
[0045] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.
[0046] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.
[0047] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.
[0048] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.
[0049] At present, analog-to-digital converters are needed in the fields of communication, control, signal processing, and computer systems. The analog-to-digital converter converts the input voltage signal into a digital signal and outputs the digital signal for use in the digital system. Figure 1 , Figure 1 A circuit structure diagram of a successive approximation analog-to-digital converter in the conventional technology is shown. The successive approximation analog-to-digital converter includes a digital-to-analog converter DAC, a comparator CMP and a successive approximation logic module.
[0050] The digital-to-analog converter DAC is mainly composed of a plurality of parallel sampling capacitors C1, C2...Cn-1, Cn, and the lower plate of each sampling capacitor C1, C2...Cn-1, Cn can be respectively connected to the analog input voltage VIN, the reference voltage Vref or the ground gnd through the control of switches S1, S2...Sn-1, Sn, and the upper plate of the sampling capacitors C1, C2...Cn-1, Cn is connected to the non-inverting input of the comparator CMP. The digital-to-analog converter DAC outputs the analog output voltage Vdac to the non-inverting input of the comparator, and a switch SW is connected between the non-inverting input and the inverting input of the comparator CMP, and the inverting input of the comparator CMP is connected to the common mode voltage Vcm.
[0051] The working process of the successive approximation analog-to-digital converter is mainly divided into a sampling stage and a conversion stage. In the sampling stage, the switch SW is closed, the lower plates of the sampling capacitors C1, C2...Cn-1, Cn are connected to the analog input voltage Vin, and the upper plates are connected to the common mode voltage Vcm through the switch SW. After the sampling is fully established, Vdac=Vcm, and the voltage difference across each sampling capacitor is Vin-Vcm.
[0052] In the conversion phase, the switch SW is disconnected synchronously, and the lower plates of the sampling capacitors C1, C2...Cn-1, and Cn stop being connected to the analog input voltage VIN. The successive approximation logic module determines the digital signal of the next cycle based on the output signal of the comparator, and controls the lower plates of the sampling capacitors C1, C2...Cn-1, and Cn to select the reference voltage Vref or the ground gnd through the digital signal. At this time, the voltage Vdac at the in-phase input of the comparator satisfies the following formula:
[0053] Vdac=Vref*Ceq / Ctotal-VIN+Vcm
[0054] Wherein, Ceq is the capacitance value of all sampling capacitors whose lower plates are connected to the reference voltage Vref, and Ctotal is the total capacitance value of the entire array of sampling capacitors C1, C2...Cn.
[0055] Since the voltage at the inverting input of the comparator is the common-mode voltage Vcm, during the comparison process of the comparator, the Vcm item is eliminated as the common-mode voltage during the transcoding comparison process. The comparator is actually judging the positive and negative of Vref*Ceq / Ctotal-VIN, and gradually approaches the logic module. According to the output result of the comparator, the output code value of the next comparison cycle is determined, thereby changing the size of the sampling capacitor Ceq, so that the voltage Vdac on the non-inverting input of the comparator gradually approaches the common-mode voltage Vcm until the analog output voltage Vdac is equal to the common-mode voltage Vcm, and finally the converted digital signal is obtained from the logic module.
[0056] However, according to the above formula, it can be known that the input range of the successive approximation analog-to-digital converter satisfies the following formula:
[0057] VIN = Vref * Ceq / Ctotal
[0058] It can be seen that since Ceq < Ctotal, that is, Ceq / Ctotal in the formula is less than or equal to 1, therefore, the successive approximation analog-to-digital converter can only perform analog-to-digital conversion when the analog input voltage VIN is less than the reference voltage Vref, which leads to the problem of limited analog-to-digital conversion of the successive approximation analog-to-digital converter.
[0059] For this reason, the present application provides a switched capacitor circuit 100, a successive approximation analog-to-digital converter, a chip, and an electronic device, which will be described in detail below.
[0060] First, refer to Figure 2 , Figure 2 FIG. shows a schematic diagram of a switched capacitor circuit 100 in an embodiment of the present application. Among them, the switched capacitor circuit 100 includes a capacitor module 10 and a switch module 20. The capacitor module 10 includes a plurality of first capacitors C1 and at least one second capacitor C2. The first plates of the first capacitor C1 and the second capacitor C2 are connected to each other. The switch module 20 is used to control the voltages applied to the first plates and the second plates of each capacitor in the capacitor module 10. For example, the switch module 20 can control the first plates of the first capacitor C1 and the second capacitor C2 to be connected to the common-mode voltage Vcm, or can control the second plates of the first capacitor C1 and the second capacitor C2 to be connected to one of the input voltage Vin, the first reference voltage Vref1, and the second reference voltage Vref2.
[0061] In the embodiment of the present application, the switched capacitor circuit 100 has a sampling stage and a conversion stage. Refer to Figure 3 , Figure 3 FIG. shows a schematic diagram of the voltages applied to the capacitor module 10 in the sampling stage in an embodiment of the present application. Among them, in the sampling stage, the switch module 20 controls the first plates of each first capacitor C1 and each second capacitor C2 to be connected to the common-mode voltage Vcm, and the second plates of each second capacitor C2 to be connected to the input voltage Vin. The second plates of each first capacitor C1 can be connected to the first reference voltage Vref1 or the second reference voltage Vref2.
[0062] For example, taking the second plates of each first capacitor C1 being connected to the second reference voltage Vref2 in the sampling stage as an example, the total charge accumulated on the first plates of the first capacitor C1 and the second capacitor C2 in the sampling stage is:
[0063] Qs = (Vin - Vcm) * Ctotal2 + (Vref2 - Vcm) * Ctotal1
[0064] Wherein, Ctotal1 is the total capacitance value of all first capacitors C1, and Ctotal2 is the total capacitance value of all second capacitors C2.
[0065] Continue reading Figure 4 , Figure 4 A schematic diagram of the voltage connected to the capacitor module 10 during the conversion phase in an embodiment of the present application is shown, wherein, during the conversion phase, the switch module 20 controls the first plate of each first capacitor C1 and each second capacitor C2 to stop connecting to the common mode voltage Vcm, the second plates of some of the first capacitors C1 are connected to the first reference voltage Vref1, and the second plates of the remaining first capacitors C1 are connected to the second reference voltage Vref2, and the second plate of each second capacitor C2 can be connected to the first reference voltage Vref1 or the second reference voltage Vref2.
[0066] For example, taking the case where the second plate of each second capacitor C2 is connected to the second reference voltage Vref2, since the switch module 20 controls the first plate of each first capacitor C1 and each second capacitor C2 to stop connecting to the common mode voltage Vcm, the total amount of charge accumulated on the first plate of the first capacitor C1 and the first plate of the second capacitor C2 remains unchanged. According to the law of charge conservation, it can be known that:
[0067] (Vin-Vcm)*Ctotal2+(Vref2-Vcm)*Ctotal1=(Vref2-Vdac)*Ctotal2+(Vref2-Vdac)*Cy+(Vref1-Vdac)*Cx
[0068] Among them, Cx is the total capacitance value of multiple first capacitors C1 connected to the first reference voltage Vref1, Cy is the total capacitance value of multiple first capacitors C1 connected to the second reference voltage Vref2, and Vdac is the analog voltage output by the first plate of each first capacitor C1 and each second capacitor C2 in the conversion stage.
[0069] The above formula is simplified by taking the second reference voltage Vref2 as the ground terminal voltage (ie 0V). At this time, the analog voltage output by the first plate of each first capacitor C1 and each second capacitor C2 satisfies the following formula:
[0070]
[0071] According to the principle of the successive approximation analog-to-digital converter, it can be known that the comparator of the successive approximation analog-to-digital converter is actually determining whether Vref1*Cx-Vin*Ctotal2 is positive or negative. Therefore, the input range of the switched capacitor circuit 100 satisfies the following relationship:
[0072] Vin = Vref1 * Cx / Ctotal2
[0073] It can be seen that Cx is less than or equal to the total capacitance value of multiple first capacitors C1 (i.e., Cx ≤ Ctotal1). When the total capacitance value of multiple first capacitors C1 is greater than the total capacitance value of at least one second capacitor C2 (i.e., Ctotal2 < Ctotal1), the input range of the switched-capacitor circuit 100 will be expanded. For example, taking Ctotal1 = 3 * Ctotal2, Vref1 = 1V, and Vref2 = 0V as an example, the input range of the switched-capacitor circuit 100 is then 0 to 3V at this time; another example is taking Ctotal1 = 4 * Ctotal2, Vref1 = 2V, and Vref2 = 0V as an example, the input range of the switched-capacitor circuit 100 is then 0 to 8V at this time.
[0074] Therefore, in the embodiment of the present application, during the sampling phase of the switched-capacitor circuit 100 of the present application, the switching module 20 controls the first plates of each first capacitor C1 and each second capacitor C2 to be connected to the common-mode voltage Vcm, and the second plates of each second capacitor C2 are connected to the input voltage Vin; while in the conversion phase, the switching module 20 controls the first plates of each first capacitor C1 and each second capacitor C2 to stop being connected to the common-mode voltage Vcm, the second plates of some first capacitors C1 are connected to the first reference voltage Vref1, and the second plates of the remaining first capacitors C1 are connected to the second reference voltage Vref2. That is to say, in the sampling phase of the present application, only the second capacitor C2 samples the input voltage Vin, and in the conversion phase, the first capacitor C1 is used for conversion. Compared with the solution in the related art where all capacitors sample the input voltage Vin, the present application is beneficial to changing the analog voltage range output by the first plates of each first capacitor C1 and each second capacitor C2, and finally can expand the input range of the switched-capacitor circuit 100, so that the successive approximation analog-to-digital converter performs analog-to-digital conversion on the input voltage Vin with a larger voltage range.
[0075] It should be noted that the magnitude of the common-mode voltage Vcm of the present application does not affect the operation of the switched-capacitor circuit 100. It is the voltage provided for the switched-capacitor circuit 100 to complete sampling. Therefore, the common-mode voltage Vcm can be equal to the first reference voltage Vref1, the common-mode voltage Vcm can also be equal to the second reference voltage Vref2, or a common-mode voltage Vcm can be provided through an additional circuit. The present application does not make specific limitations.
[0076] In some embodiments of the present application, after completing the conversion phase for the input voltage Vin that satisfies the preset voltage range, the analog voltage output by the first plate of each first capacitor C1 and each second capacitor C2 is equal to the common mode voltage Vcm; wherein the lower limit value of the preset voltage range is greater than the second reference voltage Vref2, and the upper limit value of the preset voltage range is greater than the first reference voltage Vref1.
[0077] It should be noted that, in combination with the foregoing content, it can be seen that the conversion process will not be stopped until the analog voltage output by the digital-to-analog converter in the successive approximation analog-to-digital converter during the conversion phase is approximately equal to the common-mode voltage Vcm. Under normal circumstances, the input voltage Vin of the successive approximation analog-to-digital converter is near the middle value of its input range, and an input voltage Vin close to 0V rarely appears. For example, the input range of a successive approximation analog-to-digital converter is 0-5V. Under normal circumstances, the input voltage Vin of the successive approximation analog-to-digital converter is near 2-6V, and an input voltage Vin of 0-2V rarely appears. This results in a part of the range of the successive approximation analog-to-digital converter being wasted and the part of the voltage that exceeds the input range cannot be converted into analog-to-digital.
[0078] In the above embodiment, since the lower limit value of the preset voltage range is greater than the first reference voltage Vref1, and the upper limit value of the preset voltage range is greater than the second reference voltage Vref2, for example, taking the first reference voltage Vref1 as 5V and the second reference voltage Vref2 as 0V, the lower limit value of the preset voltage range can be 1V, and the upper limit value of the preset voltage range can be 6V. At this time, the input range of the switching capacitor circuit 100 (successive approximation analog-to-digital converter) is changed to 1V~6V. Therefore, the present application can not only expand the upper limit value of the input range of the switching capacitor circuit 100, but also expand the lower limit value of the input range of the switching capacitor circuit 100, thereby avoiding the phenomenon that part of the range of the successive approximation analog-to-digital converter is wasted and part of the voltage exceeding the input range cannot be converted into analog-to-digital.
[0079] As an exemplary embodiment, see Figure 5 as well as Figure 6 , Figure 5 Another schematic diagram showing the voltage connected to the capacitor module 10 during the sampling phase in the embodiment of the present application is shown. Figure 6 Another schematic diagram of the voltage connected to the capacitor module 10 during the conversion phase in the embodiment of the present application is shown. Figure 4 The difference is that in the conversion stage, the second plate of each second capacitor C2 is connected to the first reference voltage Vref1. According to the charge conservation law, it can be known that:
[0080] (Vin - Vcm) * Ctotal2 + (Vref2 - Vcm) * Ctotal1 = (Vref1 - Vdac) * Ctotal2 + (Vref2 - Vdac) * Cy + (Vref1 - Vdac) * Cx
[0081] Similarly, taking the second reference voltage as the grounded terminal voltage (i.e., 0V) to simplify the above formula, at this time, the analog voltages output by the first plates of each first capacitor C1 and each second capacitor C2 satisfy the following formula:
[0082]
[0083] According to the principle of the successive approximation analog-to-digital converter, it can be known that the comparator of the successive approximation analog-to-digital converter is actually judging the positive and negative of Vref1 * (Cx + Ctotal2) - Vin * Ctotal2. Therefore, the input range of the switched-capacitor circuit 100 satisfies the following relational expression:
[0084] Vin = Vref1 * (Cx + Ctotal2) / Ctotal2
[0085] It can be seen that Cx is less than or equal to the total capacitance value of multiple first capacitors C1 (i.e., Cx ≤ Ctotal1). When the total capacitance value of multiple first capacitors C1 is greater than the total capacitance value of multiple second capacitors C2 (i.e., Ctotal2 < Ctotal1), then both the lower limit value and the upper limit value of the input range of the switched-capacitor circuit 100 will be raised. For example, taking Ctotal1 = 3 * Ctotal2, Vref1 = 1V, and Vref2 = 0V as an example, at this time, the input range of the switched-capacitor circuit 100 is 1 - 4V; another example, taking Ctotal1 = 4 * Ctotal2, Vref1 = 2V, and Vref2 = 0V as an example, at this time, the input range of the switched-capacitor circuit 100 is 2 - 10V.
[0086] It can be understood that the above embodiments are exemplarily described by taking the second plates of each second capacitor C2 being connected to the first reference voltage Vref1 in the conversion stage as an example. In some possible embodiments, in the conversion stage, only the second plates of some second capacitors C2 can also be connected to the first reference voltage Vref1. For example, refer to Figure 7 and Figure 8 , Figure 7 shows another schematic diagram of the voltages connected in the sampling stage of the capacitor module 10 in the embodiments of the present application, and 8 shows another schematic diagram of the voltages connected in the conversion stage of the capacitor module 10 in the embodiments of the present application. Different from Figure 6The difference is that in the conversion phase, the second plates of some second capacitors C2 are connected to the first reference voltage Vref1, and the second plates of the remaining second capacitors C2 are connected to the second reference voltage Vref2. That is to say, in the sampling phase, the second plate of each first capacitor C1 is connected to the second reference voltage Vref2, and in the conversion phase, the second plates of some second capacitors C2 are connected to the first reference voltage Vref1, and the second plates of the remaining second capacitors C2 are connected to the second reference voltage Vref2. According to the law of charge conservation, it can be known that:
[0087] (Vin-Vcm)*Ctotal2+(Vref2-Vcm)*Ctotal1=(Vref1-Vdac)*Cm+(Vref2-Vdac)*Cn+(Vref2-Vdac)*Cy+(Vref1-Vdac)*Cx
[0088] Wherein, Cm is the total capacitance value of all second capacitors C2 whose second plates are connected to the first reference voltage Vref1 during the conversion phase, and Cn is the total capacitance value of all second capacitors C2 whose second plates are connected to the second reference voltage Vref2 during the conversion phase.
[0089] Similarly, the above formula is simplified by taking the second reference voltage as the ground terminal voltage (ie, 0V). At this time, the analog voltage output by the first plate of each first capacitor C1 and each second capacitor C2 satisfies the following formula:
[0090]
[0091] According to the principle of the successive approximation analog-to-digital converter, it can be known that the comparator of the successive approximation analog-to-digital converter is actually determining the positive or negative value of Vref1*(Cx+Ctotal2)-Vin*Ctotal2, so the input range of the switched capacitor circuit 100 satisfies the following relationship:
[0092] Vin=Vref1*(Cx+Cm) / Ctotal2
[0093] It can be seen that if Cx is less than or equal to the total capacitance of the first capacitors C1 (i.e., Cx≤Ctotal1), and Cm is less than or equal to the total capacitance of the second capacitors C2 (i.e., Cm≤Ctotal2), then the lower limit and upper limit of the input range of the switch capacitor circuit 100 will be raised. For example, taking Ctotal1=3*Ctotal2, Cm=0.5*Ctotal2, Vref1=1V, and Vref2=0V as an example, according to the above formula, the input range of the switch capacitor circuit 100 is 0.5~3.5V; for another example, taking Ctotal1=4*Ctotal2, Cm=0.5*Ctotal2, Vref1=2V, and Vref2=0V as an example, the input range of the switch capacitor circuit 100 is 1~9V.
[0094] In some other possible embodiments, see Fig. 9 , Fig. 9 Another schematic diagram of the switching capacitor circuit 100 in an embodiment of the present application is shown, wherein the capacitor module 10 also includes at least one third capacitor C3, the first capacitor C1, the second capacitor C2 and the first plates of the third capacitor C3 are connected to each other, and the switching module 20 can control the voltage connected to the first plate and the second plate of the third capacitor C3.
[0095] For example, see Fig.10 , Fig.10 Another schematic diagram of the voltage connected to the capacitor module 10 in the sampling phase in the embodiment of the present application is shown. In the sampling phase, the switch module 20 also controls the first plate of each third capacitor C3 to be connected to the common mode voltage Vcm, and the second plate of each third capacitor C3 is connected to the second reference voltage Vref2. Taking the second plate of each first capacitor C1 as an example of connecting the second reference voltage Vref2, the total charge accumulated in the first plate of the first capacitor C1 and the first plate of the second capacitor C2 in the sampling phase is:
[0096] Qs=(Vin-Vcm)*Ctotal2+(Vref2-Vcm)*Ctotal1+(Vref2-Vcm)*Ctotal3
[0097] Wherein, Ctotal3 is the total capacitance value of all third capacitors C3.
[0098] Continue reading Fig.11 , Fig.11A schematic diagram of the voltage connected to the capacitor module 10 during the conversion phase in the embodiment of the present application is shown, wherein, during the conversion phase, the switch module 20 also controls the first plate of each third capacitor C3 to stop connecting to the common mode voltage Vcm, and the second plate of the third capacitor C3 is connected to the first reference voltage Vref1. Taking the second plate of each second capacitor C2 as an example of connecting to the second reference voltage Vref2, since the switch module 20 controls the first plate of each first capacitor C1, each second capacitor C2, and each third capacitor C3 to stop connecting to the common mode voltage Vcm, the total amount of charge accumulated on the first plate of the first capacitor C1 and the first plate of the second capacitor C2 remains unchanged. According to the law of charge conservation, it can be known that:
[0099] (Vin-Vcm)*Ctotal2+(Vref2-Vcm)*Ctotal1+(Vref2-Vcm)*Ctotal3=(Vref2-Vdac)*Ct otal2+(Vref2-Vdac)*Cy+(Vref1-Vdac)*Cx+(Vref1-Vdac)*Ctotal3
[0100] Similarly, the above formula is simplified by taking the second reference voltage as the ground terminal voltage (ie, 0V). At this time, the analog voltage output by the first plate of each first capacitor C1, each second capacitor C2, and each third capacitor C3 satisfies the following formula:
[0101]
[0102] According to the principle of the successive approximation analog-to-digital converter, it can be known that the comparator of the successive approximation analog-to-digital converter is actually determining the positive or negative value of Vref1*(Cx+Ctotal3)-Vin*Ctotal2, so the input range of the switched capacitor circuit 100 satisfies the following relationship:
[0103] Vin=Vref1*(Cx+Ctotal3) / Ctotal2
[0104] It can be seen that since Cx is less than or equal to the total capacitance value of multiple first capacitors C1 (i.e., Cx ≤ Ctotal1), and the total capacitance value of multiple first capacitors C1 is greater than the total capacitance value of multiple second capacitors C2 (i.e., Ctotal2 < Ctotal1), then the input range of the switched-capacitor circuit 100 will be greater than Vref2 to Vref1. For example, taking Ctotal1 = 3 * Ctotal2, Ctotal3 = Ctotal2, Vref1 = 1V, and Vref2 = 0V as an example, the input range of the switched-capacitor circuit 100 at this time is 1 to 4V; another example, taking Ctotal1 = 4 * Ctotal2, Ctotal3 = 0.5 * Ctotal2, Vref1 = 2V, and Vref2 = 0V as an example, the input range of the switched-capacitor circuit 100 at this time is 1 to 9V.
[0105] It can be understood that the second plates of multiple third capacitors C3 can also be partially connected to the first reference voltage Vref1 and the remaining part to the second reference voltage Vref2 only during the conversion stage, which can also make the input range of the switched-capacitor circuit 100 greater than Vref2 to Vref1.
[0106] In some embodiments of the present application, refer to Fig.12 , Fig.12 which shows another schematic diagram of the switched-capacitor circuit 100 in the embodiments of the present application. Among them, the switch module 20 includes a first switch unit 21, a second switch unit 22, and a third switch unit 23.
[0107] Among them, the first switch unit 21 is used to control the voltage applied to the first plates of each first capacitor C1 and each second capacitor C2. For example, during the sampling stage, the first switch unit 21 can control the first plates of each first capacitor C1 and each second capacitor C2 in the capacitor module 10 to be connected to the common-mode voltage Vcm. During the conversion stage, the first switch unit 21 can control the first plates of each first capacitor C1 and each second capacitor C2 to stop being connected to the common-mode voltage Vcm. In some embodiments of the present application, for example, in the embodiment where the capacitor module 10 further includes a third capacitor C3, the first switch unit 21 can also control the first plate of the third capacitor C3 to be connected to / stop being connected to the common-mode voltage Vcm.
[0108] The second switch unit 22 is used to control the voltage connected to the second plate of each first capacitor C1. In some embodiments of the present application, in the sampling phase, the second switch unit 22 can control the second plate of each first capacitor C1 to connect to the second reference voltage Vref2, and in the conversion phase, the second switch unit 22 can control the second plate of each first capacitor C1 to connect to the first reference voltage Vref1 or the second reference voltage Vref2 in response to a control signal (e.g., a digital signal output by the successive approximation logic module 300).
[0109] In some embodiments of the present application, in the sampling stage, the second switch unit 22 can control the second plate of each first capacitor C1 to be connected to the second reference voltage Vref2. In the conversion stage, the second switch unit 22 can control the second plates of some first capacitors C1 to be fixedly connected to the first reference voltage Vref1. At the same time, the second switch unit 22 can control the second plates of the remaining first capacitors C1 to be connected to the first reference voltage Vref1 or the second reference voltage Vref2 in response to a control signal (for example, a digital signal output by the successive approximation logic module 300).
[0110] The third switch unit 23 is used to control the voltage connected to the second plate of each second capacitor C2. In some embodiments of the present application, in the sampling stage, the third switch unit 23 can control the second plate of each second capacitor C2 to be connected to the input voltage Vin, and in the conversion stage, the third switch unit 23 can control the second plate of each second capacitor C2 to be connected to the second reference voltage Vref2. In some embodiments of the present application, in the sampling stage, the third switch unit 23 can control the second plate of part of the second capacitor C2 to be connected to the input voltage Vin, and the second plate of the remaining part of the second capacitor C2 to be connected to the second reference voltage Vref2, and in the conversion stage, the third switch unit 23 can control the second plate of each second capacitor C2 to be connected to the second reference voltage Vref2. In some embodiments of the present application, in the sampling stage, the third switch unit 23 can control the second plate of part of the second capacitor C2 to be connected to the input voltage Vin, and the second plate of the remaining part of the second capacitor C2 to be connected to the second reference voltage Vref2, and in the conversion stage, the third switch unit 23 can control the second plate of part of the second capacitor C2 to be connected to the second reference voltage Vref2, and the second plate of the remaining part of the second capacitor C2 to be connected to the third reference voltage.
[0111] In some embodiments of the present application, for example, for an embodiment in which the capacitor module 10 further includes a third capacitor C3, see Fig.13 , Fig.13Another schematic diagram of the switched capacitor circuit 100 in the embodiment of the present application is shown, wherein the switch module 20 further includes a fourth switch unit 24, and the fourth switch unit 24 can control the voltage connected to the second plate of each third capacitor C3. For example, in the sampling phase, the fourth switch unit 24 can control the second plate of each third capacitor C3 to connect to the second reference voltage Vref2, and in the conversion phase, the fourth switch unit 24 can control the second plate of each third capacitor C3 to connect to the first reference voltage Vref1.
[0112] As an exemplary embodiment of the first switch unit 21, see Fig.14 , Fig.14 Another schematic diagram of the switched capacitor circuit 100 in an embodiment of the present application is shown, wherein the first switch unit 21 includes a sampling switch SW, and the first plate of each first capacitor C1 and each second capacitor C2 is connected to the first end of the sampling switch SW, and the second end of the sampling switch SW is connected to the common mode voltage Vcm. Therefore, a sampling switch SW can be used to control whether the first plate of each first capacitor C1, each second capacitor C2 (each third capacitor C3) is connected to the common mode voltage Vcm.
[0113] It is understandable that a switch for accessing the common mode voltage Vcm may also be provided on the first plate of each capacitor (the first capacitor C1 , the second capacitor C2 , and the third capacitor C3 ) in the capacitor module 10 to control whether each capacitor is connected to the common mode voltage Vcm.
[0114] As an exemplary embodiment of the second switch unit 22, see Fig.15 , Fig.15 Another schematic diagram of the switch capacitor circuit 100 in the embodiment of the present application is shown, wherein the second switch unit 22 includes a plurality of first switches S1 and a plurality of second switches S2; the first switch S1 corresponds to the first capacitor C1 one by one, the first end of the first switch S1 is connected to the second plate of the corresponding first capacitor C1, and the second end of the first switch S1 is connected to the first reference voltage Vref1; the second switch S2 corresponds to the first capacitor C1 one by one, the first end of the second switch S2 is connected to the second plate of the corresponding first capacitor C1, and the second end of the second switch S2 is connected to the second reference voltage Vref2. Therefore, the present application can control whether the second plate of the first capacitor C1 is connected to the first reference voltage Vref1 through the first switch S1, and at the same time, the present application can control whether the second plate of the first capacitor C1 is connected to the second reference voltage Vref2 through the second switch S2.
[0115] As an exemplary embodiment of the third switch unit 23, see Fig.16 , Fig.16Another schematic diagram of the switched capacitor circuit 100 in the embodiment of the present application is shown, wherein the third switch unit 23 includes a third switch S3 and a fourth switch S4; the first end of the third switch S3 is connected to the second plate of each second capacitor C2, and the second end of the third switch S3 is connected to the input voltage Vin; the first end of the fourth switch S4 is connected to the second plate of each second capacitor C2, and the second end of the fourth switch S4 is connected to the second reference voltage Vref2. Therefore, the present application can control whether the second plate of the second capacitor C2 is connected to the input voltage Vin through the third switch S3, and at the same time, the present application can control whether the second plate of the second capacitor C2 is connected to the second reference voltage Vref2 through the fourth switch S4.
[0116] As an exemplary embodiment of the fourth switch unit 24, see Fig.17 , Fig.17 Another schematic diagram of the switched capacitor circuit 100 in the embodiment of the present application is shown, wherein the fourth switch unit 24 includes a fifth switch S5 and a sixth switch S6; the first end of the fifth switch S5 is connected to the second plate of each third capacitor C3, and the second end of the fifth switch S5 is connected to the first reference voltage Vref1; the first end of the sixth switch S6 is connected to the second plate of each third capacitor C3, and the second end of the sixth switch S6 is connected to the second reference voltage Vref2. Therefore, the present application can control whether the second plate of the third capacitor C3 is connected to the first reference voltage Vref1 through the fifth switch S5, and at the same time, the present application can control whether the second plate of the third capacitor C3 is connected to the second reference voltage Vref2 through the sixth switch S6.
[0117] It should be pointed out that the above Figures 15 to 17 As only exemplary embodiments of the switch units of the present application, those skilled in the art can make equivalent modifications and designs to the settings of the above switch units under the guidance of the present application. For example, in the embodiment in which the second plate of the second capacitor C2 is connected to the first reference voltage Vref1 during the conversion phase, refer to Fig.18 The third switch unit 23 may further be provided with a seventh switch S7 to control whether the second plate of the second capacitor C2 is connected to the first reference voltage Vref1 through the seventh switch S7.
[0118] In order to better implement the switched capacitor circuit 100 in the embodiment of the present application, based on the switched capacitor circuit 100, the present application further provides a progressive approximation analog-to-digital converter, see Fig.19 , Fig.19A schematic diagram of a gradually approximating analog-to-digital converter in an embodiment of the present application is shown, and the gradually approximating analog-to-digital converter includes a switching capacitor circuit 100, a comparison module 200, and a successive approximation logic module 300 as described in any of the above embodiments, the switching capacitor circuit 100 is used to sample the input voltage Vin in the sampling phase and output an analog voltage in the conversion phase, the comparison module 200 is used to compare the analog voltage with the common-mode voltage Vcm and output a comparison signal; the gradually approximating logic module, the gradually approximating logic module is used to input a control signal to the switching capacitor circuit 100 according to the comparison signal, so that the analog voltage approaches the common-mode voltage Vcm in a successive approximation. Since the gradually approximating analog-to-digital converter of the present application includes the above-mentioned switching capacitor circuit 100, and the switching capacitor circuit 100 can expand the input range, the successive approximation analog-to-digital converter can perform analog-to-digital conversion on the input voltage Vin with a larger voltage range.
[0119] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.
[0120] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.
Claims
1. A switched capacitor circuit, characterized in that: include: A capacitor module, wherein the capacitor module includes a plurality of first capacitors and at least one second capacitor, wherein first plates of the first capacitors and the second capacitors are connected to each other; A switch module, the switch module is used to control the voltage connected to the first plate and the second plate of each capacitor in the capacitor module; The switch capacitor circuit has a sampling phase and a conversion phase. In the sampling phase, the switch module controls the first plate of each of the first capacitors and each of the second capacitors to access the common mode voltage, the second plate of each of the first capacitors to access the first reference voltage or the second reference voltage, and the second plate of each of the second capacitors to access the input voltage; In the conversion phase, the switch module controls the first plate of each of the first capacitors and each of the second capacitors to stop being connected to the common mode voltage, the second plates of some of the first capacitors are connected to the first reference voltage, and the second plates of the remaining first capacitors are connected to the second reference voltage, and the second plate of each of the second capacitors is connected to the first reference voltage or the second reference voltage; The total capacitance of the plurality of first capacitors is greater than the total capacitance of the at least one second capacitor.
2. The switched capacitor circuit according to claim 1, wherein: After the conversion phase is completed for the input voltage that meets the preset voltage range, the analog voltage output by the first plate of each of the first capacitors and each of the second capacitors is equal to the common mode voltage; Wherein, a lower limit value of the preset voltage range is greater than the second reference voltage, and an upper limit value of the preset voltage range is greater than the first reference voltage.
3. The switched capacitor circuit according to claim 1, wherein: In the sampling phase, the second plate of each of the first capacitors is connected to the second reference voltage, and in the conversion phase, the second plate of each of the second capacitors is connected to the second reference voltage; or In the sampling phase, the second plate of each of the first capacitors is connected to the second reference voltage, and in the conversion phase, the second plate of each of the second capacitors is connected to the first reference voltage; or In the sampling phase, the second plate of each first capacitor is connected to the second reference voltage. In the conversion phase, the second plates of some of the second capacitors are connected to the first reference voltage, and the second plates of the remaining second capacitors are connected to the second reference voltage.
4. The switched capacitor circuit according to claim 1, wherein: The capacitor module further includes at least one third capacitor, and the first capacitor, the second capacitor, and the first plates of the third capacitor are connected to each other; In the sampling phase, the switch module further controls the first plate of each of the third capacitors to be connected to the common mode voltage, and the second plate of each of the third capacitors to be connected to the second reference voltage; In the conversion phase, the switch module further controls the first plate of each of the third capacitors to stop being connected to the common mode voltage, and the second plate of each of the third capacitors to be connected to the first reference voltage.
5. The switched capacitor circuit according to claim 1, wherein: The switch module includes a first switch unit, a second switch unit and a third switch unit; The first switch unit is used to control the voltage connected to the first plate of each of the first capacitors and each of the second capacitors; The second switch unit is used to control the voltage connected to the second plate of each of the first capacitors; The third switch unit is used to control the voltage connected to the second plate of each second capacitor.
6. The switched capacitor circuit according to claim 5, wherein: The first switch unit includes a sampling switch; The first electrode plate of each of the first capacitors and each of the second capacitors is connected to the first end of the sampling switch, and the second end of the sampling switch is connected to the common mode voltage.
7. The switched capacitor circuit according to claim 5, wherein: The second switch unit includes a plurality of first switches and a plurality of second switches; The first switches correspond to the first capacitors one by one, the first ends of the first switches are connected to the second plates of the corresponding first capacitors, and the second ends of the first switches are connected to the first reference voltage; The second switches correspond to the first capacitors one by one, a first end of the second switch is connected to the second plate of the corresponding first capacitor, and a second end of the second switch is connected to the second reference voltage.
8. The switched capacitor circuit according to claim 5, wherein: The third switch unit includes a third switch and a fourth switch; A first end of the third switch is connected to the second plate of each of the second capacitors, and a second end of the third switch is connected to the input voltage; A first end of the fourth switch is connected to the second plate of each second capacitor, and a second end of the fourth switch is connected to the second reference voltage.
9. The switched capacitor circuit according to claim 5, wherein: The capacitor module further includes at least one third capacitor, and the first capacitor, the second capacitor, and the first plates of the third capacitor are connected to each other; The switch module further includes a fourth switch unit, and the fourth switch unit is used to control the voltage connected to the second plate of the third capacitor.
10. The switched capacitor circuit according to claim 9, wherein: The fourth switch unit includes a fifth switch and a sixth switch; A first end of the fifth switch is connected to the second plate of each of the third capacitors, and a second end of the fifth switch is connected to the first reference voltage; A first end of the sixth switch is connected to the second plate of each of the third capacitors, and a second end of the sixth switch is connected to the second reference voltage.
11. A successive approximation analog-to-digital converter, characterized in that include: The switched capacitor circuit according to any one of claims 1 to 10, wherein the switched capacitor circuit is used to sample an input voltage in a sampling phase and output an analog voltage in a conversion phase; A comparison module, the comparison module is used to compare the analog voltage with the common mode voltage and output a comparison signal; A successive approximation logic module is used to input a control signal to the switch capacitor circuit according to the comparison signal, so that the analog voltage approaches the common mode voltage in a successive approximation manner.
12. A chip, characterized in that: Comprising the successive approximation analog-to-digital converter of claim 11.
13. An electronic device, characterized in that: Comprising the chip as claimed in claim 12.