Bias voltage generating circuit and electronic circuit

Abstract

The bias voltage generation circuit includes: a first constant current source that supplies a first constant current; a second constant current source that supplies a second constant current smaller than the first constant current; and a bias voltage generation unit that includes at least one first MOS transistor and generates a predetermined bias voltage on the basis of the second constant current or the first constant current and the second constant current, the bias voltage generation circuit being supplied with current from a current mirror circuit comprising the first MOS transistor and at least one second MOS transistor. On the basis of the operation mode switching control signal, the bias voltage generation circuit performs: when the electronic circuit is not operating, a bias voltage generation unit generates a predetermined bias voltage on the basis of the second constant current; when the electronic circuit operates, the bias voltage generation unit generates a predetermined bias voltage on the basis of the first constant current and the second constant current or the first constant current.

Description

Technical Field

[0001] The present invention relates to a bias voltage generating circuit and an electronic circuit having the bias voltage generating circuit. Background Art

[0002] In order to use a rechargeable battery for a long time, it is known that there is a need to reduce current consumption. For example, Patent Document 1 discloses a method in which, for example, in sleep mode, a mode is selectively switched according to an operation mode switching control signal so that current consumption becomes smaller than in operation mode.

[0003] The low-dropout (LDO) regulator disclosed in Patent Document 1 has:

[0004] (1) a pass-gate, in response to a pass-gate control signal as an operation mode switching control signal, controllably coupling a voltage rail to a regulator output; and

[0005] (2) A controllable voltage slew differential amplifier, configured to be switchable between a voltage slew limited state and a full voltage slew state, receiving feedback from the regulator output, and generating the pass gate control signal at a full voltage slew rate in the full voltage slew state based on a reference voltage and the feedback, and generating the pass gate control signal at a reduced voltage slew rate in the voltage slew limited state.

[0006] Next, a specific description will be given by taking the comparator circuit 100 according to a conventional example as an example.

[0007] Fig.17 1 is a circuit diagram showing the structure of a comparator circuit 100 according to a conventional example. Fig.18 It is shown Fig.17 FIG. 1 is a timing diagram of each signal of the operation of the comparator circuit 100 .

[0008] exist Fig.17 In the embodiment, the comparator circuit 100 includes a comparator section 101 and a bias voltage generating section 102. The comparator section 101 is a conventional comparator composed of a differential amplifier and an inverter INV1. Here, the differential amplifier includes MOS power field effect transistors (hereinafter referred to as MOS transistors) Q1 to Q7.

[0009] In the comparator section 101, MOS transistors (MOSFET, metal-oxide semiconductor field effect transistor) Q1, Q2, Q6 are P-channel MOS transistors, and MOS transistors Q3, Q4, Q5, Q7 are N-channel MOS transistors. The comparator circuit 100 has a non-inverting input terminal T1, an inverting input terminal T2, a block enable signal input terminal T3, and a comparison result signal output terminal T4. Here, during the operation of the comparator section 101, a tail current Itail flows through the MOS transistor Q5. The output voltage of the differential amplifier is output from the connection point of each drain of the MOS transistors Q6 and Q7 to the comparison result signal output terminal T4 via the inverter INV1.

[0010] In the bias voltage generating section 102, the power supply voltage VDD is connected to the sources of the MOS transistors Q1, Q2, and Q6 of the comparator section 101, and is grounded via the constant current source CI1 that supplies the reference current IREF, and the switches SW1 and SW2. The bias voltage VNBIAS is generated at the connection point between the switches SW1 and SW2, and is applied to the drain and gate of the MOS transistor Q8, and the gates of the MOS transistors Q5 and Q7. The sources of the MOS transistors Q8, Q5, and Q7 are grounded.

[0011] The block enable signal BLKEN as an action mode switching control signal input to the block enable signal input terminal T3 is input to the control terminal of the switch SW1, and is input to the control terminal of the switch SW2 via the inverter INV2. Here, when the H-level block enable signal BLKEN is input to the block enable signal input terminal T3, the switch SW1 is turned on (ON) and the switch SW2 is turned off (OFF). MOS transistors Q5, Q7, and Q8 constitute a current mirror circuit, and a current flows through the MOS transistor Q8 according to the bias voltage VNBIAS, and a current proportional to the current flows through the MOS transistors Q5 and Q7. On the other hand, when the L-level block enable signal BLKEN is input to the block enable signal input terminal T3, the switch SW1 is turned off and the switch SW2 is turned on.

[0012] In the comparator circuit 100 configured as described above, Fig.18As shown in FIG. 1 , if the block enable signal BLKEN switches from L level to H level at time t1, when the operation mode switches from sleep mode to start-up mode, the bias voltage VNBIAS rises from the pull-down state to the gate-source voltage Vgs of the MOS transistor Q8 corresponding to the reference current IREF during the start-up period, and becomes active mode at time t2. In other words, if the start-up period from time t1 to t2 is not passed, the original circuit capacity of the comparator circuit 100 cannot be exerted. The time required at this time depends on the magnitude of the reference current IREF and the parasitic capacitance value existing in the wiring of the bias voltage VNBIAS.

[0013] Prior art literature

[0014] Patent Literature

[0015] Patent Literature : Japanese Patent Application Publication No. 2019-053757 Summary of the invention

[0016] Problems to be solved by the invention

[0017] However, in the method of turning on / off a circuit that normally operates as in the prior art example as needed, even if the current consumption can be reduced, there is a problem that the circuit cannot operate stably immediately after starting as a side effect. For example, in Reference 1, a structure of turning on / off a single-side current source connected in parallel according to an operation mode for the purpose of switching the tail current Itail is disclosed. However, there is a problem that the circuit cannot operate stably immediately after starting (immediately).

[0018] The object of the present invention is to solve the above problems and to provide a bias voltage generating circuit for an electronic circuit that can start a desired operation immediately after switching the consumption current according to an operation mode switching control signal, and an electronic circuit having the internal power supply voltage generating circuit.

[0019] Means for solving problems

[0020] A bias voltage generating circuit according to a first aspect of the present invention includes:

[0021] A first constant current source, supplying a first constant current;

[0022] a second constant current source, supplying a second constant current smaller than the first constant current; and

[0023] The bias voltage generating unit includes at least one first MOS transistor, and generates a predetermined bias voltage based on the second constant current or the first constant current and the second constant current.

[0024] The bias voltage generating circuit is used in an electronic circuit and is supplied with current from a current mirror circuit composed of the first MOS transistor and at least one second MOS transistor.

[0025] The bias voltage generating circuit is configured to perform the following processing based on the action mode switching control signal:

[0026] (1) when the electronic circuit is not operating, the bias voltage generating unit generates a predetermined bias voltage based on the second constant current;

[0027] (2) When the electronic circuit is operating, the bias voltage generating unit generates a predetermined bias voltage based on the first constant current and the second constant current, or the first constant current.

[0028] Furthermore, an electronic circuit according to a second aspect of the present invention includes a bias voltage generating circuit, wherein the bias voltage generating circuit includes:

[0029] A first constant current source, supplying a first constant current;

[0030] a second constant current source, supplying a second constant current smaller than the first constant current; and

[0031] The bias voltage generating unit includes at least one first MOS transistor, and generates a predetermined bias voltage based on the second constant current or the first constant current and the second constant current.

[0032] The bias voltage generating circuit is supplied with current from a current mirror circuit composed of the first MOS transistor and at least one second MOS transistor.

[0033] The bias voltage generating circuit is configured to perform the following processing based on the operation mode switching control signal:

[0034] (1) when the electronic circuit is not operating, the bias voltage generating unit generates a predetermined bias voltage based on the second constant current;

[0035] (2) When the electronic circuit is operating, the bias voltage generating unit generates a predetermined bias voltage based on the first constant current and the second constant current, or the first constant current.

[0036] Effects of the Invention

[0037] Therefore, according to the bias voltage generating circuit or electronic circuit involved in the present invention, the gate voltage of the bias transistor is kept constant even if the current of the current source is reduced to reduce the current consumption according to the action mode switching control signal, so that the desired action can be started immediately after the action mode switching control signal is switched. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 : is a circuit diagram showing a configuration example of the comparator circuit 1 according to the first embodiment.

[0039] Figure 2 It is shown Figure 1 A timing diagram of each signal of the operation of the comparator circuit 1.

[0040] Figure 3 1 is a diagram showing a comparison of the operations of the comparator circuit 100 according to Comparative Example 1 and the comparator circuit 1 according to the embodiment, and is a timing chart of each signal when the bias voltage VNBIAS rises sufficiently to a predetermined voltage during signal detection.

[0041] Figure 4 1 is a diagram showing a comparison of the operations of the comparator circuit 100 according to Comparative Example 1 and the comparator circuit 1 according to the embodiment, and is a timing chart of each signal when the bias voltage VNBIAS has risen sufficiently to halfway to a predetermined voltage during signal detection.

[0042] Figure 5 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12A according to Modification 1.

[0043] Figure 6 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12B according to Modification Example 2.

[0044] Figure 7 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12C according to Modification 3.

[0045] Figure 8 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12D according to a fourth modification.

[0046] Fig. 9 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12E according to Modification 5.

[0047] Fig.10 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12F according to a sixth modification.

[0048] Fig.11 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12G according to Modification 7.

[0049] Fig.12 : is a circuit diagram showing a configuration example of the source follower circuit 3 according to the second embodiment.

[0050] Fig.13 : is a circuit diagram showing a configuration example of the voltage generating circuit 4 according to the third embodiment.

[0051] Fig.14 : is a circuit diagram showing a configuration example of the time constant circuit 5 according to the fourth embodiment.

[0052] Fig.15 : is a circuit diagram showing a configuration example of a comparator circuit 1A according to the fifth embodiment.

[0053] Fig.16 : is a circuit diagram showing a configuration example of a comparator circuit 1B according to the sixth embodiment.

[0054] Fig.17 2 is a circuit diagram showing a configuration of a comparator circuit 100 according to a conventional example.

[0055] Fig.18 It is shown Fig.17 FIG. 1 is a timing diagram of each signal of the operation of the comparator circuit 100 .

[0056] Fig.19 : is a circuit diagram showing the configuration of a comparator circuit 100A according to Comparative Example 1.

[0057] Fig. 20 It is shown Fig.19 FIG. 1 is a timing diagram of each signal of the operation of the comparator circuit 100A.

[0058] Fig.21 : is a circuit diagram showing the configuration of a comparator circuit 100B according to Comparative Example 2. DETAILED DESCRIPTION

[0059] Hereinafter, comparative examples, embodiments and modifications according to the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are attached to the same or similar components.

[0060] (Inventor's opinion)

[0061] The embodiment of the present invention is characterized in that the circuit current is reduced when it is not necessary, and when it is necessary to perform an operation immediately, in order to reduce the current consumption, the gate voltage of the bias generating transistor is kept constant even if the current of the current source is reduced.

[0062] (Comparative Example 1)

[0063] Fig.19is a circuit diagram showing a configuration example of a comparator circuit 100A according to Comparative Example 1. Fig. 20 It is shown Fig.19 FIG. 1 is a timing diagram of each signal of the operation of the comparator circuit 100A. Fig.19 The comparator circuit 100A is similar to the Fig.17 The comparator circuit 100 is different.

[0064] (1) A comparator unit 101A is provided in place of the comparator unit 101, and the comparator unit 101A further includes a circuit for generating a preliminary current Itailp ( Fig. 20 ) of constant current sources CI11 and CI12.

[0065] According to the comparative example configured as described above, in order to facilitate operation immediately after startup, the comparator unit 101A is configured so that a small amount of preliminary current Itailp ( Fig. 20 ), although the circuit current is small, the comparator unit 101A can also operate.

[0066] However, even if the comparator unit 101A wants to operate at the small standby current Itailp in Comparative Example 1, it takes the same amount of time as the circuit without countermeasures to perform the expected circuit operation. In addition, each target current path requires a standby current, and the more current paths there are, the larger the standby current needs to be.

[0067] Fig.21 : is a circuit diagram showing the configuration of a comparator circuit 100B according to Comparative Example 2. Fig.21 The comparator circuit 100B is similar to the Fig.17 The comparator circuit 100 is different.

[0068] (1) A comparator unit 101B is provided in place of the comparator unit 101. The connection point between the sources of the MOS transistors Q3 and Q4 is grounded via the switch SW3 and the MOS transistor Q5. In addition, the drain of the MOS transistor Q6 is grounded via the switch SW4 and the MOS transistor Q7. When the block enable signal BLKEN is at the H level, the switches SW3 and SW4 are turned on, and when the block enable signal BLKEN is at the L level, the switches SW3 and SW4 are turned off.

[0069] (2) A bias voltage generating unit 102B is provided in place of the bias voltage generating unit 102. Here, the power supply voltage VDD is grounded via the constant current source CI11 and the MOS transistor Q8.

[0070] According to the comparative example 2 constructed as described above, in order to operate immediately after startup (immediately), the current path is cut off to reduce consumption while the bias voltage VNBIAS is always applied to the gates of the MOS transistors Q5 and Q7. However, although the reduction of the circuit current and the start-up time countermeasure can be taken into account at the same time, the reference current IREF cannot be reduced.

[0071] Embodiments of the present invention will be described below with respect to a bias voltage generating circuit that can solve these problems and an electronic circuit including the bias voltage generating circuit.

[0072] (Implementation method 1)

[0073] Figure 1 is a circuit diagram showing a configuration example of a comparator circuit 1 according to Embodiment 1. Figure 2 It is shown Figure 1 A timing diagram of each signal of the operation of the comparator circuit 1.

[0074] exist Figure 1 In the embodiment, the comparator circuit 1 includes a comparator unit 11 and a bias voltage generating unit 12. The comparator unit 11 is composed of a differential amplifier and an inverter INV1 to form a comparator. Fig.17 Compared with the comparator unit 101 of FIG. 1 , the differential amplifier further includes switches SW3 and SW4. Here, the differential amplifier is configured to include MOS transistors Q1 to Q7. The connection point between the sources of the MOS transistors Q3 and Q4 is grounded via the switch SW3 and the MOS transistor Q5. In addition, the drain of the MOS transistor Q6 is grounded via the switch SW4 and the MOS transistor Q7.

[0075] In the comparator section 11, MOS transistors Q1, Q2, and Q6 are P-channel MOS transistors, and MOS transistors Q3, Q4, Q5, and Q7 are N-channel MOS transistors. The comparator circuit 1 has a non-inverting input terminal T1, an inverting input terminal T2, a block enable signal input terminal T3, and a comparison result signal output terminal T4. Here, in the operation of the comparator section 11, the tail current Itail flows through the MOS transistor Q5. The output voltage of the differential amplifier is output to the comparison result signal output terminal T4 from the connection point of each drain of the MOS transistors Q6 and Q7 via the inverter INV1.

[0076] In the bias voltage generation unit 12, the power supply voltage VDD is connected to the sources of the MOS transistors Q1, Q2, and Q6 of the comparator unit 11, and is grounded via a constant current source CI21 that supplies a first reference current IREFL, switches SW1 and SW2, and a MOS transistor Q9. In addition, the power supply voltage VDD is grounded via a constant current source CI22 that supplies a second reference current IREFS (<IREFL) and MOS transistors Q8 and Q9. A bias voltage VNBIAS is generated at the connection point of the switches SW1 and SW2 and is applied to the drain and gate of the MOS transistor Q8, the gate of the MOS transistor Q9, and the gates of the MOS transistors Q5 and Q7. The sources of the MOS transistors Q9, Q5, and Q7 are grounded.

[0077] A block enable signal BLKEN, which is an operation mode switching control signal, input to the block enable signal input terminal T3 is input to the control terminals of the switch SW1 and the switch SW2. Here, when the H-level block enable signal BLKEN is input to the block enable signal input terminal T3, the switches SW1 and SW2 are turned on. The MOS transistors Q5, Q7, and Q9 form a current mirror circuit, and a current flows through the MOS transistor Q9 according to the bias voltage VNBIAS, and currents proportional to this current flow through the MOS transistors Q5 and Q7. On the other hand, when the L-level block enable signal BLKEN is input to the block enable signal input terminal T3, the switches SW1 and SW2 are turned off. In addition, the gates of the MOS transistors Q1 to Q9 are control terminals.

[0078] In the comparator circuit 1 configured as described above, as Figure 2 shown, at time t11, the block enable signal BLKEN is switched from the L level to the H level, and the operation mode is switched from the sleep mode to the active mode. Here,

[0079] (1) In the sleep mode (when the comparator circuit 1 is not operating), the switches SW1 and SW2 are both off, and only the constant current source CI22 causes a constant current IREFS to flow through the series circuit of the MOS transistors Q8 and Q9. As a result, a bias voltage VBIAS (Itailpe = 0) corresponding to this constant current IREFS is generated.

[0080] (2) In the active mode (when the comparator circuit 1 is operating), the switches SW1 and SW2 are both on, and the constant current sources CI21 and CI22 cause constant currents IREFL and IREFS to flow through the MOS transistor Q9, respectively. As a result, a bias voltage VBIAS corresponding to this constant current (IREFL + IREFS) is generated, and a tail current Itail corresponding to the constant current (IREFL + IREFS) flows through the MOS transistor Q5.

[0081] That is, by switching the size of the MOS transistors on the diode-connected (gate-drain connected) (connecting the gate and the drain) side of the current mirror circuit formed by MOS transistors Q8, Q9, Q5, and Q7, the bias voltage VBIAS generated by the constant current IREFS after the current is reduced in the sleep mode and the bias voltage VBIAS generated by the constant current IREFL+IREFS that is originally intended to flow in the active mode are added, so that at time t11, a tail current Itail corresponding to the added value of the two constant currents IREFL and IREFS can flow immediately.

[0082] Figure 3 1 is a diagram showing a comparison of the operation of the comparator circuit 100 according to Comparative Example 1 and the comparator circuit 1 according to the embodiment, and is a timing diagram of each signal when the bias voltage VNBIAS rises sufficiently to a predetermined voltage during signal detection. Figure 4 1 is a diagram showing a comparison of the operations of the comparator circuit 100 according to Comparative Example 1 and the comparator circuit 1 according to the embodiment, and is a timing chart of each signal when the bias voltage VNBIAS has risen sufficiently to halfway to a predetermined voltage during signal detection.

[0083] from Figure 3 as well as Figure 4 Obviously, in Comparative Example 1, when the detection is to be performed, when the bias voltage VBIAS is sufficiently increased ( Figure 3 ) and the midway point of the ascent ( Figure 4 ), a difference is generated in the detection delay time. That is, Ta1≠Tb1. In contrast, in embodiment 1, the prescribed tail current Itail can be made to flow out immediately after the block enable signal BLKEN rises from the L level to the H level (at time t11). That is, in these two cases, there is no difference in the detection delay time, Ta2=Tb2. In addition, compared with the consumption current ICc of comparative example 1, the consumption current Ice of embodiment 1 in sleep mode is less. As described above, compared with the comparative example, embodiment 1 has the above-mentioned unique effects.

[0084] As described above, according to the first embodiment, a desired comparison operation can be started immediately after switching to an increased consumption current in accordance with the block enable signal BLKEN as an operation mode switching control signal.

[0085] (Variant 1)

[0086] Figure 5 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12A according to Modification 1. Figure 5 The bias voltage generating unit 12A is similar to the bias voltage generating unit 12A in the following aspects. Figure 1is different from the bias voltage generation unit 12.

[0087] (1) The gates and drains of the MOS transistors Q8 and Q9 are diode-connected (gate-drain connected).

[0088] In addition, the Figure 1 comparator unit 11 is used.

[0089] The comparator circuit having the bias voltage generation unit 12A configured as described above operates in the same manner as the comparator circuit 1 of Embodiment 1 except for the operation differences in the above structure.

[0090] (Modified Example 2)

[0091] Figure 6 FIG. is a circuit diagram showing a structural example of the bias voltage generation unit 12B according to Modified Example 2. Figure 6 The bias voltage generation unit 12B of Figure 1 is different from the bias voltage generation unit 12 of

[0092] (1) The power supply voltage VDD is grounded via a constant current source CI21 that supplies a constant current IREFL, a switch SW1, a switch SW2, and a MOS transistor Q9a having a threshold voltage VthS.

[0093] (2) The power supply voltage VDD is grounded via a constant current source CI22 that supplies a constant current IREFS (<IREFL), the connection point of SW1 and SW2, a switch SW5, and a MOS transistor Q9b having a threshold voltage VthL (>VthS). In addition, the connection point of SW1 and SW2 is connected to the gate of the MOS transistor Q9a and the gate of the MOS transistor Q9b.

[0094] (3) The block enable signal BLKEN is applied to the control terminals of the switches SW1 and SW2, and is also applied to the control terminal of the switch SW5 via an inverter INV3.

[0095] In addition, the Figure 1 comparator unit 11 is used.

[0096] In the bias voltage generation unit 12B configured as described above, when an L-level block enable signal BLKEN is input, the switch SW5 is turned on and the switches SW1 and SW2 are turned off. In addition, when an H-level block enable signal BLKEN is input, the switch SW5 is turned off and the switches SW1 and SW2 are turned on.

[0097] The comparator circuit having the bias voltage generation unit 12B configured as described above operates in the same manner as the comparator circuit 1 of Embodiment 1 except for the operation differences in the above structure.

[0098] (Variant 3)

[0099] Figure 7 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12C according to Modification 3. Figure 7 The bias voltage generating unit 12C is similar to the bias voltage generating unit 12C in the following aspects. Figure 1 The bias voltage generating unit 12 is different.

[0100] (1) A resistor R1 is provided instead of the MOS transistor Q8.

[0101] In addition, use Figure 1 The comparator section 11.

[0102] The comparator circuit including the bias voltage generating unit 12C configured as described above operates in the same manner as the comparator circuit 1 of the first embodiment except for the operational difference in the above-described configuration.

[0103] (Variant 4)

[0104] Figure 8 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12D according to a fourth modification. Figure 8 The bias voltage generating unit 12D is similar to the bias voltage generating unit 12D in the following aspects. Figure 5 The bias voltage generating unit 12A is different.

[0105] (1) A resistor R1 is provided instead of the MOS transistor Q8.

[0106] In addition, use Figure 1 The comparator section 11.

[0107] The comparator circuit including the bias voltage generating unit 12D configured as described above operates in the same manner as the comparator circuit of the first modification except for the operational difference in the above configuration.

[0108] (Variant 5)

[0109] Fig. 9 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12E according to Modification 5. Fig. 9 The bias voltage generating unit 12E is similar to the bias voltage generating unit 12E in the following aspects. Figure 7 The bias voltage generating unit 12C is different.

[0110] (1) A diode D1 is provided instead of the resistor R1. Here, the anode of the diode D1 is connected to the constant current source CI22, and the cathode is connected to the drain and gate of the MOS transistor Q9.

[0111] In addition, use Figure 1 The comparator section 11.

[0112] The comparator circuit having the bias voltage generating unit 12E configured as described above operates in the same manner as the comparator circuit of the third modification except for the operational difference in the above configuration.

[0113] (Variant 6)

[0114] Fig.10 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12F according to a sixth modification. Fig.10 The bias voltage generating unit 12F is similar to the bias voltage generating unit 12F in the following aspects. Figure 8 The bias voltage generating unit 12D is different.

[0115] (1) A diode D1 is provided instead of the resistor R1. Here, the anode of the diode D1 is connected to the constant current source CI22, and the cathode is connected to the drain and gate of the MOS transistor Q9.

[0116] In addition, use Figure 1 The comparator section 11.

[0117] The comparator circuit having the bias voltage generating unit 12F configured as described above operates in the same manner as the comparator circuit of the fourth modification except for the operational difference in the above configuration.

[0118] (Variant 7)

[0119] Fig.11 : is a circuit diagram showing a configuration example of a bias voltage generating unit 12G according to Modification 7. Fig.11 The bias voltage generating unit 12G is similar to the bias voltage generating unit 12G in the following aspects. Figure 5 The bias voltage generating unit 12A is different.

[0120] (1) A diode D2 is provided instead of the MOS transistor Q9. Here, the anode of the diode D2 is connected to the source of the MOS transistor Q8, and the cathode is grounded.

[0121] (2) The switch SW2 is connected to both ends of the diode D2 , and the both ends of the diode D2 are short-circuited or opened based on the block enable signal BLKEN.

[0122] In addition, use Figure 1 The comparator section 11.

[0123] The comparator circuit having the bias voltage generating unit 12G configured as described above operates in the same manner as the comparator circuit of the first modification except for the operational difference in the above configuration.

[0124] Furthermore, the MOS transistor, the resistor, and the diode used in the above-described first embodiment and modifications 1 to 7 may also be arranged on the ground side of the MOS transistor serving as a reference of the current mirror circuit.

[0125] (Implementation method 2)

[0126] Fig.12 This is a circuit diagram showing a configuration example of a source follower circuit 3 according to the second embodiment.

[0127] exist Fig.12 In the embodiment, the source follower circuit 3 has an input terminal T11, an output terminal T12, and a block enable signal input terminal T3, and is configured to have Figure 1 The bias voltage generating unit 12, the MOS transistor Q4, the switch SW5, and the MOS transistor Q10 are formed. Here, the MOS transistors Q4 and Q10 are formed of N-channel MOS transistors.

[0128] The power supply voltage VDD is grounded via the MOS transistor Q4, the switch SW5, and the MOS transistor Q10. The bias voltage VBIAS is applied to the gate of the MOS transistor Q10. The input voltage VIN is input to the input terminal T11, and when the source follower circuit 3 operates, the output voltage Vout obtained by buffering the input voltage VIN is output from the output terminal T12.

[0129] In the source follower circuit 3 constructed as described above, when the block enable signal BLKEN of the L level is applied, the switches SW1 and SW2 are turned off, and the constant current source CI22 in the bias voltage generating unit 12 operates. In addition, if the block enable signal BLKEN of the H level is applied, the constant current sources CI21 and CI22 operate, and the constant current increases from IREFS to (IREFS+IREFL), and the increased bias voltage VBIAS corresponding to the current is applied to the gate of the MOS transistor Q10.

[0130] In the source follower circuit 3 constructed as described above, the block enable signal BLKEN is switched from the L level to the H level, and the operation mode is switched from the sleep mode to the active mode. At this time, as described above, the constant current sources CI21 and CI22 operate, and the constant current increases from IREFS to (IREFS+IREFL), and the increased bias voltage VBIAS corresponding to the current is applied to the gate of the MOS transistor Q10, which can immediately put the source follower circuit 3 into operation.

[0131] As described above, according to the second embodiment, a desired buffering operation can be started immediately after switching to an increased consumption current in accordance with the block enable signal BLKEN as an operation mode switching control signal.

[0132] in addition, Fig.12 The bias voltage generating section can also be composed of Figure 5~Figure 11 The bias voltage generating units 12A to 12G of the modified examples 1 to 7 are replaced by Fig.12 It is composed of a bias voltage generating unit.

[0133] (Implementation method 3)

[0134] Fig.13 : is a circuit diagram showing a configuration example of the voltage generating circuit 4 according to the third embodiment. Fig.13 The voltage generating circuit 4 is similar to the Fig.12 The source follower circuit 3 is different.

[0135] (1) The resistor R2 is provided instead of the MOS transistor Q4.

[0136] The voltage generating circuit 4 configured as described above can operate when the block enable signal BLKEN at the H level is inputted, and can generate and output a predetermined voltage determined by the resistor R2 and the MOS transistor Q10 from the output terminal T12 .

[0137] As described above, according to the third embodiment, it is possible to start a desired voltage generation operation immediately after switching to an increased consumption current in accordance with the block enable signal BLKEN as an operation mode switching control signal.

[0138] in addition, Fig.13 The voltage generating circuit 4 can also be composed of Figure 5~Figure 11 The bias voltage generating units 12A to 12G of the modified examples 1 to 7 are replaced by Fig.13 It is composed of a bias voltage generating unit.

[0139] (Implementation method 4)

[0140] Fig.14 : is a circuit diagram showing a configuration example of the time constant circuit 5 according to the fourth embodiment. Fig.14 The time constant circuit 5 is similar to Fig.13 The voltage generating circuit 4 is different.

[0141] (1) A capacitor C1 is provided instead of the resistor R2.

[0142] The time constant circuit 5 configured as described above can operate when the block enable signal BLKEN at the H level is input, and generates and outputs a voltage decreasing by a predetermined time constant determined by the current value of the capacitor C1 and the MOS transistor Q10 from the output terminal T12 .

[0143] As described above, according to the fourth embodiment, it is possible to start the voltage generation operation having a predetermined time constant immediately after the consumption current is switched to the increased current in accordance with the block enable signal BLKEN as the operation mode switching control signal.

[0144] in addition, Fig.14 The time constant of circuit 5 can also be composed of Figure 5~Figure 11 The bias voltage generating units 12A to 12G of the modified examples 1 to 7 are replaced by Fig.14 It is composed of a bias voltage generating unit.

[0145] (Implementation method 5)

[0146] Fig.15 : is a circuit diagram showing a configuration example of a comparator circuit 1A according to the fifth embodiment. Fig.15 The comparator circuit 1A is similar to Figure 1 The comparator circuit 1 is different.

[0147] (1) MOS transistors Q11 to Q17 are provided instead of MOS transistors Q1 to Q7. Here, MOS transistors Q13 to Q15 and Q17 are P-channel MOS transistors, and MOS transistors Q11 to Q12 and Q16 are N-channel MOS transistors.

[0148] (2) Switches SW11 to SW14 are provided instead of the switches SW1 to SW4 .

[0149] As described above, by replacing some of the N-channel MOS transistors with P-channel MOS transistors, it is possible to use the transistors not only as a current source on the ground side but also as a current source on the power supply side. This is also the case in the second to fourth embodiments.

[0150] The comparator circuit 1A configured as described above can operate when the block enable signal BLKEN at the H level is input, and allows a current corresponding to IREFL+IREFS to flow through the MOS transistors Q15 and Q17.

[0151] As described above, according to the fifth embodiment, a desired comparison operation can be started immediately after the consumption current is switched to an increased state according to the block enable signal BLKEN as the operation mode switching control signal.

[0152] in addition, Fig.15 The bias voltage generating section can also be composed of Figure 5~Figure 11The circuits of Modifications 1 to 7 are replaced by Fig.15 The circuit is composed of.

[0153] (Implementation method 6)

[0154] Fig.16 : is a circuit diagram showing a configuration example of a comparator circuit 1B according to the sixth embodiment. Fig.16 The comparator circuit 1B is similar to Figure 1 The comparator circuit 1 is different.

[0155] (1) A bias voltage generating section 12H in which a switch SW11 is inserted is provided between the constant current source CI22 and the drain of the MOS transistor Q8.

[0156] (2) The block enable signal BLKEN is also input to the control terminal of the switch SW11 via the inverter INV11. That is, the bias voltage generating unit 12H generates a predetermined bias voltage based on the second constant current when the electronic circuit is not operating, and generates another predetermined bias voltage based on the first constant current when the electronic circuit is operating.

[0157] In the comparator circuit 1B configured as described above, when the block enable signal BLKEN is at the L level, the switch SW11 is turned on, and a current corresponding to IREFS can flow through the MOS transistors Q8 and Q9.

[0158] As described above, according to the sixth embodiment, a desired comparison operation can be started immediately after the consumption current is switched to an increased state according to the block enable signal BLKEN as the operation mode switching control signal.

[0159] (Other variations)

[0160] In the above embodiments and modifications, a comparator circuit, a source follower circuit, a voltage generating circuit, and a time constant circuit are configured, but the present invention is not limited thereto, and various other electronic circuits such as a differential amplifier circuit may be configured.

[0161] Industrial Applicability

[0162] As described in detail above, according to the bias voltage generating circuit or electronic circuit involved in the present invention, since the control signal is switched according to the action mode, in order to reduce the current consumption, the gate voltage of the bias transistor is kept constant even if the current of the current source is reduced, so that the desired action can be started immediately after the action mode switching control signal is switched.

[0163] Description of Reference Numerals

[0164] 1.1A, 1B Comparator Circuit

[0165] 3 Source Follower Circuit

[0166] 4 Voltage generation circuit

[0167] 5 Time constant circuit

[0168] 11 Comparator section

[0169] 12, 12A~12H Bias voltage generation unit

[0170] 100, 100A, 100B Comparator Circuit

[0171] 101, 101A, 101B Comparator section

[0172] 102, 102B bias voltage generating unit

[0173] C1 capacitor

[0174] CI1~CI32 Constant current source

[0175] D1, D2 diodes

[0176] INV1~INV11 Inverter

[0177] Q1~Q17, Q9a, Q9b MOS transistors

[0178] R1~R2 resistors

[0179] SW1~SW14 switch

[0180] T1~T12 terminal

Claims

1. A bias voltage generating circuit, comprising: A first constant current source, supplying a first constant current; a second constant current source, supplying a second constant current smaller than the first constant current; and The bias voltage generating unit includes at least one first MOS transistor and generates a predetermined bias voltage based on the second constant current or the first constant current and the second constant current. The bias voltage generating circuit is used in an electronic circuit and is supplied with current by a current mirror circuit formed by the first MOS transistor and at least one second MOS transistor. The bias voltage generating circuit is configured to perform the following operations based on the operation mode switching control signal: (1) when the electronic circuit is not operating, the bias voltage generating unit generates a predetermined bias voltage based on the second constant current; (2) When the electronic circuit is operating, the bias voltage generating unit generates a predetermined bias voltage based on the first constant current and the second constant current, or the first constant current.

2. The bias voltage generating circuit according to claim 1, wherein: The at least one first MOS transistor includes two MOS transistors connected in series with each other, and control terminals of the two MOS transistors are connected with each other.

3. The bias voltage generating circuit according to claim 1, wherein: The at least one first MOS transistor includes two MOS transistors connected in series with each other, and the two MOS transistors are respectively connected by diodes.

4. The bias voltage generating circuit according to claim 1, wherein: The at least one first MOS transistor includes two MOS transistors connected in parallel to each other and having different threshold values.

5. The bias voltage generating circuit according to claim 1, wherein: The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor, the first resistor is connected to the second constant current source, A control terminal of the third MOS transistor is connected to a connection point of the second constant current source and the resistor.

6. The bias voltage generating circuit according to claim 1, wherein: The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor, the first resistor is connected to the second constant current source, The third MOS transistor is diode-connected.

7. The bias voltage generating circuit according to claim 1, wherein: The at least one first MOS transistor includes a third MOS transistor connected in series with a first diode, the first diode being connected to the second constant current source, The third MOS transistor is diode-connected.

8. The bias voltage generating circuit according to claim 1, wherein: The at least one first MOS transistor is configured such that a third MOS transistor connected to the second constant current source is connected in series with a second diode, The third MOS transistor is diode-connected.

9. An electronic circuit having a bias voltage generating circuit, The bias voltage generating circuit comprises: A first constant current source, supplying a first constant current; a second constant current source, supplying a second constant current smaller than the first constant current; and The bias voltage generating unit includes at least one first MOS transistor and generates a predetermined bias voltage based on the second constant current or the first constant current and the second constant current. The bias voltage generating circuit is supplied with current from a current mirror circuit composed of the first MOS transistor and at least one second MOS transistor. The bias voltage generating circuit is configured to perform the following operations based on the operation mode switching control signal: (1) when the electronic circuit is not operating, the bias voltage generating unit generates a predetermined bias voltage based on the second constant current; (2) When the electronic circuit is operating, the bias voltage generating unit generates a predetermined bias voltage based on the first constant current and the second constant current, or the first constant current.

10. The electronic circuit of claim 9, wherein: The at least one first MOS transistor includes two MOS transistors connected in series with each other, and control terminals of the two MOS transistors are connected with each other.

11. The electronic circuit of claim 9, wherein: The at least one first MOS transistor includes two MOS transistors connected in series with each other, and the two MOS transistors are respectively connected by diodes.

12. The electronic circuit of claim 9, wherein: The at least one first MOS transistor includes two MOS transistors connected in parallel to each other and having different threshold values.

13. The electronic circuit of claim 9, wherein: The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor, the first resistor is connected to the second constant current source, A control terminal of the third MOS transistor is connected to a connection point of the second constant current source and the resistor.

14. The electronic circuit of claim 9, wherein: The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor, the first resistor is connected to the second constant current source, The third MOS transistor is diode-connected.

15. The electronic circuit of claim 9, wherein: The at least one first MOS transistor includes a third MOS transistor connected in series with a first diode, the first diode being connected to the second constant current source, The third MOS transistor is diode-connected.

16. The electronic circuit of claim 9, wherein: The at least one first MOS transistor is configured such that a third MOS transistor connected to the second constant current source is connected in series with a second diode, The third MOS transistor is diode-connected.

17. An electronic circuit as claimed in any one of claims 9 to 16, wherein: The electronic circuit is a comparator circuit, a source follower circuit, a voltage generating circuit, a time constant circuit, or a differential amplifier circuit.

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