Storage space management method of memory device, memory controller, memory device and electronic device

Abstract

The invention provides a method for storage space management of a memory device with aid of dynamic block configuration and a related apparatus. The method may include configuring at least a portion of the plurality of blocks into a plurality of first blocks in a first region and a plurality of second blocks in a second region according to a first reserved block threshold; combining the plurality of first blocks into a group of first super blocks in the first area; and combining at least a portion of the plurality of second blocks into a set of second super blocks in the second region, the first reserved block threshold being less than a minimum number of non-corrupted blocks in respective numbers of non-corrupted blocks of a plurality of planes, therefore, the memory controller increases the available storage capacity by increasing the ratio of the size of the second area to the size of the first area.

Description

Technical Field

[0001] The present invention relates to memory control, and more particularly to a method for managing storage space of a memory device by means of dynamic block configuration and related apparatus such as a memory controller of the memory device, the memory device and an electronic device including the memory device. Background Art

[0002] According to the related art, a memory device may be designed to have the ability to simultaneously access the respective storage cells of multiple flash memory chips therein to improve the throughput of data access, which may cause certain problems. In particular, the multiple flash memory chips may have damaged storage cells. If some storage cells in a group of storage cells to be accessed simultaneously are damaged, the operation of accessing this group of storage cells may not be successful, which may reduce the overall performance. The related art attempts to solve this problem, however, it may introduce more problems such as certain side effects. For example, when flash memory manufacturers try to increase storage capacity by increasing the three-dimensional (3D) NAND flash stacking architecture, the process yield may decrease and / or the average number of damaged storage cells increases, which may cause the memory device using 3D NAND flash memory to fail the test for sufficient storage capacity (hereinafter referred to as "sufficient capacity"). Therefore, a novel method and related architecture are needed to solve these problems without introducing any side effects or in a way that is unlikely to introduce side effects. Summary of the invention

[0003] Therefore, one of the objects of the present invention is to provide a method for managing the storage space of a memory device by means of dynamic block configuration and related equipment such as a memory controller of the memory device, the memory device and an electronic device including the memory device to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a method for managing storage space of a memory device by means of dynamic block allocation, wherein the method can be applied to a memory controller of the memory device. The memory device can include the memory controller and a non-volatile (NV) memory, the non-volatile memory can include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element can include multiple blocks. The method can include: using the memory controller to allocate a first reserved block threshold (reserved block threshold) according to the first reserved block threshold. threshold) to configure at least a portion of the plurality of blocks into a plurality of first blocks in a first area and a plurality of second blocks in a second area to reserve the plurality of first blocks for data access, wherein any block of the plurality of blocks belongs to a plane of a plurality of planes of the at least one non-volatile memory element, so as to allow the memory controller to configure the blocks respectively belonging to the plurality of planes into a super block; and combine the plurality of first blocks into a group of first super blocks in the first area, wherein the number of blocks of the first blocks in each first super block of the group of first super blocks is equal to one A first predetermined number of blocks, and a number of super blocks of the group of first super blocks is equal to the first reserved block threshold; and at least a portion of the second blocks among the plurality of second blocks are combined into a group of second super blocks in the second area, wherein the number of blocks of the second blocks in each second super block in the group of second super blocks is less than the first predetermined number of blocks, and the first reserved block threshold is less than a minimum number of non-damaged blocks among the respective numbers of non-damaged blocks of the plurality of planes, so that the memory controller increases an available storage capacity of the memory device by increasing the ratio of the size of the second area to the size of the first area.

[0005] In addition to the above method, the present invention further provides a memory controller of a memory device, wherein the memory device may include the memory controller and a non-volatile memory. The non-volatile memory may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element may include multiple blocks. In addition, the memory controller includes a processing circuit, which is used to control the memory controller according to multiple host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, wherein the processing circuit is used to manage the storage space of the memory device by means of dynamic block configuration. The memory controller also includes a transmission interface circuit, and the transmission interface circuit is used to communicate with the host device. For example, the memory controller configures at least a portion of the plurality of blocks into a plurality of first blocks in a first region and a plurality of second blocks in a second region according to a first reserved block threshold, so as to reserve the plurality of first blocks for data access, wherein any block of the plurality of blocks belongs to a plane of a plurality of planes of the at least one non-volatile memory element, so as to allow the memory controller to configure the blocks respectively belonging to the plurality of planes into a super block; the memory controller combines the plurality of first blocks into a group of first super blocks in the first region, wherein the first block in each first super block of the group of first super blocks The number of blocks of the plurality of first super blocks is equal to a first predetermined number of blocks, and a number of super blocks of the group of first super blocks is equal to the first reserved block threshold; and the memory controller combines at least a portion of the second blocks among the plurality of second blocks into a group of second super blocks in the second area, wherein the number of blocks of the second blocks in each second super block in the group of second super blocks is less than the first predetermined number of blocks, and the first reserved block threshold is less than a minimum number of non-damaged blocks among the respective numbers of non-damaged blocks of the plurality of planes, so that the memory controller increases an available storage capacity of the memory device by increasing the ratio of the size of the second area to the size of the first area.

[0006] In addition to the above method, the present invention further provides the memory device including the above memory controller, wherein the memory device includes the non-volatile memory and the memory controller. The non-volatile memory is used to store information. The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

[0007] In addition to the above method, the present invention further provides a related electronic device. The electronic device may include the above memory device, and may further include: the host device, which is coupled to the memory device. The host device may include: at least one processor, which is used to control the operation of the host device; and a power supply circuit, which is coupled to the at least one processor and is used to provide power to the at least one processor and the memory device. In addition, the memory device can provide storage space for the host device.

[0008] According to certain embodiments, the device may include at least a portion (e.g., a portion or all) of the electronic device. For example, the device may include the memory controller in the memory device. For another example, the device may include the memory device. As another example, the device may include the host device. In some examples, the device may include the electronic device.

[0009] According to some embodiments, the memory controller in the memory device may control the operation of the memory device according to the method, and the memory device may be disposed in the electronic device. In addition, the memory device may store data for the host device. The memory device may read the stored data in response to a host command from the host device, and provide the data read from the non-volatile memory to the host device.

[0010] The method and related apparatus of the present invention can ensure that the memory device can operate properly in different situations. In particular, at least one reserved block threshold can be dynamically adjusted to configure a first group of blocks and a second group of blocks in the plurality of blocks of the non-volatile memory as super blocks corresponding to a first plane count per superblock and a second plane count per superblock, respectively, so as to properly reserve super blocks with maximum throughput (regarding data access) and maximize the total storage capacity of the memory device as much as possible, so as to take into account the requirements of achieving storage capacity specifications and data access performance. In addition, the method and apparatus of the present invention can solve the problems of the related art without introducing any side effects or in a manner that is unlikely to introduce side effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 A block combination control scheme is shown.

[0013] Figure 3AAn example of bad block distribution before replacement processing of a block replacement control scheme is shown.

[0014] Figure 3B Some implementation details of an example of block combination after the permutation process of the block permutation control scheme is shown.

[0015] Figure 3C Some other implementation details of the above block combination example after the replacement process of the block replacement control scheme is completed are illustrated.

[0016] Figure 4 A flow chart of a method for managing storage space of a memory device by means of dynamic block allocation is shown according to an embodiment of the present invention.

[0017] Figure 5 A storage space enlargement control scheme of the method is described according to an embodiment of the present invention.

[0018] Fig. 6A An example of a set of original boundary blocks in the storage space augmentation control scheme is shown.

[0019] Figure 6B An example of a set of first boundary blocks in the storage space enlargement control scheme is shown.

[0020] Figure 6C An example of a set of second boundary blocks in the storage space enlargement control scheme is shown.

[0021] Fig.6D Another example of a set of boundary blocks in the storage space enlargement control scheme is shown.

[0022] Figure 7 According to an embodiment of the present invention, a workflow of a predetermined setting procedure of the method is illustrated.

[0023]

Explanation of symbols

[0024] 10: Electronic devices

[0025] 50: Host device

[0026] 52: Processor

[0027] 54: Power supply circuit

[0028] 58: Transmission interface circuit

[0029] 100: memory device

[0030] 110: memory controller

[0031] 112: Microprocessor

[0032] 112C: Program code

[0033] 112M: Read-only memory

[0034] 114: Control logic circuit

[0035] 116: Random Access Memory

[0036] 116AM: Temporary logical to physical (L2P) address mapping table

[0037] 116BR: Temporary bad block replacement (BR) management table

[0038] 118: Transmission interface circuit

[0039] 120: Non-volatile (NV) memory

[0040] 120AM: Global logical to physical (L2P) address mapping table

[0041] 120BR: Bad Block Replacement (BR) Management Table

[0042] 122-1~122-N E :Non-volatile (NV) memory devices

[0043] S10~S12, S20~S32: Steps

[0044] CH0~CH3: Channel

[0045] PL0~PL5: Flat surface

[0046] PLANE: Global plane

[0047] Fblock: Entity block

[0048] Fb0, Fb1: physical block number

[0049] XBLK(1)~XBLK(567):Super Block

[0050] XBL MAX_THROUGHPUT :Maximum throughput superblock

[0051] XBL LOWER_THROUGHPUT : Smaller throughput superblocks

[0052] R MAX_THROUGHPUT (0),R MAX_THROUGHPUT (1): Maximum throughput superblock area

[0053] R REMAIN (1): Other areas

[0054] R(1), R(2): sub-region

[0055] PLANE MAX :Total number of planes

[0056] WAY(0),WAY(1)~WAY(WAY TOTAL -1):Road DETAILED DESCRIPTION

[0057] Figure 1 1 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors), which may be collectively referred to as a processor 52, and includes a power supply circuit 54 and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other via a bus, and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more driving voltages to the memory device 100, wherein the memory device 100 may provide storage space for the host device 50, and may obtain the one or more driving voltages from the host device 50 as a power supply for the memory device 100. Examples of the host device 50 may include (but are not limited to): a multi-function mobile phone, a tablet computer, a wearable device, and a personal computer, such as a desktop computer and a notebook computer. Examples of the memory device 100 may include (but are not limited to): portable memory devices (e.g., memory cards conforming to SD / MMC, CF, MS or XD specifications, solid state drives (SSDs), and various types of embedded memory devices (e.g., embedded memory devices conforming to universal flash storage (UFS) specifications or embedded multi-media card (eMMC) specifications). According to this embodiment, the memory device 100 may include a controller such as a memory controller 110, and may further include a non-volatile (NV) memory 120, wherein the controller is used to access the NV memory 120, and the NV memory 120 is used to store information. The NV memory 120 may include at least one NV memory element (e.g., one or more NV memory elements), such as a plurality of NV memory elements 122-1, 122-2, ..., and 122-N. E , where "N E" may represent a positive integer greater than 1. For example, the NV memory 120 may be a flash memory, and the plurality of NV memory elements 122-1, 122-2, ..., and 122-N may be E They may be a plurality of flash memory chips or a plurality of flash memory dies, but the present invention is not limited thereto.

[0058] like Figure 1 As shown, the memory controller 110 may include a processing circuit such as a microprocessor 112, a storage unit such as a read only memory (ROM) 112M, a control logic circuit 114, a random access memory (RAM) 116 (for example, it can be implemented by a static random access memory) and a transmission interface circuit 118, wherein at least a portion (for example, a portion or all) of the above components can be coupled to each other via a bus. The random access memory 116 can be used to provide internal storage space to the memory controller 110 (for example, it can temporarily store information), but the present invention is not limited to this. In addition, the read only memory 112M of this embodiment is used to store program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access of the NV memory 120. Please note that the program code 112C can also be stored in the random access memory 116 or any type of memory. In addition, the control logic circuit 114 can be used to control the NV memory 120. The control logic circuit 114 may include an error correction code (ECC) circuit (not shown). Figure 1), which can perform error correction code encoding and error correction code decoding to protect data, and / or perform error correction. The transmission interface circuit 118 can comply with one or more communication specifications among various communication specifications (such as Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIe) specification, Non-Volatile Memory Express (NVMe; also known as "NVM Express") specification, Embedded Multimedia Card specification and Universal Flash Storage specification), and can communicate with the memory device 100 and the host device 50 (such as the transmission interface circuit 58) according to the one or more communication specifications. Similarly, the transmission interface circuit 58 can comply with the one or more communication specifications, and can communicate with the host device 50 and the memory device 100 (such as the transmission interface circuit 118) according to the one or more communication specifications.

[0059] In the present embodiment, the host device 50 may transmit a plurality of host commands corresponding to the logical addresses to the memory controller 110 to indirectly access the NV memory 120 in the memory device 100. The memory controller 110 receives the plurality of host commands and the logical addresses, converts the plurality of host commands into memory operation commands (which may be referred to as operation commands for simplicity), and further controls the NV memory 120 with the operation commands to read or write / program the memory cells or data pages of the specific physical addresses in the NV memory 120, wherein the physical addresses may be associated with the logical addresses. For example, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between the physical addresses and the logical addresses. The NV memory 120 may store a global L2P address mapping table 120AM to provide the memory controller 110 to control the memory device 100 to access the data in the NV memory 120, but the present invention is not limited thereto. In addition, the memory controller 110 may generate or update at least one bad-block replacement (BR) management table, such as a BR management table 120BR, and the NV memory 120 may store the BR management table 120BR. The memory controller 110 may generate or update BR management-related information in the BR management table 120BR for managing BR operations.

[0060] For better understanding, the global L2P address mapping table 120AM and the BR management table 120BR may be located in a predetermined area within the NV memory element 122-1, such as a system area, but the present invention is not limited thereto. For example, the global L2P address mapping table 120AM may be divided into a plurality of local L2P address mapping tables, and the plurality of local L2P address mapping tables may be stored in the plurality of NV memory elements 122-1, 122-2, ..., and 122-N. E In one or more NV memory elements, in particular, the NV memory elements 122-1, 122-2, ..., and 122-N may be stored in the plurality of NV memory elements 122-1, 122-2, ..., and 122-N, respectively. EWhen necessary, the memory controller 110 may load at least a portion (e.g., a portion or all) of the global L2P address mapping table 120AM into the random access memory 116 or other memory. For example, the memory controller 110 may load a local L2P address mapping table from the plurality of local L2P address mapping tables into the random access memory 116 as a temporary L2P address mapping table 116AM to access data in the NV memory 120 according to the local L2P address mapping table stored as the temporary L2P address mapping table 116AM, but the present invention is not limited thereto. The memory controller 110 may generate or update address mapping information in the temporary L2P address mapping table 116AM, and update the global L2P address mapping table 120AM according to the latest address mapping information in the temporary L2P address mapping table 116AM. In addition, the memory controller 110 may load the BR management table 120BR into the random access memory 116 or other memory. For example, the memory controller 110 may load the BR management table 120BR into the random access memory 116 as a temporary BR management table 116BR to manage BR operations according to the temporary BR management table 116BR. The memory controller 110 may generate or update BR management related information in the temporary BR management table 116BR, and update the BR management table 120BR according to the latest BR management related information in the temporary BR management table 116BR.

[0061] In addition, the at least one NV memory element (eg, one or more NV memory elements, such as the plurality of NV memory elements 122-1, 122-2, ..., and 122-N) E ) may include a plurality of blocks {BLK}, wherein the minimum unit for the memory controller 110 to perform a data erase operation on the NV memory 120 may be a block, and the minimum unit for the memory controller 110 to perform a data write operation on the NV memory 120 may be a page, but the present invention is not limited thereto. For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E Any NV memory element 122-n within (where “n” may represent an interval [1, N E]) may include a plurality of blocks, and one of the plurality of blocks may include and record a specific number of pages, wherein the memory controller 110 may access a certain page in a certain block in the plurality of blocks according to the block address and the page address. In some examples, any of the above NV memory elements 122-n may include a plurality of planes, one of the plurality of planes may include a plurality of blocks, and one of the plurality of blocks may include and record a specific number of pages, wherein the memory controller 110 may access a certain page in a certain block in a certain plane in the plurality of planes according to the plane address, the block address, and the page address.

[0062] According to some embodiments, the memory controller 110 may configure any block BLK of the plurality of blocks {BLK} as a single level cell (SLC) block for storing 1 bit per memory cell, but the present invention is not limited thereto. The memory controller 110 may configure any of the above blocks BLK as an X-level cell (XLC) block for storing X bits per memory cell, where X may be a positive integer. For example, when X=1, the XLC block may represent the SLC block. In some examples, when X>1, the XLC block may represent any one of a multiple level cell (MLC) block (e.g., a double level cell (DLC) block), a triple level cell (TLC) block, a quadruple level cell (QLC) block, etc.

[0063] In addition, the memory controller 110 may perform at least one test procedure on any of the NV memory elements 122-n to determine any damaged block in any plane therein as a bad block, and record the physical address of the bad block in the at least one BR management table (e.g., the BR management table 120BR and / or the temporary BR management table 116BR), but the present invention is not limited thereto. The memory controller 110 may select a good block (e.g., a non-damaged block) in any of the planes in any of the NV memory elements 122-n for replacement of the bad block, and in particular, record the physical address of the good block in the at least one BR management table to indicate that the good block replaces the bad block, so that the operation of accessing the bad block becomes the operation of accessing the good block. According to certain embodiments, the memory controller 110 may dynamically adjust at least one reserved block threshold Reserved_BLK_Th to configure a first group of blocks and a second group of blocks among the multiple blocks {BLK} of the NV memory 120 as super blocks corresponding to a number of planes per super block Plane_CNT_per_SB(1) and a super block corresponding to a number of planes per super block Plane_CNT_per_SB(2), respectively, so as to appropriately reserve super blocks with maximum throughput (regarding data access) and at the same time maximize the total storage capacity of the memory device 100 as much as possible, so as to take into account the requirements of meeting storage capacity specifications and data access performance.

[0064] Figure 2A block combination control scheme is shown. When any of the above NV memory elements 122-n is configured in a channel Ch(i) among a plurality of channels {CH(i)}, the memory controller 110 can access the NV memory element 122-n on the channel Ch(i), and in particular, access any block BLK(k) among a plurality of blocks {BLK(k)} of any plane PL(j) among a plurality of planes {PL(j)} within the NV memory element 122-n. For ease of understanding, it is assumed that the multiple channels {CH(i)} may include 4 channels {CH(i)|i=0,1,2,3} such as channels {CH0, CH1, CH2, CH3}, the multiple planes {PL(j)} may include 6 planes {PL(j)|j=0,1,2,3,4,5} such as planes {PL0, PL1, PL2, PL3, PL4, PL5}, and the multiple blocks {BLK(k)} may include 567 blocks {BLK(k)|k=1,2,…,567}, wherein the channel number CNT_CH of the multiple channels {CH(i)} is equal to 4, the plane number CNT_PL of the multiple planes {PL(j)} is equal to 6, and the block number CNT_BLK of the multiple blocks {BLK(k)} is equal to 567, but the present invention is not limited to this. According to some embodiments, the number of channels CNT_CH, the number of planes CNT_PL, and the number of blocks CNT_BLK may be varied. In addition, the memory controller 110 may combine the blocks {BLK(k)} corresponding to the block index k in all planes {PL(j)} of all channels {CH(i)} into a super block XBLK(k) corresponding to the same block index k, so as to simultaneously access these blocks {BLK(k)} in the super block XBLK(k) by using the same block address BLK_Add(k). Thus, the memory controller 110 may simultaneously access all blocks {BLK(k)} of any super block XBLK(k) among a plurality of super blocks {XBLK(k)} (e.g., 567 super blocks {XBLK(k)|k=1,2,…,567}) to achieve the above-mentioned maximum throughput. In addition, all planes {PL(j)} of all channels {CH(i)}, such as the respective planes {PL0, PL1, PL2, PL3, PL4, PL5} of channels {CH0, CH1, CH2, CH3}, can be plotted on the horizontal axis using the number of the global plane PLANE (for example: {0, 1, …, 23}), and all blocks {BLK(k)} of any plane PL(j) of any channel CH(i), such as blocks {BLK(1), …, BLK(567)}, can be plotted on the vertical axis using the number of the physical block Fblock (for example: {1, 2, …, 567}), but the present invention is not limited to this.

[0065] Figure 3AAn example of bad block distribution before replacement processing of a block replacement control scheme is shown. Figure 3B FIG. 1 shows some implementation details of an example of block combination after the replacement process of the block replacement control scheme is completed, and FIG. Figure 3C Some other implementation details of the above block combination example after the replacement process of the block replacement control scheme is completed are shown, wherein the blocks shown with shadows may represent damaged blocks such as bad blocks, and the blocks without shadows may represent non-damaged blocks such as good blocks, but the present invention is not limited thereto. According to some embodiments, Figure 3A The bad block distribution shown and Figure 3B and Figure 3C The block combinations shown may be varied.

[0066] The memory controller 110 may perform the above-mentioned at least one test procedure to detect any bad block BLK(k) of any global plane PLANE (e.g., any plane PL(j) of any channel CH(i)), and select a good block in the same global plane PLANE to replace the bad block BLK(k). Figure 3B and Figure 3C As shown, any good block marked with the number of the physical block Fblock (for example, any one of {1, 2, ..., 567}) can represent a replacement block, and the replacement block is used to replace a bad block belonging to the same plane. Taking PLANE=1 as an example, the memory controller 110 can use a good block such as Figure 3A The block corresponding to Fblock=567 replaces a bad block, for example Figure 3A The block corresponding to Fblock=564 in the example is used to make this good block a replacement block. Figure 3B In the example, the block marked with 567 at coordinates (PLANE=1, Fblock=564) is used to replace the bad block. Figure 3B In the example, the block 564 is marked at the coordinate (PLANE=1, Fblock=567). In addition, taking PLANE=23 as an example, the memory controller 110 may use a first good block such as Figure 3A The block corresponding to Fblock=567 replaces the first bad block, for example Figure 3A The block corresponding to Fblock=288 in the first good block is used to make the first replacement block. Figure 3C The block marked with 567 at coordinates (PLANE=23, Fblock=288) is used to replace the first bad block. Figure 3C The block 288 is indicated at coordinates (PLANE=23, Fblock=567); and the memory controller 110 may use a second best block such as Figure 3AThe block corresponding to Fblock=566 replaces a second bad block, for example Figure 3A The block corresponding to Fblock=565 in the example is used to make the second good block a second replacement block. Figure 3C The block marked with 566 at coordinates (PLANE=23, Fblock=565) is used to replace the second bad block. Figure 3C The block 565 is marked at the coordinates (PLANE=23, Fblock=566). The rest can be deduced in the same way.

[0067] Based on the block replacement control scheme, the memory controller 110 can perform the replacement processing, in particular, record the physical addresses of all bad blocks {BLK(k)} and the corresponding replacement blocks {BLK(k)} (for example: good blocks {BLK(k)} used to replace these bad blocks {BLK(k)} respectively) in the above-mentioned at least one BR management table to indicate that these replacement blocks {BLK(k)} replace these bad blocks {BLK(k)}, so that the operation of accessing these bad blocks {BLK(k)} becomes the operation of accessing these replacement blocks {BLK(k)}. The memory controller 110 may combine the blocks {BLK(k)} corresponding to the block index k in all global planes {PLANE} (e.g., all planes {PL(j)} of all channels {CH(i)}) into a super block XBLK(k) corresponding to the same block index k, so as to simultaneously access these blocks {BLK(k)} in the super block XBLK(k) by using the same block address BLK_Add(k). Thus, the memory controller 110 may simultaneously access all blocks {BLK(k)} of any super block XBLK(k) among a plurality of super blocks {XBLK(k)} (e.g., 560 super blocks {XBLK(k)|k=1,2,…,560}) to achieve the above-mentioned maximum throughput. Since the memory controller 110 can use the plurality of super blocks {XBLK(k)} (e.g., the 560 super blocks {XBLK(k)|k=1, 2, . . . , 560}) to achieve the maximum throughput, the regions of the plurality of super blocks {XBLK(k)} (e.g., Figure 3B and Figure 3C The area above the dotted line indicating Fblock=560 in FIG. 5 can be regarded as a maximum throughput super block area.

[0068] like Figure 3B and Figure 3CAs shown, the memory controller 110 can maximize the maximum throughput super block area to improve the overall performance, but the present invention is not limited thereto. For example, the NV memory 120 can be implemented by a 3D NAND flash memory or the like. In the case where a flash memory manufacturer attempts to increase storage capacity by increasing the 3D NAND flash stack architecture, the process yield may decrease, and / or the number of damaged blocks in any global plane PLANE (e.g., any plane PL(j) of any channel CH(i)) may increase, which may cause the memory device 100 using a 3D NAND flash memory as the NV memory 120 to fail the test on sufficient capacity. The memory controller 110 can operate according to one or more control schemes to avoid maximizing the maximum throughput super block area, so as to balance the need to meet storage capacity specifications and data access performance.

[0069] Figure 4 According to one embodiment of the present invention, a flow chart of a method for managing storage space of a memory device by means of dynamic block allocation is described. Any block BLK of the plurality of blocks {BLK} of the NV memory 120 may belong to a plane of a plurality of planes (e.g., a global plane {PLANE}, such as all planes {PL(j)} of all channels {CH(i)}) of the at least one NV memory element, so as to allow the memory controller 110 to configure the blocks {BLK(k)} respectively belonging to the plurality of planes (e.g., blocks {BLK(k)} corresponding to block index k in all planes {PL(j)} of all channels {CH(i)}) to become corresponding super blocks XBLK(k).

[0070] In step S10, the memory controller 110 may configure at least a portion of the plurality of blocks {BLK} into a plurality of first blocks {BLK(k)|k=1,…,Fb1} in a first region and a plurality of second blocks {BLK(k)|k=(Fb1+1),…,Fblock} in a second region according to a first reserved block threshold Reserved_BLK_Th(1). MAX}, such as the first blocks of the plurality of planes {BLK(k)|k=1,…,Fb1} and the second blocks of the plurality of planes {BLK(k)|k=(Fb1+1),…,Fblock MAX} to reserve the plurality of first blocks {BLK(k)|k=1,…,Fb1} for data access, such as data access corresponding to a first target performance, wherein the plurality of first blocks {BLK(k)|k=1,…,Fb1} of the plurality of planes may include (CNT_CH*CNT_PL*Fb1) blocks {BLK(k)}, the plurality of second blocks {BLK(k)|k=(Fb1+1),…,Fblock MAX} can contain (CNT_CH*CNT_PL*(Fblock MAX -Fb1)) blocks {BLK(k)}, and Fblock MAX =CNT_BLK. For example, the first target performance may represent the maximum throughput of the memory device 100 regarding data access. In addition, the at least a portion of the blocks {BLK} may represent non-damaged blocks among the plurality of blocks {BLK(k)}, rather than any damaged blocks.

[0071] In step S11, the memory controller 110 may combine the plurality of first blocks {BLK(k)|k=1, ..., Fb1} of the plurality of planes into a set of first super blocks {XBLK(k)|k=1, ..., Fb1} in the first region, wherein the number of blocks of the first blocks {BLK(k)} in each first super block XBLK(k) in the set of first super blocks {XBLK(k)|k=1, ..., Fb1} is equal to a first predetermined number of blocks (e.g., the total number of planes PLANE of the global planes {PLANE}). MAX ), and a super block number Fb1 of the group of first super blocks {XBLK(k)|k=1,…,Fb1} is equal to the first reserved block threshold Reserved_BLK_Th(1).

[0072] In step S12, the memory controller 110 may divide the plurality of second blocks {BLK(k)|k=(Fb1+1), . . . , Fblock MAX} are combined into a group of second super blocks {XBLK(k)|k=(Fb1+1),…,(Fb1+ΔFb)} in the second region, wherein the number of blocks of the second blocks {BLK(k)} in each second super block XBLK(k) in the group of second super blocks {XBLK(k)|k=(Fb1+1),…,(Fb1+ΔFb)} is less than the first predetermined number of blocks (for example, the total number of planes PLANE MAX), and the first reserved block threshold Reserved_BLK_Th(1) is less than a minimum number of non-damaged blocks Fb0 among the numbers of non-damaged blocks of the plurality of planes (e.g., the global plane {PLANE}), so that the memory controller 110 can increase an available storage capacity of the memory device 100 by increasing the ratio of the size of the second region to the size of the first region. For example, the memory controller 110 can determine the first reserved block threshold Reserved_BLK_Th(1) to be less than the minimum number of non-damaged blocks Fb0 and greater than or equal to a preset value Fb DEFAULT , so as to control a guaranteed performance storage capacity of the memory device 100 (e.g., the storage capacity of the first super block {XBLK(k)|k=1, ..., Fb1} in the first region) to be greater than or equal to a predetermined guaranteed performance storage capacity (e.g., Fb1 in the first region) DEFAULT The first super block {XBLK(k)|k=1,…,Fb DEFAULT} storage capacity) for data access corresponding to the first target performance (eg, the maximum throughput mentioned above), wherein the preset value Fb DEFAULT It may be a predetermined value that is less than or equal to the number of super blocks Fb1.

[0073] The memory controller 110 may determine the first reserved block threshold Reserved_BLK_Th(1) according to a reserved block threshold preset setting, but the present invention is not limited thereto. For example, the memory controller 110 may determine the first reserved block threshold Reserved_BLK_Th(1) according to any one of the reserved block threshold preset setting and a reserved block threshold user setting. For another example, the memory controller 110 may determine the first reserved block threshold Reserved_BLK_Th(1) according to a statistical result of the plurality of blocks {BLK}, and the statistical result may include a damaged block statistical result (e.g., indicating Figure 3B and Figure 3C a bad block statistics result of the bad block distribution in the Figure 3B and Figure 3C The good block statistics of the good block distribution in the multiple planes (e.g., the global plane {PLANE}), the minimum number of non-damaged blocks Fb0 among the number of non-damaged blocks of the multiple planes (e.g., the global plane {PLANE}), and the maximum number of damaged blocks (Fblock) among the number of damaged blocks of the multiple planes (e.g., the global plane {PLANE}). MAX-Fb0). Typically, there are damaged blocks among the plurality of blocks {BLK}. For example, when the NV memory 120 is implemented by a 3D NAND flash memory, the number of damaged blocks may be large, so it is not necessary to combine all non-damaged blocks into a super block. As long as it does not hinder the implementation of the present invention, the memory controller 110 may determine the first reserved block threshold Reserved_BLK_Th(1) in any of various ways. In addition, the memory controller 110 may control the number of super blocks Fb1 of the group of first super blocks {XBLK(k)|k=1, . . . , Fb1} to be equal to the first reserved block threshold Reserved_BLK_Th(1) instead of a maximum available reserved block threshold Reserved_BLK_Th(0), so as to increase the number of second super blocks in the second region by increasing the number of second blocks in a plane PLANE having the minimum number of non-defective blocks Fb0, so as to increase the available storage capacity and / or balance the guaranteed performance storage capacity of the memory device 100 (e.g., the storage capacity of the group of first super blocks {XBLK(k)|k=1, . . . , Fb1} in the first region) and the available storage capacity, wherein the maximum available reserved block threshold Reserved_BLK_Th(0) may represent the minimum number of non-defective blocks Fb0.

[0074] Figure 5 A storage space increase control scheme of the method is illustrated according to an embodiment of the present invention. For ease of understanding, the memory controller 110 may operate according to a first storage capacity setting, such as a maximum throughput super block area maximization setting, and in particular, a plurality of super blocks {XBLK(k)} (e.g., Fb0 super blocks {XBLK(k)|k=1,2,…,Fb0}) are used to achieve the above-mentioned maximum throughput, and the area of ​​the plurality of super blocks {XBLK(k)} (e.g., the area above the dotted line indicating Fblock=Fb0) may be regarded as a maximum throughput super block area R MAX_THROUGHPUT (0), but the present invention is not limited thereto. Figure 3B and Figure 3C Taking the block combination shown as an example, when Fb0=560, the memory controller 110 can use the 560 super blocks {XBLK(k)|k=1,2,…,560} to achieve the above maximum throughput, and the area of ​​the 560 super blocks {XBLK(k)|k=1,2,…,560} (for example: Figure 3B and Figure 3C The area above the dotted line with Fblock = 560 in the figure can be regarded as the maximum throughput super block area R MAX_THROUGHPUT (0).

[0075] In addition, the memory controller 110 may operate according to a second storage capacity setting, such as a maximum throughput super block area non-maximization setting, to increase the available storage capacity and / or balance the guaranteed performance storage capacity and the available storage capacity. For example, Reserved_BLK_Th(0)=Fb0 and Reserved_BLK_Th(1)=Fb1, and the memory controller 110 may control the first area to become a maximum throughput super block area R corresponding to the first reserved block threshold Reserved_BLK_Th(1). MAX_THROUGHPUT (1), rather than the maximum throughput super block region R corresponding to the maximum available reserved block threshold Reserved_BLK_Th(0) MAX_THROUGHPUT (0), in the second region, for example, the remaining region R REMAIN (1) Allocate more second super blocks {XBLK(k)}. Maximum throughput super block area R MAX_THROUGHPUT The first super block {XBLK(k)|k=1, ..., Fb1} in (1) may represent a super block corresponding to the number of planes per super block Plane_CNT_per_SB(1), and the remaining regions R REMAIN The set of second super blocks {XBLK(k)|k=(Fb1+1),…,(Fb1+ΔFb)} in (1) (or its sub-region R(1)) may represent super blocks corresponding to the number of planes per super block Plane_CNT_per_SB(2), where Plane_CNT_per_SB(1)=PLANE MAX And Plane_CNT_per_SB(2)=(Plane_CNT_per_SB(1)-1)=(PLANE MAX -1).

[0076] by Figure 3B and Figure 3CTaking the distribution of bad blocks after the replacement process is completed with respect to the global plane PLANE as an example, the number of damaged blocks (or bad blocks) reaches a maximum value at PLANE=16. In this case, the memory controller 110 may combine the second blocks {BLK(k)|k=561,...,564} of the global plane {PLANE(p)|p=0,...,15,17,...,23} into a second super block {XBLK(k)|k=561,...,564} instead of using the four bad blocks on the coordinates {(PLANE=16,Fblock=561),...,(PLANE=16,Fblock=564)} for data access corresponding to a second target performance (e.g., a lower throughput). In some embodiments, in order to obtain more storage space, the memory controller 110 may combine the second blocks {BLK(k)|k=565} of the global plane {PLANE(p)|p=0,1,3,5,…,15,17,…,23} into a second super block XBLK(565) instead of using the three bad blocks at the coordinates {(PLANE=2,Fblock=565),(PLANE=4,Fblock=565),(PLANE=16,Fblock=565)}, and the rest may be deduced in the same manner, wherein the throughput may become smaller, but the present invention is not limited thereto. Based on the storage space increase control scheme, the memory controller 110 may control the first region to become the maximum throughput super block region R corresponding to the first reserved block threshold Reserved_BLK_Th(1). MAX_THROUGHPUT (1) In the remaining area R REMAIN (1) Allocate more second super blocks {XBLK(k)} for data access corresponding to the second target performance (e.g., the smaller throughput). Figure 3B and Figure 3C With respect to the distribution of the bad blocks after the replacement process is completed relative to the global plane PLANE, the memory controller 110 may reserve the good blocks at the coordinates {(PLANE=16, Fblock=(Fb1+1)),…,(PLANE=16, Fblock=560)} for configuration into super blocks corresponding to the number of planes per super block Plane_CNT_per_SB(2) instead of the number of planes per super block Plane_CNT_per_SB(1).

[0077] After completing the replacement process, the memory controller 110 may perform a REMAIN(1) Perform a re-permutation process to re-arrange at least a part of the bad blocks {BLK(k)} within the second region, in particular, re-arrange the above at least a part of the bad blocks {BLK(k)} in sequence into a block arrangement pattern where each column (or each vertical position in the integer coordinate system (PLANE,Fblock), along the Fblock axis) has only one bad block, for configuring into super-blocks corresponding to each super-block plane number Plane_CNT_per_SB(2). The above at least a part of the bad blocks {BLK(k)} may represent the remaining region R REMAIN The bad blocks {BLK(k)} corresponding to Fblock = FbTh or Fblock < FbTh in (1), such as all the bad blocks {BLK(k)} in the blocks {BLK(k)|k=(Fb1 + 1),…,FbTh} of the multiple planes (e.g., global plane {PLANE}), where the memory controller 110 can obtain from the remaining region R REMAIN Select the bad blocks {BLK(k)} corresponding to Fblock ≤ FbTh from the bad blocks {BLK(k)} within (1) as the above at least a part of the bad blocks {BLK(k)}. For example, assuming FbTh = 566, the memory controller 110 can Figure 3B re-arrange the bad blocks at coordinates {(PLANE = 2,Fblock = 565),(PLANE = 2,Fblock = 566),(PLANE = 4,Fblock = 565),(PLANE = 4,Fblock = 566),(PLANE = 15,Fblock = 566)} to coordinates {(PLANE = 2,Fblock = (Fb1 + 1)),(PLANE = 2,Fblock = (Fb1 + 2)),(PLANE = 4,Fblock = (Fb1 + 3)),(PLANE = 4,Fblock = (Fb1 + 4)),(PLANE = 15,Fblock = (Fb1 + 5))}, and Figure 3CThe bad blocks at coordinates {(PLANE=16, Fblock=561), ..., (PLANE=16, Fblock=566), (PLANE=20, Fblock=566), (PLANE=21, Fblock=566), (PLANE=23, Fblock=566)} are rearranged to coordinates {(PLANE=16, Fblock=(Fb1+6)), ..., (PLANE=16, Fblock=(Fb1+11)), (PLANE=20, Fblock=(Fb1+12)), (PLANE=21, Fblock=(Fb1+13)), (PLANE=23, Fblock=(Fb1+14))}, but the present invention is not limited thereto. According to some embodiments, the block arrangement pattern may be changed.

[0078] like Figure 5 As shown, the second region, for example, the remaining region R REMAIN (1) may include a plurality of sub-regions such as sub-regions R(1) and R(2). The memory controller 110 may determine the boundary between the sub-regions R(1) and R(2) based on any one of a sub-region boundary default setting and a sub-region boundary user setting, but the present invention is not limited thereto. For example, the memory controller 110 may determine the boundary between the sub-regions R(1) and R(2) based on the statistical result of the plurality of blocks {BLK}, and in particular, may first determine the bad block selection threshold FbTh based on the statistical result of the plurality of blocks {BLK}, and select the bad block selection threshold FbTh from the remaining regions R(1) based on the bad block selection threshold FbTh. REMAIN (1) selects the bad blocks {BLK(k)} corresponding to Fblock≤FbTh as the at least one portion of the bad blocks {BLK(k)} for the re-permutation process, thereby determining the boundary between the sub-regions R(1) and R(2). Assuming that the at least one portion of the bad blocks {BLK(k)} includes ΔFb bad blocks, after performing the re-permutation process to sequentially rearrange the at least one portion of the bad blocks {BLK(k)} into the block arrangement pattern with only one bad block in each column, the memory controller 110 can obtain ΔFb columns of good blocks {BLK(k)}, such as good blocks {BLK(k)|k=(Fb1+1),…,(Fb1+ΔFb)} corresponding to Fblock=(Fb1+1),…,(Fb1+ΔFb), respectively, and each column of good blocks {BLK(k)} has (PLANE MAX -1) plane (PLANE MAX-1) good blocks {BLK(k)} as at least a portion of the second block {BLK(k)|k=(Fb1+1),…,(Fb1+ΔFb)}. Then, the memory controller 110 may combine the remaining regions R REMAIN The above-mentioned ΔFb in (1) is used to sort the good blocks {BLK(k)} to generate the super blocks corresponding to the number of planes per super block Plane_CNT_per_SB(2) as the group of second super blocks {XBLK(k)|k=(Fb1+1),…,(Fb1+ΔFb)} located in the sub-region R(1), wherein the memory controller 110 can retain the good blocks {BLK(k)} in the sub-region R(2) for processing for other purposes without rearranging the bad blocks {BLK(k)} in the sub-region R(2). In the case where the total number of bad blocks of the plurality of blocks {BLK} is large, there can be a large number of bad blocks {BLK(k)} in the sub-region R(2), and the bad block selection threshold FbTh can be close to the boundary between the sub-regions R(1) and R(2), for example, Fb0=(Fb1+ΔFb), but the present invention is not limited thereto. In addition, the block arrangement pattern may change accordingly with the change of the statistical result of the plurality of blocks {BLK} and / or the change of the bad block number ΔFb of at least a portion of the bad blocks {BLK(k)}.

[0079] Based on the storage space increase control scheme, the memory controller 110 may use the second block {BLK(k)} in the plane PLANE with the minimum number of non-defective blocks Fb0 as a margin for configuring the second super block {XBLK(k)|k=(Fb1+1),…,(Fb1+ΔFb)}, but the present invention is not limited thereto. According to some embodiments, the memory controller 110 may use the second block {BLK(k)} in the plane PLANE with the minimum number of non-defective blocks Fb0 as a margin for configuring the second region (e.g., the remaining region R REMAIN (1)) wherein the number of blocks of the second blocks {BLK(k)} in each second super block XBLK(k) of the one or more additional second super blocks {XBLK(k)} is less than the first predetermined number of blocks (e.g., the total number of planes PLANE MAX ). For example, the at least one NV memory element may represent the plurality of NV memory elements 122-1, 122-2, ..., and 122-N. E Any block BLK among the plurality of blocks {BLK} may belong to the plurality of NV memory elements 122-1, 122-2, ..., and 122-N. EIn the embodiment of the present invention, the memory controller 110 configures the blocks {BLK(k)} belonging to the multiple planes {PL(j)} of an NV memory element to be the corresponding super block XBLK(k) so as to achieve the first target performance (e.g., the maximum throughput) by accessing the blocks {BLK(k)} belonging to the multiple planes {PL(j)} of the NV memory element to allow the memory controller 110 to configure the blocks {BLK(k)} belonging to the multiple planes (e.g., the global plane {PLANE}) to be the corresponding super block XBLK(k) so as to achieve the first target performance (e.g., the maximum throughput) by accessing the blocks {BLK(k)} simultaneously. For the sake of simplicity, similar contents in these embodiments are not repeated here.

[0080] Fig. 6A An example of a set of original boundary blocks in the storage space enlargement control scheme is shown. Figure 6B An example of a set of first boundary blocks in the storage space enlargement control scheme is shown. Figure 6C An example of a set of second boundary blocks in the storage space enlargement control scheme is shown. Fig.6D Another example of a group of boundary blocks in the storage space enlargement control scheme is shown. For ease of understanding, assume that Fb0=453, Fb1=309 and the boundary between sub-regions R(1) and R(2) can be the boundary between the block {BLK(506)} corresponding to Fblock=506 and the block {BLK(507)} corresponding to Fblock=507, such as Fig. 6A , Figure 6B and Figure 6C For example, the minimum number of non-damaged blocks Fb0, the number of super blocks Fb1, and / or the boundary between sub-regions R(1) and R(2) may be changed.

[0081] exist Fig. 6A , the set of original boundary blocks before boundary adjustment may be the block {BLK(453)} corresponding to Fblock=453. In this case, the memory controller 110 may configure 453 super blocks {XBLK(1), ..., XBLK(453)} corresponding to the number of planes per super block Plane_CNT_per_SB(1) as the maximum throughput super block {XBLK(1), ..., XBLK(453)} with the maximum throughput (regarding data access). MAX_THROUGHPUT}, where block {BLK(453)} can be considered to contain these maximum throughput superblocks {XBLK MAX_THROUGHPUT Maximum throughput of superblock region R MAX_THROUGHPUT For example, the number of planes per super block Plane_CNT_per_SB(1) may be equal to the total number of planes of the global plane {PLANE} PLANE MAX .by Figure 2Taking the respective planes {PL0, PL1, PL2, PL3, PL4, PL5} of the channels {CH0, CH1, CH2, CH3} as an example, the channel number CNT_CH of the channels {CH0, CH1, CH2, CH3} is equal to 4, and the plane number CNT_PL of the planes {PL0, PL1, PL2, PL3, PL4, PL5} in any channel CH(i) of the channels {CH0, CH1, CH2, CH3} is equal to 6, so Plane_CNT_per_SB(1)=PLANE MAX =(CNT_CH*CNT_PL)=(4*6)=24.

[0082] exist Figure 6B , the first boundary block after boundary adjustment may be a block {BLK(309)} corresponding to Fblock=309. In this case, the memory controller 110 may configure 309 super blocks {XBLK(1), ..., XBLK(309)} corresponding to the number of planes per super block Plane_CNT_per_SB(1) as the maximum throughput super block {XBLK(1), ..., XBLK(309)} with the maximum throughput (regarding data access). MAX_THROUGHPUT}, where block {BLK(309)} can be considered to contain these maximum throughput superblocks {XBLK MAX_THROUGHPUT}Maximum throughput of superblock region R MAX_THROUGHPUT For example, the number of planes per super block Plane_CNT_per_SB(1) may be equal to the total number of planes PLANE MAX .by Figure 2 Taking the planes {PL0, PL1, PL2, PL3, PL4, PL5} of the channels {CH0, CH1, CH2, CH3} as an example, Plane_CNT_per_SB(1)=PLANE MAX =(CNT_CH*CNT_PL)=(4*6)=24.

[0083] exist Figure 6C In the example, the second boundary block after the re-permutation process may be the block {BLK(506)} corresponding to Fblock=506. Figure 6B and Figure 6C As shown, after the re-permutation process is performed, the memory controller 110 may configure 197 super blocks {XBLK(310), ..., XBLK(506)} corresponding to the number of planes per super block Plane_CNT_per_SB(2) as the lower throughput super blocks {XBLK LOWER_THROUGHPUT}, where block {BLK(506)} can be considered to contain these smaller throughput superblocks {XBLK LOWER_THROUGHPUT For example, the number of planes per super block Plane_CNT_per_SB(2) may be equal to the total number of planes PLANE MAX Minus one. Figure 2 Taking the planes {PL0, PL1, PL2, PL3, PL4, PL5} of the channels {CH0, CH1, CH2, CH3} as an example, Plane_CNT_per_SB(2)=(PLANE MAX -1)=(CNT_CH*CNT_PL-1)=(4*6-1)=23.

[0084] For ease of understanding, the NV memory 120 may have an internal configuration of one way, such as the internal configuration of the multiple channels {CH(i)} (each having its own plane {PL(j)}), and the related operations may be described above, but the present invention is not limited thereto. For example, the NV memory 120 may have an internal configuration of more than one way, such as multiple ways {WAY(Intlv)|Intlv=0,…,(WAY TOTAL -1)}, and the multiple ways {WAY(Intlv)|Intlv=0,…,(WAY TOTAL -1)} may include a plurality of global planes {PLANE} of corresponding NV memory elements {122-n} (e.g., CNT_CH NV memory elements {122-n}) on the plurality of channels {CH(i)}, such as a global plane {PLANE(p)|p=0,…,(PLANE MAX =WAY(Intlv)|Intlv=0,…,(WAY TOTAL -1)}, the memory controller 110 can perform similar operations according to the storage space increase control scheme to obtain WAY TOTAL processing results. Since the multiple paths {WAY(Intlv)|Intlv=0,…,(WAY TOTAL =-1)} may have different bad block distributions from each other, so the memory controller 110 may configure the multiple ways {WAY(Intlv)|Intlv=0, . . . , (WAY TOTAL -1)} of their respective maximum throughput superblock regions {R MAX_THROUGHPUT (1)} are identical to each other, and from (such as the WAY TOTAL The multiple ways {WAY(Intlv)|Intlv=0,…,(WAY TOTAL-1)} selects a minimum sub-region R(1) to configure the multiple ways {WAY(Intlv)|Intlv=0,…,(WAY TOTAL -1)} are all equal to the smallest sub-area R(1). Fig.6D As shown, for the multiple roads {WAY(Intlv)|Intlv=0,…,(WAY TOTAL After the re-permutation process of each way WAY(Intlv) in {WAY(Intlv)|Intlv=0, . . . , (WAY TOTAL The respective sub-regions {R(1)} of sub-region R(-1)} are identical to each other, so that the other set of boundary blocks is the block {BLK(495)} corresponding to Fblock=495. In addition, the memory controller 110 may reserve the good blocks {BLK(k)} in the sub-region R(2) for processing for other purposes, such as replacement at runtime.

[0085] Figure 7 According to an embodiment of the present invention, a predetermined setting procedure of the method is described. The memory controller 110 may set the plurality of ways {WAY(Intlv)|Intlv=0, . . . , (WAY TOTAL -1)}, the initial value of the way index Intlv is equal to 0, and the way index Intlv is increased by a predetermined increment, such as a predetermined increment (labeled as "Intlv++" for simplicity) before re-entering step S21 after executing at least a part of the steps in steps S21 to S31, but the present invention is not limited to this. For example, the operation of setting the initial value of the way index Intlv can be integrated into step S20. In addition, after executing step S22, the memory controller 110 can set the initial values ​​of the plane index I_plane, the bad block indicator N and the bad block selection threshold FbTh respectively, and in particular, set I_plane=0, N=0 and FbTh=Fb0 to select the global plane {PLANE} (for example: the global plane {PLANE(p)|p=0,…,(PLANE MAX -1)}) as a target plane PLANE TARGET (I_plane) for related operations, where FbTh=Fb0 represents moving the bad block selection threshold FbTh along the Fblock axis to the position corresponding to the minimum number of non-damaged blocks Fb0 (for example: Figure 3B and Figure 3Ccorresponding to Fblock=560 in the current way WAY (Intlv) to indicate the maximum value of the bad block distribution, for example, the maximum number of bad blocks (Fblock) in the number of bad blocks of the global plane {PLANE} of the current way WAY (Intlv) MAX -Fb0).

[0086] In step S20 , the memory controller 110 may determine a first reserved block threshold Reserved_BLK_Th( 1 ).

[0087] In step S21, the memory controller 110 may determine whether the way index Intlv is smaller than the plurality of ways {WAY(Intlv)|Intlv=0, . . . , (WAY TOTAL -1)} Total number of WAY TOTAL If it is (for example: Intlv <WAY TOTAL ), go to step S22; if not, go to step S32.

[0088] In step S22 , the memory controller 110 may calculate the number of bad blocks {BLK} of each global plane {PLANE} in the global plane {PLANE} of the current way WAY (Intlv).

[0089] In step S23, the memory controller 110 may determine whether the plane index I_plane is less than the total number of planes PLANE MAX The difference obtained by subtracting one (PLANE MAX -1) and the bad block indicator N is less than or equal to the bad block indicator upper limit N MAX (labeled as "I_plane<(PLANE MAX -1)&&N≤N MAX " for simplicity). If (for example: I_plane<(PLANE MAX -1) and N≤N MAX ), go to step S24; if not, go to step S27.

[0090] In step S24, the memory controller 110 may update the plane index I_plane and the previous bad block indicator pre_N so that the plane index I_plane increases by an increment, such as 1, and the previous bad block indicator pre_N is equal to the bad block indicator N (respectively labeled as "I_plane+=1" and "pre_N=N" for simplicity).

[0091] In step S25, the memory controller 110 may update the bad block selection threshold FbTh to move the bad block selection threshold FbTh along the Fblock axis to a position corresponding to the next minimum number of non-destructive blocks (eg: Figure 3Band Figure 3C The position corresponding to Fblock=564 in the current way (Intlv) is used to indicate the next maximum value of the bad block distribution, for example, the next maximum number of bad blocks in the respective bad block numbers of the global plane {PLANE}. Figure 3B and Figure 3C Take the bad block distribution shown as an example:

[0092] (1) When I_plane = 0, PLANE TARGET (I_plane)=PLANE(p=16), and FbTh=Fb0=560, for indicating the maximum value of the bad block distribution, for example, the first maximum value corresponding to the coordinate (PLANE=16, Fblock=560) (or the bad block below it);

[0093] (2) When I_plane = 1, PLANE TARGET (I_plane)=PLANE(p=2), and FbTh=564, for indicating the next maximum value of the bad block distribution, for example, the second maximum value corresponding to the coordinate (PLANE=2, Fblock=564) (or the bad block below it);

[0094] (3) When I_plane = 2, PLANE TARGET (I_plane)=PLANE(p=4), and FbTh=564, for indicating the next maximum value of the bad block distribution, for example, the third maximum value corresponding to the coordinate (PLANE=4, Fblock=564) (or the bad block below it), wherein the third maximum value may be equal to the second maximum value;

[0095] (4) When I_plane = 3, PLANE TARGET (I_plane)=PLANE(p=15), and FbTh=565, for indicating the next maximum value of the bad block distribution, for example, the 4th maximum value corresponding to the coordinate (PLANE=15, Fblock=565) (or the bad block below it);

[0096] (5) When I_plane = 4, PLANE TARGET (I_plane)=PLANE(p=20), and FbTh=565, for indicating the next maximum value of the bad block distribution, for example, the 5th maximum value corresponding to the coordinate (PLANE=20, Fblock=565) (or the bad block below it), wherein the 5th maximum value may be equal to the 4th maximum value;

[0097] (6) When I_plane = 5, PLANE TARGET (I_plane) = PLANE(p = 21), and FbTh = 565, to indicate the next maximum value of the bad block distribution, for example, the 6th maximum value corresponding to the coordinates (PLANE = 21, Fblock = 565) (or the bad blocks below it), where the 6th maximum value may be equal to the 5th maximum value; and

[0098] (7) When I_plane = 6, PLANE TARGET (I_plane) = PLANE(p = 23), and FbTh = 565, to indicate the next maximum value of the bad block distribution, for example, the 7th maximum value corresponding to the coordinates (PLANE = 23, Fblock = 565) (or the bad blocks below it), where the 7th maximum value may be equal to the 6th maximum value;

[0099] The rest can be deduced by analogy, but the present invention is not limited thereto.

[0100] In step S26, the memory controller 110 may update or calculate the bad block indicator N. For example, the bad block indicator N may be equal to the number of bad blocks {BLK(k)} in the bad block distribution corresponding to Fblock ≤ FbTh plus the number of candidate bad blocks {BLK(k)} in the candidate bad blocks corresponding to Fblock > FbTh, where the candidate bad blocks {BLK(k)} may include the bad blocks {BLK(k)} corresponding to FbTh < Fblock ≤ FbTh2 in the target planes {PLANE TARGET (0), …, PLANE TARGET (I_plane)} that have been checked at the current time point (for example, the time point when step S26 is executed), and "FbTh2" may represent the next-level candidate value of the bad block selection threshold FbTh to indicate the next-level maximum value of the bad block distribution. Taking Figure 3B and Figure 3C the shown bad block distribution as an example:

[0101] (1) When I_plane = 1, PLANE TARGET (I_plane) = PLANE(p = 2), and FbTh = 564 and FbTh2 = 565, where N = 4 + (1 * (I_plane + 1)) = 4 + (1 * 2) = 6;

[0102] (2) When I_plane = 2, PLANE TARGET (I_plane) = PLANE(p = 4), and FbTh = 564 and FbTh2 = 565, where N = 4 + (1 * (I_plane + 1)) = 4 + (1 * 3) = 7;

[0103] (3) When I_plane = 3, PLANE TARGET (I_plane)=PLANE(p=15), and FbTh=565 and FbTh2=566, where N=7+(1*(I_plane+1))=7+(1*4)=11;

[0104] (4) When I_plane = 4, PLANE TARGET (I_plane)=PLANE(p=20), and FbTh=565 and FbTh2=566, where N=7+(1*(I_plane+1))=7+(1*5)=12;

[0105] (5) When I_plane = 5, PLANE TARGET (I_plane)=PLANE(p=21), and FbTh=565 and FbTh2=566, where N=7+(1*(I_plane+1))=7+(1*6)=13; and

[0106] (6) When I_plane = 6, PLANE TARGET (I_plane)=PLANE(p=23), and FbTh=565 and FbTh2=566, where N=7+(1*(I_plane+1))=7+(1*7)=14;

[0107] The rest can be deduced similarly, but the present invention is not limited thereto.

[0108] For example, before executing a first loop including steps S23 to S26, the memory controller 110 may calculate a first predetermined value (e.g., the difference between the minimum number of non-damaged blocks Fb0 and the first reserved block threshold Reserved_BLK_Th(1) (Fb0-Reserved_BLK_Th(1))) as the upper limit N of the bad block indicator in step S23. MAX , for controlling the execution condition of the first loop, but the present invention is not limited thereto. For another example, the memory controller 110 may pre-set the upper limit N of the bad block indicator before executing the first loop. MAX The initial value of is equal to the first predetermined value, and the upper limit N of the bad block indicator is updated during the execution of the first loop. MAXIn particular, at a first time point t1(I_plane) when the operation of step S25 is completed, the latest bad block selection threshold FbTh is obtained as the latest bad block selection threshold FbTh(I_plane) corresponding to the plane index I_plane, and at any time point t in the interval [t1(I_plane), t2(I_plane)] between the first time point t1(I_plane) and a second time point t2(I_plane) when step S23 is re-entered, the upper limit N of the bad block indicator is set to MAX Updated to the difference between the latest bad block selection threshold FbTh(I_plane) and the first reserved block threshold Reserved_BLK_Th(1) (FbTh(I_plane)-Reserved_BLK_Th(1)) to control the execution condition of the first loop. According to some embodiments, the calculation method of the bad block indicator N can be changed, and the upper limit N of the bad block indicator MAX The bad block indicator N may be changed accordingly with the change of the calculation method of the bad block indicator N. For example, before executing the first loop, the memory controller 110 may pre-set the bad block indicator upper limit N MAX The initial value is equal to the first predetermined value (for example, the number of blocks CNT BLK or Fblock MAX ), and generate a bad block number estimation value N according to the statistical result of the plurality of blocks {BLK} EST (I_plane) is used as a bad block indicator N to indicate the number of bad blocks N to be included in the estimated bad blocks {BLK(k)} REAL (I_plane), where the estimated number of bad blocks is N EST (I_plane) can correspond to the number of bad blocks N REAL (I_plane), in particular, the number of bad blocks N REAL N of (I_plane) FACTOR times, and the upper limit N of the bad block indicator in step S23 MAX Can be replaced by Fblock MAX , for example N FACTOR =(Fblock MAX / N MAX ), but the present invention is not limited to this.

[0109] In step S27, the memory controller 110 may determine whether the previous bad block indicator pre_N is less than or equal to the bad block indicator upper limit N. MAX (denoted as "pre_N≤N MAX " for simplicity). If (for example: pre_N≤N MAX ), go to step S28; if not, go to step S30.

[0110] In step S28, the memory controller 110 may fine-tune the bad block selection threshold FbTh. In particular, with a predetermined increment, for example, increasing the bad block selection threshold FbTh (e.g., FbTh += 1), so that the bad block selection threshold FbTh moves along the Fblock axis in the increasing direction, for the purpose of attempting to increase the number of bad blocks {BLK(k)} to be rearranged during the execution of a second loop including steps S27 - S29, thereby increasing the sub-region R(1) and / or increasing the number of smaller throughput super-blocks {XBLK LOWER_THROUGHPUT}, but the present invention is not limited thereto.

[0111] In step S29, the memory controller 110 may update or calculate the previous bad block indicator pre_N. For example, the previous bad block indicator pre_N may be equal to the number of bad blocks {BLK(k)} corresponding to Fblock ≤ FbTh in the bad block distribution plus the number of candidate bad blocks {BLK(k)} corresponding to Fblock > FbTh, where the candidate bad blocks {BLK(k)} may include the bad blocks {BLK(k)} corresponding to FbTh < Fblock ≤ FbTh3 in the target planes {PLANE TARGET (0), …, PLANE TARGET (I_plane)} that have been examined at the current time point (e.g., the time point of executing step S29), and "FbTh3" may represent the next-layer candidate value of the latest bad block selection threshold FbTh after fine-tuning the bad block selection threshold FbTh, for indicating the next-layer maximum value of the bad block distribution, but the present invention is not limited thereto. According to some embodiments, the candidate bad blocks {BLK(k)} in step S29 may be varied. For example, the candidate bad blocks {BLK(k)} may include the bad blocks {BLK(k)} corresponding to FbTh < Fblock ≤ FbTh3 in the global plane {PLANE}.

[0112] In step S30, the memory controller 110 may rearrange at least a part of the above-mentioned bad blocks {BLK(k)} starting from the boundary between the (maximum throughput super-block region R MAX_THROUGHPUT (1) and the remaining region R REMAIN (1)) corresponding to the first reserved block threshold Reserved_BLK_Th(1) and starting from the global plane PLANE(p = 0).

[0113] In step S31, the memory controller 110 may store the positions of the respective starting bad blocks of the global plane {PLANE} as the processing result of the current way {WAY(Intlv)} for generating the at least one BR management table (eg, the BR management table 120BR and / or the temporary BR management table 116BR).

[0114] In step S32, the memory controller 110 may generate the at least one BR management table (eg, the BR management table 120BR and / or the temporary BR management table 116BR), in particular, according to the plurality of ways {WAY(Intlv)|Intlv=0, . . . , (WAY TOTAL -1)}, the respective processing results, from (such as the WAY TOTAL The multiple ways {WAY(Intlv)|Intlv=0,…,(WAY TOTAL -1)} selects a minimum sub-region R(1) as a common sub-region R(1) to configure the multiple ways {WAY(Intlv)|Intlv=0,…,(WAY TOTAL -1)} are all equal to the common sub-region R(1), so as to generate the at least one BR management table corresponding to the configuration of the common sub-region R(1).

[0115] For a better understanding, the method can be used Figure 7 According to some embodiments, one or more steps may be performed in Figure 7 For example, after leaving the first loop including steps S23 to S26, the memory controller 110 can directly perform the operation of step S30 based on the latest bad block selection threshold FbTh, without having to fine-tune the bad block selection threshold FbTh by executing the second loop including steps S27 to S29 one or more times. For another example, assuming that there are not many bad blocks in the bad block distribution, the memory controller 110 may be due to "I_plane<(PLANE MAX -1)” is satisfied and leaves the first loop. In this case, the memory controller 110 may further check in step S27 whether the bad block selection threshold FbTh is less than Fblock MAX In particular, in step S27, the memory controller 110 may determine whether the bad block selection threshold FbTh is less than Fblock MAX And the previous bad block indicator pre_N is less than or equal to the bad block indicator upper limit N MAX (It can be Figure 7The <Fblock MAX &&pre_N≤N MAX " for simplicity). If it is (for example: FbTh <Fblock MAX And pre_N≤N MAX ), go to step S28; if not, go to step S30. In addition, the memory controller 110 may control the candidate values ​​FbTh2 and FbTh3 not to exceed Fblock MAX To avoid any possible calculation errors. For the sake of brevity, similar contents in these embodiments are not repeated here.

[0116] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for managing storage space of a memory device by means of dynamic block configuration, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the at least one non-volatile memory element comprising a plurality of blocks, the method comprising: Using the memory controller to configure at least a portion of the plurality of blocks into a plurality of first blocks in a first region and a plurality of second blocks in a second region according to a first reserved block threshold, so as to reserve the plurality of first blocks for data access, wherein any block of the plurality of blocks belongs to a plane of a plurality of planes of the at least one non-volatile memory element, so as to allow the memory controller to configure the blocks respectively belonging to the plurality of planes into a super block; Combining the plurality of first blocks into a group of first super blocks in the first region, wherein the number of blocks of the first blocks in each first super block in the group of first super blocks is equal to a first predetermined number of blocks, and a super block number of the group of first super blocks is equal to the first reserved block threshold; as well as At least a portion of the second blocks among the plurality of second blocks are combined into a group of second super blocks in the second region, wherein the number of blocks of the second blocks in each second super block in the group of second super blocks is less than the first predetermined number of blocks, and the first reserved block threshold is less than a minimum number of non-damaged blocks among the respective numbers of non-damaged blocks of the plurality of planes, so that the memory controller increases an available storage capacity of the memory device by increasing the ratio of the size of the second region to the size of the first region.

2. The method according to claim 1, It is characterized in that The memory controller is used to determine the first reserved block threshold to be less than the minimum number of non-damaged blocks and greater than or equal to a preset value, so as to control a guaranteed performance storage capacity of the memory device to be greater than or equal to a predetermined guaranteed performance storage capacity for data access corresponding to a first target performance.

3. The method according to claim 2, It is characterized in that The first target performance represents a maximum throughput of the memory device with respect to data access.

4. The method according to claim 1, It is characterized in that The memory controller is used to control the number of super blocks of the group of first super blocks to be equal to the first reserved block threshold rather than a maximum available reserved block threshold, so as to increase the number of second super blocks in the second area by increasing the number of second blocks in a plane with the minimum number of non-damaged blocks, so as to balance a guaranteed performance storage capacity and the available storage capacity of the memory device, wherein the maximum available reserved block threshold represents the minimum number of non-damaged blocks.

5. The method according to claim 1, It is characterized in that The memory controller is used to use a second block in a plane having the minimum number of non-defective blocks as a margin for configuring one or more additional second super blocks in the second area, wherein the number of blocks of the second blocks in each of the one or more additional second super blocks is less than the first predetermined number of blocks.

6. The method according to claim 1, It is characterized in that The memory controller configures the at least a portion of the plurality of blocks as the plurality of first blocks in the first area and the plurality of second blocks in the second area according to the first reserved block threshold, so as to reserve the plurality of first blocks for data access corresponding to a first target performance.

7. The method according to claim 6, It is characterized in that At least one non-volatile memory element represents a plurality of non-volatile memory elements, and any block among the plurality of blocks belongs to a plane among a plurality of planes of a non-volatile memory element among the plurality of non-volatile memory elements, so as to allow the memory controller to configure the blocks respectively belonging to the plurality of planes to become the super block, so as to achieve the first target performance by simultaneous access.

8. The method according to claim 6, It is characterized in that The first target performance represents a maximum throughput of the memory device with respect to data access.

9. The method according to claim 1, It is characterized in that The at least a portion of the blocks represent non-damaged blocks among the plurality of blocks, but not any damaged blocks.

10. The method according to claim 1, It is characterized in that The second area includes a plurality of sub-areas, and the plurality of sub-areas include a first sub-area and a second sub-area, wherein the group of second super blocks is located in the first sub-area; and the memory controller is used to determine the boundary between the first sub-area and the second sub-area based on any one of a sub-area boundary default setting, a sub-area boundary user setting and a statistical result of the plurality of blocks.

11. The method according to claim 1, It is characterized in that The memory controller is used to determine the first reserved block threshold according to any one of a reserved block threshold preset setting, a reserved block threshold user setting, and a statistical result of the plurality of blocks.

12. A memory controller of a memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the at least one non-volatile memory element comprising a plurality of blocks, the memory controller comprising: a processing circuit for controlling the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, wherein the processing circuit is used to perform storage space management of the memory device by means of dynamic block configuration; and a transmission interface circuit for communicating with the host device; in: The memory controller configures at least a portion of the plurality of blocks into a plurality of first blocks in a first area and a plurality of second blocks in a second area according to a first reserved block threshold, so as to reserve the plurality of first blocks for data access, wherein any block of the plurality of blocks belongs to a plane of a plurality of planes of the at least one non-volatile memory element, so as to allow the memory controller to configure the blocks respectively belonging to the plurality of planes into a super block; The memory controller combines the plurality of first blocks into a group of first super blocks in the first region, wherein the number of blocks of the first blocks in each first super block in the group of first super blocks is equal to a first predetermined number of blocks, and a super block number of the group of first super blocks is equal to the first reserved block threshold; as well as The memory controller combines at least a portion of the second blocks among the plurality of second blocks into a group of second super blocks in the second region, wherein the number of blocks of the second blocks within each second super block in the group of second super blocks is less than the first predetermined number of blocks, and the first reserved block threshold is less than a minimum number of non-damaged blocks among the respective numbers of non-damaged blocks of the plurality of planes, so that the memory controller increases an available storage capacity of the memory device by increasing the ratio of the size of the second region to the size of the first region.

13. The memory device comprising the memory controller as claimed in claim 12, wherein the memory device comprises: The non-volatile memory is used to store information; and The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

14. An electronic device comprising the memory device as claimed in claim 13, and further comprising: The host device is coupled to the memory device, wherein the host device comprises: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor for providing power to the at least one processor and the memory device; The memory device provides storage space for the host device.

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