Initialization debugging method suitable for DDR PHY module and DDR PHY module

Abstract

The invention relates to an initialization debugging method suitable for a DDR PHY module and the DDR PHY module. The method comprises the following steps: for a chip with a DDR, transmitting initialization configuration source data of a first clock domain to a DDR PHY module in a lightening stage; in the DDR PHY module, the received initialization configuration source data are converted and processed into initialization target information of the second clock domain, the DDR PHY module is driven to be initialized based on the initialization target information, the DDR PHY module enters a debugging state after initialization, and the initialization target information is matched with standard debugging driving information of the second clock domain. According to the method, in the chip lightening stage, the initialization debugging work of the DDR PHY module is moved leftwards and independently carried out, so that parallel debugging with a CPU-DDR channel is achieved, and the initialization debugging efficiency of the DDR PHY module is improved.

Description

Technical Field

[0001] The present invention relates to an initialization debugging method and a DDR PHY module, in particular to an initialization debugging method and a DDR PHY module suitable for the DDR PHY module. Background Art

[0002] The production of chips generally goes through stages such as design, verification, tape-out, and lighting. During the lighting stage, since there are many factors in the real physical world that affect the operation of the chip, and the means of observing the operation of the chip are limited, how to complete the debugging of each module of the chip more efficiently and accurately is the constant pursuit of every engineer.

[0003] At present, most chips contain double-rate synchronous dynamic random access memory (DDR) during architecture design. Whether in data storage or program operation, DDR plays a key role as a large amount of data transfer center and plays an important role in the efficient operation of the chip. Therefore, when the chip is completed and returned to the laboratory for lighting, the debugging of the DDRPHY module has always been a focus of attention.

[0004] Currently, for a small chip, debugging of a DDR PHY module includes pre-debugging operations, wherein the pre-debugging operations include powering on the chip, resetting correctly, starting the CPU normally, and the corresponding operation steps of the CPU sending data to the DDR after starting; wherein the CPU is the processor in the chip. After the above pre-debugging operations are completed, the configuration and data reading and writing of DDRC (DDRControler) and DDR PHY can be realized, thereby realizing debugging of the DDR PHY module.

[0005] It should be noted that the pre-debugging operation often takes a lot of time, causing the debugging time of the DDR PHY module to be pushed back continuously. That is, this sequential execution debugging method causes the debugging work of the DDR PHY module to not be carried out in the first time. It also causes the debugging of the DDR PHY module to be dependent on the status of the pre-debugging operation to a certain extent. Among them, the dependence on the status of the pre-debugging operation specifically includes two major factors: whether the steps in the pre-debugging operation are successful or not, and whether the related circuit functions of the pre-debugging operation are complete or not.

[0006] Therefore, in order to improve the chip production efficiency, it is necessary to improve the debugging efficiency. For example, a method is needed to start the DDRPHY module debugging work as soon as possible, so that the debugging of the DDR PHY module and the CPU debugging and other tasks can be carried out in parallel, rather than in the above sequence. This has become an urgent need for chiplet debugging. Summary of the invention

[0007] The purpose of the present invention is to overcome the shortcomings of the prior art and provide an initialization debugging method and a DDR PHY module suitable for a DDR PHY module. In the chip lighting stage, the initialization debugging of the DDR PHY module is shifted left and carried out independently, so as to at least achieve parallel debugging with the CPU-DDR path, thereby improving the efficiency of initialization debugging of the DDR PHY module.

[0008] According to the technical solution provided by the present invention, an initialization debugging method suitable for a DDR PHY module configures the initialization debugging of the DDR PHY module to be independent of the debugging of the CPU-DDR path during the lighting stage, and shifts the execution timing of the initialization debugging of the DDR PHY module to the left from the standard initialization debugging position, wherein the initialization debugging method for the DDR PHY module includes:

[0009] For a chip with DDR, in the lighting stage, the initialization configuration source data of the first clock domain is transmitted to the DDR PHY module, wherein at least in the CPU-DDR path debugging stage of the chip, the initialization configuration source data of the first clock domain is transmitted to the DDR PHY module via the interface control module;

[0010] In the DDR PHY module, the received initialization configuration source data is converted and processed into the initialization target information of the second clock domain, so as to drive the DDR PHY module to initialize based on the initialization target information, and enter the debugging state after initialization, wherein,

[0011] The initialization target information matches the standard debugging drive information of the second clock domain, wherein after the CPU-DDR path debugging is successfully performed on the chip, the standard debugging drive information is transmitted to the DDR PHY module through the CPU-DDR path;

[0012] Perform standard initialization debugging on the DDR PHY module based on standard debugging driver information.

[0013] The DDR PHY module at least includes a configuration data selection module, an APB control module, a TDR control module and a TDR configuration module, wherein:

[0014] When the standard debugging driving information of the second clock domain is transmitted to the configuration data selection module via the APB control module, the DDR PHY module is driven to perform standard initialization debugging;

[0015] The TDR control module and the TDR configuration module convert the initialization configuration source data of the first clock domain to generate corresponding second clock domain initialization target information, and transmit the initialization target information of the second clock domain to the configuration data selection module, so that the initialization debugging execution timing of the DDR PHY module is shifted left from the standard initialization debugging position.

[0016] When transmitting the initialization target information of the second clock domain to the configuration data selection module, firstly transmitting the initialization configuration source data of the first clock domain to the TDR control module;

[0017] Based on the initialization configuration source data of the first clock domain, the TDR control module generates initialization configuration information of the first clock domain, and transmits the generated initialization configuration information of the first clock domain to the TDR configuration module;

[0018] The TDR configuration module converts the initialization configuration information of the first clock domain into the initialization target information of the second clock domain, and transmits the initialization target information of the second clock domain to the configuration data selection module.

[0019] When the initialization debugging execution timing of the DDR PHY module is shifted leftward from the standard initialization debugging position, the TDR configuration module is configured to be at least in the first state and the second state, wherein:

[0020] When the TDR configuration module is in the first state, the TDR configuration module converts the initialization configuration information of the first clock domain into the initialization target information of the second clock domain, and transmits the initialization target information of the second clock domain to the configuration data selection module;

[0021] When the TDR configuration module is in the second state, the DDR PHY debugging information of the first clock domain is transmitted to the TDR configuration module via the TDR control module.

[0022] The TDR configuration module selects the DDR PHY debugging information of the first clock domain, and transmits the selected DDR PHY debugging information of the first clock domain to the configuration data selection module, so as to debug the DDR PHY module by using the DDR PHY debugging information of the first clock domain.

[0023] The TDR configuration module includes a cross-clock domain processing module, a data processing module and a selection processor connected in sequence, wherein:

[0024] The cross-clock domain processing module is adapted and connected with the TDR control module;

[0025] When the TDR configuration module is in the first state, the initialization configuration information of the first clock domain transmitted by the TDR control module is converted into the initialization configuration information of the second clock domain by the cross-clock domain processing module.

[0026] The initialization configuration information of the second clock domain is processed by the data processing module to generate the initialization target information of the second clock domain, wherein the data processing performed by the data processing module on the initialization configuration information of the second clock domain at least includes signal width processing;

[0027] The initialization target information of the second clock domain generated by the data processing module is selected and output by the selection processor, and transmitted to the configuration data selection module;

[0028] When the TDR configuration module is in the second state, the DDR PHY debugging information of the first clock domain transmitted by the TDR control module is selected and output by the selection processor, and the DDR PHY debugging information of the first clock domain is transmitted to the configuration data selection module.

[0029] The selection processor at least includes a multiplexer, wherein:

[0030] The output end of the data processing module is connected to the first selection input end of the multiplexer, and the output end of the TDR control module is also connected to the second selection input end of the multiplexer;

[0031] The selection control end of the multiplexer receives a conversion processing enable control signal, wherein when the TDR configuration module is configured to be in a first state based on the conversion processing enable control signal, the input information corresponding to the first selection input end of the multiplexer is selected and output;

[0032] When the TDR configuration module is configured to be in the second state based on the conversion processing enable control signal, the input information corresponding to the second selection end of the multiplexer is selected and output.

[0033] The conversion processing enabling control signal is provided by the interface control module and transmitted to the selection control terminal of the multiplexer;

[0034] The interface control module also provides DDR PHY debug source data of the first clock domain, wherein:

[0035] The DDR PHY debugging source data of the first clock domain is transmitted to the TDR control module to form the DDR PHY debugging information of the first clock domain through the TDR control module.

[0036] The interface control module includes a JTAG control module, wherein:

[0037] When the interface control module adopts the JTAG control module, the DDR PHY module receives the initialization configuration source data of the first clock domain, the DDR PHY debugging source data of the first clock domain, and the conversion processing enable control signal transmitted by the JTAG control module through the PHY PUB bus;

[0038] The APB control module receives standard debugging driving information of the second clock domain through the PHY PUB bus.

[0039] The configuration data selection module is also connected to a decoder unit, wherein:

[0040] The decoder unit includes at least a first decoder, a second decoder and a third decoder.

[0041] A DDR PHY module, the DDR PHY module comprising:

[0042] An APB control module, used for transmitting standard debugging drive information of the second clock domain to the configuration data selection module;

[0043] A TDR control configuration unit, configured to receive the initialization configuration source data of the first clock domain, generate the initialization target information of the second clock domain based on the initialization configuration source data of the first clock domain, and transmit the initialization target information of the second clock domain to the configuration data selection module;

[0044] The configuration data selection module receives the standard debugging drive information of the second clock domain or the initialization target information of the second clock domain, wherein:

[0045] Based on the standard debugging driving information of the second clock domain, the DDR PHY module where the driver is located performs standard initialization debugging;

[0046] Based on the initialization target information of the second clock domain, the execution timing of the initialization debugging of the DDR PHY module is configured to be shifted leftward from the standard initialization debugging position.

[0047] The advantages of the present invention are as follows: at least in the CPU-DDR path debugging stage of the chip, the initialization configuration source data of the first clock domain is transmitted to the DDR PHY module; in the DDR PHY module, the received initialization configuration source data is converted and processed into the initialization target information of the second clock domain, so as to perform the initialization debugging of the DDR PHY module based on the initialization target information. At this time, in the lighting stage, the initialization debugging of the DDR PHY module and the debugging of the CPU-DDR path can be configured into a parallel debugging state, so that the initialization debugging work of the DDR PHY module can be shifted to the left and carried out independently, that is, in the lighting stage, the DDR PHY module can be quickly started in the early stage of the chip lighting stage, thereby improving the initialization debugging efficiency of the DDR PHY module. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 The present invention is an implementation flow chart of initializing and debugging a DDR PHY module.

[0049] Figure 2 The figure is a structural block diagram of an embodiment of a DDR PHY module of the present invention.

[0050] Figure 3 The figure is a structural block diagram of an embodiment of the TDR configuration module of the present invention.

[0051] Figure 4 A schematic diagram of an embodiment of a cross-clock processing module of the present invention.

[0052] Figure 5 for Figure 4 A working timing diagram of an embodiment of a mid-span clock processing module.

[0053] Figure 6 A schematic diagram of an embodiment of signal width processing performed by a data processing module of the present invention.

[0054] Explanation of the accompanying drawings: 1-DDR PHY module, 2-JTAG control module, 3-TDR control module, 4-TDR configuration module, 5-APB control module, 6-configuration data selection module, 7-first decoder, 8-second decoder, 9-third decoder, 10-cross-clock processing module, 11-data processing module, 12-selection processor. DETAILED DESCRIPTION

[0055] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0056] In order to shift the initialization debugging work of the DDR PHY module 1 to the left and carry it out independently in the chip lighting stage, and improve the debugging efficiency of the DDR PHY module 1, the present invention provides an initialization debugging method suitable for the DDR PHY module 1. Specifically, in the lighting stage, the initialization debugging of the DDR PHY module 1 is configured to be independent of the debugging of the CPU-DDR path, and the execution timing of the initialization debugging of the DDR PHY module 1 is shifted to the left from the standard initialization debugging position. The initialization debugging method for the DDR PHY module 1 includes:

[0057] Step S1, for a chip with DDR, in the lighting stage, transmitting the initialization configuration source data of the first clock domain to the DDR PHY module 1, wherein at least in the CPU-DDR path debugging stage of the chip, the initialization configuration source data of the first clock domain is transmitted to the DDR PHY module 1 via the interface control module;

[0058] Step S2: in the DDR PHY module 1, the received initialization configuration source data is converted into the initialization target information of the second clock domain, so as to drive the DDR PHY module 1 to initialize based on the initialization target information, and enter the debugging state after initialization, wherein:

[0059] The initialization target information matches the standard debugging drive information of the second clock domain, wherein the standard debugging drive information is transmitted to the DDR PHY module 1 through the CPU-DDR path after the CPU-DDR path debugging is successfully performed on the chip;

[0060] The standard initialization debugging is performed on the DDR PHY module 1 based on the standard debugging driving information.

[0061] It should be noted that for chips with DDR, when using DDR from the initial state, the DDR needs to be reset first. After the reset, it has to go through an initialization phase. After the initialization phase, data reading and writing operations can be performed on the DDR. Among them, the initialization phase of DDR will write configuration data to the registers in the DDR IP and execute some instructions. The specific configuration data corresponds to the DDR type, engineering design requirements, etc., depending on the situation.

[0062] In one embodiment of the present invention, the initialization debugging of the DDR PHY module 1 specifically refers to initializing the DDR PHY module 1 for a chip having DDR during the lighting stage, and driving the DDR PHY module 1 to enter the debugging state after initialization, that is, performing the above-mentioned initialization stage operation of the DDR. The DDR in the chip can adopt the existing commonly used DDR architecture, such as DDR can at least include a DDR controller (DDRC, DDR Controler), a DDR PHY module 1 and DDR particles, wherein the DDR controller is mainly responsible for the transmission efficiency and scheduling when other subsystems (such as CPU) and DDR perform data interaction, and the DDR PHY module 1 is mainly responsible for the transmission speed scheduling during the data interaction process. The role of the DDR controller, the DDR PHY module 1 and the DDR particles in the DDR can be consistent with the existing DDR, so as to cooperate to realize data transfer.

[0063] As can be seen from the above background technology, the lighting stage is a stage in the chip production process, which mainly debugs the chip. At present, when initializing and debugging the DDR PHY module 1, it is necessary to perform the debugging pre-operation first, wherein the debugging pre-operation includes the normal startup of the CPU, and the corresponding operation steps of the CPU sending data to the DDR after startup. The operation of the CPU sending data to the DDR after startup is to perform the debugging of the CPU-DDR path, that is, only when the debugging of the CPU-DDR path is passed, can the DDR PHY module 1 be initialized and debugged; it can be seen that in the prior art, the initialization debugging of the DDR PHY module 1 cannot be carried out independently. As can be seen from the above description, the debugging method of sequential execution steps in the current lighting stage will result in low efficiency in the initialization debugging of the DDR PHY module 1, and further lead to low execution efficiency of the chip in the lighting stage.

[0064] It should be noted that after the debugging of the CPU-DDR path is passed, when the DDR PHY module 1 is debugged, the standard debugging drive information of the second clock domain is transmitted to the DDR PHY module 1 through the CPU-DDR path. At this time, the standard initialization debugging can be performed on the DDR PHY module 1 based on the standard debugging drive information; wherein, the standard initialization debugging is the initialization debugging performed on the DDR PHY module 1 in the existing lighting stage.

[0065] In order to improve the execution efficiency of the chip in the lighting stage, in one embodiment of the present invention, the initialization debugging of the DDR PHY module 1 is configured to be independent of the debugging of the CPU-DDR path, and the execution timing of the initialization debugging of the DDR PHY module 1 is shifted to the left from the standard initialization debugging position, wherein the initialization debugging of the DDR PHY module 1 is independent of the debugging of the CPU-DDR path, that is, there is no need to wait for the debugging of the CPU-DDR path to succeed before initializing and debugging the DDR PHY module 1. The execution timing of the initialization debugging of the DDR PHY module 1 is shifted to the left from the standard initialization debugging position, that is, the execution timing of the initialization debugging of the DDR PHY module 1 of the present invention can be earlier than the execution timing of the existing standard initialization debugging. Therefore, compared with the existing initialization debugging of the DDR PHY module 1, when the present invention performs initialization debugging of the DDR PHY module 1, it is not necessary to wait for the debugging of the CPU-DDR path to succeed, and the initialization debugging of the DDR PHY module 1 can be carried out at an earlier timing position than the standard initialization debugging.

[0066] Specifically, the standard initialization debugging position is used as the reference timing position, and the timing position earlier than the standard initialization debugging position is the left-shifted timing position. In one embodiment of the present invention, the left-shifted timing position from the standard initialization debugging position can be selected, such as the execution timing of the initialization debugging of the DDR PHY module 1 can be left-shifted to the parallel stage with the CPU-DDR path debugging. At this time, the initialization debugging of the DDR PHY module 1 and the CPU-DDR path debugging are configured in a parallel debugging state. In specific implementation, the execution timing of the initialization debugging of the DDR PHY module 1 is the execution position or execution order of the DDR PHY module 1, wherein the execution position and execution order are the position or order in the lighting stage.

[0067] In one embodiment of the present invention, the initialization debugging of the DDR PHY module 1 and the CPU-DDR path debugging are configured in a parallel debugging state, specifically, while executing the CPU-DDR path debugging, the initialization debugging of the DDR PHY module 1 is executed, without waiting for the CPU-DDR path debugging to succeed before initializing the DDR PHY module 1, that is, the debugging of the DDR PHY module 1 and the CPU-DDR path debugging are configured in a parallel debugging state, specifically, the initialization debugging position of the DDR PHY module 1 is shifted left to the stage of CUP-DDR path debugging. In other words, the initialization debugging of the DDR PHY module 1 and the CPU-DDR path debugging are configured in a parallel debugging state, which is an embodiment of shifting the execution timing of the initialization debugging of the DDR PHY module 1 to the left. At this time, the initialization debugging of the DDR PHY module 1 can be independently carried out.

[0068] It can be seen from the above description that when initializing and debugging the DDR PHY module 1, the DDR PHY module 1 needs to be initialized first and enter the debugging state after initialization. Figure 1 An embodiment of the present invention for initializing and debugging the DDR PHY module 1 is shown in FIG. Figure 1 It can be known that in order to initialize the DDR PHY module 1, in one embodiment of the present invention, at least in the CPU-DDR path debugging stage, the initialization configuration source data of the first clock domain is transmitted to the DDR PHY module 1; thereafter, in the DDR PHY module 1, the initialization configuration source data received in the first clock domain is converted and processed to obtain the initialization target information of the second clock domain. The initialization configuration source data of the first clock domain can be transmitted to the DDR PHY module 1 through the interface control module, and the method of transmitting the initialization configuration source data of the first clock domain to the DDR PHY module 1 through the interface control module and other processes can refer to the corresponding description below.

[0069] It should be noted that the CPU-DDR channel debugging phase specifically refers to the debugging of the CPU-DDR channel mentioned above; the initialization target information of the second clock domain is the initialization clock signal and the initialization data signal that can meet the initialization of the DDR PHY module 1 and enter the debugging state after initialization. Specifically, the first clock domain and the second clock domain specifically refer to two different clock frequency states.

[0070] Based on the initialization target information, the DDR PHY module 1 can be driven to initialize and enter the debugging state after initialization. Therefore, the initialization target information should match the standard debugging drive information of the second clock domain. Specifically, it matches the standard debugging drive information of the second clock domain, which specifically means that it is positively corresponding to the standard debugging drive information of the second clock domain. The positive correspondence is to satisfy the drive DDR PHY module 1 initialization and enter the debugging state after initialization. Therefore, the initialization target information of the second clock domain, in addition to being in the same second clock domain as the standard debugging drive information, also needs to have the same signal information, specifically to satisfy the drive DDR PHY module 1 initialization and enter the debugging state after initialization. It should be noted that the standard debugging drive information is the reference information transmitted to the DDR PHY module 1 after the CPU-DDR path debugging is successfully executed in the prior art, that is, in the prior art, the DDR PHY module 1 is initialized mainly based on the standard debugging drive information and enters the debugging state after initialization.

[0071] The standard debugging drive information is composed of a reference clock signal and a reference data signal. It can be seen that when the initialization target information matches the standard debugging drive information, it can be obtained that: the initialization clock signal matches the reference clock signal, and the initialization data signal matches the reference data signal. The matching specifically refers to the ability to initialize the DDR PHY module 1 and drive it into the debugging state.

[0072] As can be seen from the above description, the CPU-DDR path debugging phase is executed on the chip, the initialization configuration source data of the first clock domain is transmitted to the DDR PHY module 1, and the initialization target information of the second clock domain is generated in the DDR PHY module 1, so as to drive the initialization of the DDR PHY module 1 based on the initialization target information, and enter the debugging phase after initialization. At this time, the present invention can at least configure the initialization debugging of the DDR PHY module 1 and the debugging of the CPU-DDR path into a parallel debugging state, thereby shifting the initialization debugging work of the DDR PHY module 1 to the left and carrying out it independently, thereby improving the initialization debugging efficiency of the DDR PHY module 1.

[0073] In one embodiment of the present invention, the DDR PHY module at least includes a configuration data selection module 6, an APB control module 5, a TDR control module 3 and a TDR configuration module 4, wherein:

[0074] When the standard debugging driving information of the second clock domain is transmitted to the configuration data selection module 6 via the APB control module 5, the DDR PHY module 1 is driven to perform standard initialization debugging;

[0075] The TDR control module 3 and the TDR configuration module 4 convert the initialization configuration source data of the first clock domain to generate corresponding second clock domain initialization target information, and transmit the second clock domain initialization target information to the configuration data selection module 6, so that the initialization debugging execution timing of the DDR PHY module 1 is shifted left from the standard initialization debugging position.

[0076] Specifically, when the initialization target information of the second clock domain is transmitted to the configuration data selection module 6, the initialization configuration source data of the first clock domain is first transmitted to the TDR control module 3;

[0077] Based on the initialization configuration source data of the first clock domain, the TDR control module 3 generates initialization configuration information of the first clock domain, and transmits the generated initialization configuration information of the first clock domain to the TDR configuration module 4;

[0078] The TDR configuration module 4 converts the initialization configuration information of the first clock domain into the initialization target information of the second clock domain, and transmits the initialization target information of the second clock domain to the configuration data selection module 6 .

[0079] Figure 2 , an embodiment of the DDR PHY module 1 is shown in the figure, in which the DDR PHY module 1 may at least include a configuration data selection module 6, an APB control module 5, a TDR control module 3 and a TDR configuration module 4, wherein the configuration data selection module 6 is adaptively connected to the APB control module 5, and the configuration data selection module 6 is adaptively connected to the TDR control module 3 through the TDR configuration module 4. Specifically, the adaptive connection with the configuration data selection module 6 specifically refers to the ability to perform the required data interaction with the configuration data selection module 6. For the data interaction, please refer to the corresponding description below.

[0080] During specific implementation, the APB control module 5 disassembles and processes the external standard debugging drive source data to generate a corresponding clock signal / data signal after the disassembly, that is, to obtain standard debugging drive information. From the above description, it can be seen that the standard debugging drive information includes a corresponding reference clock signal and a reference data signal, and the standard debugging drive information after the disassembly is transmitted to the configuration data selection module 6.

[0081] The TDR control module 3 disassembles and processes the initialization configuration source data of the first clock domain to generate a corresponding clock signal / data signal. That is, the function of the TDR control module 3 is similar to that of the APB control module 5, but the data sources are different and different disassembly processes are required. From the above description, it can be seen that based on the clock signal and data signal disassembled and generated by the TDR control module 3, the initialization target information of the second clock domain can be generated through the TDR configuration module 4.

[0082] The configuration data selection module 6 collects the clock signal / data signal output by the previous APB control module 5 / TDR configuration module 4, and selects the test function, that is, the method of initialization and entering the debugging state. In addition, after the selection is completed, some signal processing operations are added, and then output to the subsequent decoder unit and other functional unit modules. The situation of the decoder unit can refer to the following description. The other functional unit modules are not shown in the drawings of the present invention. The situation of other functional units may be related to the architecture of the existing DDR PHY module 1, so as to meet the working conditions of the DDR PHY module 1. The situation of other functional modules will not be repeated here.

[0083] It can be seen from the above description that in the prior art, the standard debugging driving information of the second clock domain can be used to drive the DDR PHY module 1 to perform standard initialization debugging. In order to improve the efficiency of initialization debugging of the DDR PHY module 1; in addition, an embodiment of the present invention can convert the initialization configuration source data of the first clock domain into the initialization target information of the second clock domain, and drive the initialization of the DDR PHY module 1 based on the initialization target information, and enter the debugging state after initialization. Therefore, in order to drive the DDR PHY module 1 to perform initialization debugging, it is generally necessary to transmit the standard debugging driving information of the second clock domain to the configuration data selection module 6, or transmit the initialization target information of the second clock domain to the configuration data selection module 6.

[0084] It can be understood that after the initialization target information of the second clock domain or the standard debugging drive information of the second clock domain is transmitted to the configuration data selection module 6, the DDR PHY module 1 where the configuration data selection module 6 is driven to perform initialization, and the method of entering the debugging state after initialization can be consistent with the existing one, specifically based on whether it can meet the requirements of initializing the DDR PHY module 1 and entering the debugging state after initialization.

[0085] When the configuration data selection module 6 performs initialization debugging on the DDR PHY module 1 where it is located, a feasible initialization debugging step may include:

[0086] Step 1: Initialize all clocks in DDR PHY module 1 and configure parameters such as skew and jitter;

[0087] Step 2: Calibrate the Delay lines of all AC / Dbyte / Master.

[0088] Step 3: Calibrate the impedance and set other parameters;

[0089] The above steps of initializing and debugging the DDR PHY module 1 are generally implemented by reading and writing the corresponding registers in the DDR PHY module 1; it should be noted that the steps of initializing and debugging the DDR PHY module 1 and the method of initializing and debugging the DDR PHY module 1 can be selected according to actual needs, so as to meet the initialization and debugging of the current DDR PHY module 1. In addition, the corresponding execution contents and execution processes in the above steps 1 to 3 can be executed by existing commonly used technical means, specifically, so as to meet the initialization and debugging of the DDR PHY module 1.

[0090] In the above description, skew is clock offset. Clock offset skew refers to the time difference between the same clock signal reaching two different registers, which is related to wiring and load. Jitter is clock jitter. Clock jitter refers to the difference between two clock cycles, which is related to the crystal oscillator and the internal circuit of the clock. AC / Dbyte / Master are the corresponding components of DDR PHY module 1. Usually DDR PHY consists of 1 Master host module, several ACs and several Dbytes; specifically, AC is the address and command module, and Dbyte is the data transmission module; Delay line is the delay chain. During the data transmission process, the phase of the clock and data usually has a certain deviation. The phase deviation needs to be adjusted to meet the timing requirements. This requires the delay line chain to compensate the signal for phase, so the Delay line calibration needs to be completed. Impedence calibration is impedance calibration.

[0091] It should be noted that the AC / Dbyte / Master corresponding to DDR PHY module 1 is Figure 2 The connection and coordination relationship among the APB control module 5, the TDR control module 3 and the decoder unit shown in the figure may be consistent with the connection structure in the existing DDR PHY module 1, and the specific corresponding connection relationship will not be repeated here.

[0092] In order to transmit the standard debug driving information of the second clock domain to the configuration data selection module 6, in one embodiment of the present invention, the standard debug driving information of the second clock domain is transmitted to the configuration data selection module 6 via the APB control module 5; Figure 2 In the embodiment, the standard debug driving information of the second clock domain is the standard debug driving information under the DFICLK clock. At this time, the DFICLK clock is the clock of the second clock domain. The method of transmitting the standard debug driving information of the second clock domain to the configuration data selection module 6 via the APB control module 5 can be consistent with the existing one. The APB control module 5 and the configuration data selection module 6 can specifically select the structural form commonly used in the existing DDR PHY module 1.

[0093] In order to obtain the standard debug driver information of the second clock domain, Figure 2 An embodiment is shown in the figure, in which the standard debug drive source data can generate standard debug drive information of the second clock domain through the APB control module 5 under the action of the clock PCLK, and the method of generating the standard debug drive information of the second clock domain can be consistent with the existing method.

[0094] In order to transmit the initialization target information of the second clock domain to the configuration data selection module, in one embodiment of the present invention, the initialization configuration source data of the first clock domain is converted and processed by at least the TDR control module 3 and the TDR configuration module 4 to generate the corresponding initialization target information of the second clock domain, and the initialization target information of the second clock domain is transmitted to the configuration data selection module 6. In specific implementation, the initialization configuration source data of the first clock domain is first transmitted to the TDR control module 3; thereafter, based on the initialization configuration source data of the first clock domain, the TDR control module 3 generates the initialization configuration information of the first clock domain, and transmits the generated initialization configuration information of the first clock domain to the TDR configuration module 4, that is, the TDR control module 3 processes the initialization configuration source data of the first clock domain, and generates the initialization configuration information of the first clock domain after corresponding processing.

[0095] It can be seen from the above description that the initialization configuration source data of the first clock domain includes a number of clock signals / data signals for reading and writing registers in the DDR PHY module 1; specifically, the content of the initialization configuration source data of the first clock domain is to satisfy the formation of the initialization target information of the second clock domain, and to initialize the DDR PHY module 1, and to enter the debugging state upon initialization. In specific implementation, the initialization configuration source data of the first clock domain can be disassembled and processed using the TDR control module 3. The disassembly and processing of the initialization configuration source data of the first clock domain, the method and purpose of the disassembly and processing can refer to the above corresponding description.

[0096] Figure 2 In the embodiment, under the TDRCLK clock, the initialization configuration source data of the first clock domain can be transmitted to the TDR control module 3, and the TDRCLK clock is the first clock domain. As can be seen from the above description, the frequency of the TDRCLK clock is different from the frequency of the PCLK clock and the DFICLK clock; Figure 2 In DDR PHY module 1, the clock frequencies of PCLK and DFICLK must be higher than the clock frequency of TDRCLK.

[0097] Further, the TDR configuration module 4 converts the initialization configuration information of the first clock domain into the initialization target information of the second clock domain, and transmits the initialization target information of the second clock domain to the configuration data selection module 6. In specific implementation, the manner in which the TDR configuration module 4 converts the initialization configuration information of the first clock domain into the initialization target information of the second clock domain can be referred to the following description.

[0098] In one embodiment of the present invention, when the initialization debugging execution timing of the DDR PHY module 1 is shifted leftward from the standard initialization debugging position, the TDR configuration module 4 is configured to be at least in the first state and the second state, wherein:

[0099] When the TDR configuration module 4 is in the first state, the TDR configuration module 4 converts the initialization configuration information of the first clock domain into the initialization target information of the second clock domain, and transmits the initialization target information of the second clock domain to the configuration data selection module 6;

[0100] When the TDR configuration module 4 is in the second state, the DDR PHY debugging information of the first clock domain is transmitted to the TDR configuration module 4 via the TDR control module 3.

[0101] The TDR configuration module 4 selects the DDR PHY debugging information of the first clock domain, and transmits the selected DDR PHY debugging information of the first clock domain to the configuration data selection module 6, so as to debug the DDR PHY module 1 using the DDR PHY debugging information of the first clock domain.

[0102] In order to form Figure 2 As well as the DDR PHY module 1 described above, a TDR configuration module 4 can be added to the existing DDR PHY module 1 to form. At this time, the role of the TDR control module 3 in the DDR PHY module 1 is consistent with the existing one, such as transmitting the DDR PHY debugging information of the first clock domain to the configuration data selection module 6. After the TDR configuration module 4 is added to the DDR PHY module 1, the DDR PHY debugging information of the first clock domain should also be transmitted to the data selection module 6 through the TDR configuration module 4. By using the DDR PHY debugging information of the first clock domain transmitted to the configuration data selection module 6, ATE debugging of the current DDR PHY module 1 can be implemented. ATE debugging is another functional debugging in parallel with the initialization debugging of the DDR PHY module 1. The method and purpose of ATE debugging of the DDR PHY module 1 can be consistent with the existing ATE debugging.

[0103] In order to meet the working requirements of the data selection module 6, in an embodiment of the present invention, the TDR configuration module 4 can be in a first state and a second state. The first state and the second state of the TDR configuration module 4 are specifically described below.

[0104] It can be seen from the above description that after adding the TDR configuration module 4 in the DDR PHY module 1, the TDR control module 3 can be used to generate the initialization configuration information of the first clock domain based on the initial configuration source data of the first clock domain. The TDR configuration module 4 can convert the initialization configuration information of the first clock domain and generate the initialization target information of the second clock domain. At this time, the TDR configuration module 4 is in the first state, and the TDR control module 3 is adaptively connected with the configuration data selection module 6 through the TDR configuration module 4. Based on the first state of the TDR configuration module 4, the DDR PHY module 1 can be initialized and debugged.

[0105] In specific implementation, when the DDR PHY module 1 is initialized and debugged, the TDR configuration module 4 needs to be configured in the first state. At this time, the TDR configuration module 4 can convert the initialization configuration information of the first clock domain to generate the initialization target information of the second clock domain. It can be seen from the above description that the initialization debugging of the DDR PHY module 1 can be driven based on the initialization target information of the second clock domain. Since the TDR configuration module 4 can convert the signal of the first clock domain into the signal of the second clock domain when it is in the first state, and when the DDR PHY module 1 is debugged by ATE, the DDR PHY debugging information of the first clock domain needs to be transmitted to the configuration data selection module 6, therefore, when the DDR module 1 needs to be debugged by ATE, the TDR configuration module 1 needs to be configured in the second state.

[0106] It can be seen from the above description that in order not to affect the transmission of the DDR PHY debugging information of the first clock domain to the configuration data selection module 6 by the TDR control module 3, in one embodiment of the present invention, the TDR configuration module 4 needs to be configured in the second state. When the TDR configuration module 4 is in the second state, the TDR configuration module 4 will not perform the operation of converting the signal of the first clock domain into the signal of the second clock domain. In specific implementation, when the DDR PHY module 1 needs to be debugged by ATE, the TDR configuration module 4 needs to be adjusted to be in the second state. At this time, the DDR PHY debugging information of the first clock domain is transmitted to the TDR configuration module 4 via the TDR control module 3. The TDR configuration module 4 selects the DDR PHY debugging information of the first clock domain and transmits the selected DDR PHY debugging information of the first clock domain to the configuration data selection module 6. That is, after the TDR configuration module 4 is adjusted to be in the second state, the TDR configuration module 4 will not convert the DDR PHY debugging information of the first clock domain, but only transmits the DDR PHY debugging information of the first clock domain to the configuration data selection module 6.

[0107] In one embodiment of the present invention, the TDR configuration module 4 includes a cross-clock domain processing module 10, a data processing module 11 and a selection processor 12 connected in sequence, wherein:

[0108] The cross-clock domain processing module 10 is adaptively connected to the TDR control module 3;

[0109] When the TDR configuration module 4 is in the first state, the initialization configuration information of the first clock domain transmitted by the TDR control module 3 is converted into the initialization configuration information of the second clock domain through the cross-clock domain processing module 10.

[0110] The initialization configuration information of the second clock domain is processed by the data processing module 11 to generate the initialization target information of the second clock domain, wherein the data processing performed by the data processing module 11 on the initialization configuration information of the second clock domain at least includes signal width processing;

[0111] The initialization target information of the second clock domain generated by the data processing module 11 is selected and output by the selection processor 12, and transmitted to the configuration data selection module 6;

[0112] When the TDR configuration module 4 is in the second state, the DDR PHY debugging information of the first clock domain transmitted by the TDR control module 3 is selected and outputted through the selection processor 12 , and the DDR PHY debugging information of the first clock domain is transmitted to the configuration data selection module 6 .

[0113] Figure 3An embodiment of a TDR configuration module 4 is shown. In the figure, the TDR configuration module 4 includes a cross-clock domain processing module 10, a data processing module 11 and a selection processor 12 which are connected in sequence. In addition, the cross-clock processing module 10 is also adaptively connected to the TDR control module 3, wherein the adaptive connection with the TDR control module 3 specifically refers to the connection between the input end of the cross-clock processing module 10 and the output end of the TDR control module 3. In addition, the output end of the TDR control module 3 is also connected to the selection processor 12.

[0114] As can be seen from the above description, when the DDR PHY module 1 needs to be driven for initialization debugging, the initialization configuration information of the first clock domain needs to be transmitted to the TDR configuration module 4, and the TDR configuration module 4 needs to be configured in the first state. At this time, the initialization configuration information of the first clock domain will be converted to generate the initialization configuration information of the second clock domain by the cross-clock domain processing module 10. Thereafter, the initialization configuration information of the second clock domain will be processed by the data processing module 11 to generate the initialization target information of the second clock domain. Since the current TDR configuration module 4 is in the first state, the generated second clock domain initialization target information can be selected and output by the selection processor 12 and transmitted to the configuration data selection module 6.

[0115] When ATE debugging needs to be performed on the DDR PHY module 1, it is necessary to transmit the DDR PHY debugging information of the first clock domain to the TDR configuration module 4, and configure the TDR configuration module 4 to be in the second state. At this time, the DDR PHY debugging information of the first clock domain transmitted by the TDR control module 3 can be selected and output by the selection processor 12 to be transmitted to the configuration data selection module 6.

[0116] It can be seen from the above description that the clock frequency of the first clock domain is smaller than the clock frequency of the second clock domain. Therefore, in order to meet the needs, the cross-clock domain processing module 10 can use the method of inserting a two-stage trigger to synchronize the single-bit signal, and the multi-bit signal can be processed by asynchronous fifo and other methods. That is, the cross-clock domain processing module 10 mainly realizes the signal synchronization of clock domains with different frequencies and improves the stability of signal synchronization.

[0117] Figure 3In the figure, for the initialization configuration information of the first clock domain output by the TDR control module 3, an embodiment in which the initialization configuration information includes a TDR_CsrCmdUpdate signal is shown. The following takes the TDR_CsrCmdUpdate signal as an example to explain the working process of the cross-clock domain processing module 10 and the data processing module 11. Specifically, the TDR_CsrCmdUpdate signal is equivalent to a single-bit signal in the standard debug drive information of the second clock domain. The equivalent signal is a signal sampled in the DFICLK clock domain with a width of 1 clock cycle. However, since the TDR_CsrCmdUpdate signal undergoes signal widening before crossing the clock domain (the signal widening is from the ATE function requirement, that is, the signal output by the TDR control module 3 will undergo signal widening processing), if it is directly sampled after crossing the clock domain, the signal width will be inconsistent with the standard timing, resulting in an error.

[0118] Figure 4 An embodiment of the cross-clock domain processing module 10 is shown in FIG. 1 , in which the cross-clock domain processing module 10 includes a D flip-flop DR1, a D flip-flop DR2 and a D flip-flop DR3, wherein:

[0119] The q terminal of the D flip-flop DR1 is connected to the d terminal of the D flip-flop DR2, and the q terminal of the D flip-flop DR2 is connected to the d terminal of the D flip-flop DR3;

[0120] The clock end of the D flip-flop DR1 is connected to the clock signal aclk, the clock ends of the D flip-flop DR2 and the clock ends of the D flip-flop DR3 are both connected to the clock signal bclk, the d end of the D flip-flop DR1 is connected to the output end of the TDR control module 3, and the q end of the D flip-flop DR3 serves as the output end of the cross-clock domain processing module 10.

[0121] Figure 4 In the cross-clock domain processing module 10 shown in the figure, the clock signal aclk forms the first clock domain, and the clock signal bclk forms the second clock domain. Taking the TDR_CsrCmdUpdate signal as an example, the data signal is the TDR_CsrCmdUpdate signal, and the data signal is loaded to the d end of the D flip-flop DR1. At this time, the q end of the D flip-flop DR1 outputs the adata signal, and the adata signal is transmitted to the d end of the D flip-flop DR2. The output end of the D flip-flop DR2 outputs the bdata0 signal, and the bdata0 signal is loaded to the d end of the D flip-flop DR3, and the bdata1 signal is output through the q end of the D flip-flop DR3. Figure 5 A timing diagram of an embodiment corresponding to the clock signal aclk, the clock signal bclk, the adata signal, the bdata0 signal and the bdata1 signal in the cross-clock domain processing module 10 is shown in FIG.

[0122] When the adata signal is transmitted to the d-terminal of the D flip-flop DR2, the adata signal is an asynchronous signal to the clock signal bclk. Since the adata signal does not meet the setup and hold time of the D flip-flop DR2 in the second clock domain, a metastable state will occur, such as Figure 5 In the metastable region, the bdata0 signal output from the q-terminal of the D flip-flop DR2 in the second clock domain will eventually stabilize, and will stabilize within one cycle of the clock signal bclk. At this time, the bdata0 signal input to the d-terminal of the D flip-flop DR3 in the second clock domain is a stable value and meets the setup and hold time requirements of the D flip-flop, as shown in Figure 1. Figure 5 The stable area is marked in the middle, and thus the bdata1 signal outputted from the q end of the D flip-flop DR3 in the second clock domain is a stable value, and no metastable state is generated.

[0123] right Figure 4 , Figure 5 The cross-clock domain processing module 10 described above can realize the conversion of the initialization configuration information of the first clock domain into the initialization configuration information of the second clock domain, and the converted second clock domain initialization configuration information is in a stable state, which satisfies the corresponding processing by the data processing module later. In specific implementation, the cross-clock domain processing module 10 can also adopt other implementation forms, which can be selected according to needs, so as to meet the corresponding processing requirements of the cross-clock domain processing module 10 in the present invention.

[0124] Specifically, when the data signal is the TDR_CsrCmdUpdate signal, a corresponding signal in the second clock domain can be generated after passing through the cross-clock domain processing module 10. Thereafter, the signal width processing can be performed using the data processing module 11. The signal width processing performed using the data processing module 11 may include processing such as intercepting or extracting the signal length. When performing signal width processing, edge sampling and other means may be used to implement signal width processing.

[0125] Figure 6 FIG. 1 shows a timing diagram of an embodiment of signal width processing using the data processing module 11. In the diagram, bdata1 is the signal output by the cross-clock domain processing module 10. After that, the rising edge and falling edge detection of the bdata1 signal can be performed. Figure 6 The edge detection signal in the figure is an embodiment of performing rising edge and falling edge detection on the bdata1 signal. In the figure, when the bdata1 signal has a rising edge, a rising edge detection pulse is generated after detection. Similarly, when the bdata1 signal has a falling edge, a corresponding falling edge detection pulse is generated after detection. Figure 6In the example, rising edge detection is the rising edge detection pulse, and falling edge detection is the falling edge detection pulse.

[0126] During specific implementation, between the rising edge detection module and the falling edge detection pulse, the time for signal width processing can be determined according to the sampling clock signal clk, and the time for signal width processing should be a multiple of the clock period of the sampling clock signal clk. According to the determined time for signal width processing, signal interception is performed on the bdata1 signal to implement signal width processing; specifically, the intercepted signal is the part between the rising edge and the falling edge of the bdata1 signal, and the time for signal width processing can be selected as needed, so as to meet the matching with the standard debugging drive information of the second clock domain, that is, to meet the requirements for initialization debugging of the DDRPHY module 1.

[0127] During specific implementation, for a determined DDR PHY module 1, standard debugging driving information of the second clock domain of the DDR PHY module 1 during initialization debugging can be determined; for the initialization configuration information of the first clock domain transmitted via the TDR control module 3, personnel in this technical field can determine the equivalent corresponding state of the corresponding clock signal, data signal and the standard debugging driving information of the second clock domain, and thereafter, the initialization target information of the second clock domain can be generated by the cross-clock domain processing module 10 and the data processing module 11, that is, the cross-clock domain processing module 10 and the data processing module 11 cooperate to generate the initialization target information of the second clock domain from the initialization configuration information of the first clock domain.

[0128] It can be understood that, for a certain DDR PHY module 1, based on the standard debug drive information of the second clock domain, the operation of the cross-clock domain processing module 10 and the data processing module 11 can be configured to meet the requirements of generating the initialization target information of the second clock domain that matches the standard debug drive information of the second clock domain. Therefore, the above description can be referred to to determine the corresponding working states of the cross-clock domain processing module 10 and the data processing module 11.

[0129] In one embodiment of the present invention, the selection processor 12 at least includes a multiplexer, wherein:

[0130] The output end of the data processing module 11 is connected to the first selection input end of the multiplexer 12, and the output end of the TDR control module 3 is also connected to the second selection input end of the multiplexer 12;

[0131] The selection control end of the multiplexer receives a conversion processing enable control signal, wherein when the TDR configuration module 4 is configured to be in the first state based on the conversion processing enable control signal, the input information corresponding to the first selection input end of the multiplexer is selected and output;

[0132] When the TDR configuration module 4 is configured to be in the second state based on the conversion processing enable control signal, the input information corresponding to the second selection terminal of the multiplexer is selected and output.

[0133] Specifically, the multiplexer can be a commonly used selector. Figure 3 , an embodiment in which the multiplexer is a two-way selector is shown. It is understandable that the multiplexer can also be a selector of other numbers. When the selection processor 12 adopts a multiplexer, the output end of the data processor 11 should be connected to the first selection input end of the multiplexer, and the output end of the TDR control module 3 should be connected to the second selection input end of the multiplexer. The first selection input end and the second selection input end of the multiplexer are the corresponding input ends of the multiplexer.

[0134] also, Figure 3 Only the processing of single-bit signals is shown. When there are multiple bits, it is necessary to configure a multi-channel unit in the TDR configuration module 4. Each channel unit includes a cross-clock domain processing module 10, a data processor 11 and a selection processor 12. Each channel unit can work synchronously or be enabled to work as needed.

[0135] In specific implementation, the conversion processing enable control signal is received through the selection control end of the multiplexer. If the multiplexer is a two-way selector, the conversion processing enable control signal can be a binary code. For example, when the conversion processing enable control signal is "1", the input information of the first selection input end of the multiplexer can be selected and output. At this time, the TDR configuration module 4 is in the first state; when the conversion processing can control signal is "0", the input information of the second selection input end of the multiplexer can be selected and output. At this time, the TDR configuration module 4 is in the second state; of course, the conversion processing enable control signal can also be in other forms, so as to realize the configuration of the TDR configuration module 4 in the first state or the second state. It can be understood that when the multiplexer is a selector of other types, it can be processed by decoding and the like, so as to select the output of the corresponding selection input end, and examples are not given here one by one.

[0136] In one embodiment of the present invention, based on the conversion processing enable control signal, when the TDR configuration module 4 is configured in the first state, the initialization target information corresponding to the first selection input terminal of the multiplexer can be selected for output. Further, based on the conversion processing enable control signal, when the TDR configuration module 4 is in the second state, the DDR PHY debugging information corresponding to the second selection input terminal of the multiplexer can be selected for output.

[0137] It can be understood that when the TDR configuration module 4 adopts other forms, the TDR configuration module 4 can be configured in the first state or the second state by corresponding technical means according to the form adopted by the TDR configuration module 4. The specific configuration method in the first state or the second state can be selected as needed, and will not be listed here one by one.

[0138] In one embodiment of the present invention, the selection processor 12 further includes a buffer 13, wherein:

[0139] The output end of the multiplexer 12 is adaptively connected to the configuration data selection module 6 through the buffer 13 .

[0140] Figure 3 1 shows an embodiment in which the selection processor 12 is connected to the buffer 13. The buffer in the figure is the buffer 13. The input end of the buffer 13 is connected to the output end of the multiplexer 12, and the output end of the buffer 12 is connected to the input end of the configuration data selection module 6. The buffer 13 can be in an existing commonly used form, such as an inverter, etc. The form of the buffer 13 can be selected according to needs. The use of the buffer 13 can improve the ability to drive the configuration data selection module 6 and is conducive to improving the subsequent timing.

[0141] As can be seen from the above description, the TDR configuration module 4 can be added to the existing DDR PHY module 1 to form the DDR PHY module 1 of the present invention; specifically, when the TDR configuration module 4 is added, the corresponding TDR configuration module 4 can be designed in the RTL design stage of the chip. It can be understood that the TDR configuration module 4 can be independent of the configuration data selection module 6, or can be placed in the configuration data selection module 6, or placed in the TDR control module 3, so as not to affect the transmission of the initialization target information of the second clock domain and the DDR PHY debugging information of the first clock domain to the configuration data selection module 6; Figure 2 FIG. 4 shows an embodiment in which the TDR configuration module 4 is independent of the configuration data selection module 6 .

[0142] It can be seen from the above description that in order to transmit the first clock domain initialization configuration source data to the DDR PHY module 1, an embodiment of the present invention further includes an interface control module for adapting and connecting with the DDR PHY module 1, wherein:

[0143] The conversion processing enabling control signal is provided by the interface control module and transmitted to the selection control terminal of the multiplexer;

[0144] The interface control module also provides initialization configuration source data of the first clock domain and / or DDRPHY debugging source data of the first clock domain, wherein:

[0145] The initialization configuration source data of the first clock domain is transmitted to the TDR control module 3 to form the initialization configuration information of the first clock domain through the TDR control module 3;

[0146] The DDR PHY debugging source data of the first clock domain is transmitted to the TDR control module 3 to form the DDR PHY debugging information of the first clock domain through the TDR control module 3 .

[0147] It can be seen from the above description that when the DDR PHY module 1 is initialized and debugged, it is necessary to provide the first clock domain initialization configuration source data, the DDR PHY debug source data of the first clock domain, and the corresponding conversion processing enable control signal transmitted to the TDR control module 3. In one embodiment of the present invention, the interface control module is adapted to be connected with the DDR PHY module 1, so that the interface control module can provide the first clock domain initialization configuration source data, the DDR PHY debug source data of the first clock domain, and the corresponding conversion processing enable control signal required for the above initialization and debugging.

[0148] It can be understood that after the DDR PHY debug source data of the first clock domain forms the DDR PHY debug information of the first clock domain, the DDR PHY debug information of the first clock domain can be used to perform ATE debugging on the DDR PHY module 1. Therefore, the form of the DDR PHY debug source data of the first clock domain is based on whether it can meet the ATE debugging requirements of the DDR PHY module 1, that is, the DDR PHY debug source data of the first clock domain is related to the ATE test of the DDR PHY module 1.

[0149] In one embodiment of the present invention, the interface control module includes a JTAG control module 2, wherein:

[0150] When the interface control module adopts the JTAG control module 2, the DDR PHY module 1 receives the initialization configuration source data of the first clock domain, the DDR PHY debugging source data of the first clock domain, and the conversion processing enable control signal transmitted by the JTAG control module 2 through the PHY PUB bus;

[0151] The APB control module 5 receives the standard debugging driving information of the second clock domain through the PHY PUB bus.

[0152] Figure 2An embodiment of the interface control module using the JTAG control module 2 is shown in the figure. In the figure, the JTAG control module 2 and the DDR PHY module 1 use the PHY PUB bus. At this time, the initialization configuration source data of the first clock domain, the DDR PHY debugging source data of the first clock domain, and the conversion processing enable control signal transmitted by the JTAG control module 2 are received through the PHY PUB bus; the APB control module 5 receives the standard debugging drive source data of the second clock domain through the PHY PUB bus. In specific implementation, when the interface control module uses the JTAG control module 2, on the one hand, the JTAG interface has universality, and on the other hand, the original ATE test function of the DDR IP requires the TDR control module 3, and it is more convenient to use the data output from the JTAG control module 2 to the TDR control module 3. Therefore, the sampling JTAG control module 2 can be easily integrated and compatible with the existing DDR PHY module 1.

[0153] During specific implementation, the PHY PUB bus may adopt an existing bus form, which is based on whether it can meet the needs of the DDR PHY module 1 to transmit and receive data. Figure 2 The TDR signal in is the initial configuration source data of the first clock domain or the DDR PHY debugging source data of the first clock domain mentioned above, and the TDR_CFG time switch signal (JTAG_Init_en) is the conversion processing enable control signal mentioned above. Figure 2 The APB signal in is the third clock domain. From the above description, it can be seen that, currently, the standard debug drive information is transmitted to the configuration data selection module 6 under the APB signal; in addition, when the chip is used normally, the write information is transmitted to the DDR PHY module 1 through the APB signal.

[0154] In one embodiment of the present invention, the configuration data selection module 6 is further connected to a decoder unit, wherein:

[0155] The decoder unit comprises at least a first decoder 7 , a second decoder 8 and a third decoder 9 .

[0156] Figure 2An embodiment of setting a decoder unit on the configuration data selection module 6 is shown in the figure. In the figure, the decoder unit includes a first decoder 7, a second decoder 8 and a third decoder 9; the decoder unit is used to decode the output of the configuration data selection module 6, and the configuration data selection module 6 will receive data of multiple functions, including the initialization target information of the second clock domain transmitted by the TDR configuration module 4, the DDR PHY debugging information of the first clock domain, and / or, the standard debugging drive information of the second clock domain transmitted by the APB control module 5, etc. Therefore, the configuration data selection module 6 collects a large amount of data and outputs it to the subsequent decoder and other functional unit modules after processing. According to the function currently running by the DDR PHY module 1, the corresponding decoder performs decoding work. Therefore, the specific decoding method and process of the first decoder 7, the second decoder 8 and the third decoder 9 can be consistent with the existing ones, so as to meet the working requirements of the DDR PHY module 1.

[0157] In specific implementation, inside the DDR PHY module 1, for some registers, for reasons of physical proximity (making these registers physically closer together) and easy copying, it is necessary to divide them into multiple register groups. The first decoder 7, the second decoder 8 and the third decoder 9 analyze the cmd (data representing the command) sent to the configuration data selection module 6, determine whether the cmd is a read or write command for which register group, and then feedback; for example, the first decoder 7 determines whether the cmd data at this time is a read or write operation for the APBONLY register group. If it is a read or write operation for the APBONLY register group, it will output a corresponding signal for the subsequent logic to know that the cmd is a read or write operation for the APBONLY register group; if not, it will also output a corresponding signal for the subsequent logic to know that the cmd is not a read or write operation for the APBONLY register group.

[0158] The second decoder 8 and the third decoder 9 also correspond to corresponding DRTUB register groups and INITENG register groups. The specific functions of the second decoder 8 and the third decoder 9 can be referred to the description of the first decoder 7 above, which will not be repeated here.

[0159] During specific implementation, for DDR, the reading and writing of non-configuration storage data will go through DDRC (DDR controller) and DDR PHY module 1, and will finally point to DDR particles. For data pointing to DDR particles, the reading and writing of complete data can be realized through the AXI bus. After the DDR PHY module 1 is initialized and debugged, the prdata signal transmitted through the APB control module 5 can be used to determine whether the DDR PHY module 1 has completed initialization and debugging. Specifically, the prdata signal can read a response signal of 1 at the registers with addresses 32'h400001bc and 32'h40001cbc, and determine whether the DDR PHY module 1 has been initialized and debugged. The method of determining whether the DDR PHY module 1 has completed initialization and debugging through the prdata signal is consistent with the existing method and will not be repeated here.

[0160] It can be seen from the above description that the present invention sets a TDR configuration module 4 in the DDR PHY module 1. When the JTAG control module 2 controls the initialization of the DDR PHY module 1, it can be established on the basis of the original JTAG control module 2. The TDR configuration module 4 completes the processing of part of the signals and timing, and has a small area. The state of the TDR configuration module 4 is controlled by the JTAG control module 2. No additional hardware resources (PAD) are required at the top level of the chip, thereby reducing the cost of initialization and debugging of the DDR PHY module 1.

[0161] From the above description, a DDR PHY module 1 can be obtained. In one embodiment of the present invention, the DDR PHY module 1 includes:

[0162] APB control module 5, used for transmitting standard debugging drive information of the second clock domain to configuration data selection module 6;

[0163] A TDR control configuration unit, configured to receive the initialization configuration source data of the first clock domain, generate the initialization target information of the second clock domain based on the initialization configuration source data of the first clock domain, and transmit the initialization target information of the second clock domain to the configuration data selection module 6;

[0164] The configuration data selection module 6 receives the standard debugging drive information of the second clock domain or the initialization target information of the second clock domain, wherein:

[0165] Based on the standard debugging driving information of the second clock domain, the DDR PHY module 1 where the driver is located performs standard initialization debugging;

[0166] Based on the initialization target information of the second clock domain, the execution timing of the initialization debugging of the DDR PHY module 1 is configured to be shifted leftward from the standard initialization debugging position.

[0167] Specifically, the DDR PHY module 1 of the present invention can be referred to Figure 2 As shown in the figure, it can be known from the above description that the DDR PHY module 1 at least includes an APB control module 5, a configuration data selection module 6 and a TDR control configuration unit, wherein the TDR control configuration unit includes the above-mentioned TDR control module 3 and TDR configuration module 4. The TDR control module 3 and TDR configuration module 4 can be used to transmit the initialization target information of the second clock domain or the DDR PHY debugging information of the first clock domain to the configuration data selection module 6.

[0168] It can be seen from the above description that in the chip lighting stage, for the DDR PHY module 1 of the present invention, the debugging of the DDR PHY module 1 and the debugging of the CPU-DDR path can be configured into a parallel debugging state. At this time, the initialization debugging work of the DDR PHY module 1 can be shifted to the left and carried out independently, thereby improving the initialization debugging efficiency of the DDR PHY module 1. The initialization debugging method and process of the DDR PHY module 1 can refer to the above description and will not be repeated here.

Claims

1. An initialization debugging method suitable for a DDR PHY module, characterized in that: In the lighting stage, the initialization debugging of the DDR PHY module is configured to be independent of the debugging of the CPU-DDR path, and the execution timing of the initialization debugging of the DDR PHY module is shifted left from the standard initialization debugging position, wherein the initialization debugging method of the DDR PHY module includes: For a chip with DDR, in the lighting stage, the initialization configuration source data of the first clock domain is transmitted to the DDR PHY module, wherein at least in the CPU-DDR path debugging stage of the chip, the initialization configuration source data of the first clock domain is transmitted to the DDR PHY module via the interface control module; In the DDR PHY module, the received initialization configuration source data is converted and processed into the initialization target information of the second clock domain, so as to drive the DDR PHY module to initialize based on the initialization target information, and enter the debugging state after initialization, wherein, The initialization target information matches the standard debugging drive information of the second clock domain, wherein after the CPU-DDR path debugging is successfully performed on the chip, the standard debugging drive information is transmitted to the DDR PHY module through the CPU-DDR path; Perform standard initialization debugging on the DDR PHY module based on standard debugging driver information.

2. The initialization debugging method suitable for a DDR PHY module according to claim 1, characterized in that: The DDR PHY module at least includes a configuration data selection module, an APB control module, a TDR control module and a TDR configuration module, wherein: When the standard debugging driving information of the second clock domain is transmitted to the configuration data selection module via the APB control module, the DDR PHY module is driven to perform standard initialization debugging; The TDR control module and the TDR configuration module convert the initialization configuration source data of the first clock domain to generate corresponding second clock domain initialization target information, and transmit the initialization target information of the second clock domain to the configuration data selection module, so that the initialization debugging execution timing of the DDR PHY module is shifted left from the standard initialization debugging position.

3. The initialization debugging method suitable for a DDR PHY module according to claim 2, characterized in that: When transmitting the initialization target information of the second clock domain to the configuration data selection module, firstly transmitting the initialization configuration source data of the first clock domain to the TDR control module; Based on the initialization configuration source data of the first clock domain, the TDR control module generates initialization configuration information of the first clock domain, and transmits the generated initialization configuration information of the first clock domain to the TDR configuration module; The TDR configuration module converts the initialization configuration information of the first clock domain into the initialization target information of the second clock domain, and transmits the initialization target information of the second clock domain to the configuration data selection module.

4. The initialization debugging method suitable for a DDR PHY module according to claim 3, characterized in that: When the initialization debugging execution timing of the DDR PHY module is shifted leftward from the standard initialization debugging position, the TDR configuration module is configured to be at least in the first state and the second state, wherein: When the TDR configuration module is in the first state, the TDR configuration module converts the initialization configuration information of the first clock domain into the initialization target information of the second clock domain, and transmits the initialization target information of the second clock domain to the configuration data selection module; When the TDR configuration module is in the second state, the DDR PHY debugging information of the first clock domain is transmitted to the TDR configuration module via the TDR control module. The TDR configuration module selects the DDR PHY debugging information of the first clock domain, and transmits the selected DDR PHY debugging information of the first clock domain to the configuration data selection module, so as to debug the DDR PHY module using the DDR PHY debugging information of the first clock domain.

5. The initialization debugging method suitable for a DDR PHY module according to claim 4, characterized in that: The TDR configuration module includes a cross-clock domain processing module, a data processing module and a selection processor connected in sequence, wherein: The cross-clock domain processing module is adapted and connected with the TDR control module; When the TDR configuration module is in the first state, the initialization configuration information of the first clock domain transmitted by the TDR control module is converted into the initialization configuration information of the second clock domain by the cross-clock domain processing module. The initialization configuration information of the second clock domain is processed by the data processing module to generate the initialization target information of the second clock domain, wherein the data processing performed by the data processing module on the initialization configuration information of the second clock domain at least includes signal width processing; The initialization target information of the second clock domain generated by the data processing module is selected and output by the selection processor, and transmitted to the configuration data selection module; When the TDR configuration module is in the second state, the DDR PHY debugging information of the first clock domain transmitted by the TDR control module is selected and output by the selection processor, and the DDR PHY debugging information of the first clock domain is transmitted to the configuration data selection module.

6. The initialization debugging method suitable for a DDR PHY module according to claim 5, characterized in that: The selection processor at least includes a multiplexer, wherein: The output end of the data processing module is connected to the first selection input end of the multiplexer, and the output end of the TDR control module is also connected to the second selection input end of the multiplexer; The selection control end of the multiplexer receives a conversion processing enable control signal, wherein when the TDR configuration module is configured to be in a first state based on the conversion processing enable control signal, the input information corresponding to the first selection input end of the multiplexer is selected and output; When the TDR configuration module is configured to be in the second state based on the conversion processing enable control signal, the input information corresponding to the second selection end of the multiplexer is selected and output.

7. The initialization debugging method suitable for a DDR PHY module according to claim 6, characterized in that: The conversion processing enabling control signal is provided by the interface control module and transmitted to the selection control terminal of the multiplexer; The interface control module also provides DDR PHY debug source data of the first clock domain, wherein: The DDR PHY debugging source data of the first clock domain is transmitted to the TDR control module to form the DDR PHY debugging information of the first clock domain through the TDR control module.

8. The initialization debugging method suitable for a DDR PHY module according to claim 7, characterized in that: The interface control module includes a JTAG control module, wherein: When the interface control module adopts the JTAG control module, the DDR PHY module receives the initialization configuration source data of the first clock domain, the DDR PHY debugging source data of the first clock domain, and the conversion processing enable control signal transmitted by the JTAG control module through the PHY PUB bus; The APB control module receives standard debugging driving information of the second clock domain through the PHY PUB bus.

9. The initialization debugging method suitable for a DDR PHY module according to any one of claims 2 to 8, characterized in that: The configuration data selection module is also connected to a decoder unit, wherein: The decoder unit includes at least a first decoder, a second decoder and a third decoder.

10. A DDR PHY module, characterized in that: The DDR PHY module includes: An APB control module, used for transmitting standard debugging drive information of the second clock domain to the configuration data selection module; A TDR control configuration unit, configured to receive the initialization configuration source data of the first clock domain, generate the initialization target information of the second clock domain based on the initialization configuration source data of the first clock domain, and transmit the initialization target information of the second clock domain to the configuration data selection module; The configuration data selection module receives the standard debugging drive information of the second clock domain or the initialization target information of the second clock domain, wherein: Based on the standard debugging driving information of the second clock domain, the DDR PHY module where the driver is located performs standard initialization debugging; Based on the initialization target information of the second clock domain, the execution timing of the initialization debugging of the DDR PHY module is configured to be shifted leftward from the standard initialization debugging position.

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