Schottky device and manufacturing method thereof

Abstract

The invention provides a Schottky device and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate structure, forming an N-type high-voltage well which is located in the substrate structure and is provided with an N-end active region and a P-end active region, forming a P well located on the upper surface layer of the N-type high-voltage well, forming a field oxide layer located on the N-type high-voltage well, and forming an N well located on the upper surface layer of the N-type high-voltage well, forming an N-type lead-out region located on the upper surface layer of the N well, forming an N-end metal silicide layer located on the N-end active region, forming a P-end metal silicide layer located on the P-end active region, forming an interlayer dielectric layer located on the substrate structure, forming N-end metal contact columns located in the interlayer dielectric layer and P-end metal contact columns arranged in a dot-matrix mode, and forming a cathode metal layer and an anode metal layer on the interlayer dielectric layer. The Schottky device can be better compatible with a submicron BCD process while ensuring electrical performance parameters, and has more stable process performance in long-term mass production.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to a Schottky device and a manufacturing method thereof. Background Art

[0002] The current mainstream BCD process generally includes many devices such as bipolar transistors, complementary metal oxide semiconductors, junction field effect transistors and diodes, which are highly integrated and can meet the application scenarios of different products. Schottky diodes occupy a special position in high-frequency product applications with their unique fast recovery characteristics, but most of the current Schottky diodes are produced in the form of discrete devices. Schottky diodes have a simple structure and special functional characteristics. Many application scenarios have the need to make Schottky diodes compatible with the BCD process. However, Schottky diodes occupy a large area and have special requirements for the metal-semiconductor contact surface, especially the process treatment of contact holes. It is not necessary to simply reduce the contact resistance, but a certain Schottky barrier is required to support the diode characteristics. This contradiction makes it difficult for Schottky diodes to be compatible with conventional BCD processes, resulting in the fact that Schottky diodes are rarely used as an option in the BCD process.

[0003] Therefore, how to improve the manufacturing process of Schottky devices to be compatible with the sub-micron BCD process and have a highly stable process performance in long-term production has become an important issue that needs to be urgently solved by technical personnel in this field.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a Schottky device and a method for manufacturing the same, so as to solve the problem that the Schottky device in the prior art is difficult to be compatible with the submicron BCD process and difficult to maintain highly stable process performance in long-term production.

[0006] To achieve the above object and other related objects, the present invention provides a method for manufacturing a Schottky device, comprising the following steps:

[0007] A substrate structure is provided, wherein an N-type high-voltage well is provided in the substrate structure, and the N-type high-voltage well includes an N-terminal active region and a P-terminal active region which are arranged at intervals;

[0008] Forming a P-well, a field oxide layer, an N-well and an N-type lead-out region, wherein the P-well is located on the upper surface layer of the N-type high-voltage well and is located at the edge region of the P-terminal active region, the field oxide layer is located on the N-type high-voltage well and isolates the N-terminal active region from the P-terminal active region in the N-type high-voltage well, the N-well is located on the upper surface layer of the N-type high-voltage well and is located in the N-terminal active region, and the N-type lead-out region is located on the upper surface layer of the N-well;

[0009] Forming an N-terminal metal silicide layer on the N-terminal active region, and forming a P-terminal metal silicide layer on the P-terminal active region;

[0010] forming an interlayer dielectric layer on the base structure, wherein the interlayer dielectric layer covers the field oxide layer, the N-terminal metal silicide layer and the P-terminal metal silicide layer;

[0011] Forming an N-terminal metal contact column and a P-terminal metal contact column in the interlayer dielectric layer, wherein the N-terminal metal contact column is located above the N-terminal active region and contacts the N-terminal metal silicide layer, and the P-terminal metal contact column is located above the P-terminal active region and contacts the P-terminal metal silicide layer, and the number of the P-terminal metal contact columns is multiple and arranged in a matrix;

[0012] A cathode metal layer and an anode metal layer are formed on the interlayer dielectric layer, wherein the cathode metal layer is electrically connected to the N-terminal metal contact column, and the anode metal layer is electrically connected to the P-terminal metal contact column.

[0013] Optionally, the base structure includes a substrate, a blocking buried layer and an epitaxial layer, the blocking buried layer is located on the upper surface layer of the substrate, the epitaxial layer is located on the substrate and covers the blocking buried layer, the N-type high-voltage well is located in the epitaxial layer and the bottom surface of the N-type high-voltage well stops at the blocking buried layer, and the formation of the base structure includes the following steps:

[0014] providing a substrate;

[0015] Performing ion implantation in a preset area on the upper surface of the substrate;

[0016] An epitaxial layer is grown on the substrate, and the epitaxial layer covers the ion implantation region so that the ion implantation region becomes the blocking buried layer.

[0017] Optionally, forming the P-well, the field oxide layer, the N-well and the N-type lead-out region comprises the following steps:

[0018] Forming a P well on the upper surface layer of the N-type high-voltage well, wherein the P well is located at the edge area of ​​the P-end active area;

[0019] Forming a field oxide layer on the N-type high-voltage well, wherein the field oxide layer isolates the N-end active region and the P-end active region in the N-type high-voltage well;

[0020] Forming an N-well on the upper surface layer of the N-type high-voltage well, wherein the N-well is located in the N-terminal active area;

[0021] The N-type lead-out region is formed on the upper surface layer of the N-well.

[0022] Optionally, forming an N-terminal metal contact column and a P-terminal metal contact column in the interlayer dielectric layer includes the following steps:

[0023] Forming a photoresist layer on the interlayer dielectric layer, and patterning the photoresist layer to obtain an N-end etching pattern and a P-end etching pattern, wherein the P-end etching pattern includes a dot matrix opening;

[0024] Etching the interlayer dielectric layer based on the patterned photoresist layer to obtain an N-terminal contact hole and a P-terminal contact hole, wherein the P-terminal contact holes are arranged in a dot matrix;

[0025] The N-terminal contact hole is filled with metal to form the N-terminal metal contact column, and the P-terminal contact hole is filled with metal to form the P-terminal metal contact column.

[0026] Optionally, before forming the N-terminal metal silicide layer and the P-terminal metal silicide layer, a step of forming a silicide blocking layer on the field oxide layer is further included, wherein the silicide blocking layer is provided with an opening exposing the P-terminal active area.

[0027] Optionally, the N-end metal silicide layer and the P-end metal silicide layer are made of the same material, including at least one of titanium silicide, platinum silicide and cobalt silicide.

[0028] Optionally, the plurality of P-terminal metal contact pillars are arranged into at least two rows and at least two columns, and a cross-sectional area of ​​the P-terminal metal contact pillar is greater than a cross-sectional area of ​​the N-terminal metal contact pillar.

[0029] The present invention also provides a Schottky device, comprising:

[0030] A substrate structure, wherein an N-type high-voltage well is provided in the substrate structure, and the N-type high-voltage well includes an N-terminal active region and a P-terminal active region which are arranged at intervals;

[0031] A P-well, a field oxide layer, an N-well and an N-type lead-out region, wherein the P-well is located on the upper surface layer of the N-type high-voltage well and is located at the edge region of the P-terminal active region, the field oxide layer is located on the N-type high-voltage well and isolates the N-terminal active region and the P-terminal active region in the N-type high-voltage well, the N-well is located on the upper surface layer of the N-type high-voltage well and is located in the N-terminal active region, and the N-type lead-out region is located on the upper surface layer of the N-well;

[0032] An N-terminal metal silicide layer and a P-terminal metal silicide layer, wherein the N-terminal metal silicide layer is located on the N-terminal active region, and the P-terminal metal silicide layer is located on the P-terminal active region;

[0033] an interlayer dielectric layer, located on the base structure and covering the field oxide layer, the N-terminal metal silicide layer and the P-terminal metal silicide layer;

[0034] An N-terminal metal contact column, located in the interlayer dielectric layer on the N-terminal active region and in contact with the N-terminal metal silicide layer;

[0035] A P-terminal metal contact column, located in the interlayer dielectric layer on the P-terminal active area and in contact with the P-terminal metal silicide layer, wherein the number of the P-terminal metal contact columns is plural and arranged in a lattice;

[0036] A cathode metal layer, located on the interlayer dielectric layer and electrically connected to the N-terminal metal contact column;

[0037] The anode metal layer is located on the interlayer dielectric layer and is electrically connected to the P-terminal metal contact column.

[0038] Optionally, the base structure includes a substrate, a blocking buried layer and an epitaxial layer, the blocking buried layer is located on the upper surface of the substrate, the epitaxial layer is located on the substrate and covers the blocking buried layer, the N-type high-voltage well is located in the epitaxial layer and the bottom surface of the N-type high-voltage well stops at the blocking buried layer.

[0039] Optionally, a silicide blocking layer is further provided between the field oxide layer and the interlayer dielectric layer, and the silicide blocking layer has an opening exposing the P-terminal active region.

[0040] As described above, the manufacturing method of the Schottky device of the present invention includes: providing a substrate structure, forming an N-type high-voltage well located in the substrate structure, forming a P-type well located on the upper surface of the N-type high-voltage well, forming a field oxide layer located on the N-type high-voltage well, forming an N-type well located on the upper surface of the N-type high-voltage well, forming an N-type lead-out region located on the upper surface of the N-type well, forming an N-terminal metal silicide layer located on the N-terminal active region, forming a P-terminal metal silicide layer located on the P-terminal active region, forming an interlayer dielectric layer located on the substrate structure, forming an N-terminal metal contact column and a P-terminal metal contact column located in the interlayer dielectric layer, and forming a cathode metal layer and an anode metal layer located on the interlayer dielectric layer. The invention discloses a method for manufacturing a Schottky device for a Schottky device of the present invention. The method comprises a substrate, a barrier buried layer and an epitaxial layer from bottom to top, the N-type high-voltage well comprises an N-terminal active area and a P-terminal active area which are arranged at intervals, the P-terminal well is located at the edge area of ​​the P-terminal active area, the field oxide layer isolates the N-terminal active area and the P-terminal active area in the N-type high-voltage well, the N-terminal well is located at the N-terminal active area, the N-terminal metal contact column is located above the N-terminal active area and contacts the N-terminal metal silicide layer, the P-terminal metal contact column is located above the P-terminal active area and contacts the P-terminal metal silicide layer, the number of the P-terminal metal contact columns is multiple and arranged in a dot matrix, the cathode metal layer is electrically connected to the N-terminal metal contact column, and the anode metal layer is electrically connected to the P-terminal metal contact column. The Schottky device of the present invention can be more compatible with the submicron BCD process while ensuring the electrical performance parameters of the Schottky device, and has a more stable process performance in the long-term mass production of the BCD process. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 The schematic diagram shows a structure obtained after forming a base structure, an N-type high-voltage well, a P-well and a field oxide layer in a method for manufacturing a Schottky diode compatible with a BCD process.

[0042] Figure 2 The diagram shows a structure obtained after forming an N-well, an N-type lead-out region, a silicide barrier layer and a metal silicide layer in a method for manufacturing a Schottky diode compatible with a BCD process.

[0043] Figure 3 The diagram shows a structure obtained after forming an interlayer dielectric layer in a method for manufacturing a Schottky diode compatible with a BCD process.

[0044] Figure 4 It is a schematic diagram showing a structure obtained after forming a first opening and a second opening in a method for manufacturing a Schottky diode compatible with a BCD process.

[0045] Figure 5 A schematic diagram showing a structure obtained after forming a first tungsten column, a second tungsten column, a cathode metal layer and an anode metal layer in a method for manufacturing a Schottky diode compatible with a BCD process.

[0046] Figure 6 Shown is a top view of a structure obtained after forming a first opening and a second opening in a method for manufacturing a Schottky diode compatible with a BCD process.

[0047] Figure 7 Shown is a cross-sectional view of the P-terminal contact region after etching of the Schottky diode contact region compatible with the BCD process.

[0048] Figure 8 Shown is a long-term process control plot of the on-state voltage of a Schottky diode compatible with a BCD process.

[0049] Fig. 9 Shown is a process flow chart of the method for manufacturing the Schottky device of the present invention.

[0050] Fig.10 It is a schematic diagram showing the structure obtained after forming a base structure in the method for manufacturing a Schottky device of the present invention.

[0051] Fig.11 It is a schematic diagram showing the structure obtained after forming a P well, a field oxide layer, an N well and an N region lead-out region in the method for manufacturing a Schottky device of the present invention.

[0052] Fig.12 It is a schematic diagram showing the structure obtained after forming a silicide barrier layer, an N-type metal silicide layer and a P-type metal silicide layer in the method for manufacturing a Schottky device of the present invention.

[0053] Fig.13 It is a schematic diagram showing the structure obtained after forming an interlayer dielectric layer in the method for manufacturing a Schottky device of the present invention.

[0054] Fig.14 It is a schematic diagram showing the structure obtained after forming the N-terminal metal contact column and the P-terminal metal contact column in the method for manufacturing the Schottky device of the present invention.

[0055] Fig.15 It is a schematic diagram showing the structure obtained after forming a patterned photoresist layer in the method for manufacturing a Schottky device of the present invention.

[0056] Fig.16 Shown is a top view of a patterned photoresist layer in the method for manufacturing a Schottky device of the present invention.

[0057] Fig.17 It is a schematic diagram showing the structure obtained after forming the N-terminal contact hole and the P-terminal contact hole in the method for manufacturing the Schottky device of the present invention.

[0058] Fig.18 It is a schematic diagram showing the structure obtained after forming a cathode metal layer and an anode metal layer in the method for manufacturing a Schottky device of the present invention.

[0059] Fig.19 Shown is a graph of the variability in breakdown voltage for two Schottky devices of the same size.

[0060] Fig. 20 Shown is a graph of the variability of the on-state voltage for two Schottky devices of the same size.

[0061] Fig.21 Shown is a long-term process control graph of the on-voltage of the Schottky device of the present invention.

[0062] Description of Reference Numerals

[0063] 101 Base structure

[0064] 1011 Substrate

[0065] 1012 blocking buried layer

[0066] 1013 Epitaxial layer

[0067] 102 N-type high voltage well

[0068] 103 P-well

[0069] 104 Field Oxide Layer

[0070] 105 N-well

[0071] 106 N-type lead-out area

[0072] 107 Silicide barrier layer

[0073] 108 Metal silicide layer

[0074] 109 interlayer dielectric layer

[0075] 110 First Opening

[0076] 111 Second Opening

[0077] 112 First Tungsten Column

[0078] 113 Second Tungsten Pillar

[0079] 114 cathode metal layer

[0080] 115 Anode metal layer

[0081] 201 Base structure

[0082] 2011 Substrate

[0083] 2012 Blocking buried layer

[0084] 2013 Epitaxial Layer

[0085] 202 N-type high voltage well

[0086] 203 P-well

[0087] 204 Field Oxide Layer

[0088] 205 N-well

[0089] 206 N-type lead-out area

[0090] 207 N-terminal metal silicide layer

[0091] 208 P-side metal silicide layer

[0092] 209 Silicide barrier layer

[0093] 210 Interlayer dielectric layer

[0094] 211 N-terminal metal contact column

[0095] 212 P-terminal metal contact column

[0096] 213 Photoresist layer

[0097] 2131 N-terminal etching pattern

[0098] 2132 P-end etching pattern

[0099] 214 N-terminal contact hole

[0100] 215 P terminal contact hole

[0101] 216 cathode metal layer

[0102] 217 Anode metal layer

[0103] IN active area

[0104] II P terminal active area

[0105] The length of the etching pattern at the L1 P end

[0106] Width of etching pattern at L2 P end

[0107] L3 Horizontal spacing of dot matrix openings

[0108] L4 Vertical spacing of dot matrix openings

[0109] L5 Diameter of circular dot-matrix opening

[0110] Steps S1 to S6 DETAILED DESCRIPTION

[0111] See also Figures 1 to 5, which is a structural schematic diagram showing the steps of a method for manufacturing a Schottky diode compatible with a BCD process, wherein at least the following steps are included:

[0112] (1) Figure 1 As shown, a base structure 101 is first provided, and the base structure 101 includes a substrate 1011, a blocking buried layer 1012 and an epitaxial layer 1013 from bottom to top. N-type ion implantation is performed to obtain an N-type high-voltage well 102 in the epitaxial layer 1013, and P-type ion implantation is performed to obtain a P-well 103 in the N-type high-voltage well 102. A field oxide layer 104 is grown on the non-active area of ​​the base structure 101.

[0113] (2) Figure 2 As shown, N-type ion implantation is performed to obtain an N-well 105 in the N-type high-voltage well 102, and N-type ion implantation is performed to obtain an N-type lead-out region 106 on the upper surface layer of the N-well 105, and a silicide barrier layer 107 is formed on the N-type high-voltage well 102. The silicide barrier layer 107 covers the P-well 103 and the area surrounded by the P-well 103, and a metal silicide layer 108 is formed on the N-type lead-out region 106.

[0114] (3) Figure 3 As shown, an interlayer dielectric layer 109 is formed on the substrate structure 101 .

[0115] (4) Figure 4 As shown, a first opening 110 and a second opening 111 are formed in the interlayer dielectric layer 109 by using photolithography and etching processes.

[0116] (5) Figure 5 As shown, tungsten is filled in the first opening 110 to form a first tungsten column 112 , tungsten is filled in the second opening 111 to form a second tungsten column 113 , a cathode metal layer 114 is formed on the first tungsten column 112 , and an anode metal layer 115 is formed on the second tungsten column 113 .

[0117] See also Figure 6, showing a top view of the structure obtained after the first opening 110 and the second opening 111 are formed in the above-mentioned manufacturing method, wherein the areas of the first opening 110 (N end) and the second opening 111 (P end) are different, the N end is the semiconductor end of the Schottky diode, and the contact hole ohmic contact in the conventional BCD process can be used, but the P end is the metal end of the Schottky diode, which is used to form a metal-semiconductor contact, and the contact area needs to be increased to generate a Schottky barrier to form the characteristics of the Schottky diode. In the BCD process of the line width node of 0.35μm and below, the contact hole is basically a fixed dot matrix, so when the area of ​​the P end becomes larger, it puts forward high requirements for the etching process in the BCD process. During the etching process, the inconsistent local transmittance can easily lead to the incomplete etching of the middle part of the P end, and there is a residue in the interlayer dielectric layer, which leads to the instability of the electrical parameters of the Schottky diode. Especially in the long-term mass production process, this instability will be more prominent.

[0118] See also Figure 7 , showing the cross-sectional view of the P-terminal contact area after the above-mentioned Schottky diode contact area is etched. It can be seen that the central area of ​​the P-terminal can easily cause the normal BCD etching process to fail to etch to the silicon surface due to the large area transmittance, forming silicon oxide residue, which in turn leads to the failure of the electrical performance of the Schottky diode. The etching stability of the BCD process will also be affected by the size of the P-terminal. The P-terminal area designed with different aspect ratios will put forward higher requirements for the etching process, which greatly increases the difficulty of mass production of devices in the BCD process.

[0119] See also Figure 8 , which shows the long-term process control diagram of the on-state voltage of the above-mentioned Schottky diode. It can be seen that the unstable electrical parameter performance greatly affects the production efficiency during the mass production of Schottky diodes.

[0120] The inventors of this application have improved the manufacturing method of the Schottky device structure through extensive analysis and research, so that the above-mentioned Schottky diode can be better compatible with the mature submicron BCD process, while ensuring the electrical performance parameters and having a more stable process performance in the long-term mass production process.

[0121] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0122] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0123] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0124] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0125] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," "on," etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0126] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0127] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0128] See also Fig. 9 , which is a process flow chart of a method for manufacturing a Schottky device of the present invention, comprising the following steps:

[0129] S1: providing a substrate structure, wherein an N-type high-voltage well is provided in the substrate structure, and the N-type high-voltage well includes an N-terminal active region and a P-terminal active region which are arranged at intervals;

[0130] S2: forming a P-well, a field oxide layer, an N-well and an N-type lead-out region, wherein the P-well is located on the upper surface layer of the N-type high-voltage well and is located at the edge region of the P-terminal active region, the field oxide layer is located on the N-type high-voltage well and isolates the N-terminal active region and the P-terminal active region in the N-type high-voltage well, the N-well is located on the upper surface layer of the N-type high-voltage well and is located in the N-terminal active region, and the N-type lead-out region is located on the upper surface layer of the N-well;

[0131] S3: forming an N-terminal metal silicide layer on the N-terminal active region, and forming a P-terminal metal silicide layer on the P-terminal active region;

[0132] S4: forming an interlayer dielectric layer on the base structure, wherein the interlayer dielectric layer covers the field oxide layer, the N-terminal metal silicide layer and the P-terminal metal silicide layer;

[0133] S5: forming an N-terminal metal contact column and a P-terminal metal contact column in the interlayer dielectric layer, wherein the N-terminal metal contact column is located above the N-terminal active region and contacts the N-terminal metal silicide layer, and the P-terminal metal contact column is located above the P-terminal active region and contacts the P-terminal metal silicide layer, and the number of the P-terminal metal contact columns is plural and arranged in a matrix;

[0134] S6: forming a cathode metal layer and an anode metal layer on the interlayer dielectric layer, wherein the cathode metal layer is electrically connected to the N-terminal metal contact column, and the anode metal layer is electrically connected to the P-terminal metal contact column.

[0135] The following will be combined Figures 10 to 18 , detailing each step of the method for manufacturing the Schottky device of the present invention.

[0136] First, please refer to Fig.10 , performing step S1: providing a substrate structure 201, wherein the substrate structure 201 is provided with an N-type high-voltage well 202, wherein the N-type high-voltage well 202 includes an N-end active region I and a P-end active region II which are arranged at intervals;

[0137] As an example, the base structure 201 includes a substrate 2011, a blocking buried layer 2012 and an epitaxial layer 2013, wherein the blocking buried layer 2012 is located on the upper surface of the substrate 2011, the epitaxial layer 2013 is located on the substrate 2011 and covers the blocking buried layer 2012, the N-type high-voltage well 202 is located in the epitaxial layer 2013 and the bottom surface of the N-type high-voltage well 202 stops at the blocking buried layer 2012, and the formation of the base structure 201 includes the following steps:

[0138] (1) Providing a substrate 2011;

[0139] (2) performing ion implantation in a predetermined area on the upper surface of the substrate 2011;

[0140] (3) An epitaxial layer 2013 is grown on the substrate 2011, and the epitaxial layer 2013 covers the ion implantation region so that the ion implantation region becomes the blocking buried layer 2012. In the BCD process, many different devices are integrated on the substrate 2011, and the blocking buried layer 2012 can play an isolation role to prevent the current of one device from flowing to the substrate 2011 to interfere with the circuits of other devices, thereby improving the voltage resistance of the device.

[0141] As an example, the blocking buried layer 2012 is preferably an N-type buried layer.

[0142] As an example, the implanted ions used to form the N-type high-voltage well 202 are phosphorus ions, and the implantation angle may be vertical implantation or implantation at a relatively small inclination angle (eg, implantation with a deviation from the wafer normal in the range of 0 to 10°).

[0143] Please see again Fig.11 , perform the step S2: form a P well 203, a field oxide layer 204, an N well 205 and an N-type lead-out region 206, the P well 203 is located on the upper surface layer of the N-type high-voltage well 202 and is located at the edge area of ​​the P-end active region I, the field oxide layer 204 is located on the N-type high-voltage well 202 and isolates the N-end active region I and the P-end active region II in the N-type high-voltage well 202, the N well 205 is located on the upper surface layer of the N-type high-voltage well 202 and is located in the N-end active region I, and the N-type lead-out region 206 is located on the upper surface layer of the N-type high-voltage well 205.

[0144] As an example, forming the P well 203, the field oxide layer 204, the N well 205 and the N-type lead-out region 206 includes the following steps:

[0145] (1) injecting P-type ions into the upper surface layer of the N-type high-voltage well 202 to form a P-well 203, wherein the P-well 203 is located at the edge region of the P-end active region II;

[0146] (2) forming a field oxide layer 204 on the N-type high-voltage well 202 by using an oxidation technique, wherein the field oxide layer 204 isolates the N-end active region I and the P-end active region II in the N-type high-voltage well 202;

[0147] (3) injecting N-type ions into the upper surface layer of the N-type high-voltage well 202 to form an N-well 205, wherein the N-well 205 is located in the N-end active region II;

[0148] (4) Implanting N-type ions into the upper surface layer of the N-well 205 to form the N-type lead-out region 206 .

[0149] As an example, the implanted ions used to form the P-well 203 may be boron ions, and the implantation angle may be vertical implantation (eg, implantation with a deviation from the wafer normal in a range of 0 to 10°).

[0150] As an example, the required field oxide layer 204 may be formed by using a local oxidation technique.

[0151] As an example, the material of the field oxide layer 204 may be silicon oxide, silicon nitride, local silicon oxide or silicon oxynitride, etc. The field oxide layer 204 is used to isolate the active area to avoid electrical crosstalk between adjacent active devices.

[0152] As an example, the implanted ions for forming the N well 205 and the N type lead-out region 206 are phosphorus ions, and the implantation angle may be vertical implantation or implantation at a smaller tilt angle (eg, implantation with a deviation from the wafer normal in the range of 0 to 10°).

[0153] Please see again Fig.12 , performing the step S3: forming an N-terminal metal silicide layer 207 on the N-terminal active region I, and forming a P-terminal metal silicide layer 208 on the P-terminal active region II.

[0154] As an example, the N-end metal silicide layer 207 and the P-end silicide layer 208 are made of the same material, including at least one of titanium silicide, platinum silicide and cobalt silicide. In this embodiment, the N-end metal silicide layer 207 and the P-end silicide layer 208 are preferably made of titanium silicide.

[0155] As an example, before forming the N-terminal metal silicide layer 207 and the P-terminal metal silicide layer 208, a step of forming a silicide blocking layer 209 on the field oxide layer 204 is also included, and the silicide blocking layer 209 is provided with an opening to expose the P-terminal active area II. This is because the Schottky device of the present invention is used to be compatible with the BCD process. In the BCD process, many different devices will be integrated on the substrate 2011, and different devices have different requirements for the metal silicide layer. Therefore, in the preparation process of the BCD process, a silicide blocking layer 209 is often required to be formed before forming the metal silicide layer.

[0156] Please see again Fig.13 , executing the step S4: forming an interlayer dielectric layer 210 on the base structure 201 , wherein the interlayer dielectric layer 210 covers the field oxide layer 204 , the N-terminal metal silicide layer 207 and the P-terminal metal silicide layer 208 .

[0157] As an example, the material of the interlayer dielectric layer 210 includes at least one of boron-phosphorus-doped silicon oxide and tetraethoxysilane silicon oxide.

[0158] As an example, after forming the field interlayer dielectric layer 210, the interlayer dielectric layer 210 is polished by chemical mechanical polishing to flatten the upper surface of the interlayer dielectric layer 210 and eliminate the surface unevenness caused by covering the field oxide layer 204, the N-end metal silicide layer 207 and the P-end metal silicide layer 208.

[0159] Please see again Fig.14 , perform the step S5: form an N-end metal contact column 211 and a P-end metal contact column 212 in the interlayer dielectric layer 210, the N-end metal contact column 211 is located above the N-end active area I and contacts the N-end metal silicide layer 207, the P-end metal contact column 212 is located above the P-end active area II and contacts the P-end metal silicide layer 208, and the number of the P-end metal contact columns 212 is multiple and arranged in a matrix.

[0160] As an example, forming the N-terminal metal contact column 211 and the P-terminal metal contact column 212 in the interlayer dielectric layer 210 includes the following steps:

[0161] (1) Please refer to Fig.15 , forming a photoresist layer 213 on the interlayer dielectric layer 210, patterning the photoresist layer 213 to obtain an N-end etching pattern 2131 and a P-end etching pattern 2132, and referring to Fig.16 , showing a top view of the patterned resist layer 213, wherein the P-end etching pattern 2132 is a dot matrix opening;

[0162] (2) Please refer to Fig.17 , etching the interlayer dielectric layer 210 based on the patterned photoresist layer 213 to obtain an N-terminal contact hole 214 and a P-terminal contact hole 215, wherein the P-terminal contact holes 215 are arranged in a dot matrix;

[0163] (3) Filling the N-terminal contact hole 214 with metal to form the N-terminal metal contact column 211 , and filling the P-terminal contact hole 215 with metal to form the P-terminal metal contact column 212 .

[0164] As an example, after forming the P-end metal contact column 212 and the N-end metal contact column 211, the P-end metal contact column 212 and the N-end metal contact column 211 are ground by chemical mechanical polishing to achieve planarization after the N-end contact hole 214 and the P-end contact hole 215 are filled, providing a flat surface for the electrical interconnection of subsequent metal layers.

[0165] As an example, the dot matrix openings of the P-end etching pattern 2132 are arranged into at least two rows and at least two columns. The dot matrix openings can unify the sizes of all contact holes of the Schottky device, so that the etching process of the BCD process will no longer be affected by fluctuations. After the P-end etching pattern 2132 becomes a dot matrix opening, the etching morphology and local transmittance are unified, so that the etching process of the BCD process can be stable for a long time, and the problem of different contact hole sizes affecting the stability of the etching process is solved.

[0166] As an example, the plurality of P-end metal contact pillars 212 are arranged in at least two rows and at least two columns, and the cross-sectional area of ​​the P-end metal contact pillars 212 is greater than the cross-sectional area of ​​the N-end metal contact pillars 211 .

[0167] As an example, the arrangement shape of the dot matrix openings of the P-end etching pattern 2132 can be determined as needed. In this embodiment, the dot matrix openings are arranged in a rectangular area.

[0168] As an example, the length L1 and the width L2 of the rectangular area can be selected as needed. In this embodiment, the length L1 of the rectangle is 30 μm, and the width L2 of the rectangle is 4 μm.

[0169] As an example, the lateral spacing L3 and the longitudinal spacing L4 of the dot matrix openings can be selected as needed. In the present embodiment, the lateral spacing L3 and the longitudinal spacing L4 of the dot matrix openings are both 0.5 μm.

[0170] As an example, the dot matrix opening is circular, and the diameter L5 of the dot matrix opening can be selected as needed. In the present embodiment, the diameter L5 of the dot matrix opening is 0.5 μm.

[0171] As an example, the metal material of the N-end metal contact column 211 and the P-end metal contact column 212 includes at least one of gold, aluminum, copper or tungsten. In this embodiment, the N-end metal contact column 211 and the P-end metal contact column 212 preferably use the metal material tungsten. Tungsten has a higher density, and tungsten columns have better stability and vibration resistance when used as contact columns.

[0172] Please see again Fig.18 , perform the step S6: form a cathode metal layer 216 and an anode metal layer 217 on the interlayer dielectric layer 210, the cathode metal layer 216 is electrically connected to the N-terminal metal contact column 211, and the anode metal layer 217 is electrically connected to the P-terminal metal contact column 212.

[0173] Thus, a Schottky device is manufactured, which includes a substrate structure 201, an N-type high-voltage well 202, a P-type well 203, a field oxide layer 204, an N-type well 205, an N-type lead-out region 206, an N-terminal metal silicide layer 207, a P-terminal metal silicide layer 208, an interlayer dielectric layer 210, an N-terminal metal contact column 211, a P-terminal metal contact column 212, a cathode metal layer 216 and an anode metal layer 217, wherein the N-type high-voltage well 202 is located in the substrate structure 201, and the N-type The high-voltage well 202 includes an N-terminal active region I and a P-terminal active region II which are arranged at intervals. The P-type well 203 is located on the upper surface layer of the N-type high-voltage well 202 and is located at the edge region of the P-terminal active region II. The field oxide layer 204 is located on the N-type high-voltage well 202 and isolates the N-terminal active region I from the P-terminal active region II in the N-type high-voltage well 202. The N-type well 205 is located on the upper surface layer of the N-type high-voltage well 202 and is located at the N-terminal active region I. The N-type lead-out region 206 is located at the The upper surface layer 205 of the N-well 205, the N-terminal metal silicide layer 207 is located on the N-terminal active region I, the P-terminal metal silicide layer 208 is located on the P-terminal active region II, the interlayer dielectric layer 210 is located on the base structure 201 and covers the field oxide layer 204, the N-terminal metal silicide layer 207 and the P-terminal metal silicide layer 208, the N-terminal metal contact column 211 is located in the interlayer dielectric layer 210 on the N-terminal active region I and is connected to the N-terminal metal The P-end metal contact column 212 is located in the interlayer dielectric layer 210 on the P-end active area II and is in contact with the P-end metal silicide layer 208. The number of the P-end metal contact columns 212 is multiple and arranged in a matrix. The cathode metal layer 216 is located on the interlayer dielectric layer 210 and is electrically connected to the N-end metal contact column 211. The anode metal layer 217 is located on the interlayer dielectric layer 210 and is electrically connected to the P-end metal contact column 212.

[0174] Currently, most integrated circuits are still based on Figures 1 to 5 The electrical parameters of the Schottky diode compatible with the BCD process shown in FIG. 1 are designed. Therefore, the electrical parameters of the Schottky device are similar to those based on Figures 1 to 5 It is necessary to keep the electrical parameters of the Schottky diode compatible with the BCD process consistent. The on-voltage of the Schottky device without the P-terminal metal silicide layer 208 will be too high, and the reverse recovery time will increase, which will not meet the requirements of various application scenarios for the characteristics of the Schottky device. The P-terminal metal silicide layer 208 in the Schottky device can keep the electrical parameters of the device original.

[0175] As an example, the base structure 201 includes a substrate 2011, a blocking buried layer 2012 and an epitaxial layer 2013, the blocking buried layer 2012 is located on the upper surface of the substrate 2011, the epitaxial layer 2013 is located on the substrate 2011 and covers the blocking buried layer 2012, the N-type high-voltage well 202 is located in the epitaxial layer 2013 and the bottom surface of the N-type high-voltage well 202 stops at the blocking buried layer 2012.

[0176] As an example, a silicide blocking layer 209 is further provided between the field oxide layer 204 and the interlayer dielectric layer 210, and the silicide blocking layer 209 has an opening exposing the P-end active area I. This is because the above-mentioned Schottky device needs to be compatible with the BCD process. The BCD process integrates many different types of devices, and the silicide blocking layer 209 needs to be formed during the preparation process.

[0177] See also Fig.19 , showing the breakdown voltage variability diagram of two Schottky devices of the same size, wherein the left side shows the breakdown voltage variability diagram of the Schottky device of the present invention, and the right side shows the breakdown voltage variability diagram based on Figures 1 to 5 The variability diagram of the breakdown voltage of the Schottky diode compatible with the BCD process is shown. From the figure, it can be seen that the voltage withstand levels of the two Schottky diodes of the same size remain consistent.

[0178] See also Fig. 20 , showing the variability diagram of the on-state voltage of two Schottky devices of the same size, wherein the left side shows the variability diagram of the on-state voltage of the Schottky device of the present invention, and the right side shows the variability diagram based on Figures 1 to 5 The variability diagram of the on-state voltage of the Schottky diode compatible with the BCD process is shown in FIG. 1 . It can be seen from the figure that the on-state voltage value of the Schottky device of the present invention is compared with Figures 1 to 5 The Schottky diode compatible with the BCD process shown is reduced by about 10%, but its drift direction and amplitude are within the control range of general processes. Therefore, the Schottky device of the present invention will not affect the design of the original circuit and can be directly placed in the originally designed integrated circuit to work.

[0179] See also Fig.21 , which is a long-term process control diagram of the on-voltage of the Schottky device of the present invention, compared with Figure 8 The Schottky device of the present invention has a more stable process performance in long-term production, and the drift of the electrical parameters of the Schottky diode caused by the fluctuation of the etching process basically does not occur.

[0180] In summary, the manufacturing method of the Schottky device of the present invention includes: providing a substrate structure, forming an N-type high-voltage well in the substrate structure, forming a P-type well on the upper surface of the N-type high-voltage well, forming a field oxide layer on the N-type high-voltage well, forming an N-type well on the upper surface of the N-type high-voltage well, forming an N-type lead-out region on the upper surface of the N-type well, forming an N-terminal metal silicide layer on the N-terminal active region, forming a P-terminal metal silicide layer on the P-terminal active region, forming an interlayer dielectric layer on the substrate structure, forming an N-terminal metal contact column and a P-terminal metal contact column in the interlayer dielectric layer, and forming a cathode metal layer and an anode metal layer on the interlayer dielectric layer. Layer, wherein the base structure includes a substrate, a blocking buried layer and an epitaxial layer from bottom to top, the N-type high-voltage well includes an N-terminal active area and a P-terminal active area arranged at intervals, the P-terminal well is located at the edge area of ​​the P-terminal active area, the field oxide layer isolates the N-terminal active area and the P-terminal active area in the N-type high-voltage well, the N-well is located in the N-terminal active area, the N-terminal metal contact column is located above the N-terminal active area and contacts the N-terminal metal silicide layer, the P-terminal metal contact column is located above the P-terminal active area and contacts the P-terminal metal silicide layer, the number of the P-terminal metal contact columns is multiple and arranged in a dot matrix, the cathode metal layer is electrically connected to the N-terminal metal contact column, and the anode metal layer is electrically connected to the P-terminal metal contact column. The Schottky device of the present invention can be better compatible with the submicron BCD process while ensuring the electrical performance parameters of the Schottky device, and has a more stable process performance in the long-term mass production of the BCD process. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0181] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a Schottky device, characterized in that: The following steps are involved: A substrate structure is provided, wherein an N-type high-voltage well is provided in the substrate structure, and the N-type high-voltage well includes an N-terminal active region and a P-terminal active region which are arranged at intervals; Forming a P-well, a field oxide layer, an N-well and an N-type lead-out region, wherein the P-well is located on the upper surface layer of the N-type high-voltage well and is located at the edge region of the P-terminal active region, the field oxide layer is located on the N-type high-voltage well and isolates the N-terminal active region from the P-terminal active region in the N-type high-voltage well, the N-well is located on the upper surface layer of the N-type high-voltage well and is located in the N-terminal active region, and the N-type lead-out region is located on the upper surface layer of the N-well; Forming an N-terminal metal silicide layer on the N-terminal active region, and forming a P-terminal metal silicide layer on the P-terminal active region; forming an interlayer dielectric layer on the base structure, wherein the interlayer dielectric layer covers the field oxide layer, the N-terminal metal silicide layer and the P-terminal metal silicide layer; Forming an N-terminal metal contact column and a P-terminal metal contact column in the interlayer dielectric layer, wherein the N-terminal metal contact column is located above the N-terminal active region and contacts the N-terminal metal silicide layer, and the P-terminal metal contact column is located above the P-terminal active region and contacts the P-terminal metal silicide layer, and the number of the P-terminal metal contact columns is multiple and arranged in a matrix; A cathode metal layer and an anode metal layer are formed on the interlayer dielectric layer, wherein the cathode metal layer is electrically connected to the N-terminal metal contact column, and the anode metal layer is electrically connected to the P-terminal metal contact column.

2. The method for preparing a Schottky device according to claim 1, characterized in that: The base structure includes a substrate, a blocking buried layer and an epitaxial layer, wherein the blocking buried layer is located on the upper surface layer of the substrate, the epitaxial layer is located on the substrate and covers the blocking buried layer, the N-type high-voltage well is located in the epitaxial layer and the bottom surface of the N-type high-voltage well stops at the blocking buried layer, and the formation of the base structure includes the following steps: providing a substrate; Performing ion implantation in a preset area on the upper surface of the substrate; An epitaxial layer is grown on the substrate, and the epitaxial layer covers the ion implantation region so that the ion implantation region becomes the blocking buried layer.

3. The method for preparing a Schottky device according to claim 1, characterized in that: Forming the P-well, the field oxide layer, the N-well and the N-type lead-out region comprises the following steps: Forming a P well on the upper surface layer of the N-type high-voltage well, wherein the P well is located at the edge area of ​​the P-end active area; Forming a field oxide layer on the N-type high-voltage well, wherein the field oxide layer isolates the N-end active region and the P-end active region in the N-type high-voltage well; Forming an N-well on the upper surface layer of the N-type high-voltage well, wherein the N-well is located in the N-terminal active area; The N-type lead-out region is formed on the upper surface layer of the N-well.

4. The method for preparing a Schottky device according to claim 1, characterized in that: Forming an N-terminal metal contact column and a P-terminal metal contact column in the interlayer dielectric layer includes the following steps: Forming a photoresist layer on the interlayer dielectric layer, and patterning the photoresist layer to obtain an N-end etching pattern and a P-end etching pattern, wherein the P-end etching pattern includes a dot matrix opening; Etching the interlayer dielectric layer based on the patterned photoresist layer to obtain an N-terminal contact hole and a P-terminal contact hole, wherein the P-terminal contact holes are arranged in a dot matrix; The N-terminal contact hole is filled with metal to form the N-terminal metal contact column, and the P-terminal contact hole is filled with metal to form the P-terminal metal contact column.

5. The method for preparing a Schottky device according to claim 1, characterized in that: Before forming the N-terminal metal silicide layer and the P-terminal metal silicide layer, the method further includes forming a silicide blocking layer on the field oxide layer, wherein the silicide blocking layer is provided with an opening for exposing the P-terminal active area.

6. The method for preparing a Schottky device according to claim 1, characterized in that: The N-end metal silicide layer is made of the same material as the P-end metal silicide layer, including at least one of titanium silicide, platinum silicide and cobalt silicide.

7. The method for preparing a Schottky device according to claim 1, characterized in that: The plurality of P-terminal metal contact pillars are arranged in at least two rows and at least two columns, and the cross-sectional area of ​​the P-terminal metal contact pillars is greater than the cross-sectional area of ​​the N-terminal metal contact pillars.

8. A Schottky device, characterized in that: include: A substrate structure, wherein an N-type high-voltage well is provided in the substrate structure, and the N-type high-voltage well includes an N-terminal active region and a P-terminal active region which are arranged at intervals; A P-well, a field oxide layer, an N-well and an N-type lead-out region, wherein the P-well is located on the upper surface layer of the N-type high-voltage well and is located at the edge region of the P-terminal active region, the field oxide layer is located on the N-type high-voltage well and isolates the N-terminal active region and the P-terminal active region in the N-type high-voltage well, the N-well is located on the upper surface layer of the N-type high-voltage well and is located in the N-terminal active region, and the N-type lead-out region is located on the upper surface layer of the N-well; An N-terminal metal silicide layer and a P-terminal metal silicide layer, wherein the N-terminal metal silicide layer is located on the N-terminal active region, and the P-terminal metal silicide layer is located on the P-terminal active region; an interlayer dielectric layer, located on the base structure and covering the field oxide layer, the N-terminal metal silicide layer and the P-terminal metal silicide layer; An N-terminal metal contact column, located in the interlayer dielectric layer on the N-terminal active region and in contact with the N-terminal metal silicide layer; A P-terminal metal contact column, located in the interlayer dielectric layer on the P-terminal active area and in contact with the P-terminal metal silicide layer, wherein the number of the P-terminal metal contact columns is plural and arranged in a lattice; A cathode metal layer, located on the interlayer dielectric layer and electrically connected to the N-terminal metal contact column; The anode metal layer is located on the interlayer dielectric layer and is electrically connected to the P-terminal metal contact column.

9. The Schottky device according to claim 8, characterized in that: The base structure includes a substrate, a blocking buried layer and an epitaxial layer, wherein the blocking buried layer is located on the upper surface of the substrate, the epitaxial layer is located on the substrate and covers the blocking buried layer, the N-type high-voltage well is located in the epitaxial layer and the bottom surface of the N-type high-voltage well stops at the blocking buried layer.

10. The Schottky device according to claim 8, characterized in that: A silicide blocking layer is also provided between the field oxide layer and the interlayer dielectric layer, and the silicide blocking layer has an opening exposing the P-terminal active region.

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