Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a device layer; forming a dielectric layer over the device layer; a field plate is formed above the dielectric layer, the field plate comprises a first field plate layer and a second field plate layer, the first field plate layer comprises a silicon layer and a silicon oxide layer connected to the periphery of the silicon layer, at least one part of the upper surface of the silicon oxide layer extends along the silicon oxide layer obliquely away from the silicon layer, and the second field plate layer comprises first metal and second metal connected to the periphery of the first metal; and the extension direction of the second metal is consistent with the extension direction of the upper surface of the silicon oxide layer. According to the manufacturing method, a laminated field plate comprising a first field plate and a second field plate layer is formed, the second field plate layer comprises second metal extending in the inclined direction and is of an inclined field plate-like structure, high dielectric breakdown voltage is kept while high electric field modulation capacity is achieved through the field plates, and high working performance and high reliability are achieved; the whole process steps are compatible with the existing process.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit devices and manufacturing, and relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the progress of material science in recent years, gallium nitride materials have been widely used in many fields such as power management and radio communications due to their superior physical properties. However, when GaN-based high electron mobility transistors (HEMTs) are working, there is an electric field concentration phenomenon at the edge of the gate close to the drain, which increases the gate leakage current and easily leads to dielectric breakdown, thus failing to maximize the voltage resistance advantage of gallium nitride materials.

[0003] In order to improve the breakdown characteristics of GaN devices, a common method is to use a field plate structure to improve the breakdown and other performance of GaN devices. The field plate refers to a layer of structure (for example, a metal plate) covering the surface of the GaN device, which is isolated from the device surface by a dielectric layer. The electric field can be modulated to reduce the local excessive electric field. However, in actual applications, it is found that there are still electric field peaks at the edge of the field plate (equivalent to the original electric field concentration phenomenon on the side of the gate facing the drain being eliminated due to the setting of the field plate, but a new electric field concentration effect is generated at the edge of the field plate), and the problem of tip discharge continues to exist, which still affects the device performance.

[0004] In order to further alleviate the problem of field plate spike discharge, the following technical means can be used to improve or alleviate it: 1) Increase the thickness of the dielectric layer under the field plate to alleviate the dielectric layer breakdown problem, but this method will lead to an unexpected decrease in the original electric field modulation capability of the field plate; 2) Use a multi-layer field plate structure, and the multi-layer field plates are distributed in a staggered manner, but this method will increase the difficulty of the device manufacturing process, and will also cause the problem of uneven wafer surface affecting subsequent processes; 3) Use tilted field plates, which are complex and difficult to mass produce; 4) Floating field plates, which still have edge electric field spike problems and are easy to break down. In other words, the technical means currently used either cannot effectively solve the problem of local electric field concentration, or will introduce new problems or weaken the electric field regulation capability that the field plate structure can originally achieve, or the process is cumbersome and complex and difficult to mass produce.

[0005] Therefore, how to provide a semiconductor device and a method for manufacturing the same to effectively improve the electric field concentration problem without increasing the difficulty and complexity of the process has become an important technical problem that needs to be urgently solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which are used to solve the problems that the prior art cannot effectively improve the electric field concentration phenomenon at the edge of the field plate or increases the process complexity and is not easy to mass produce.

[0008] To achieve the above object and other related objects, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0009] providing a device layer;

[0010] forming a dielectric layer above the device layer;

[0011] A field plate is formed above the dielectric layer, the field plate comprising a first field plate layer and a second field plate layer, the first field plate layer being located between the dielectric layer and the second field plate layer, wherein the first field plate layer comprises a silicon layer and a silicon oxide layer, the silicon oxide layer is connected to the periphery of the silicon layer and at least a portion of the upper surface of the silicon oxide layer extends in an oblique direction away from the silicon layer, and the second field plate layer comprises a first metal and a second metal, the second metal is connected to the periphery of the first metal and an extension direction of the second metal is consistent with an extension direction of the upper surface of the silicon oxide layer.

[0012] Optionally, forming a field plate above the dielectric layer comprises the following steps:

[0013] Sequentially forming a silicon base layer and a metal base layer on the dielectric layer, wherein the metal base layer covers the upper surface of the silicon base layer and the end surface of the silicon base layer in the horizontal direction is exposed;

[0014] The oxidation treatment is performed to oxidize the edge portion of the silicon base layer into a silicon oxide layer, the unoxidized portion of the silicon base layer constitutes the silicon layer, and the portion of the metal base layer located above the edge portion constitutes the second metal based on the formation of the silicon oxide layer.

[0015] Optionally, the temperature range of the oxidation treatment is 600-900° C., the time of the oxidation treatment is less than or equal to 30 minutes, and the oxidation treatment method includes at least one of dry oxygen oxidation, wet oxygen oxidation, water vapor oxidation, plasma oxidation, photochemical oxidation and electrochemical oxidation.

[0016] Optionally, the length of the silicon oxide layer is equal to the thickness of the silicon layer.

[0017] Optionally, in a direction from the silicon layer to the silicon oxide layer, the thickness of the silicon oxide layer increases gradually; or, the thickness of the silicon oxide layer first increases gradually and then remains unchanged.

[0018] Optionally, the material of the silicon layer includes at least one of amorphous silicon and polycrystalline silicon, the thickness range of the silicon layer is 5 to 20 nm, and the method for forming the silicon layer includes at least one of CVD, PVD and ALD; the second field plate layer includes at least one of a single metal material layer, a composite metal material layer and a stacked metal material layer, the material of the second field plate layer includes at least one of Al, Ni, W, Ti, Au, Ag, TiN, TiW and TaN, the thickness range of the second field plate layer is 50 to 200 nm, and the method for forming the second field plate layer includes at least one of CVD, PVD and ALD.

[0019] Optionally, the material of the dielectric layer includes at least one of SiN, SiO, SiON, AlN and Al2O3, the thickness range of the dielectric layer is 50 to 150 nm, and the formation method of the dielectric layer includes at least one of PECVD, SACVD, PVD and ALD.

[0020] Optionally, the device layer includes a substrate, a transition layer, a channel layer, a barrier layer and a gate structure stacked in sequence from bottom to top, wherein the substrate includes at least one of a silicon substrate, a silicon carbide substrate, a sapphire substrate and a diamond substrate, the transition layer includes at least one of an AlN nucleation layer, a multi-quantum well buffer layer, an Al composition gradient buffer layer and a GaN buffer layer, the thickness of the transition layer is in the range of 1 to 10 μm, and the barrier layer includes Al x Ga 1-x N (0≤x≤1) layer and In y Al 1-y N (0≤y≤1) layer, the thickness of the barrier layer is in the range of 10 to 25 nm, and the gate structure includes a P-type GaN gate, a P-type Al z Ga 1-z At least one of an N (0≤z≤1) gate, a metal gate, and a metal / insulator / semiconductor gate, wherein the gate thickness ranges from 50 to 150 nm.

[0021] The present invention also provides a semiconductor device, comprising:

[0022] Device layer;

[0023] a dielectric layer, located above the device layer;

[0024] A field plate is located above the dielectric layer, the field plate includes a first field plate layer and a second field plate layer, the first field plate layer is located between the dielectric layer and the second field plate layer, wherein the first field plate layer includes a silicon layer and a silicon oxide layer, the silicon oxide layer is connected to the periphery of the silicon layer and at least a portion of the upper surface of the silicon oxide layer extends along an oblique direction away from the silicon layer, and the second field plate layer includes a first metal and a second metal, the second metal is connected to the periphery of the first metal and the extension direction of the second metal is consistent with the extension direction of the upper surface of the silicon oxide layer.

[0025] Optionally, the length of the silicon oxide layer is equal to the thickness of the silicon layer.

[0026] As described above, the method for manufacturing a semiconductor device of the present invention forms a locally inclined field plate structure by forming a stacked field plate including a first field plate layer and a second field plate layer, and the second field plate layer includes a second metal extending obliquely, and the field plate is used to achieve high electric field modulation capability while still maintaining a high dielectric breakdown voltage, and has both high working performance and high reliability. In addition, by utilizing the thickness increase characteristic of silicon oxidation to silicon oxide, the metal is tilted due to mechanical action, and a second metal similar to an inclined field plate is obtained without additional process steps. The overall process steps are simple and easy to implement, and are basically compatible with existing processes. Compared with traditional improvement methods, the advantages are outstanding and suitable for large-scale production. The semiconductor device of the present invention has a stacked field plate structure including a first field plate layer and a second field plate layer, and the second field plate includes a second metal located at the edge and extending obliquely. While ensuring high electric field regulation capability, it has high breakdown voltage and high reliability. The overall structure is simple and low cost, and it is suitable for popularization and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a partial cross-sectional schematic diagram of a structure obtained after providing a device layer in the method for manufacturing a semiconductor device of the present invention.

[0028] Figure 2 It is a partial cross-sectional schematic diagram of a structure obtained after a dielectric layer is formed in the method for manufacturing a semiconductor device of the present invention.

[0029] Figure 3 It is a partial cross-sectional schematic diagram of a structure obtained after forming a silicon initial layer and a metal initial layer in the method for manufacturing a semiconductor device of the present invention.

[0030] Figure 4 It is a partial cross-sectional schematic diagram of a structure obtained after a silicon base layer and a metal base layer are formed in the method for manufacturing a semiconductor device of the present invention.

[0031] Figure 5 It is a partial cross-sectional schematic diagram of a structure obtained after forming a field plate in the method for manufacturing a semiconductor device of the present invention.

[0032] Figure 6 Display as Figure 5 The first enlarged schematic diagram of a local area in .

[0033] Figure 7 Display as Figure 5 The second enlarged schematic diagram of the local area in the figure.

[0034] Description of Reference Numerals

[0035] 10 Device Layer

[0036] 11 Substrate

[0037] 12 Transition layer

[0038] 13 Channel layer

[0039] 14 Barrier layer

[0040] 15 Gate structure

[0041] 20 Dielectric layer

[0042] 30 Silicon initial layer

[0043] 31 Silicon base layer

[0044] 310 First Field Layer

[0045] 311 Silicon layer

[0046] 312 Silicon oxide layer

[0047] 40 Metal initial layer

[0048] 41 Metal Base Layer

[0049] 410 Second Field Layer

[0050] 411 First Metal

[0051] 412 Second Metal

[0052] 50 Field Board DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] See also Figures 1 to 7It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0055] Embodiment 1

[0056] This embodiment provides a method for manufacturing a semiconductor device, the method comprising the following steps:

[0057] S1: providing a device layer;

[0058] S2: forming a dielectric layer above the device layer;

[0059] S3: Form a field plate above the dielectric layer, the field plate comprising a first field plate layer and a second field plate layer, the first field plate layer being located between the dielectric layer and the second field plate layer, wherein the first field plate layer comprises a silicon layer and a silicon oxide layer, the silicon oxide layer is connected to the periphery of the silicon layer and at least a portion of the upper surface of the silicon oxide layer extends along an oblique direction away from the silicon layer, and the second field plate layer comprises a first metal and a second metal, the second metal is connected to the periphery of the first metal and an extension direction of the second metal is consistent with an extension direction of the upper surface of the silicon oxide layer.

[0060] First, see Figure 1 , execute step S1 to provide a device layer 10.

[0061] As an example, the device layer 10 includes a substrate 11, a transition layer 12, a channel layer 13, a barrier layer 14 and a gate structure 15 stacked in sequence from bottom to top, and the barrier layer 14 and the channel layer 13 form a heterojunction to form a two-dimensional electron gas. In a specific example, step S1 includes the following steps: providing a substrate 11, epitaxially growing the transition layer 12, the channel layer 13 and the barrier layer 14 on the substrate 11 in sequence; forming a gate structure 15 above the barrier layer 14. In addition, although not shown in the drawings, the device layer 10 also includes structures such as a source metal and a drain metal arranged on both sides of the gate structure 15.

[0062] Furthermore, the substrate 11 includes at least one of a silicon substrate, a silicon carbide substrate, a sapphire substrate and a diamond substrate. In this embodiment, the substrate 11 is a silicon substrate.

[0063] Furthermore, the transition layer 12 includes at least one of an AlN nucleation layer, a multi-quantum well (MQW) buffer layer, an Al composition gradient buffer layer and a GaN buffer layer. The thickness of the transition layer 12 is in the range of 1 to 10 μm, including but not limited to 2 μm, 5 μm and 8 μm. In this embodiment, the transition layer 12 is a GaN buffer layer.

[0064] Furthermore, the channel layer 13 includes GaN, and the thickness of the channel layer ranges from 300 to 1200 nm, including but not limited to 500 nm and 1000 nm.

[0065] Furthermore, the barrier layer 14 includes Al x Ga 1-x N (0≤x≤1) layer and In y Al 1-y N (0≤y≤1) layer, the thickness of the barrier layer 14 is in the range of 10 to 25 nm, including but not limited to 13 nm, 18 nm and 22 nm. In this embodiment, the barrier layer 14 is Al 0.2 Ga 0.8 N (ie x=0.2), and its thickness is 15 nm.

[0066] Furthermore, the gate structure 15 includes a P-type GaN gate, a P-type Al z Ga 1-z At least one of N (0≤z≤1) gate, metal gate and metal / insulator / semiconductor gate (Metal-Insulator-Semiconductor, referred to as MIS), the gate thickness range is 50 to 150nm, including but not limited to 75nm, 95nm and 125nm, and the gate structure 15 in this embodiment is a P-type GaN gate, and its thickness is 100nm.

[0067] It should be noted that when the semiconductor device includes a HEMT device, the device layer includes multiple structural layers as described above, and in other embodiments, when the semiconductor device is another type of device (for example, a MOS device), a field plate structure can also be used to modulate the internal electric field, that is, the semiconductor device of this embodiment includes but is not limited to a HEMT device.

[0068] Next, see Figure 2 , perform step S2 to form a dielectric layer 20 above the device layer 10 .

[0069] As an example, the material of the dielectric layer 20 includes at least one of SiN, SiO (i.e., silicon oxide, including silicon dioxide), SiON, AlN and Al2O3, the thickness of the dielectric layer 20 ranges from 50 to 150 nm, including but not limited to 75 nm, 100 nm and 125 nm, the method for forming the dielectric layer 20 includes at least one of PECVD, SACVD, PVD and ALD, the material of the dielectric layer 20 in this embodiment is SiN, the thickness of the dielectric layer 20 is 50 nm, and it is formed by PECVD. It should be noted that, in the case where the field plate 50 of this embodiment is not provided, the thickness of the dielectric layer usually needs to be maintained above a certain value (for example, 150 to 250 nm) to avoid the occurrence of dielectric layer breakdown caused by the local electric field concentration phenomenon at the gate edge or the edge of the field plate 50, and in this embodiment, the device is provided with a field plate 50 of the above structure, the thickness of the dielectric layer 20 can be set relatively thin and is not prone to breakdown, while ensuring that the field plate 50 has a good electric field control capability.

[0070] Next, see Figures 3 to 5 , executing step S2, forming a field plate 50 above the dielectric layer 20, the field plate 50 includes a first field plate layer 310 and a second field plate layer 410, the first field plate layer 310 is located between the dielectric layer 20 and the second field plate layer 410, wherein the first field plate layer 310 includes a silicon layer 311 and a silicon oxide layer 312, the silicon oxide layer 312 is connected to the periphery of the silicon layer 311 (equivalent to the silicon oxide layer 312 being located at the edge of the first field plate layer 310), and at least a portion of the upper surface of the silicon oxide layer 312 extends along an oblique direction away from the silicon layer 311 (i.e., forming an acute angle with a horizontal plane), the second field plate layer 410 includes a first metal 411 and a second metal 412, the second metal 412 is connected to the periphery of the first metal 411 (equivalent to the second metal 412 being located at the edge of the second field plate layer 410), and the extension direction of the second metal 412 is consistent with the extension direction of the upper surface of the silicon oxide layer 312.

[0071] Specifically, the field plate structure in this embodiment has a first metal similar to a conventional field plate structure and a second metal similar to an inclined field plate, wherein the second metal extending obliquely is arranged at the periphery of the first metal, which is equivalent to tilting the edge portion of the conventional field plate where the electric field is easily concentrated locally to serve as an inclined field plate. The second metal is arranged to change the distribution of the electric field lines to reduce the electric field concentration, thereby avoiding the problem of electric field concentration at the edge of the field plate, and avoiding the problem of dielectric breakdown without increasing the thickness of the dielectric layer under the field plate, thereby improving the voltage resistance and reliability of the device and expanding its application prospects. In addition, Figure 5This is equivalent to locally enlarging the second metal to fully demonstrate the inclined extension morphology of the second metal. In fact, in order to ensure that the field plate structure can avoid the problem of electric field concentration at the edge, the length of the second metal needs to be much smaller than the length of the first metal (for example, the length ratio of the two is ≤1 / 30), that is, the second metal is located at the edge terminal position of the field plate and belongs to the edge part of the second field plate layer. In the field plate of this embodiment, the first metal serves as the main structure for modulating the electric field in the field plate, and the second metal serves as an auxiliary structure for adjusting the distribution of edge electric field lines in the field plate.

[0072] It should be noted that, since the field plate structure extending from one side of the gate to the other side of the gate is used as an example in this embodiment, the gate is formed above the barrier layer and the upper surface is significantly higher than the upper surface of the barrier layer. In the case where the thickness of the dielectric layer needs to be strictly limited to ensure a good electric field modulation effect of the field plate, a thicker dielectric layer will not be used to compensate for the surface flatness so that the upper surface of the dielectric layer is completely parallel to the upper surface of the barrier layer. This makes it inevitable that there is a height difference between the part located above the gate and the part located on both sides of the gate in the same structural layer. At this time, the part transitioning from the top of the gate to the two sides of the gate is also regarded as extending in the horizontal direction, but there is a difference in height. That is, in the field plate structure of this embodiment, except for the oblique extension of the second metal, the silicon layer and the first metal both extend in the horizontal direction.

[0073] As an example, forming the field plate 50 above the dielectric layer 20 includes the following steps:

[0074] like Figure 3 and Figure 4 As shown, a silicon base layer 31 and a metal base layer 41 are formed above the dielectric layer 20, the metal base layer 41 covers the upper surface of the silicon base layer 31 and the end surface of the silicon base layer 31 in the horizontal direction is exposed;

[0075] Furthermore, forming the silicon base layer 31 and the metal base layer 41 on the dielectric layer 20 includes the following steps:

[0076] like Figure 3 As shown, a silicon initial layer 30 and a metal initial layer 40 are sequentially formed on the dielectric layer 20;

[0077] like Figure 4 As shown, a photoresist layer (not shown) is formed on the metal initial layer 40 and the photoresist layer is photolithographically processed to form an etching window (not shown), wherein the etching window exposes at least a portion of the upper surface of the metal initial layer 40, and the position and pattern of the initial field plate (i.e., the structure composed of the silicon base layer and the metal base layer) are defined by the photolithography step;

[0078] Etching is performed based on the photoresist layer after photolithography to expose at least a portion of the upper surface of the dielectric layer 20, so as to form a silicon base layer 31 based on the silicon initial layer 30 and to form a metal base layer 41 based on the metal initial layer 40 (i.e., a portion of the metal initial layer 40 and a portion of the silicon initial layer 30 are etched away, so that the remaining silicon initial layer 30 is used as the silicon base layer 31, and the remaining metal initial layer 40 is used as the metal base layer 41), and the end face of the silicon base layer 31 in the horizontal direction is exposed to the outside to facilitate subsequent oxidation treatment.

[0079] like Figure 5 As shown, an oxidation treatment is performed to oxidize the edge portion of the silicon base layer 31 into a silicon oxide layer 312, and the unoxidized portion of the silicon base layer 31 constitutes the silicon layer 311. The portion of the metal base layer 41 located above the edge portion is tilted and deformed based on the formation of the silicon oxide layer 312 to constitute the second metal 412. Accordingly, the portion of the metal base layer 41 located above the silicon layer 311 serves as the first metal 411, and the first metal 41 and the second metal 412 together constitute the second field plate layer 410 (i.e., the edge portion of the metal base layer 41 is tilted to obtain the second field plate layer 410). It should be noted that "edge portion" is a relative concept, and the degree of the edge is adjusted based on the specific parameters of the oxidation process so that the structural parameters of the second metal (including length, tilt angle, morphology, etc.) meet the problem of changing the electric field concentration.

[0080] As an example, the material of the silicon layer 311 includes at least one of amorphous silicon and polycrystalline silicon; the thickness of the silicon layer 311 ranges from 5 to 20 nm, including but not limited to 8 nm, 12 nm and 18 nm; the formation method of the silicon layer 311 includes at least one of CVD, PVD and ALD, and naturally, the above parameters of the silicon initial layer 30 and the silicon base layer 31 are consistent with the silicon layer 311. In this embodiment, the material of the silicon layer 311 is amorphous silicon, the thickness of the silicon layer 311 is 10 nm, and it is formed by PECVD.

[0081] It should be noted that the silicon layer 311 in this embodiment cannot be made of single crystal silicon. Since the deposition temperature of the single crystal silicon thin film is as high as 1200°C, it is easy to cause thermal damage to the GaN buffer layer and dielectric layer in the device layer and other already formed structural layers during its growth process, which affects the actual working performance of the device. Therefore, when selecting the material for making the silicon layer 311, it is necessary to use a material with a deposition temperature less than or equal to 900°C, such as polycrystalline silicon (the deposition temperature is 580-680°C, which is relatively low) or amorphous silicon (the deposition temperature can be as low as room temperature). Of course, the silicon layer 311 can also be made of other materials whose deposition temperature can meet the above temperature conditions. Since the thickness of the silicon layer 311 needs to meet the control of the oxidation process to achieve a certain angle of inclination of the second field plate layer 410 part (i.e., the second metal) located above the silicon oxide layer compared to the second field plate layer 410 part (i.e., the first metal) located above the silicon layer 311 in order to improve the local electric field concentration phenomenon at the edge, the thickness range of the silicon layer 311 is summarized after multiple tests, verifications and adjustments.

[0082] As an example, the second field plate layer 410 includes at least one of a single metal material layer (a single structural layer including only one metal or metal compound), a composite metal material layer (a single structural layer including multiple metals or metal compounds at the same time), and a stacked metal material layer (including at least two layers, each layer of the structure has the same or different materials and each layer of the material can be single or multiple). In this embodiment, the second field plate layer 410 is a single metal material layer.

[0083] Further, the material of the second field plate layer 410 includes at least one of Al, Ni, W, Ti, Au, Ag, TiN, TiW and TaN, and the thickness of the second field plate layer 410 ranges from 50 to 200 nm, including but not limited to 90 nm, 130 nm and 180 nm; the formation method of the second field plate layer 410 includes at least one of CVD, PVD and ALD, and the above parameters of the metal initial layer 40 and the metal base layer 41 are consistent with the second field plate layer 410. In this embodiment, the material of the second field plate layer 410 is TiN, the thickness of the second field plate layer 410 is 80 nm and is formed by PVD. The material of the second field plate layer 410 is preferably a metal or metal compound that is not easily oxidized under high temperature conditions (≥600°C), such as Au, Ag, TiN, etc. Since the metal base layer 41 is also in an oxidizing environment during the subsequent oxidation treatment process to oxidize the edge of the silicon base layer 31 into a silicon oxide layer 312, if an active metal is used, it is very likely to be undesirably oxidized and lose or weaken its basic electric field modulation capability as a field plate. Alternatively, the oxidized metal base layer needs to be subjected to additional steps to remove the metal oxide to obtain the second field plate layer 410, which will increase the process cost. Of course, if the process cost is not considered and only the electric field regulation effect of the field plate structure itself is considered, the second field plate layer 410 can also be made of active metal materials such as Al and Ni. In order to ensure that the structure of the second field plate layer 410 meets the needs of electric field regulation, a barrier layer can be used to wrap the second field plate layer 410 to prevent its surface from being exposed to an oxidizing environment, thereby avoiding the occurrence of metal oxidation reactions. Alternatively, a relatively thick metal initial layer is formed and allowed to be exposed to an oxidizing environment. After the oxidation treatment process is completed, the metal oxide layer on its surface is etched or corroded so that the remaining unoxidized portion serves as the second field plate layer 410. No specific limitation is made here, and the material and thickness of the second field plate layer can be selected based on actual needs.

[0084] As an example, the temperature range of the oxidation treatment is 600-900°C, including but not limited to 680°C, 750°C and 820°C; the time of the oxidation treatment is less than or equal to 30 minutes, including but not limited to 10 minutes, 18 minutes and 25 minutes; the oxidation treatment method includes at least one of dry oxygen oxidation, wet oxygen oxidation, water vapor oxidation, plasma oxidation, photochemical oxidation and electrochemical oxidation. The temperature and time of the oxidation treatment are reasonably selected based on the inclination degree and morphology requirements of the pre-formed second metal 412. Preferably, the edge of the silicon base layer 31 (i.e., the surface in the horizontal direction) is completely oxidized. In this embodiment, the oxidation treatment is 900°C high-temperature oxidation, which can increase the oxidation rate.

[0085] As an example, the length of the silicon oxide layer 312 (ie, the oxidation depth, Figure 6 w) is adjusted by the process parameters of the oxidation treatment. Preferably, please refer to Figure 6 , the length of the silicon oxide layer 312 is equal to the thickness of the silicon layer 311 ( Figure 6 (shown in t).

[0086] Specifically, in this embodiment, since the structure of the second metal 412 corresponds to the structure of the silicon oxide layer 312, the thickness of the dielectric layer 20 below the field plate 50 is limited. If the length of the silicon oxide layer 312 is too large (that is, the degree of oxidation is too deep), the proportion of the second metal 412 is too large (causing the tilted portion of the second field plate layer to be located not only at the edge terminal position but also at the main position). During the operation of the device, since the second metal 412 includes both the silicon oxide layer 312 and the dielectric layer 20 below, the field plate dielectric is thicker as a whole, resulting in a weakened electric field modulation capability. If the length of the silicon oxide layer 312 is too small, the size of the second metal 412 is smaller, and the local tilting degree of the second field plate layer 410 is not sufficient to effectively improve the electric field concentration problem. Therefore, it is preferred that the length of the silicon oxide layer 312 is equal to the thickness of the silicon layer 311. Since the morphology (especially the cross-sectional morphology) and size of the second metal 412 in the field plate structure are directly related to the morphology and size of the silicon oxide layer 312, and the silicon oxide layer 312 is obtained based on the oxidation at the edge of the silicon base layer 31 and is directly related to the thickness of the silicon base layer 31 (consistent with the thickness of the silicon layer 311), therefore, based on the principle that "the length of the silicon oxide layer is equal to the thickness of the silicon layer", the appropriate size range of the second metal 412 is limited (that is, the vertical projection length of the second metal 412 is equal to the thickness of the silicon layer 311). Within the above-mentioned appropriate size range, the second metal 312 only belongs to the field plate edge terminal structure, and the field plate structure can reduce or avoid the occurrence of electric field concentration problems at the edge of the field plate and will not degrade other working performances of the device.

[0087] In one example, if Figure 6 As shown, it is shown as Figure 5 1 is a first enlarged schematic diagram of a local area (the area indicated by the dotted box) in which, in the direction from the silicon layer 311 to the silicon oxide layer 312, the thickness of the silicon oxide layer 312 first increases and then remains unchanged, that is, the portion of the silicon oxide layer 312 that is higher than the silicon layer 311 ( Figure 6 The vertical cross-section of the gate structure 14 in the width direction (the area above the middle dotted line) is trapezoidal, so that the second metal 412 is first inclined and then platform-shaped. At this time, the inclined portion of the second metal 412 has a technical effect similar to that of a traditional inclined field plate. Due to the presence of the silicon oxide layer 312, even if the platform portion is located at the very edge, the presence of the silicon oxide layer 312 thereunder will not cause the underlying dielectric layer 20 to break down.

[0088] In another example, see Figure 7 , displayed as Figure 5 The second enlarged schematic diagram of the local area (the area shown in the dotted box) in the middle shows that in the direction from the silicon layer 311 to the silicon oxide layer 312, the thickness of the silicon oxide layer 312 increases, that is, the portion of the silicon oxide layer 312 that is higher than the silicon layer 311 ( Figure 7 The vertical cross section of the gate structure 14 in the width direction (the area above the middle dotted line) is triangular so that the second metal 412 is tilted as a whole. At this time, the second metal 412 can play the role of electric field regulation of the traditional inclined field plate without increasing the complexity of the process. The above two thickness change trends of the silicon oxide layer 312 are adjusted by the ratio of the vertical oxidation rate to the horizontal oxidation rate when the silicon base layer is oxidized. When the horizontal oxidation rate is slower than the vertical oxidation rate, the side silicon material exposed by the silicon base layer is completely consumed and oxidized to silicon oxide. The horizontal oxidation depth still does not meet the actual needs and continues to oxidize. At this time, the silicon oxide thickness at the edge no longer changes and is in a platform shape, such as Figure 6 As shown; when the horizontal oxidation speed is faster than the horizontal oxidation speed, the side silicon material exposed by the silicon base layer is completely consumed and oxidized to silicon oxide, and the horizontal oxidation depth also meets the actual needs and stops further oxidation, as shown Figure 7 shown.

[0089] It should be noted that, although the field plate extending from one side of the gate to the other side of the gate is used as an example in this embodiment, in fact, the position of the field plate can extend from above the gate to between the gate and the drain, can be located between the gate and the source, etc. In addition, from the perspective of electrical connection, the field plate can be a contact field plate (for example, a source field plate, a gate field plate, or a drain field plate, etc.) or a floating field plate (not connected to any electrode and in a floating state), which is not mandatory here.

[0090] Specifically, the manufacturing method of this embodiment first manufactures an initial stacked field plate structure of a silicon base layer and a metal base layer, and then performs an oxidation treatment to cause an oxidation reaction at the edge of the silicon base layer to be converted into a silicon oxide layer. In the process of silicon oxidation reaction to grow silicon oxide, on the one hand, the thickness of the silicon oxide layer increases compared to the thickness of the silicon base layer. Taking the conversion of silicon to silicon dioxide as an example, each unit thickness of silicon dioxide grown consumes about 0.44 units of silicon thickness, that is, 10nm of amorphous silicon is oxidized to form about 23nm of silicon dioxide, which causes the portion of the metal base layer attached to the corresponding position above the silicon base layer (that is, the second metal) to be lifted up by the silicon oxide layer below and gradually deformed with the oxidation of the silicon oxide layer; on the other hand, during the oxidation process, the oxidant diffuses from the edge of the silicon base layer to the inside ( Figure 6 The dotted arrow in the middle shows the diffusion direction of the oxidant). As the oxidant diffusion concentration gradually decreases from the outside to the inside, the degree of oxidation of the silicon base layer gradually decreases, so that the thickness of the silicon oxide layer gradually decreases. The silicon oxide layer finally obtained presents a morphology that is at least partially tilted, and the second metal presents a similar tilted morphology. The portion of the silicon base layer that remains after oxidation is used as the silicon layer and the partially tilted metal base layer is used as the second field plate layer, thereby forming a stacked field plate including the first field plate layer and the second field plate layer. Based on the tilted structure of the second metal, the overall field plate can produce a technical effect similar to that of a tilted field plate. In short, the manufacturing method has the following advantages:

[0091] 1) The edge region of the second field plate layer in the field plate structure (i.e., the second metal) is at least partially inclined, which is equivalent to forming a local inclined field plate structure at the edge of the field plate, effectively improving the field plate's ability to regulate the electric field without causing edge electric field concentration problems;

[0092] 2) The field plate can be applied above a relatively thin dielectric layer to ensure that the field plate has good control over the electric field, and dielectric breakdown will not occur due to the thin dielectric layer, effectively improving the withstand voltage performance of the device and giving full play to and utilizing the withstand voltage advantage of GaN materials;

[0093] 3) The silicon oxide layer obtained by partial oxidation of the edge of the silicon base layer is used as an additional structure of the dielectric layer, so that the dielectric thickness at the edge of the field plate is increased. Even when the local electric field at the edge of the field plate is strong, the dielectric under the field plate can be guaranteed not to be broken down, and the parasitic capacitance problem caused by the multi-layer field plate can be avoided. In addition, only the structure of the local area is increased, and the electric field regulation ability of the field plate itself will not be weakened.

[0094] 4) When the edge of the silicon base layer is oxidized, since the oxidation reaction gradually develops from the edge to the middle, the length of the silicon oxide layer can be adjusted by setting the oxidation process (the longer the oxidation time, the deeper the oxygen element diffuses into the silicon base layer, making the area thickened by oxidation wider), and the controllability is good;

[0095] 5) The oxidation treatment is a self-alignment process, which does not require lithography, etching and other steps. The process flow is simple and the process accuracy is easy to ensure, and the repeatability and process stability are good;

[0096] 6) The overall process is simple and easy to implement, and is fully compatible with existing device processes without the need to develop new processes or equipment, making it suitable for large-scale high-quality production.

[0097] The method for manufacturing the semiconductor device of this embodiment forms a stacked field plate of a silicon layer-metal layer including a first field plate layer and a second field plate layer, and the second field plate layer includes a second metal extending obliquely to form a locally inclined field plate structure, and uses the field plate to achieve high electric field modulation capability while still maintaining a high dielectric breakdown voltage, and has both high working performance and high reliability. In addition, by utilizing the thickness increase characteristic of silicon oxidation to silicon oxide, the metal is inclined due to mechanical action, and no additional process steps are required to obtain a second metal similar to an inclined field plate. The overall process steps are simple and easy to implement, and are basically compatible with existing processes. Compared with traditional improvement methods, it has outstanding advantages and is suitable for large-scale production.

[0098] Embodiment 2

[0099] The present invention also provides a semiconductor device, which can be manufactured by the manufacturing method described in the first embodiment or other suitable methods. Figure 5 , which is a partial cross-sectional view of the device, and the device includes a device layer 10, a dielectric layer 20 and a field plate 50.

[0100] Specifically, the dielectric layer 20 is located above the device layer 10, the field plate 50 is located above the dielectric layer 20, the field plate 50 includes a first field plate layer 310 and a second field plate layer 410, the first field plate layer 310 is located between the dielectric layer 20 and the second field plate layer 410, wherein the first field plate layer 310 includes a silicon layer 311 and a silicon oxide layer 312, the silicon oxide layer 312 is connected to the periphery of the silicon layer 311 and at least a portion of the upper surface of the silicon oxide layer 312 extends along an oblique direction away from the silicon layer 311, and the second field plate layer 410 includes a first metal 411 and a second metal 412, the second metal 412 is connected to the periphery of the first metal 411 and the extension direction of the second metal 412 is consistent with the extension direction of the upper surface of the silicon oxide layer 312.

[0101] Specifically, the inclined morphology of the second metal 412 in the field plate 50 enables the field plate 50 to well regulate the electric field without causing the problem of local concentration of the edge electric field. The silicon oxide layer 312 is used to assist in forming the special structure of the field plate 50, and on the other hand, as an additional part of the dielectric layer 20 under the field plate 50, it does not affect the electric field modulation capability while improving the device breakdown characteristics.

[0102] As an example, the device layer 10 includes a substrate 11, a transition layer 12, a channel layer 13, a barrier layer 14 and a gate structure 15 stacked in sequence from bottom to top. In addition, the device layer 10 also includes structures such as a source metal and a drain metal arranged on both sides of the gate structure 15.

[0103] As an example, the length of the silicon oxide layer 312 is equal to the thickness of the silicon layer 311 .

[0104] As an example, in the direction from the silicon layer 311 to the silicon oxide layer 312 , the thickness of the silicon oxide layer 312 increases gradually; or, the thickness of the silicon oxide layer 312 increases gradually first and then remains unchanged.

[0105] The semiconductor device of this embodiment has a stacked field plate including a first field plate layer and a second field plate layer, and the second field plate layer includes a second metal located at the edge and extending obliquely. It has high breakdown voltage and high reliability while ensuring high electric field regulation capability. The overall structure is simple and the cost is low, and it is suitable for popularization and application.

[0106] In summary, the method for manufacturing a semiconductor device of the present invention forms a stacked field plate including a first field plate layer and a second field plate layer, and the second field plate layer includes a second metal extending obliquely to present a locally inclined field plate structure, and uses the field plate to achieve high electric field modulation capability while still maintaining a high dielectric breakdown voltage, and has both high working performance and high reliability. In addition, by utilizing the thickness increase characteristic of silicon oxidation to silicon oxide, the metal is tilted due to mechanical action, and no additional process steps are required to obtain a second metal similar to an inclined field plate. The overall process steps are simple and easy to implement, and are basically compatible with existing processes. Compared with traditional improvement methods, the advantages are outstanding and suitable for large-scale production. The semiconductor device of the present invention has a stacked field plate including a first field plate layer and a second field plate layer, and the second field plate layer includes a second metal located at the edge and extending obliquely. While ensuring high electric field regulation capability, it has high breakdown voltage and high reliability. The overall structure is simple, the cost is low, and it is suitable for promotion and application. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0107] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, It is characterized in that The following steps are involved: providing a device layer; forming a dielectric layer above the device layer; A field plate is formed above the dielectric layer, the field plate comprising a first field plate layer and a second field plate layer, the first field plate layer being located between the dielectric layer and the second field plate layer, wherein the first field plate layer comprises a silicon layer and a silicon oxide layer, the silicon oxide layer is connected to the periphery of the silicon layer and at least a portion of the upper surface of the silicon oxide layer extends in an oblique direction away from the silicon layer, and the second field plate layer comprises a first metal and a second metal, the second metal is connected to the periphery of the first metal and an extension direction of the second metal is consistent with an extension direction of the upper surface of the silicon oxide layer.

2. The method for manufacturing a semiconductor device according to claim 1, Features: Forming a field plate above the dielectric layer comprises the following steps: Sequentially forming a silicon base layer and a metal base layer on the dielectric layer, wherein the metal base layer covers the upper surface of the silicon base layer and the end surface of the silicon base layer in the horizontal direction is exposed; The oxidation treatment is performed to oxidize the edge portion of the silicon base layer into a silicon oxide layer, the unoxidized portion of the silicon base layer constitutes the silicon layer, and the portion of the metal base layer located above the edge portion constitutes the second metal based on the formation of the silicon oxide layer.

3. The method for manufacturing a semiconductor device according to claim 2, Features: The temperature range of the oxidation treatment is 600-900° C., the time of the oxidation treatment is less than or equal to 30 minutes, and the oxidation treatment method includes at least one of dry oxygen oxidation, wet oxygen oxidation, water vapor oxidation, plasma oxidation, photochemical oxidation and electrochemical oxidation.

4. The method for manufacturing a semiconductor device according to claim 2, Features: The length of the silicon oxide layer is equal to the thickness of the silicon layer.

5. The method for manufacturing a semiconductor device according to claim 2, Features: In the direction from the silicon layer to the silicon oxide layer, the thickness of the silicon oxide layer increases gradually; or, the thickness of the silicon oxide layer increases gradually first and then remains unchanged.

6. The method for manufacturing a semiconductor device according to claim 1, Features: The material of the silicon layer includes at least one of amorphous silicon and polycrystalline silicon, the thickness range of the silicon layer is 5 to 20 nm, and the method for forming the silicon layer includes at least one of CVD, PVD and ALD; the second field plate layer includes at least one of a single metal material layer, a composite metal material layer and a stacked metal material layer, the material of the second field plate layer includes at least one of Al, Ni, W, Ti, Au, Ag, TiN, TiW and TaN, the thickness range of the second field plate layer is 50 to 200 nm, and the method for forming the second field plate layer includes at least one of CVD, PVD and ALD.

7. The method for manufacturing a semiconductor device according to claim 1, Features: The material of the dielectric layer includes SiN, SiO, SiON, AlN and Al 2 O 3 At least one of the following, the thickness of the dielectric layer is in the range of 50 to 150 nm, and the dielectric layer is formed by at least one of PECVD, SACVD, PVD and ALD.

8. The method for manufacturing a semiconductor device according to claim 1, Features: The device layer includes a substrate, a transition layer, a channel layer, a barrier layer and a gate structure stacked in sequence from bottom to top, wherein the substrate includes at least one of a silicon substrate, a silicon carbide substrate, a sapphire substrate and a diamond substrate, the transition layer includes at least one of an AlN nucleation layer, a multi-quantum well buffer layer, an Al component gradient buffer layer and a GaN buffer layer, the thickness of the transition layer is in the range of 1 to 10 μm, and the barrier layer includes Al x Ga 1-x N (0≤x≤1) layer and In y Al 1-y N (0≤y≤1) layer, the thickness of the barrier layer is in the range of 10 to 25 nm, and the gate structure includes a P-type GaN gate, a P-type Al z Ga 1-z At least one of an N (0≤z≤1) gate, a metal gate, and a metal / insulator / semiconductor gate, wherein the gate thickness ranges from 50 to 150 nm.

9. A semiconductor device, It is characterized in that include: Device layer; a dielectric layer, located above the device layer; A field plate is located above the dielectric layer, the field plate includes a first field plate layer and a second field plate layer, the first field plate layer is located between the dielectric layer and the second field plate layer, wherein the first field plate layer includes a silicon layer and a silicon oxide layer, the silicon oxide layer is connected to the periphery of the silicon layer and at least a portion of the upper surface of the silicon oxide layer extends along an oblique direction away from the silicon layer, and the second field plate layer includes a first metal and a second metal, the second metal is connected to the periphery of the first metal and the extension direction of the second metal is consistent with the extension direction of the upper surface of the silicon oxide layer.

10. The semiconductor device according to claim 9, Features: The length of the silicon oxide layer is equal to the thickness of the silicon layer.

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