Power diode and preparation method thereof

Abstract

The invention provides a power diode and a preparation method thereof. The power diode comprises a substrate; the epitaxial layer is located on one side of the substrate and is provided with the first doping type; the active region is located in the epitaxial layer and comprises first doped regions, second doped regions and third doped regions, the third doped regions are distributed in multiple rows at intervals in the first direction and distributed in multiple columns at intervals in the second direction, the first doped region is at least located between any adjacent third doped regions in the first direction, and the second doped region is at least located between any adjacent third doped regions in the second direction. The second doped regions are at least located between any adjacent third doped regions in the second direction, the first doped regions, the second doped regions and the third doped regions have a second doping type, the doping concentration of the first doped regions is smaller than that of the second doped regions, and the doping concentration of the third doped regions is larger than that of the second doped regions. The power diode solves the problems that in the prior art, the reverse recovery time of the power diode is prolonged under high voltage, and the switching speed of a device is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular, to a power diode and a method for preparing the same. Background Art

[0002] At present, the rapid development of third-generation semiconductor materials has brought new development space to power semiconductor devices, especially the third-generation wide bandgap semiconductor materials represented by SiC. With its excellent material properties, it has been widely used in the manufacture of automotive-grade diodes, metal oxide semiconductor field-effect transistors (MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor) and other devices. Taking power diode devices (PiN, Positive-intrinsic-Negative diode) as an example, compared with the same type of Si-based products, devices made of SiC materials have higher on-state current density and withstand voltage level, and their forward conduction and reverse cutoff characteristics have been greatly improved. However, PiN diodes usually use epitaxial layers as the "i" region, the doping concentration of this region is much lower than the substrate concentration, and a large number of free carriers will be injected during the conduction process to form charge storage, resulting in carrier storage problems in the "i" region, which will cause the reverse recovery time of the device to be prolonged under high voltage, thereby affecting the switching characteristics, and this problem has a tendency to worsen in SiC-based devices. Summary of the invention

[0003] The main purpose of the present application is to provide a power diode and a method for manufacturing the same, so as to at least solve the problem in the prior art that the reverse recovery time of the power diode is prolonged under high voltage, thereby reducing the switching speed of the device.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a power diode is provided, comprising: a substrate; an epitaxial layer, located on one side of the substrate, and having a first doping type; an active region, located in the epitaxial layer, the active region comprising a first doping region, a second doping region and a third doping region, the third doping regions being spaced apart in a first direction in a plurality of rows and spaced apart in a second direction in a plurality of columns, the first doping region being at least located between any adjacent third doping regions in the first direction, the second doping region being at least located between any adjacent third doping regions in the second direction, the first doping region, the second doping region and the third doping region having a second doping type, the doping concentration of the first doping region being less than the doping concentration of the second doping region, the doping concentration of the third doping region being greater than the doping concentration of the second doping region, the first direction and the second direction being parallel to a surface of the epitaxial layer facing away from the substrate, and the first direction being perpendicular to the second direction.

[0005] Optionally, a projection area of ​​each of the first doping regions on the substrate is the same as a projection area of ​​each of the second doping regions on the substrate.

[0006] Optionally, a depth of the third doping region along the thickness direction of the epitaxial layer is greater than a depth of the first doping region and a depth of the second doping region along the thickness direction of the epitaxial layer.

[0007] Optionally, the power diode also includes a terminal structure, which includes a field limiting ring and a field plate, the field limiting ring is arranged around the active area, the field plate is located on the side of the field limiting ring facing away from the substrate, the field limiting ring includes a fourth doping region, the fourth doping region is located in the epitaxial layer, and a surface on a side of the fourth doping region facing away from the substrate is located in a surface on a side of the epitaxial layer facing away from the substrate.

[0008] Optionally, a projection area of ​​each of the first doping regions on the substrate is larger than a projection area of ​​each of the second doping regions on the substrate.

[0009] Optionally, the power diode further includes a first electrode and a second electrode, wherein: the first electrode is located on a side of the active region away from the substrate, and the first electrode is respectively in contact with the first doped region, the second doped region and the third doped region; the second electrode is located on a side of the substrate away from the epitaxial layer.

[0010] Optionally, the field plate includes a first portion and a second portion, the first portion is located on a side of the epitaxial layer facing away from the substrate, and the second portion is located on a side of the first portion facing away from the epitaxial layer and away from the substrate.

[0011] According to another aspect of the present application, a method for preparing a power diode is provided, comprising: providing a substrate; forming an epitaxial layer on one side of the substrate, the epitaxial layer having a first doping type; forming an active region in the epitaxial layer, performing a first ion implantation on the active region to form a first preliminary doping region, performing a second ion implantation on the active region to form a second preliminary doping region, an overlapping region of the first preliminary doping region and the second preliminary doping region being a third doping region, an area where the first preliminary doping region does not overlap with the second preliminary doping region being a first doping region, an area where the second preliminary doping region does not overlap with the first preliminary doping region being a second doping region, the first doping region, the second doping region and the third doping region having a second doping type, a doping concentration of the first doping region being less than a doping concentration of the second doping region, and a doping concentration of the third doping region being greater than a doping concentration of the second doping region.

[0012] Optionally, the step of forming the third doping region includes: providing a mask plate, the mask plate having a plurality of hollow areas; placing the mask plate on a side of the epitaxial layer away from the substrate, and performing a first ion implantation into the prepared active region through the hollow areas to form the first prepared doping region; rotating the mask plate by a preset angle with the center of the mask plate as a rotation point, and performing a second ion implantation into the prepared active region through the hollow areas to form the second prepared doping region, and the overlapping area between the first prepared doping region and the second prepared doping region is the third doping region.

[0013] Optionally, the epitaxial layer includes a terminal structure, the terminal structure includes a region, and the preparation method further includes: placing the mask plate on the side of the terminal region away from the substrate, performing a third ion implantation into the prepared terminal region through the hollow area to form a field limiting ring; and forming a field plate on the side of the field limiting ring away from the substrate.

[0014] The present application provides a power diode, comprising a substrate, an epitaxial layer and an active region, wherein the active region comprises a first doping region, a second doping region and a third doping region, the first doping region and the second doping region have the same doping type, the doping concentration of the first doping type is lower than the doping concentration of the second doping type, when the power diode is in an on state, a small amount of carriers will pass through the first doping region and the epitaxial layer into the i region of the power diode, when the device is switched from an on state to an off state, the carrier concentration of the i region of the region is very low, the reverse recovery speed of the region is accelerated, and the depletion region formed by the first doping region is deeper, the junction capacitance value of the depletion layer is smaller, and the reverse recovery can be completed faster, thereby solving the problem in the prior art that the reverse recovery time of the power diode is prolonged under high voltage, thereby reducing the switching speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 A schematic diagram of a partial cross-sectional structure of a power diode provided in an embodiment of the present application is shown;

[0017] Figure 2 A schematic diagram of a partial top view of a power diode provided in an embodiment of the present application is shown;

[0018] Figure 3 A schematic diagram of a partial cross-sectional structure of another power diode provided in an embodiment of the present application is shown;

[0019] Figure 4A partial top view of another power diode provided in an embodiment of the present application is shown;

[0020] Figure 5 A schematic diagram of the process structure of a method for preparing a power diode provided in an embodiment of the present application is shown;

[0021] Figure 6 Shown in Figure 5 In the preparation method, a schematic diagram of the cross-sectional structure of the substrate after providing the substrate;

[0022] Figure 7 Shown in Figure 6 A schematic diagram of the cross-sectional structure of the substrate after an epitaxial layer is formed on the middle substrate;

[0023] Figure 8 Shown in Figure 7 A schematic diagram of the cross-sectional structure of the substrate after forming the doped region in the active region in the epitaxial layer and the terminal structure.

[0024] The above drawings include the following reference numerals:

[0025] 10. Substrate; 20. Epitaxial layer; 30. Active region; 31. First doped region; 32. Second doped region; 33. Third doped region; 40. Terminal structure; 41. Field limiting ring; 411. Fourth doped region; 42. Field plate; 421. First part; 422. Second part; 50. First electrode; 60. Second electrode. DETAILED DESCRIPTION

[0026] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] As introduced in the background technology, in the prior art, PiN diodes usually use an epitaxial layer as the "i" region. The doping concentration of this region is much lower than the substrate concentration, and a large number of free carriers will be injected into it during the conduction process to form charge storage, which will cause carrier storage problems in the "i" region. This will cause the reverse recovery time of the device to be prolonged under high voltage, thereby affecting the switching characteristics, and this problem tends to worsen in SiC-based devices.

[0030] According to an embodiment of the present application, a power diode is provided, such as Figure 1 and Figure 2 As shown, it includes: a substrate 10; an epitaxial layer 20, which is located on one side of the substrate 10 and has a first doping type; an active area 30, which is located in the epitaxial layer 20, the active area 30 includes a first doping area 31, a second doping area 32 and a third doping area 33, the third doping areas 33 are arranged in a plurality of rows in a first direction X, and are arranged in a plurality of columns in a second direction Y, the first doping area 31 is at least located between any adjacent third doping areas 33 in the first direction X, the second doping area 32 is at least located between any adjacent third doping areas 33 in the second direction Y, the first doping area 31, the second doping area 32 and the third doping area 33 have a second doping type, the doping concentration of the first doping area 31 is less than the doping concentration of the second doping area 32, the doping concentration of the third doping area 33 is greater than the doping concentration of the second doping area 32, the first direction X and the second direction Y are both parallel to a surface of the epitaxial layer 20 that is away from the substrate 10, and the first direction X is perpendicular to the second direction Y.

[0031] Power diodes usually use an epitaxial layer as the "i" region. The doping concentration in this region is much lower than the substrate concentration, and a large number of free carriers are injected during the conduction process to form charge storage. When the device switches from the on state to the off state, the excess carriers in the "i" region need to be removed first, and the device can only enter the cut-off state after the carrier concentration in the "i" region returns to normal levels. This causes the reverse recovery time of the PiN diode to be longer than that of an ordinary diode, limiting the switching speed of the device. The present application introduces a first doping region in the active region of a power diode, the first doping region and the second doping region have the same doping type, the doping concentration of the first doping type is lower than the doping concentration of the second doping type, when the power diode is in an on state, a small amount of carriers will pass through the first doping region and the epitaxial layer into the i region of the power diode, when the device is switched from an on state to an off state, the carrier concentration of the i region of the region is very low, the reverse recovery speed of the region is accelerated, and the depletion region formed by the first doping region is deeper, the junction capacitance value of the depletion layer is smaller, and the reverse recovery can be completed faster, thereby solving the problem in the prior art that the reverse recovery time of the power diode is prolonged under high voltage, thereby reducing the switching speed of the device.

[0032] In the above optional embodiment, the doping concentration of the epitaxial layer is usually lower than 1.5e 16 , the doping concentration of the second doping region should exceed 1.5e 18 , the concentration of the first doping region should be less than 1e 17 , which can achieve a withstand voltage of more than kilovolts. The present application has two different concentrations of doping on the surface "i" layer, in which the high-concentration doping area, the second doping area, and the low-concentration doping area, the first doping area, are arranged alternately and are located in designated areas on the surface of the device. The second doping area is connected to the substrate by contacting the epitaxial layer to form the "P" of a conventional device. + -iN - " structure, and the "first doping region" forms a "P - -IN - " structure, the above device is a vertical structure, the surface of the active area is the anode end of the diode, and the substrate end is the cathode.

[0033] In some optional embodiments, a projected area of ​​each of the first doping regions on the substrate is the same as a projected area of ​​each of the second doping regions on the substrate.

[0034] In the above optional embodiment, the projection sizes of the above first doping region and the above second doping region are set to be consistent, and the same mask plate or mask can be used when doping the above first doping region and the above second doping region, saving the cost of one layer of mask plate or mask.

[0035] In some optional embodiments, a depth of the third doping region along the thickness direction of the epitaxial layer is greater than a depth of the first doping region and a depth of the second doping region along the thickness direction of the epitaxial layer.

[0036] In the above optional implementation, the third doping region is formed after the first doping region and the second doping region are formed. Since the third doping region has undergone two injections, the surface injection concentration is high and the injection depth is also high. In other words, the third doping region is the injection ions injected into the first doping region and the second doping region at the same time. When the device is in a high-voltage cut-off state, the third doping region can form a wider depletion region, avoiding avalanche breakdown caused by the "spherical junction" of the device, thereby improving the stability of the device.

[0037] In some optional embodiments, such as Figure 3 As shown, the power diode further includes a terminal structure 40, which includes a field limiting ring 41 and a field plate 42. The field limiting ring 41 is arranged around the active area 30, and the field plate 42 is located on the side of the field limiting ring 41 away from the substrate 10. The field limiting ring 41 includes a fourth doping region 411, and the fourth doping region 411 is located in the epitaxial layer 20. A surface on one side of the fourth doping region 411 away from the substrate 10 is located in a surface on one side of the epitaxial layer 20 away from the substrate 10.

[0038] In the above optional implementation, if Figure 3 As shown, the terminal structure 40 is composed of a field limiting ring 41 and a field plate 42. The field limiting ring 41 can be formed by a single implantation using the same mask as the P region, and the field plate 42 can be formed by photolithography and etching.

[0039] In some optional embodiments, such as Figure 1 and Figure 4 As shown, the projected area of ​​each of the first doping regions 31 on the substrate 10 is greater than the projected area of ​​each of the second doping regions 32 on the substrate.

[0040] In the above optional implementation, if Figure 4 As shown in FIG. 1 , the area of ​​the first doping region 31 can be increased to 1 to 1.5 times of the original area, which can further reduce the reverse recovery time and improve the withstand voltage level. However, when increasing the area of ​​the first doping region 31, the size of a single chip needs to be increased at the same time, such as Figure 1 and Figure 4 As shown, Figure 4 Relative to Figure 1The area of ​​the first doped region 31 is increased, and the area inside the chip is increased, and the structure of the active region 30 and the area size of the second doped region 32 remain unchanged, so that the forward current conduction capability of the device can be guaranteed.

[0041] In some optional embodiments, such as Figure 3 As shown, the power diode further includes a first electrode 50 and a second electrode 60, wherein: the first electrode 50 is located on the side of the active region 30 away from the substrate 10, and the first electrode 50 is respectively in contact with the first doping region 31, the second doping region 32 and the third doping region 33; the second electrode 60 is located on the side of the substrate 10 away from the epitaxial layer 20.

[0042] In the above optional implementation, if Figure 3 As shown, the first electrode 50 forms a metal-semiconductor ohmic contact with the doped region in the active region 30. The second electrode 60 is located on the side of the substrate 10 away from the epitaxial layer 20. The materials of the first electrode 50 and the second electrode 60 can be ohmic contact metals such as Ni, Ti and TiN, and can be formed by high-temperature sintering at 900°C to 1000°C.

[0043] In some optional embodiments, such as Figure 3 As shown, the field plate 42 includes a first portion 421 and a second portion 422 . The first portion 421 is located on a side of the epitaxial layer 20 away from the substrate 10 , and the second portion 422 is located on a side of the first portion 421 away from the epitaxial layer 20 and away from the substrate 10 .

[0044] In the above optional implementation, if Figure 3 As shown, the first portion 421 is located between the second portion 422 and the field limiting ring 41 . The material of the first portion 421 may be SiO 2 , and the material of the second portion 422 may be Si 3 N 4 .

[0045] When the diode is in the on state, the majority of carriers (holes) in the second doping region are injected into the i region of the diode due to the high doping concentration of the second doping region. + N junction flows to the i region, causing the carrier concentration in this region to increase and form a large injection current; at this time, P - The concentration in the area is much lower than that of P + The injected current is much lower than P + N junction can be almost ignored, so it can be approximately considered that P -The i region does not participate in the device conduction. When the device is switched from the on state to the off state, for a conventional PiN diode structure, it is necessary to release a large number of carriers stored in the i region during the conduction process before the device can completely enter the off state. - The carrier concentration injected into the i region by the second doping region (P + Area); and P - The doping concentration in the region is low, and a deeper depletion layer can be formed under the action of reverse voltage to protect the active region of the device from breakdown, reflecting the fast recovery and high withstand voltage characteristics of the PIN diode of the present application.

[0046] Moreover, after simulation verification, the reverse recovery time of the PiN diode of the present application can be stabilized at the ns level, and the reverse characteristics are significantly improved compared with conventional Si-based devices; at the same time, while ensuring that the forward current transmission characteristics of the device remain unchanged, the area is only increased by about 1.2 to 1.5 times.

[0047] According to another aspect of the present application, a method for preparing a power diode is provided, such as Figure 5 As shown, including:

[0048] Step S101: providing a substrate;

[0049] Step S102: forming an epitaxial layer on one side of the substrate, wherein the epitaxial layer has a first doping type;

[0050] Step S103: forming an active region in the epitaxial layer, performing a first ion implantation on the active region to form a first preliminary doping region, performing a second ion implantation on the active region to form a second preliminary doping region, the overlapping region of the first preliminary doping region and the second preliminary doping region is a third doping region, the region where the first preliminary doping region does not overlap with the second preliminary doping region is a first doping region, the region where the second preliminary doping region does not overlap with the first preliminary doping region is a second doping region, the first doping region, the second doping region and the third doping region have a second doping type, the doping concentration of the first doping region is less than the doping concentration of the second doping region, and the doping concentration of the third doping region is greater than the doping concentration of the second doping region.

[0051] The power diode prepared by adopting the preparation method of the power diode introduces a first doping region in the active region, the first doping region and the second doping region have the same doping type, the doping concentration of the first doping type is lower than the doping concentration of the second doping type, when the power diode is in the on state, a small amount of carriers will pass through the first doping region and the epitaxial layer into the i region of the power diode, when the device is switched from the on state to the off state, the carrier concentration of the i region of the above region is very low, the reverse recovery speed of the region is accelerated, and the depletion region formed by the first doping region is deeper, the junction capacitance value of the depletion layer is smaller, and the reverse recovery can be completed faster, thereby solving the problem in the prior art that the reverse recovery time of the power diode is prolonged under high voltage and the switching speed of the device is reduced.

[0052] The exemplary embodiments of the method for preparing a power diode provided in the present application will be described in more detail below. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0053] First, proceed to step S101: Figure 6 As shown, a substrate 10 is provided;

[0054] Specifically, the substrate 10 may be a silicon carbide substrate, and the substrate 10 has a first type of doping, which may be a P-type.

[0055] After the step of providing the substrate is completed, step S102 is performed: Figure 7 As shown, an epitaxial layer 20 is formed on one side of the substrate, and the epitaxial layer 20 has a first doping type;

[0056] Specifically, an epitaxial layer 20 may be grown on the substrate 10 by an epitaxial growth process. The material of the epitaxial layer 20 may be any one of silicon carbide and silicon nitride. The epitaxial layer 20 has a first doping type, and the doping concentration is much lower than the doping concentration of the substrate 10 .

[0057] After the step of forming an epitaxial layer on one side of the substrate, step S103 is performed: Figure 8As shown, an active area 30 is formed in the above-mentioned epitaxial layer 20, and a first ion implantation is performed on the above-mentioned active area 30 to form a first preliminary doping area, and a second ion implantation is performed on the above-mentioned active area 30 to form a second preliminary doping area, the overlapping area of ​​the above-mentioned first preliminary doping area and the above-mentioned second preliminary doping area is a third doping area 33, the area where the above-mentioned first preliminary doping area does not overlap with the above-mentioned second preliminary doping area is a first doping area 31, and the area where the above-mentioned second preliminary doping area does not overlap with the above-mentioned first preliminary doping area is a second doping area 32, the above-mentioned first doping area 31, the second doping area 32 and the third doping area 33 have a second doping type, the doping concentration of the above-mentioned first doping area 31 is less than the concentration of the above-mentioned second doping area 32, and the doping concentration of the above-mentioned third doping area 33 is greater than the doping concentration of the above-mentioned second doping area 32.

[0058] In some optional embodiments, the step of forming the above-mentioned third doping region includes: providing a mask plate, the above-mentioned mask plate having a plurality of hollow areas; placing the above-mentioned mask plate on the side of the above-mentioned epitaxial layer away from the above-mentioned substrate, and performing a first ion implantation into the prepared active area through the above-mentioned hollow areas to form the above-mentioned first preparatory doping region; rotating the above-mentioned mask plate by a preset angle with the center of the above-mentioned mask plate as the rotation point, and performing a second ion implantation into the above-mentioned prepared active area through the above-mentioned hollow areas to form the above-mentioned second preparatory doping region, and the overlapping area between the above-mentioned first preparatory doping region and the above-mentioned second preparatory doping region is the third doping region.

[0059] In the above optional implementation, the mask plate is a barrier layer for implantation of the doped region in the active region, and can be formed by depositing SiO2 using a chemical vapor deposition process. Considering the high concentration of ion implantation in the second doped region, the thickness of the mask plate should be greater than 3μm to ensure that the non-implanted region is not damaged. The mask plate can be divided into a second doped region layer and a fourth doped region layer. First, a specific material film layer (usually SiO2) is grown on the surface of the substrate, and then a second doped region and a field limiting ring are formed by a photolithography-etching process.

[0060] In some optional embodiments, such as Figure 8 As shown, the epitaxial layer 20 includes a terminal region, and the preparation method further includes: placing the mask plate on the side of the terminal region away from the substrate, performing a third ion implantation into the prepared terminal region through the hollow region to form a field limiting ring 41; and forming a field plate 42 on the side of the field limiting ring 41 away from the substrate 10.

[0061] In the above optional implementation, if Figure 8As shown, while forming the second doping region 32, the second doping region 32 and the fourth doping region 411 can be formed simultaneously through the mask plate, that is, the second doping region 32 and the field limiting ring 41 are formed simultaneously, and the second doping region 32 and the fourth doping region 411 have the same doping concentration. A first portion 421 and a second portion 422 are sequentially formed on the side of the field limiting ring 41 away from the substrate 10 to obtain the field plate 42.

[0062] It should be noted that the second doping region and the fourth doping region in this application are implanted together, otherwise the blocking characteristics of the device will be affected. Therefore, it is necessary to pay attention to the internal structure of the device without missing and the size of the doping region of the active area is within the specification. The size of the doping region of the active area has a great influence on the turn-on-off characteristics of the device, and hard mask technology needs to be used. The above-mentioned mask plates are all hard masks.

[0063] In the above optional implementation, if Figure 3 As shown, a first electrode 50 is formed on a side of the active region 30 facing away from the substrate 10 , and a second electrode 60 is formed on a side of the substrate 10 facing away from the epitaxial layer 20 .

[0064] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0065] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0066] 1) The present application introduces a first doping region into the active region of a power diode. The first doping region and the second doping region have the same doping type, and the doping concentration of the first doping type is lower than the doping concentration of the second doping type. When the power diode is in the on state, a small amount of carriers will pass through the first doping region and the epitaxial layer into the i region of the power diode. When the device is switched from the on state to the off state, the carrier concentration of the i region of the above region is very low, and the reverse recovery speed of the region is accelerated. The depletion region formed by the first doping region is deeper, and the junction capacitance value of the depletion layer is smaller, so the reverse recovery can be completed faster, thereby solving the problem in the prior art that the reverse recovery time of the power diode is prolonged under high voltage, thereby reducing the switching speed of the device.

[0067] 2) The present application forms a third doping region in the power diode, and the surface injection concentration of the third doping region is higher than that of the second doping region, and the injection depth is also higher. When the device is in a high-voltage cut-off state, the third doping region can form a wider depletion region, avoiding avalanche breakdown caused by the device's "spherical junction", thereby improving the stability of the device.

[0068] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A power diode, characterized in that: include: substrate; an epitaxial layer, located on one side of the substrate, having a first doping type; An active region is located in the epitaxial layer, the active region includes a first doping region, a second doping region and a third doping region, the third doping regions are spaced apart in a first direction in a plurality of rows, and spaced apart in a second direction in a plurality of columns, the first doping region is at least located between any adjacent third doping regions in the first direction, the second doping region is at least located between any adjacent third doping regions in the second direction, the first doping region, the second doping region and the third doping region have a second doping type, the doping concentration of the first doping region is less than the doping concentration of the second doping region, the doping concentration of the third doping region is greater than the doping concentration of the second doping region, the first direction and the second direction are both parallel to a surface of the epitaxial layer facing away from the substrate, and the first direction is perpendicular to the second direction.

2. The power diode according to claim 1, characterized in that: A projection area of ​​each of the first doping regions on the substrate is the same as a projection area of ​​each of the second doping regions on the substrate.

3. The power diode according to claim 1, characterized in that: A depth of the third doping region along a thickness direction of the epitaxial layer is greater than a depth of the first doping region and a depth of the second doping region along the thickness direction of the epitaxial layer.

4. The power diode according to claim 1, characterized in that: The power diode also includes a terminal structure, which includes a field limiting ring and a field plate. The field limiting ring is arranged around the active area, and the field plate is located on a side of the field limiting ring facing away from the substrate. The field limiting ring includes a fourth doping region, and the fourth doping region is located in the epitaxial layer. A surface on a side of the fourth doping region facing away from the substrate is located in a surface on a side of the epitaxial layer facing away from the substrate.

5. The power diode according to claim 1, characterized in that: A projected area of ​​each of the first doping regions on the substrate is greater than a projected area of ​​each of the second doping regions on the substrate.

6. The power diode according to any one of claims 1 to 5, characterized in that: The power diode further comprises a first electrode and a second electrode, wherein: The first electrode is located on a side of the active region away from the substrate, and the first electrode is in contact with the first doping region, the second doping region and the third doping region respectively; The second electrode is located on a side of the substrate away from the epitaxial layer.

7. The power diode according to claim 4, characterized in that: The field plate includes a first portion and a second portion. The first portion is located on a side of the epitaxial layer facing away from the substrate, and the second portion is located on a side of the first portion facing away from the epitaxial layer and away from the substrate.

8. A method for preparing a power diode, characterized in that: include: providing a substrate; forming an epitaxial layer on one side of the substrate, the epitaxial layer having a first doping type; An active region is formed in the epitaxial layer, a first ion implantation is performed on the active region to form a first preliminary doping region, a second ion implantation is performed on the active region to form a second preliminary doping region, an overlapping region of the first preliminary doping region and the second preliminary doping region is a third doping region, a region where the first preliminary doping region does not overlap with the second preliminary doping region is a first doping region, a region where the second preliminary doping region does not overlap with the first preliminary doping region is a second doping region, the first doping region, the second doping region and the third doping region have a second doping type, a doping concentration of the first doping region is less than a doping concentration of the second doping region, and a doping concentration of the third doping region is greater than a doping concentration of the second doping region.

9. The preparation method according to claim 8, characterized in that: The step of forming the third doping region comprises: Providing a mask plate, wherein the mask plate has a plurality of hollow areas; Placing the mask plate on a side of the epitaxial layer away from the substrate, and performing first ion implantation into the prepared active region through the hollowed-out region to form the first prepared doped region; The mask plate is rotated by a preset angle with the center of the mask plate as the rotation point, and a second ion implantation is performed into the prepared active area through the hollow area to form the second prepared doping area, and the overlapping area of ​​the first prepared doping area and the second prepared doping area is the third doping area.

10. The preparation method according to claim 9, characterized in that: The epitaxial layer includes a terminal region, and the preparation method further includes: Placing the mask plate on a side of the terminal region away from the substrate, and performing a third ion implantation into the prepared terminal region through the hollow region to form a field limiting ring; A field plate is formed on a side of the field limiting ring facing away from the substrate.

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