Low-power-consumption management circuit and method and electronic equipment

Abstract

The invention discloses a low-power-consumption management circuit, a low-power-consumption management method and electronic equipment. The circuit comprises a low-power-consumption control circuit, a level trigger circuit and a clock driving circuit, the low-power-consumption control circuit is connected with the external controller and the clock driving circuit, and is used for receiving a low-power-consumption starting instruction sent by the external controller and controlling the clock driving circuit to stop working according to the low-power-consumption starting instruction; and the level trigger circuit is connected with the external controller, the clock driving circuit and the low-power-consumption control circuit, and is used for receiving a low-power-consumption exit instruction sent by the external controller and controlling the clock driving circuit to recover working according to the low-power-consumption exit instruction. The method has the technical effects that the system is conveniently controlled to enter the low-power-consumption mode, the power consumption reduction effect is good, the low-power-consumption mode quitting system clock starting efficiency is high, and the reliability is high.

Description

Technical Field

[0001] The present application relates to the field of power management technology, and in particular to a low power consumption management circuit, method and electronic device. Background Art

[0002] The management of low-power states in embedded chip design is becoming increasingly strict, and the focus of management is on how to reduce the standby power consumption of the device and reduce the time to enter and exit the low-power mode. In order to achieve the goal of reducing standby power consumption, clock gating, power gating and other methods are generally adopted. To reduce the entry and exit time of low-power mode, a high-speed clock is often used as a driver, but in the scenario where a high-speed clock is used as a driving clock, it is often impossible to achieve an extremely low standby current. Therefore, the high-speed clock drive circuit needs to be turned off in low-power mode, and when the state of low-power mode is restored to normal working state, the high-speed clock drive circuit needs to be restarted. Summary of the invention

[0003] In view of this, the present application provides a low power consumption management circuit, method and electronic device, in order to solve the technical problem of low power consumption management of a clock driving circuit.

[0004] Specifically, the technical solution of this application is as follows:

[0005] A low power consumption management circuit, comprising: a low power consumption control circuit, a level trigger circuit and a clock driving circuit;

[0006] The low-power control circuit is connected to the external controller and also connected to the clock driving circuit, and is used to receive the low-power start instruction sent by the external controller, and control the clock driving circuit to stop working according to the low-power start instruction;

[0007] The level trigger circuit is connected to the external controller, the clock driving circuit, and the low-power control circuit. It is used to receive the low-power exit instruction sent by the external controller, latch the indication status of the low-power exit instruction, and continuously control the clock driving circuit to resume work.

[0008] In some implementations, a first trigger terminal of the level trigger circuit is connected to an external controller, an output terminal of the level trigger circuit is connected to a first input terminal of the clock driving circuit, and the output terminal of the level trigger circuit is further connected to a first input terminal of the low power consumption control circuit;

[0009] The second input end of the low power control circuit is connected to the external controller, the first output end of the low power control circuit is connected to the second trigger end of the level trigger circuit, and the second output end of the low power control circuit is connected to the second input end of the clock driving circuit;

[0010] The output terminal of the clock driving circuit is connected to the third input terminal of the low power consumption control circuit.

[0011] In some implementations, when the external controller sends a low power exit command to the level-triggered circuit,

[0012] The level trigger circuit is also used to send a start instruction to the low power control circuit and the clock drive circuit;

[0013] A clock driving circuit, used for sending a driving instruction to the low power consumption control circuit according to the start instruction;

[0014] The low power consumption control circuit is also used to control the external system to enter the normal working mode according to the driving instruction and the starting instruction.

[0015] In some implementations, the low power management circuit further includes:

[0016] A wake-up source shielding circuit, wherein the input end of the wake-up source shielding circuit is connected to an external controller, the output end of the wake-up source shielding circuit is connected to a first trigger end of a level triggering circuit, and the control end of the wake-up source shielding circuit is connected to a third output end of a low-power control circuit, for shielding low-power exit instructions mistakenly sent by an external controller.

[0017] In some implementations, the low power control circuit is further used to start the wake-up source shielding circuit when receiving a low power startup instruction, and to turn off the wake-up source shielding circuit when receiving a driving instruction and a startup instruction.

[0018] In some implementations, the low-power control circuit is also used to provide a high level to the second trigger end of the level trigger circuit when a low-power start instruction is received, and to provide a low level to the second trigger end of the level trigger circuit after the clock drive circuit stops working, and to provide a high level for a preset cycle time to the second trigger end of the level trigger circuit when a drive instruction and a start instruction are received to reset the level trigger circuit.

[0019] In some implementations, the signal priority of the second trigger terminal of the level trigger circuit is greater than or equal to the signal priority of the first trigger terminal of the level trigger circuit;

[0020] in,

[0021] When the second trigger terminal of the level trigger circuit is at a high level, the output terminal of the level trigger circuit outputs a low level or outputs an invalid signal;

[0022] When the second trigger terminal of the level trigger circuit is at a low level and the first trigger terminal of the level trigger circuit is at a high level, the output terminal of the level trigger circuit outputs a high level or outputs a valid signal;

[0023] When the second trigger terminal of the level trigger circuit is at a low level and the first trigger terminal of the level trigger circuit is at a low level, the output terminal of the level trigger circuit maintains the current state.

[0024] Based on the same technical concept, the present application also provides a low power consumption management method, which is applied to any of the above-mentioned low power consumption management circuits, and includes the following steps:

[0025] Receiving a low-power startup instruction sent by an external controller through a low-power control circuit;

[0026] Sending a clock stop instruction to the clock driving circuit through the low power control circuit, the clock stop instruction is used to control the clock driving circuit to stop working;

[0027] Receiving a low-power exit instruction sent by an external controller through a level trigger circuit;

[0028] A start instruction is sent to the clock driving circuit through a level trigger circuit, and the start instruction is used to control the clock driving circuit to resume operation.

[0029] In some implementations, after sending the start instruction to the clock driving circuit through the level trigger circuit, the method further includes:

[0030] Sending a start instruction to the low-power control circuit via a level trigger circuit;

[0031] Sending a driving instruction to a low-power control circuit via a clock driving circuit;

[0032] The external system is controlled to enter a normal working mode according to the driving instruction and the starting instruction through the low-power control circuit.

[0033] Based on the same technical concept, the present application also provides an electronic device, including any of the low power consumption management circuits implemented above.

[0034] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0035] 1. This application uses a level trigger circuit and a clock drive circuit, which is different from the traditional use of 32.768Khz as the wake-up start clock source. The level trigger circuit is used to latch the low-power exit state to ensure the stability and continuity of the low-power exit instruction. Starting the clock drive circuit through the level trigger circuit basically solves the problem of turning off all system clocks for extreme low power consumption in low-power mode. The latching function of the level trigger circuit ensures that the clock drive circuit is turned on continuously and stably, providing a stable clock source for the subsequent low-power control circuit to complete the entire low-power wake-up start process, and smoothly completing the handover of control.

[0036] 2. This application is different from the traditional technology of reducing the frequency of the clock driving circuit from the working frequency to the low power consumption frequency. Instead, the clock driving circuit is completely stopped from working, and the exit of the low power consumption mode is achieved through a level trigger circuit that realizes the relevant control process by level triggering, so that the energy consumption of the entire system in the low power consumption mode is further reduced.

[0037] 3. The present application uses a low-power control circuit to combine the start-up instruction sent by the level trigger circuit and the drive instruction sent by the clock drive circuit to comprehensively determine whether to wake up the entire system where the low-power management circuit is located to exit the low-power mode, thereby preventing misjudgment and improving the reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present application.

[0039] Figure 1 It is a circuit structure diagram of a low power consumption management circuit provided in an embodiment of the present application;

[0040] Figure 2 is a circuit structure diagram of a low power consumption management circuit provided in an embodiment of the present application;

[0041] Figure 3 is a circuit structure diagram of a low power consumption management circuit provided by another embodiment of the present application;

[0042] Figure 4 This is a flow chart of a low power consumption management method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0044] In order to simplify the drawings, only the parts related to the application are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0045] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0046] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0047] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0048] In one implementation, refer to the attached specification Figure 1 , a low power management circuit provided in the present application includes: a low power control circuit 100, a level trigger circuit 200 and a clock driving circuit 300;

[0049] The low power control circuit 100 is connected to the external controller 400 and also connected to the clock driving circuit 300, and is used to receive the low power startup instruction sent by the external controller 400, and control the clock driving circuit 300 to stop working according to the low power startup instruction;

[0050] Specifically, the low power control circuit 100 is mainly responsible for managing the entry of the system low power mode in which the low power management circuit is located and the exit process of the low power mode. When the low power control circuit 100 receives the low power startup instruction sent by the external controller 400 from the GPIO (General Purpose Input Output, referred to as IO port, i.e. bus expander), the low power control circuit 100 is responsible for managing the system startup and controlling the system to enter the low power mode. In the low power mode, the system will take a series of actions to reduce energy consumption, extend battery life or save energy, such as reducing the CPU frequency and voltage, reducing the operating frequency and voltage of the processor, and controlling energy consumption; turning off the backlight or screen, for electronic devices or systems with screens, it can be controlled to automatically turn off the screen backlight or put the screen into sleep mode; or turn off unnecessary components, such as turning off wireless networks (Wi-Fi, Bluetooth), USB ports or other external interfaces to reduce energy consumption. In the low power mode, the system can maintain certain necessary functionality to further reduce power consumption. The clock driving circuit 300 plays a vital role in the system. It is mainly used to generate high-frequency clock signals and synchronize the operations of various electronic components and devices. However, its power consumption is often large. In the low-power management process of the present application, the low-power control circuit 100 is controlled by the low-power start instruction of the external memory to suspend the clock driving circuit 300 and save energy as much as possible.

[0051] The level trigger circuit 200 is connected to the external controller 400, the clock driving circuit 300, and the low power control circuit 100, and is used to receive the low power exit instruction sent by the external controller 400, latch the indication state of the low power exit instruction, and continuously control the clock driving circuit 300 to resume work.

[0052] Specifically, due to its electrical and physical properties, the level trigger circuit 200 itself has the function of storing and memorizing input information. Even if the input signal changes or disappears, the level trigger circuit 200 can still maintain its output state, and can be used as the timing and clock signal of the control circuit to ensure that certain operations occur or stop at a specific time. The internal structure of the level trigger circuit 200 can maintain a stable state and switch states under specific conditions, with high reliability. Therefore, in the present application, the level trigger circuit 200 receives the low-power exit instruction sent by the external controller 400 from the GPIO, and the external controller 400 only needs to send a short period of low-power exit instructions, and the corresponding control instructions can be continuously output to the clock drive circuit 300 until the system completely exits the low-power mode, so that the clock drive circuit 300 can resume normal working state.

[0053] In one implementation, refer to the attached specification Figure 2 , the first trigger terminal S of the level trigger circuit 200 is connected to the external controller 400, the output terminal Cout of the level trigger circuit 200 is connected to the first input terminal Tout1Tin1 of the clock driving circuit 300, and the output terminal Cout of the level trigger circuit 200 is also connected to the first input terminal Lin1 of the low power consumption control circuit 100;

[0054] The second input terminal Lin2 of the low power control circuit 100 is connected to the external controller 400, the first output terminal Lout1 of the low power control circuit 100 is connected to the second trigger terminal R of the level trigger circuit 200, and the second output terminal Lout2 of the low power control circuit 100 is connected to the second input terminal Tin2 of the clock driving circuit 300;

[0055] The output terminal of the clock driving circuit 300 is connected to the third input terminal Lin3 of the low power consumption control circuit 100 .

[0056] When the external controller 400 sends a low power consumption exit instruction to the level trigger circuit 200 , the low power consumption exit instruction enters the level trigger circuit 200 from the first trigger terminal S of the level trigger circuit 200 ;

[0057] The level trigger circuit 200 is also used to send a start instruction to the low power control circuit 100 and the clock driving circuit 300;

[0058] Specifically, after the level trigger circuit 200 receives the low-power exit instruction from the first trigger terminal S of the level trigger circuit 200, the output terminal Cout of the level trigger circuit 200 enables the output of the start instruction, and the start instruction can be continuously output under the action of the level trigger circuit 200, so that the clock drive circuit 300 resumes normal operation. Among them, the level trigger circuit 200 includes an RS trigger, and the level trigger circuit 200 can also be other triggers with a level trigger function, and the low-power control purpose is achieved by setting the relevant contents of the truth table, such as a JK trigger, or a plurality of triggers or electronic components form a level trigger circuit with the same function as the RS trigger. It should be noted that the level trigger circuit 200 needs to trigger the relevant functions through the level, and does not need clock drive, which leads to the key element of the present application that the level trigger circuit 200 can realize the relevant functions without clock drive, so that when the clock drive circuit 300 stops working, it can still receive various control instructions normally and complete the low-power control process. In the prior art, when entering the low power consumption mode, the clock circuit with the same or similar function as the clock driving circuit 300 of the present application does not stop working completely, but reduces power by reducing the frequency, for example, reducing the frequency to 32.768Khz (normal operation generally uses 1-48Mhz clock as the driving clock) to reduce power consumption, while the present application completely stops the clock driving circuit 300, so that power consumption is further reduced. When the level trigger circuit 200 is working, due to its level triggering nature, it does not need clock driving at all, and the low power consumption function can be achieved.

[0059] The clock driving circuit 300 is used to send a driving instruction to the low power consumption control circuit 100 according to the start instruction;

[0060] Specifically, the clock driving circuit 300 is successfully awakened after receiving the start-up instruction, and starts to send driving instructions to the low power control circuit 100, so that the low power control circuit 100 can further control the entire system to exit the low power mode.

[0061] The low power consumption control circuit 100 is also used to control the external system to enter a normal working mode according to the driving instruction and the starting instruction.

[0062] Specifically, when the low-power control circuit 100 only receives the start-up instruction but does not receive the drive instruction, it can be considered that the start-up instruction given by the level trigger circuit 200 at this time may be a wrong instruction. At this time, no reaction can be made, and the system does not exit the low-power mode to prevent the wrong exit from causing increased power consumption. The power consumption increase caused by the wrong exit is very serious. Since the components in the electronic equipment and the system need to consume a lot of electric energy at the moment of startup, this itself violates the purpose of the low-power mode. The wrong exit will cause the low-power balance to be broken, causing difficulties in system energy management. When the low-power control circuit 100 receives the start-up instruction of the level trigger circuit 200 and the drive instruction sent by the clock drive circuit 300 at the same time, it can be considered that the system is ready to exit the low-power mode, so it can further help the system to resume normal operation. Among them, the drive instruction can be a trigger signal without any information in a certain time period, or a command signal with information. At the same time, it can also be directly that the clock drive circuit 300 provides a clock signal as a drive instruction for the low-power control circuit 100. No specific restrictions are made here. The signal type in the application scenario is the protection scope of this application.

[0063] In one implementation, the low power management circuit, see the attached specification Figure 3 , also includes:

[0064] A wake-up source shielding circuit, wherein the input end of the wake-up source shielding circuit is connected to the external controller 400, the output end of the wake-up source shielding circuit is connected to the first trigger end S of the level trigger circuit 200, and the control end of the wake-up source shielding circuit is connected to the third output end Lout3 of the low power control circuit 100, for shielding the low power exit instruction mistakenly sent by the external controller 400.

[0065] Specifically, the wake-up source shielding circuit manages and filters the signals from the wake-up source (external controller 400) in the low-power management circuit, and prevents unnecessary signals from interfering with the wake-up device when the system enters the low-power mode, so as to ensure that the device can effectively maintain a low-power state. When filtering invalid signals, the wake-up source shielding circuit can identify and filter out valid signals that are not actually used to wake up the device to exit the low-power mode. These signals may come from the external environment, misoperation, or other sources that are not intended to wake up the device. By shielding invalid signals, the system is ensured to remain stable in low-power mode, and unnecessary wake-up signals are prevented from entering the system to further reduce power consumption and improve energy efficiency. At the same time, by screening valid signals, the wake-up source shielding circuit can improve the recognition rate and accuracy of the wake-up signal, prevent the level trigger circuit 200 that is sensitive to the signal and whose output will be continuously maintained from malfunctioning, and ensure that the system can be quickly and reliably awakened when needed.

[0066] In one implementation, the low power control circuit 100 is further configured to start the wake-up source shielding circuit when receiving a low power startup instruction, and to shut down the wake-up source shielding circuit when receiving a driving instruction and a startup instruction.

[0067] Specifically, the wake-up source shielding circuit is controlled by the low-power control circuit 100. Under the low-power start-up instruction, the low-power control circuit 100 will start the wake-up shielding circuit so that it can continuously detect valid low-power exit instructions in the entire low-power state, ensuring that the instruction can be received by the level trigger circuit 200, and filtering invalid signals to prevent invalid signals from affecting the level trigger circuit 200.

[0068] In one implementation, the low power control circuit 100 is also used to provide a high level to the second trigger terminal R of the level trigger circuit 200 when a low power start instruction is received, and to provide a low level to the second trigger terminal R of the level trigger circuit 200 after the clock drive circuit 300 stops working, and to provide a high level for a preset cycle time to the second trigger terminal R of the level trigger circuit 200 when a drive instruction and a start instruction are received to reset the level trigger circuit 200.

[0069] The signal priority of the second trigger terminal R of the level trigger circuit 200 is greater than or equal to the signal priority of the first trigger terminal S of the level trigger circuit 200;

[0070] When the second trigger terminal R of the level trigger circuit 200 is at a high level, the output terminal Cout of the level trigger circuit 200 outputs a low level or an invalid signal;

[0071] When the second trigger terminal R of the level trigger circuit 200 is at a low level and the first trigger terminal S of the level trigger circuit 200 is at a high level, the output terminal Cout of the level trigger circuit 200 outputs a high level or a valid signal;

[0072] When the second trigger terminal R of the level trigger circuit 200 is at a low level and the first trigger terminal S of the level trigger circuit 200 is at a low level, the output terminal Cout of the level trigger circuit 200 maintains the current state.

[0073] Specifically, under the instruction of the low-power start instruction, the low-power control circuit 100 needs to ensure that a low-power exit instruction contrary to the instruction is not generated. The second trigger terminal R of the level trigger circuit 200 is a reset terminal. When the low-power control circuit 100 provides a high level to the second trigger terminal R of the level trigger circuit 200, the output terminal Cout of the level trigger circuit 200 will not output a signal or output an invalid signal, so that the level trigger circuit 200 does not affect the clock drive circuit 300 and does not start the clock drive circuit 300 that has been turned off by the low-power control circuit 100. And when the second trigger terminal R of the level trigger circuit 200 is at a high level, no matter what signal the first trigger terminal S of the level trigger circuit 200 is, the output terminal Cout of the level trigger circuit 200 outputs a low level or an invalid signal.

[0074] When the low power control circuit 100 provides a low level to the second trigger terminal R of the level trigger circuit 200, the level trigger circuit 200 will output according to the signal reception of the first trigger terminal S of the level trigger circuit 200. If the first trigger terminal S of the level trigger circuit 200 receives a low power exit instruction from the external controller 400 and sets it to a high level, the output terminal Cout of the level trigger circuit 200 will output a high level or a valid signal and keep outputting a high level or a valid signal, thereby restoring the clock driving circuit 300 from the stop state in the low power mode to the working state. If the first trigger terminal S of the level trigger circuit 200 does not receive a low power exit instruction from the external controller 400, the trigger terminal is at a low level, and the output terminal Cout of the level trigger circuit 200 maintains the existing state, and does not send a signal or perform a corresponding action on the clock driving circuit 300.

[0075] Based on the same technical concept, the present application also provides a low power consumption management method, which is applied to any of the above-mentioned low power consumption management circuits. Figure 4 , including the steps of:

[0076] S100, receiving a low power start instruction sent by an external controller through a low power control circuit;

[0077] S200, sending a clock stop instruction to the clock driving circuit through the low power consumption control circuit, where the clock stop instruction is used to control the clock driving circuit to stop working;

[0078] Specifically, the low-power control circuit is mainly responsible for managing the entry into the low-power mode of the system in which the low-power management circuit is located and the exit process of the low-power mode. Therefore, when the low-power start instruction sent by the external controller is received through the low-power control circuit, the low-power control circuit is responsible for managing the system startup and controlling the system to enter the low-power mode. And under normal system conditions, the clock drive circuit is mainly used to generate a high-frequency clock signal, synchronize the operations in various electronic components and devices, and ensure that the electronic components operate in the same timing. It is crucial for high-speed electronic devices such as digital circuits and processors to avoid data loss or conflicts. It usually consumes a lot of power, so it is the main object to be considered for closing in low-power mode. In low-power mode, the system will take a series of actions to reduce energy consumption, extend battery life or save energy, such as reducing the CPU frequency and voltage, reducing the operating frequency and voltage of the processor, and controlling energy consumption; turning off the backlight or screen. For electronic devices or systems with screens, it can be controlled to automatically turn off the screen backlight or put the screen into sleep mode; or turn off unnecessary components, such as turning off wireless networks (Wi-Fi, Bluetooth), USB ports or other external interfaces to reduce energy consumption. In the low power mode, the system can maintain certain necessary functionality, further reducing power consumption. In the low power management process of the present application, the clock driving circuit is suspended under the control of the low power startup instruction of the external memory by the low power control circuit, thereby saving power as much as possible.

[0079] S300, receiving a low power consumption exit instruction sent by an external controller through a level trigger circuit;

[0080] S400, sending a start instruction to the clock driving circuit through a level trigger circuit, where the start instruction is used to control the clock driving circuit to resume operation.

[0081] Specifically, the level trigger circuit can be an RS trigger or other types of triggers or electronic component combinations with similar functions to RS triggers. Due to its electrical and physical properties, it has the function of storing and memorizing input information. Even if the input signal changes or disappears, the level trigger circuit can still maintain its output state, and can be used as the timing and clock signal of the control circuit to ensure that certain operations occur or stop at a specific moment. The internal structure of the level trigger circuit can maintain a stable state and switch states under specific conditions, with high reliability. Therefore, in the present application, the low-power exit instruction sent by the external controller is received by the level trigger circuit, and the external controller sends a short period of low-power exit instruction, which can continuously keep outputting the start instruction to the clock drive circuit until the system completely exits from the low-power mode, so that the clock drive circuit can resume normal working state.

[0082] In one implementation, after sending the start instruction to the clock driving circuit through the level trigger circuit, the method further includes:

[0083] S210, sending a start instruction to the low power consumption control circuit through a level trigger circuit;

[0084] S220, sending a driving instruction to the low power consumption control circuit through the clock driving circuit;

[0085] S230, controlling the external system to enter a normal working mode according to the driving instruction and the starting instruction through the low power consumption control circuit.

[0086] Specifically, when the low-power control circuit receives a startup instruction but does not receive a drive instruction, it can be considered that the startup instruction given by the level trigger circuit at this time may be a wrong instruction. At this time, no reaction can be made, and the system does not exit the low-power mode to prevent the wrong exit from causing increased power consumption. The power consumption increase caused by the wrong exit is very serious. Since the electronic equipment and the components in the system need to consume a lot of electric energy at the moment of startup, this itself violates the purpose of the low-power mode. The wrong exit will cause the low-power balance to be broken, causing difficulties in system energy management. When the low-power control circuit receives the startup instruction of the level trigger circuit and the drive instruction sent by the clock drive circuit at the same time, it can be considered that the system is ready to exit the low-power mode, so it can further help the system to resume normal operation. Among them, the drive instruction can be a trigger signal without any information in a certain time period, or a command signal with information. At the same time, it can also be a clock drive circuit directly providing a clock signal as a drive instruction for the low-power control circuit. No specific restrictions are made here. The signal type in the application scenario is the protection scope of this application.

[0087] Based on the same technical concept, the present application also provides an electronic device, including any of the low power consumption management circuits implemented above.

[0088] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application, and these improvements and modifications should also be regarded as the protection scope of the present application.

Claims

1. A low power consumption management circuit, characterized in that: include: Low power consumption control circuit, level trigger circuit and clock drive circuit; The low-power control circuit is connected to the external controller and also connected to the clock driving circuit, and is used to receive a low-power startup instruction sent by the external controller, and control the clock driving circuit to stop working according to the low-power startup instruction; The level trigger circuit is connected to the external controller, the clock driving circuit, and the low-power control circuit, and is used to receive a low-power exit instruction sent by the external controller, latch the indication status of the low-power exit instruction, and continuously control the clock driving circuit to resume work.

2. The low power consumption management circuit according to claim 1, characterized in that: The first trigger terminal of the level trigger circuit is connected to the external controller, the output terminal of the level trigger circuit is connected to the first input terminal of the clock driving circuit, and the output terminal of the level trigger circuit is also connected to the first input terminal of the low power consumption control circuit; The second input end of the low power consumption control circuit is connected to the external controller, the first output end of the low power consumption control circuit is connected to the second trigger end of the level trigger circuit, and the second output end of the low power consumption control circuit is connected to the second input end of the clock driving circuit; The output end of the clock driving circuit is connected to the third input end of the low power consumption control circuit.

3. The low power consumption management circuit according to claim 1, characterized in that: When the external controller sends the low power consumption exit instruction to the level trigger circuit, The level trigger circuit is further used to send a start instruction to the low power consumption control circuit and the clock driving circuit; The clock driving circuit is used to send a driving instruction to the low power consumption control circuit according to the start instruction; The low power consumption control circuit is further used to control the external system to enter a normal working mode according to the driving instruction and the starting instruction.

4. The low power consumption management circuit according to claim 3, characterized in that: Also includes: A wake-up source shielding circuit, wherein the input end of the wake-up source shielding circuit is connected to the external controller, the output end of the wake-up source shielding circuit is connected to the first trigger end of the level trigger circuit, and the control end of the wake-up source shielding circuit is connected to the third output end of the low-power control circuit, for shielding the low-power exit instruction mistakenly sent by the external controller.

5. The low power consumption management circuit according to claim 4, characterized in that: The low power control circuit is further used to start the wake-up source shielding circuit when receiving the low power startup instruction, and to turn off the wake-up source shielding circuit when receiving the driving instruction and the startup instruction.

6. The low power consumption management circuit according to claim 3, characterized in that: The low power consumption control circuit is further configured to provide a high level to the second triggering terminal of the level triggering circuit when receiving the low power consumption start instruction; After the clock driving circuit stops working, providing a low level to the second triggering terminal of the level triggering circuit; When the driving instruction and the starting instruction are received, a high level of a preset cycle time is provided to the second trigger terminal of the level trigger circuit to reset the level trigger circuit.

7. The low power consumption management circuit according to any one of claims 2 to 6, characterized in that: The signal priority of the second trigger terminal of the level trigger circuit is greater than or equal to the signal priority of the first trigger terminal of the level trigger circuit; in, When the second trigger terminal of the level trigger circuit is at a high level, the output terminal of the level trigger circuit outputs a low level or an invalid signal; When the second trigger terminal of the level trigger circuit is at a low level and the first trigger terminal of the level trigger circuit is at a high level, the output terminal of the level trigger circuit outputs a high level or outputs a valid signal; When the second triggering end of the level triggering circuit is at a low level and the first triggering end of the level triggering circuit is at a low level, the output end of the level triggering circuit maintains the existing state.

8. A low power consumption management method, characterized in that: The low power consumption management circuit according to any one of claims 1 to 7 comprises the steps of: Receiving the low power startup instruction sent by the external controller through the low power control circuit; Sending a clock stop instruction to the clock driving circuit through the low power consumption control circuit, wherein the clock stop instruction is used to control the clock driving circuit to stop working; Receiving a low-power consumption exit instruction sent by the external controller through the level trigger circuit; A start instruction is sent to the clock driving circuit through the level trigger circuit, and the start instruction is used to control the clock driving circuit to resume operation.

9. The low power consumption management method according to claim 8, characterized in that: After the start instruction is sent to the clock driving circuit through the level trigger circuit, the method further includes: Sending a start instruction to the low power consumption control circuit through the level trigger circuit; Sending a driving instruction to the low-power control circuit through the clock driving circuit; The low power consumption control circuit controls the external system to enter a normal working mode according to the driving instruction and the starting instruction.

10. An electronic device, characterized in that: The low power consumption management circuit comprises the low power consumption management circuit as claimed in any one of claims 1 to 7.

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