Comprehensive tool logic unit resource sharing optimization method, computer readable storage medium and electronic equipment

Abstract

The invention provides a comprehensive tool logic unit resource sharing optimization method which comprises the following steps: traversing all logic units in a circuit, establishing a connection relation graph G between the logic units and signals according to input and output relations among the logic units, and inserting all the logic units in the circuit into a logic unit set N of next iteration; traversing all the logic units in the logic unit set N, for each logic unit c, calculating a hash value h of the logic unit c according to parameters and port signals of the logic unit c, generating a key value pair < c, h >, and inserting the key value pair < c, h > into a hash-to-logic unit mapping table M; if the insertion is successful, continuing to traverse the logic unit c in the logic unit set N, and inserting a key value pair < c, h >; and if the insertion fails, optimizing the logic unit c of which the key value pair insertion fails, and updating the connection relation graph G.

Description

Technical Field

[0001] The present invention belongs to the technical field of logic synthesis tools for programmable logic devices, and in particular relates to a synthesis tool logic unit resource sharing optimization method, a computer-readable storage medium, and an electronic device. Background Art

[0002] Logic synthesis is an important step in the FPGA EDA software design process. It converts the Verilog (a hardware description language, HDL) or VHDL circuit file (a hardware description language used to describe the hardware functions of electronic systems) at the behavioral level or register transfer level (RTL) input by the user into a netlist file composed of FPGA basic logic units such as lookup tables (LUTs) and flip-flops (FFs). FPGA logic synthesis includes two stages: synthesis and mapping. Synthesis is to convert the circuit file at the behavioral level or RTL into a logic netlist composed of gate circuits; mapping is to map the logic netlist composed of gate circuits into a netlist file composed of FPGA basic logic units.

[0003] Area, that is, the number of resources, is an important indicator of FPGA logic synthesis tools. Reducing the number of resources after FPGA logic synthesis plays a very important role in improving the routing rate and timing performance of FPGA software. Resource sharing is an issue that logic synthesis tools must deal with. It merges logic units with the same input into one logic unit to achieve the purpose of resource sharing, thereby reducing the number of resources in the synthesis result. As the scale of user circuits becomes larger and larger, the number of synthesized logic units is also very large. Performing complete resource sharing processing is a very time-consuming process. Therefore, it is a technical challenge to quickly and accurately perform resource sharing and merge logic units with the same input. Summary of the invention

[0004] The present invention provides a synthesis tool logic unit resource sharing optimization method, a computer-readable storage medium and an electronic device, which can accurately perform resource sharing, merge logic units with the same input, and improve the speed and efficiency of logic synthesis.

[0005] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0006] To achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a method for optimizing resource sharing of logic units in a comprehensive tool, including traversing all logic units in a circuit, establishing a connection relationship graph G between logic units and signals according to the input and output relationships between logic units, and inserting all logic units in the circuit into a logic unit set N of the next iteration; traversing all logic units in the logic unit set N, for each logic unit c, calculating a hash value h of the logic unit c according to the parameters and port signals of the logic unit c, and generating a key-value pair 〈c, h〉, and inserting the key-value pair 〈c , h〉 is inserted into the hash-to-logic-unit mapping table M; if the insertion is successful, the logic unit c in the logic unit set N is traversed continuously, and the key-value pair 〈c, h〉 is inserted; if the insertion fails, the equivalent logic unit c1 corresponding to the hash value h of the logic unit c that failed to be inserted is found in the hash-to-logic-unit mapping table M; the key-value pair of the logic unit c that failed to be inserted is optimized, and the connection relationship graph G is updated; the logic unit c2 corresponding to each output edge of the logic unit c that failed to be inserted is inserted into the logic unit set N, and the logic unit c that failed to be inserted is deleted in the current netlist and the logic unit set N. The beneficial effect of this technical solution is that the logic units with the same input can be quickly merged into one logic unit to achieve the purpose of resource sharing, thereby reducing the number of resources for the application circuit synthesis result and improving the performance of the application circuit.

[0007] If the number of logic units in the logic unit set N is greater than 0 after deleting the logic unit c that failed to be inserted in the current netlist and set, continue to traverse the logic unit c in the logic unit set N and insert the key-value pair 〈c, h〉; if the number of logic units in the logic unit set N is less than or equal to 0, exit the optimization.

[0008] According to the input and output relationships between the logic units, a connection relationship diagram G between the logic units and the signals is established, including establishing a resource sharing optimized logic unit type set T; all logic units c in the circuit are traversed, and if the type of the logic unit c is in the logic unit type set T, all port signals s of the logic unit c are traversed, and if the port signal s is an input port signal, the port signal s is inserted into the input edge set of the logic unit c, and the logic unit c is added to the output edge set of the port signal s; if the port signal s is not an input port signal, the port signal s is inserted into the output edge set of the logic unit c.

[0009] If the logical unit c in the logical unit type set T has the keep attribute, the logical unit c is not processed.

[0010] If the type of the logic unit c is not in the logic unit type set T, the processing continues with the next logic unit c.

[0011] If all port signals s of the logic unit c have been processed, the process proceeds to the next logic unit c; otherwise, the process continues to process the next port signal s of the logic unit c.

[0012] The calculation of the hash value h of the logic unit c includes: finding whether the current logic unit c has a corresponding hash value in the mapping relationship set cache of logic units to hash values; if the current logic unit c has a hash value in the mapping relationship set cache, then returning the hash value of the current logic unit c and exiting the calculation process; if there is no corresponding hash value, then inserting the type of the logic unit c into the hash string hash_str; if the type of the logic unit c belongs to a binary operator, assigning the signal with a smaller string to the input A terminal of the logic unit c, and the larger signal to the input B terminal of the logic unit c, and assigning each port of the logic unit c The name and signal name are combined into a string, and the string is inserted into the connection string set conn_str; if the type of the logic unit c does not belong to a binary operator, each port name and signal name of the logic unit c is directly combined into a string, and the string is inserted into the connection string set conn_str; the connection string set conn_str is sorted in ascending order, each string in the sorted connection string set conn_str is inserted into the hash string hash_str, the hash function is called to calculate the hash value h of the hash string hash_str, and the calculated result is returned.

[0013] When the key-value pair fails to be inserted, after finding the equivalent logic unit c1, the logic unit c where the key-value pair fails to be inserted is optimized, and the connection relationship graph G is updated, including traversing each output port signal s of the logic unit c where the insertion fails, finding the signal s1 of the same port as the port signal s in the equivalent logic unit c1, and adding a connection edge from the port signal s to the port signal s1 in the current netlist; traversing the logic unit c2 corresponding to each output edge of the logic unit c where the insertion fails on the connection relationship graph G, and inserting the logic unit c2 into the output edge set of the equivalent logic unit c1; traversing the logic unit c3 corresponding to each input edge of the logic unit c where the insertion fails on the connection relationship graph G, and deleting the logic unit c where the insertion fails from the output edge set of the logic unit c3.

[0014] Another technical solution of the present invention provides a computer-readable storage medium, in which program codes are stored. The program codes are called by a processor to execute the above-mentioned synthesis tool logic unit resource sharing optimization method.

[0015] Another technical solution of the present invention provides an electronic device, comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the synthesis tool logic unit resource sharing optimization method described above.

[0016] Compared with the prior art, the beneficial effects of the present invention mainly include more quickly and comprehensively identifying logic units with the same input through iteration, and merging them into one logic unit, thereby achieving the purpose of resource sharing.

[0017] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a flow chart of the logic unit resource sharing method of the present invention.

[0020] Figure 2 The figure is a flow chart of establishing the connection relationship between the logic unit and the signal according to the present invention.

[0021] Figure 3 It is a schematic diagram of the process of calculating the hash value of the logic unit of the present invention.

[0022] Figure 4 It is a schematic diagram of the flow of processing the logic unit to be optimized and updating the connection relationship graph G according to the present invention. DETAILED DESCRIPTION

[0023] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0024] Embodiment 1 provides a method for optimizing resource sharing of logic units of a synthesis tool. The method for optimizing resource sharing of logic units of a synthesis tool in Embodiment 1 is described in detail in Figure 1, the method first traverses all the logic units c of the circuit, and establishes the connection relationship diagram G between the logic units c and the signal according to the input-output relationship between the logic units c; then all the logic units c in the circuit are inserted into the logic unit set N of the next iteration, and then a loop iteration optimization process is performed. In each iteration, a logic unit c is taken out from the set N, and the hash value h of the logic unit c is first calculated according to the parameters and port signals of c; then a key-value pair is generated. In the above, the connection relationship diagram G between the logic unit and the signal is established. The flowchart of this process can be seen in Figure 2 , the specific steps are as follows: S11: Establish a set T of logic unit types optimized for resource sharing.

[0025] S12: traverse all logic units c of the circuit, and execute S13 for each logic unit c.

[0026] S13: If the type of the logic unit c is in the set T of logic unit types, execute S14; otherwise, enter the processing of the next logic unit c.

[0027] S14: If the logic unit c has the keep attribute, the keep attribute here indicates that the logic unit needs to be retained and cannot be simplified, so the logic unit c does not need to be optimized, and the processing of the next logic unit c begins; otherwise, execute S15.

[0028] S15: traverse all port signals of the logic unit c, and execute S16 for each port signal s.

[0029] S16: if the port signal s is a signal of an input port, insert the port signal s into the input edge set of the logic unit c, and add the logic unit c to the output edge set of the port signal s; If the port signal s is not a signal of an input port, the port signal s is inserted into the output edge set of the logic unit c.

[0030] S17: If all ports of the logic unit c have been processed, proceed to the processing of the next logic unit c; otherwise, continue to process the next port signal s of c.

[0031] In Example 1, the hash value h of the logic unit c is calculated, see Figure 3 The flow chart of the hash value h is calculated based on all the parameters and port signals of the logic unit c. The hash value h of the logic unit c is calculated to determine whether two logic units are equivalent, because two logic units with the same hash value are equivalent. The specific steps are as follows: S21: Find out whether the current logical unit c has a corresponding hash value in a hash set cache, where cache is a set of mapping relationships from logical units to hash values.

[0032] S22: If the corresponding hash value of the logic unit c exists in the hash set cache, the value of the logic unit c in the cache is returned (the hash value of the logic unit c is directly output to combine the key-value pair), and the hash value calculation step is exited; otherwise, step S23 is executed.

[0033] S23: Insert the type of the logic unit c into the hash string hash_str.

[0034] S24: Determine whether the type of c is a binary operator (an operator that uses two operands to perform an operation) such as and, or, xor, add, logic_and, or logic_or. If so, execute step S25; otherwise, execute step S26.

[0035] S25: Compare the signals of the A and B ports of the logic unit c, assign the signal with the smaller string to the input A terminal of the logic unit c, and assign the larger signal to the input B terminal of the logic unit c.

[0036] S26: traverse each port signal of the logic unit c, combine each port name and signal name into a string, and insert it into the connection string set conn_str.

[0037] S27: Sort the connection string set conn_str in ascending order of the strings.

[0038] S28: Insert each string in the sorted connection string set conn_str into the hash string hash_str.

[0039] S29: Call the hash function, calculate the hash value h of the hash string hash_str, and return h.

[0040] Optimize the logic unit c that failed to be inserted and update the connection relationship graph G. Figure 4 The specific steps are as follows: S31: traverse each output port signal s of the logic unit c that fails to be inserted, and execute S32.

[0041] S32: Find the signal s1 with the same port as the output port signal s in the equivalent logic unit c1.

[0042] S33: Add a connection edge from output port signal s to output port signal s1 in the current netlist.

[0043] S34: traverse the logic unit c2 corresponding to each output edge of the logic unit c where the insertion failed on the connection relationship graph G, and execute S35.

[0044] S35: Insert the logic unit c2 into the output edge set of the equivalent logic unit c1.

[0045] S36: traverse the logic unit c3 corresponding to each input edge of the logic unit c where the insertion failed on the connection relationship graph G, and execute S37.

[0046] S37: Delete the logic unit c where the insertion fails from the output edge set of the logic unit c3.

[0047] Embodiment 2 provides a computer-readable storage medium, in which a program code is stored, and the program code is called by a processor to execute the method for optimizing resource sharing of a logic unit of a comprehensive tool mentioned in Embodiment 1. By storing a program for implementing the method for optimizing resource sharing of a logic unit of a comprehensive tool in a computer-readable storage medium and calling and executing it through a processor, the execution efficiency of the method for optimizing resource sharing of a logic unit of a comprehensive tool can be effectively improved, while ensuring that no error occurs during each execution.

[0048] Embodiment 3 provides an electronic device comprising one or more processors, a memory, and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the synthesis tool logic unit resource sharing optimization method in Embodiment 1.

[0049] The above is a detailed introduction to a comprehensive tool logic unit resource sharing optimization method, a computer-readable storage medium, and an electronic device provided by the present invention. This article uses specific examples to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for optimizing resource sharing of logic units in a synthesis tool, It is characterized in that Including, traversing all logic units in the circuit, establishing a connection relationship graph G between logic units and signals according to the input and output relationship between the logic units, and inserting all logic units in the circuit into the logic unit set N of the next iteration; Traverse all logic units in the logic unit set N, for each logic unit c, calculate the hash value h of the logic unit c according to the parameters and port signals of the logic unit c, and generate a key-value pair 〈c, h〉, and insert the key-value pair 〈c, h〉 into the hash-to-logic unit mapping table M; If the insertion is successful, continue to traverse the logical unit c in the logical unit set N and insert the key-value pair 〈c, h〉; If the insertion fails, then find the equivalent logical unit c1 corresponding to the hash value h of the logical unit c where the insertion failed in the mapping table M from hash to logical unit; Optimizing the logic unit c where the key-value pair insertion fails, and updating the connection relationship graph G; The logic cell c2 corresponding to each output edge of the logic cell c that failed to be inserted is inserted into the logic cell set N, and the logic cell c that failed to be inserted is deleted from the current netlist and the logic cell set N.

2. A method for optimizing resource sharing of logic units of a synthesis tool according to claim 1, It is characterized in that If the number of logic units in the logic unit set N is greater than 0 after deleting the logic unit c that failed to be inserted in the current netlist and set, then continue to traverse the logic unit c in the logic unit set N and insert the key-value pair 〈c, h〉; If the number of logic units in the logic unit set N is less than or equal to 0, the optimization is exited.

3. A method for optimizing resource sharing of logic units of a synthesis tool according to claim 1, It is characterized in that According to the input and output relationships between the logic units, a connection relationship diagram G between the logic units and the signals is established, including establishing a resource sharing optimized logic unit type set T; Traverse all logic cells c in the circuit. If the type of logic cell c is in the logic cell type set T, traverse all port signals s of logic cell c. If port signal s is an input port signal, insert the port signal s into the input edge set of logic cell c, and add logic cell c to the output edge set of port signal s. If the port signal s is not an input port signal, the port signal s is inserted into the output edge set of the logic unit c.

4. A method for optimizing resource sharing of logic units of a synthesis tool according to claim 3, It is characterized in that If the logical unit c in the logical unit type set T has the keep attribute, the logical unit c is not processed.

5. A method for optimizing resource sharing of logic units of a synthesis tool according to claim 3, It is characterized in that If the type of the logic unit c is not in the logic unit type set T, the processing continues with the next logic unit c.

6. A method for optimizing resource sharing of logic units of a synthesis tool according to claim 1, It is characterized in that If all port signals s of the logic unit c have been processed, the process proceeds to the next logic unit c; otherwise, the process continues to process the next port signal s of the logic unit c.

7. A method for optimizing resource sharing of logic units of a synthesis tool according to claim 1, It is characterized in that The calculation of the hash value h of the logic unit c includes searching whether the current logic unit c has a corresponding hash value in the mapping relationship set cache of logic units to hash values. If the current logic unit c has a hash value in the mapping relationship set cache, the hash value of the current logic unit c is returned, and the calculation process is exited; If there is no corresponding hash value, the type of the logical unit c is inserted into the hash string hash_str; If the type of the logic unit c is a binary operator, the signal with a smaller string is assigned to the input A terminal of the logic unit c, and the larger signal is assigned to the input B terminal of the logic unit c, and each port name and signal name of the logic unit c is combined into a string and inserted into the string set conn_str; If the type of the logic unit c does not belong to a binary operator, directly combine each port name and signal name of the logic unit c into a string and insert it into the connection string set conn_str; The connection string set conn_str is sorted in ascending order, each string in the sorted connection string set conn_str is inserted into the hash string hash_str, a hash function is called to calculate a hash value h of the hash string hash_str, and the calculated result is returned.

8. A method for optimizing resource sharing of logic units of a synthesis tool according to claim 1, It is characterized in that When the key-value pair fails to be inserted, after finding the equivalent logic unit c1, the logic unit c where the key-value pair fails to be inserted is optimized, and the connection relationship graph G is updated, including traversing each output port signal s of the logic unit c where the insertion fails, finding the signal s1 with the same port as the port signal s in the equivalent logic unit c1, and adding a connection edge from the port signal s to the port signal s1 in the current netlist; Traversing the logic unit c2 corresponding to each output edge of the logic unit c that failed to be inserted on the connection relationship graph G, and inserting the logic unit c2 into the output edge set of the equivalent logic unit c1; The logical unit c3 corresponding to each input edge of the logical unit c where the insertion fails is traversed on the connection relationship graph G, and the logical unit c where the insertion fails is deleted from the output edge set of the logical unit c3.

9. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores program code, and the program code is called by a processor to execute the synthesis tool logic unit resource sharing optimization method as described in any one of claims 1-8.

10. An electronic device, It is characterized in that comprising one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the synthesis tool logic unit resource sharing optimization method as described in any one of claims 1-8.

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