A signal processing method and device based on a heterogeneous computing platform

Abstract

The present invention discloses a signal processing method and apparatus based on a heterogeneous computing platform. The method includes: dividing the function of a signal processing digital prototype to obtain a set of atomic modules; the set of atomic modules includes N atomic modules; processing the set of atomic modules to obtain an optimized signal processing digital prototype; using a main processing device, a slave processing device, an external device, and the optimized signal processing digital prototype to perform signal processing to obtain a signal processing result. When decoupling a complex signal processing digital prototype, the present invention maximally utilizes the high-speed signal processing capability of the processor; at the same time, while significantly reducing the construction difficulty of the signal processing digital prototype, it significantly improves the running speed of the processing digital prototype. It realizes the construction of a signal processing digital prototype under a heterogeneous computing platform, improves the technical means of heterogeneous model data interaction, and provides a method and apparatus for constructing a signal processing digital prototype.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular, to a signal processing method and device based on a heterogeneous computing platform. Background Art

[0002] During the operation of a large-scale joint simulation platform system, the construction mode of the signal processing digital prototype will directly affect indicators such as the system operation speed, data credibility, platform stability, simulation verification, and system scalability.

[0003] Currently, the industry usually constructs digital prototypes by means of dynamic library loading. The advantages are that the prototype construction is convenient and fast, while the disadvantages are single construction method, fixed model source, and inability to share resources of other platforms, etc. Based on the heterogeneous computing platform, a method for constructing a signal processing digital prototype is realized. At the same time, a device for constructing a signal processing digital prototype is developed, which solves the problem of sharing resources with other platforms, improves the digital prototype construction speed, ensures the stability of the signal digital prototype, pioneers the signal processing digital prototype industry field, and provides new ideas for the development of the simulation computing field. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a signal processing method and device based on a heterogeneous computing platform, which are compatible with the latest main processor, slave processor, and external devices, construct a ring data buffer exchanger, adapt to the mainstream parallel system architecture, establish a data asynchronous interaction mechanism, realize concurrent asynchronous interaction of radiation signal data, solve the problem of concurrent asynchronous interaction of data between joint simulation models, ensure the authenticity and reliability of joint simulation data, and provide a signal processing digital prototype construction method and implementation means for equipment performance verification, equipment iterative transformation, tactical and combat theory research, and equipment confrontation strategy verification.

[0005] To solve the above technical problem, in the first aspect of an embodiment of the present invention, a signal processing method based on a heterogeneous computing platform is disclosed, and the method includes:

[0006] S1, perform function partitioning on a signal processing digital prototype to obtain an atomic module set; the atomic module set includes N atomic modules;

[0007] S2, process the atomic module set to obtain an optimized signal processing digital prototype;

[0008] S3, use a main processing device, a slave processing device, an external device, and the optimized signal processing digital prototype to perform signal processing to obtain a signal processing result.

[0009] As an optional implementation manner, in the first aspect of an embodiment of the present invention, the processing the atomic module set to obtain an optimized signal processing digital prototype includes:

[0010] S21. Generate an algorithm integration template for each atomic module according to its function, obtaining N algorithm integration templates for the atomic modules;

[0011] The algorithm integration template includes algorithm codes adapted to run on different processing devices;

[0012] S22. Obtain signal processing requirement information;

[0013] S23. According to the signal processing requirement information, obtain K atomic modules from the set of atomic modules, where K is a positive integer;

[0014] S24. Perform a double directed acyclic graph assembly on the K atomic modules to obtain an optimized signal processing digital prototype.

[0015] As an optional implementation manner, in the first aspect of the embodiments of the present invention, using the main processing device, the slave processing device, the external device, and the optimized signal processing digital prototype to perform signal processing to obtain a signal processing result includes:

[0016] S31. Use the main processing device to generate a signal descriptor; the signal descriptor includes an inter-pulse carrier frequency component, an inter-pulse amplitude component, and a frequency modulation slope;

[0017] S32. Use the slave processing device to process the signal descriptor to obtain a reconstructed signal, and send the reconstructed signal to the main processing device;

[0018] S33. The main processing device sends the reconstructed signal to the optimized signal processing digital prototype;

[0019] S34. Use the optimized signal processing digital prototype to process the reconstructed signal to obtain a signal processing result, and display the signal processing result on the external device.

[0020] As an optional implementation manner, in the first aspect of the embodiments of the present invention, using the slave processing device to process the signal descriptor to obtain a reconstructed signal includes:

[0021] S321. Use the slave processing device to process the signal descriptor to obtain a synthesized signal;

[0022] S322. Use a reconstruction model to process the synthesized signal to obtain a reconstructed signal;

[0023] The expression of the reconstruction model is:

[0024] s(t) = p(t)x(t)

[0025] Wherein, s(t) is the reconstructed signal, and p(t) is the synthesized signal. rect() represents the rectangular function, δ(t) is the unit impulse signal, and T s is the preset sampling period, and T p is the time length of each step, and t is the time variable;

[0026] As an optional implementation manner, in the first aspect of the embodiments of the present invention, the processing the reconstructed signal by using the optimized signal processing digital prototype to obtain a signal processing result includes:

[0027] S341, segmenting the reconstructed signal to obtain a first reconstructed signal, a second reconstructed signal, and a third reconstructed signal;

[0028] S342, extracting features from the first reconstructed signal to obtain first feature information;

[0029] S343, extracting features from the second reconstructed signal to obtain second feature information;

[0030] S344, extracting features from the third reconstructed signal to obtain third feature information;

[0031] S345, fusing the first feature information, the second feature information, and the third feature information to obtain fused feature information;

[0032] S346, training a preset signal recognition model by using the fused feature information to obtain an optimized signal recognition model;

[0033] S347, processing the reconstructed signal to be processed by using the optimized signal recognition model to obtain a signal processing result.

[0034] As an optional implementation manner, in the first aspect of the embodiments of the present invention, the extracting features from the first reconstructed signal to obtain first feature information includes:

[0035] Processing the first reconstructed signal by using a first feature extraction model to obtain first feature information;

[0036] The expression of the first feature extraction model is:

[0037]

[0038] Wherein, C 1 (i, j) is the first feature information, i = 1, 2,..., M, j = 1, 2,..., M, x 1 (n) is the first reconstructed signal, and M is the length of the first reconstructed signal.

[0039] As an alternative implementation, in the first aspect of the embodiments of the present invention, the fusion of the first feature information, the second feature information, and the third feature information to obtain the fused feature information includes:

[0040] S3451, using an information integration model to fuse the first feature information, the second feature information, and the third feature information to obtain integrated feature information;

[0041] The expression of the information integration model is:

[0042]

[0043] In the formula, C(i,j) is the integrated feature information, i = 1, 2, …, M, j = 1, 2, …, M, C i (i,j) is the i-th feature information;

[0044] S3452, using a spectral decomposition model to process the integrated feature information to obtain the fused feature information;

[0045] The expression of the spectral decomposition model is:

[0046]

[0047] In the formula, F(u,v) is the fused feature information, u, v are frequency variables, H(i,j) is a preset two-dimensional lag function, and M is the length of the reconstructed signal.

[0048] The second aspect of the embodiments of the present invention discloses a signal processing device based on a heterogeneous computing platform. The device includes:

[0049] A function partitioning module for partitioning the signal processing digital prototype to obtain a set of atomic modules; the set of atomic modules includes N atomic modules;

[0050] A signal processing digital prototype construction module for processing the set of atomic modules to obtain an optimized signal processing digital prototype;

[0051] A signal processing module for using the main processing device, the slave processing device, the external device, and the optimized signal processing digital prototype to perform signal processing to obtain a signal processing result.

[0052] As an alternative implementation, in the second aspect of the embodiments of the present invention, the processing of the set of atomic modules to obtain an optimized signal processing digital prototype includes:

[0053] S21, generating an algorithm integration template for any atomic module according to the function of the atomic module to obtain N algorithm integration templates for the atomic modules;

[0054] The algorithm integration template includes algorithm codes adapted to run on different processing devices;

[0055] S22. Obtain signal processing requirement information;

[0056] S23. According to the signal processing requirement information, obtain K atomic modules from the atomic module set, where K is a positive integer;

[0057] S24. Perform double directed acyclic graph assembly on the K atomic modules to obtain an optimized signal processing digital prototype.

[0058] As an optional implementation manner, in the second aspect of the embodiments of the present invention, using the main processing device, the slave processing device, the external device and the optimized signal processing digital prototype to perform signal processing to obtain a signal processing result includes:

[0059] S31. Use the main processing device to generate a signal descriptor; the signal descriptor includes an inter-pulse carrier frequency component, an inter-pulse amplitude component and a frequency modulation slope;

[0060] S32. Use the slave processing device to process the signal descriptor to obtain a reconstructed signal, and send the reconstructed signal to the main processing device;

[0061] S33. The main processing device sends the reconstructed signal to the optimized signal processing digital prototype;

[0062] S34. Use the optimized signal processing digital prototype to process the reconstructed signal to obtain a signal processing result, and display the signal processing result on the external device.

[0063] As an optional implementation manner, in the second aspect of the embodiments of the present invention, using the slave processing device to process the signal descriptor to obtain a reconstructed signal includes:

[0064] S321. Use the slave processing device to process the signal descriptor to obtain a synthesized signal;

[0065] S322. Use a reconstruction model to process the synthesized signal to obtain a reconstructed signal;

[0066] The expression of the reconstruction model is:

[0067] s(t) = p(t)x(t)

[0068] In the formula, s(t) is the reconstructed signal, p(t) is the synthesized signal, rect() represents a rectangular function, δ(t) is a unit impulse signal, T sis a preset sampling period, T p is the time length of each step, and t is the time variable;

[0069] As an alternative implementation, in the second aspect of the embodiments of the present invention, the processing of the reconstructed signal by using the optimized signal processing digital prototype to obtain a signal processing result includes:

[0070] S341, segmenting the reconstructed signal to obtain a first reconstructed signal, a second reconstructed signal, and a third reconstructed signal;

[0071] S342, extracting features from the first reconstructed signal to obtain first feature information;

[0072] S343, extracting features from the second reconstructed signal to obtain second feature information;

[0073] S344, extracting features from the third reconstructed signal to obtain third feature information;

[0074] S345, fusing the first feature information, the second feature information, and the third feature information to obtain fused feature information;

[0075] S346, training a preset signal recognition model by using the fused feature information to obtain an optimized signal recognition model;

[0076] S347, processing the reconstructed signal to be processed by using the optimized signal recognition model to obtain a signal processing result.

[0077] As an alternative implementation, in the second aspect of the embodiments of the present invention, the extracting features from the first reconstructed signal to obtain first feature information includes:

[0078] Processing the first reconstructed signal by using a first feature extraction model to obtain first feature information;

[0079] The expression of the first feature extraction model is:

[0080]

[0081] In the formula, C 1 (i,j) is the first feature information, i = 1, 2,..., M, j = 1, 2,..., M, x 1 (n) is the first reconstructed signal, and M is the length of the first reconstructed signal.

[0082] As an alternative implementation, in the second aspect of the embodiments of the present invention, the fusing the first feature information, the second feature information, and the third feature information to obtain fused feature information includes:

[0083] S3451. Use the information integration model to integrate the first feature information, the second feature information, and the third feature information to obtain integrated feature information;

[0084] The expression of the information integration model is:

[0085]

[0086] In the formula, C(i,j) is the integrated feature information, i = 1, 2, …, M, j = 1, 2, …, M, C i (i,j) is the i-th feature information;

[0087] S3452. Use the spectral decomposition model to process the integrated feature information to obtain fused feature information;

[0088] The expression of the spectral decomposition model is:

[0089]

[0090] In the formula, F(u,v) is the fused feature information, u and v are frequency variables, H(i,j) is a preset two-dimensional lag function, and M is the length of the reconstructed signal.

[0091] The third aspect of the present invention discloses another signal processing device based on a heterogeneous computing platform, and the device includes:

[0092] A memory storing executable program code;

[0093] A processor coupled to the memory;

[0094] The processor calls the executable program code stored in the memory and executes some or all of the steps in the signal processing method based on a heterogeneous computing platform disclosed in the first aspect of the embodiments of the present invention.

[0095] The fourth aspect of the present invention discloses a computer-readable storage medium, and the computer-readable storage medium stores computer instructions, which are used to execute some or all of the steps in the signal processing method based on a heterogeneous computing platform disclosed in the first aspect of the embodiments of the present invention when called.

[0096] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0097] When decoupling the digital prototype of complex signal processing, the method of the present invention makes the most of the high-speed signal processing capabilities of the processor. At the same time, while significantly reducing the difficulty of constructing the digital prototype of signal processing, it significantly improves the running speed of the digital prototype of signal processing. The main processor, slave processor, and external devices cover current mainstream technical devices, and a data circular buffer memory is used to ensure data exchange between simulation signal digital prototypes. The construction of the digital prototype of signal processing under a heterogeneous computing platform is realized, the technical means of data interaction for heterogeneous models is improved, and a method and device for constructing the digital prototype of signal processing are provided. Using the digital prototype of signal processing to process signals has the characteristics of flexibility and convenience. BRIEF DESCRIPTION OF THE DRAWINGS

[0098] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0099] Figure 1 It is a schematic flowchart of a signal processing method based on a heterogeneous computing platform disclosed in an embodiment of the present invention;

[0100] Figure 2 It is a schematic flowchart of another signal processing method based on a heterogeneous computing platform disclosed in an embodiment of the present invention;

[0101] Figure 3 It is a running flowchart of constructing a digital prototype of signal processing based on a heterogeneous computing platform disclosed in an embodiment of the present invention;

[0102] Figure 4 It is a schematic structural diagram of a signal processing device based on a heterogeneous computing platform disclosed in an embodiment of the present invention;

[0103] Figure 5 It is a schematic structural diagram of another signal processing device based on a heterogeneous computing platform disclosed in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0104] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0105] In the description, claims and the above drawings of the present invention, terms such as "first" and "second" are used to distinguish different objects rather than to describe a specific order. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0106] Reference to "embodiment" herein means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present invention. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0107] The present invention discloses a signal processing method and apparatus based on a heterogeneous computing platform. The method includes: performing functional partitioning on a signal processing digital prototype to obtain a set of atomic modules; the set of atomic modules includes N atomic modules; processing the set of atomic modules to obtain an optimized signal processing digital prototype; and using a main processing device, a slave processing device, an external device and the optimized signal processing digital prototype to perform signal processing to obtain a signal processing result. When decoupling a complex signal processing digital prototype, the present invention maximally utilizes the high-speed signal processing capability of the processor; at the same time, while significantly reducing the construction difficulty of the signal processing digital prototype, it significantly improves the running speed of the processing digital prototype. It realizes the construction of a signal processing digital prototype under a heterogeneous computing platform, improves the technical means of heterogeneous model data interaction, and provides a method and apparatus for constructing a signal processing digital prototype. The following will be described in detail respectively.

[0108] Embodiment 1

[0109] Please refer to Figure 1 , Figure 1 which is a schematic flowchart of a signal processing method based on a heterogeneous computing platform disclosed in an embodiment of the present invention. Among them, Figure 1 the described signal processing method based on a heterogeneous computing platform is applied to the field of signal processing technology. When significantly reducing the construction difficulty of the signal processing digital prototype, it significantly improves the running speed of the processing digital prototype, which is not limited in the embodiments of the present invention. As Figure 1 shown, the signal processing method based on a heterogeneous computing platform may include the following operations:

[0110] S1. Divide the functional digital prototype of signal processing to obtain a set of atomic modules; the set of atomic modules includes N atomic modules;

[0111] S2. Process the set of atomic modules to obtain an optimized functional digital prototype of signal processing;

[0112] S3. Use the main processing device, slave processing device, external device, and the optimized functional digital prototype of signal processing to perform signal processing and obtain a signal processing result.

[0113] An atomic module is a functional module obtained by dividing the functional digital prototype of signal processing;

[0114] Optionally, the processing the set of atomic modules to obtain an optimized functional digital prototype of signal processing includes:

[0115] S21. Generate an algorithm integration template for each atomic module according to the function of any atomic module, and obtain N algorithm integration templates for atomic modules;

[0116] The algorithm integration template includes algorithm codes adapted to run on different processing devices;

[0117] S22. Obtain signal processing requirement information;

[0118] S23. According to the signal processing requirement information, obtain K atomic modules from the set of atomic modules, where K is a positive integer;

[0119] S24. Perform double directed acyclic graph assembly on the K atomic modules to obtain an optimized functional digital prototype of signal processing.

[0120] In this embodiment, the structure of the double directed acyclic graph is as Figure 2 shown.

[0121] Optionally, the using the main processing device, slave processing device, external device, and the optimized functional digital prototype of signal processing to perform signal processing and obtain a signal processing result includes:

[0122] S31. Use the main processing device to generate a signal descriptor; the signal descriptor includes the inter-pulse carrier frequency component, inter-pulse amplitude component, and frequency modulation slope;

[0123] S32. Use the slave processing device to process the signal descriptor to obtain a reconstructed signal, and send the reconstructed signal to the main processing device;

[0124] S33. The main processing device sends the reconstructed signal to the optimized functional digital prototype of signal processing;

[0125] S34. Use the optimized signal processing digital prototype to process the reconstructed signal, obtain a signal processing result, and display the signal processing result on the external device.

[0126] Optionally, the step of using the processing device to process the signal descriptor to obtain a reconstructed signal includes:

[0127] S321. Use the processing device to process the signal descriptor to obtain a synthesized signal;

[0128] Optionally, the synthesized signal is:

[0129]

[0130] where \(p(t)\) is the synthesized signal, \(f\) i is the inter-pulse carrier frequency component of the radiation signal descriptor within the \(i\)-th step, \(A\) i is the inter-pulse amplitude component of the radiation signal descriptor within the \(i\)-th step, \(r\) i is the frequency modulation slope of the radiation signal descriptor within the \(i\)-th step, and \(t\) represents time;

[0131] S322. Use the reconstruction model to process the synthesized signal to obtain a reconstructed signal;

[0132] The expression of the reconstruction model is:

[0133] \(s(t)=p(t)x(t)\)

[0134] where \(s(t)\) is the reconstructed signal, \(p(t)\) is the synthesized signal, \(rect()\) represents the rectangular function, \(\delta(t)\) is the unit impulse signal, \(T\) s is the preset sampling period, \(T\) p is the time length of each step, and \(t\) is the time variable;

[0135] Optionally, the step of using the optimized signal processing digital prototype to process the reconstructed signal to obtain a signal processing result includes:

[0136] S341. Segment the reconstructed signal to obtain a first reconstructed signal, a second reconstructed signal, and a third reconstructed signal;

[0137] Segment the reconstructed signal into a first reconstructed signal, a second reconstructed signal, and a third reconstructed signal. The length of each reconstructed signal is equal, which is \(M\). If the length cannot be divided by 3 evenly, it can be achieved by padding with zeros.

[0138] S342. Extract features from the first reconstructed signal to obtain first feature information;

[0139] S343. Extract features from the second reconstructed signal to obtain second feature information;

[0140] S344. Extract features from the third reconstructed signal to obtain third feature information;

[0141] S345. Fuse the first feature information, the second feature information, and the third feature information to obtain fused feature information;

[0142] S346. Use the fused feature information to train a preset signal recognition model to obtain an optimized signal recognition model;

[0143] S347. Use the optimized signal recognition model to process the reconstructed signal to be processed to obtain a signal processing result.

[0144] Optionally, the extracting features from the first reconstructed signal to obtain first feature information includes:

[0145] Use a first feature extraction model to process the first reconstructed signal to obtain first feature information;

[0146] The expression of the first feature extraction model is:

[0147]

[0148] where C 1 (i, j) is the first feature information, i = 1, 2, …, M, j = 1, 2, …, M, x 1 (n) is the first reconstructed signal, and M is the length of the first reconstructed signal.

[0149] The expression of the second feature extraction model is:

[0150]

[0151] where C 2 (i, j) is the second feature information, i = 1, 2, …, M, j = 1, 2, …, M, x 2 (n) is the second reconstructed signal, and M is the length of the second reconstructed signal.

[0152] The expression of the third feature extraction model is:

[0153]

[0154] where C 3 (i, j) is the third feature information, i = 1, 2, …, M, j = 1, 2, …, M, x 3 (n) is the third reconstructed signal, and M is the length of the third reconstructed signal.

[0155] Optionally, the fusion of the first feature information, the second feature information, and the third feature information to obtain fused feature information includes:

[0156] S3451. Using an information integration model, fuse the first feature information, the second feature information, and the third feature information to obtain integrated feature information;

[0157] The expression of the information integration model is:

[0158]

[0159] In the formula, C(i,j) is the integrated feature information, i = 1, 2,..., M, j = 1, 2,..., M, C k (i,j) is the k-th feature information, k = 1, 2, 3;

[0160] S3452. Using a spectral decomposition model, process the integrated feature information to obtain fused feature information;

[0161] The expression of the spectral decomposition model is:

[0162]

[0163] In the formula, F(u,v) is the fused feature information, u, v are frequency variables, H(i,j) is a preset two-dimensional lag function, and M is the length of the reconstructed signal.

[0164] Optionally, the method for fusing the first feature information, the second feature information, and the third feature information to obtain fused feature information is:

[0165] Fuse the first feature information and the second feature information to obtain fourth feature information;

[0166] Fuse the fourth feature information and the third feature information to obtain fused feature information;

[0167] The same method is used for the two fusions. Specifically (taking the fusion of the first feature information and the second feature information as an example):

[0168] Process the first feature information to obtain the first covariance matrix;

[0169] The first feature information is X, and the first covariance matrix is S XX ;

[0170] S XX = cov(X,X)

[0171] cov represents covariance calculation;

[0172] Process the second feature information to obtain the second covariance matrix;

[0173] The second feature information is Y, and the second covariance matrix is S YY ;

[0174] S YY = cov(Y, Y)

[0175] Process the first feature information and the second feature information to obtain the first cross-covariance matrix and the second cross-covariance matrix;

[0176] The first cross-covariance matrix is S XY ;

[0177] S XY = cov(X, Y)

[0178] The second cross-covariance matrix is S YX ;

[0179] S YX = cov(Y, X)

[0180] S XY = S YX T ;

[0181] T represents transpose;

[0182] Process the first covariance matrix, the second covariance matrix, the first cross-covariance matrix, and the second cross-covariance matrix to obtain a feature fusion matrix;

[0183]

[0184] M 1 is the feature fusion matrix;

[0185] Process the feature fusion matrix to obtain a first singular vector and a second singular vector;

[0186] Solve for the singular values of M 1 to obtain the largest singular value and its preceding and succeeding singular vectors as the first singular vector u 1 and the second singular vector v 1 ;

[0187] Process the first singular vector and the second singular vector to obtain a first projection vector and a second projection vector;

[0188]

[0189] where a is the first projection vector and b is the second projection vector;

[0190] Process the first projection vector and the second projection vector to obtain the fourth feature information.

[0191]

[0192] Where Z is the fourth feature information.

[0193] It can be seen that the method of the present invention makes maximum use of the high-speed signal processing capability of the processor when decoupling the complex signal processing digital prototype; at the same time, when significantly reducing the construction difficulty of the signal processing digital prototype, it significantly improves the running speed of the processing digital prototype. The main processor, slave processor and external devices cover the current mainstream technical devices, and the data circular buffer memory is used to ensure the data exchange between the simulation signal data prototypes. The construction of the signal processing digital prototype under the heterogeneous computing platform is realized, the technical means of heterogeneous model data interaction is improved, and the method and device for constructing the signal processing digital prototype are provided. Using the signal processing digital prototype to implement signal processing has the characteristics of flexibility and convenience.

[0194] Embodiment 2

[0195] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of another signal processing method based on a heterogeneous computing platform disclosed in the embodiments of the present invention. Among them, Figure 2 The described signal processing method based on a heterogeneous computing platform is applied to the field of signal processing technology. When significantly reducing the construction difficulty of the signal processing digital prototype, it significantly improves the running speed of the processing digital prototype, which is not limited in the embodiments of the present invention. As Figure 2 shown, the signal processing method based on a heterogeneous computing platform may include the following operations:

[0196] The slave processing device + the master processing device is used to implement the construction of the signal digital prototype. The main principle is: using the circular buffer memory to realize lock-free concurrent asynchronous data replication between the slave processing device, the master processing device and the external device, and through the external device and the master and slave processing devices for signal processing digital prototype construction, storage and invocation, to realize the construction of the heterogeneous computing platform data prototype, as Figure 2 shown.

[0197] Master processing device

[0198] The master processing device covers the current mainstream processing devices, including processing devices with X86 / AMD64 architecture, ARM architecture processing devices, LongArch architecture processing devices, RISC-V architecture processing devices, and artificial (AI) intelligent processing devices.

[0199] Slave processing device

[0200] The processing devices cover current mainstream processing devices, including: Graphics Processing Unit (GPU) devices, General-Purpose Graphics Processing Unit (GPGPU) devices, Neural Network Processing Unit (NPU) devices, Digital Signal Processor (DSP) devices, Field-Programmable Gate Array (FPGA) devices, and Co-Processing Unit (PPU).

[0201] External devices

[0202] The external devices cover Hard Disk (HD) and its arrays or devices, Solid State Drive (SD) and its arrays or devices, Ethernet network cards or devices, InfiniBand (IB) network cards or devices, sampling signal playback and / or Digital-to-Analog Conversion (DAC) cards or devices, fiber optic reflective memory cards or devices, General-Purpose Interface Bus (GPIB) cards or devices, and data acquisition and recording devices.

[0203] Multi-dimensional computing platform integration.

[0204] This simulation platform is not limited to the platform framework, and also realizes the integration capabilities of OpenMP, MPI, thread pools, and other parallel frameworks.

[0205] Simulation application integration interface

[0206] This simulation platform is not limited to the platform executable program, and can also integrate computer programming language code, code developed based on the programming interface (API) of the slave processing device, dynamic / static link libraries, scripts, or other forms of description.

[0207] Method for constructing a signal processing digital prototype based on a heterogeneous computing platform

[0208] Divide the atomic modules of the signal processing digital prototype; generate an algorithm integration template for the atomic modules, and integrate the signal processing algorithm code of the atomic modules to adapt to the environment running on different processing devices; script or graphically assemble multiple atomic modules into a dual directed acyclic graph of execution flow / data flow to form a signal processing digital prototype; schedule and execute the atomic modules of the signal processing digital prototype according to the dual directed acyclic graph; record the simulation results in a concurrent asynchronous manner, display waveforms and spectra; and output the signal processing results to external devices.

[0209] Cover signal processing digital prototype types

[0210] Radar signal processing digital prototype, electronic reconnaissance signal processing digital prototype, communication signal processing digital prototype, infrared / photoelectric image signal processing digital prototype, and other signal processing digital prototypes.

[0211] The operation process of constructing a signal processing digital prototype based on a heterogeneous computing platform is as Figure 3 shown:[[]]END]]

[0212] (1) Divide the atomic modules of the signal processing digital prototype;

[0213] (2) Generate an algorithm integration template for the atomic modules, and integrate the signal processing algorithm codes of the atomic modules to adapt to the environments running on different processing devices;

[0214] (3) Script or graphically assemble multiple atomic modules, assemble a double directed acyclic graph of the execution flow / data flow, and constitute a signal processing digital prototype;

[0215] (4) Schedule and execute the atomic modules of the signal processing digital prototype according to the double directed acyclic graph;

[0216] (5) Record the simulation results in a concurrent asynchronous manner, and display waveforms and spectra;

[0217] (6) Output the signal processing results to external devices.

[0218] Embodiment III

[0219] Please refer to Figure 4 , Figure 4 which is a schematic structural flow diagram of a signal processing device based on a heterogeneous computing platform disclosed in an embodiment of the present invention. Among them, Figure 4 the described signal processing device based on a heterogeneous computing platform is applied to the field of signal processing technology. When significantly reducing the construction difficulty of the signal processing digital prototype, the running speed of the processing digital prototype is significantly improved, which is not limited in the embodiments of the present invention. As Figure 4 shown, the signal processing device based on a heterogeneous computing platform may include the following operations:

[0220] S301, a function division module, configured to perform function division on the signal processing digital prototype to obtain a set of atomic modules; the set of atomic modules includes N atomic modules;

[0221] S302, a signal processing digital prototype construction module, configured to process the set of atomic modules to obtain an optimized signal processing digital prototype;

[0222] S303, a signal processing module, configured to use a main processing device, a slave processing device, an external device, and the optimized signal processing digital prototype to perform signal processing to obtain a signal processing result.

[0223] Embodiment IV

[0224] Please refer to Figure 5 , Figure 5 which is a schematic structural flow diagram of another signal processing device based on a heterogeneous computing platform disclosed in an embodiment of the present invention. Among them, Figure 5The described signal processing device based on a heterogeneous computing platform is applied to the field of signal processing technology. While significantly reducing the difficulty of constructing a signal processing digital prototype, it significantly improves the running speed of the processing digital prototype. The embodiments of the present invention are not limited. As Figure 5 shown, the signal processing device based on a heterogeneous computing platform may include the following operations:

[0225] A memory 401 storing executable program code;

[0226] A processor 402 coupled to the memory 401;

[0227] The processor 402 calls the executable program code stored in the memory 401 to execute the steps in the signal processing method based on a heterogeneous computing platform described in Embodiment 1 and Embodiment 2.

[0228] Embodiment 5

[0229] An embodiment of the present invention discloses a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to execute the steps in the signal processing method based on a heterogeneous computing platform described in Embodiment 1 and Embodiment 2.

[0230] The device embodiments described above are merely illustrative. Modules described as separate components may or may not be physically separated, and components shown as modules may or may not be physical modules, i.e., they may be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative labor.

[0231] Through the specific descriptions of the above embodiments, those skilled in the art can clearly understand that each implementation manner can be realized by means of software plus a necessary general hardware platform, and of course, it can also be realized by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, and the storage medium includes read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc memories, magnetic disk memories, tape memories, or any other medium that can be used to carry or store data and is computer-readable.

[0232] Finally, it should be noted that: The signal processing method and device based on a heterogeneous computing platform disclosed in the embodiments of the present invention only disclose the preferred embodiments of the present invention, and are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A signal processing method based on a heterogeneous computing platform, characterized in that: The method comprises: S1, functionally dividing the signal processing digital prototype to obtain an atomic module set; the atomic module set includes N atomic modules, where N is a positive integer; S2, processing the set of atomic modules to obtain an optimized signal processing digital prototype, including: S21, generating an algorithm integration template of any atomic module according to the function of the atomic module, and obtaining algorithm integration templates of N atomic modules; The algorithm integration template includes algorithm codes adapted to run on different processing devices; S22, obtaining signal processing requirement information; S23, acquiring K atomic modules from the atomic module set according to the signal processing requirement information, where K is a positive integer; S24, performing dual directed acyclic graph assembly on the K atomic modules to obtain an optimized signal processing digital prototype; S3, using the master processing device, the slave processing device, the external device and the optimized signal processing digital prototype to perform signal processing to obtain a signal processing result, including: S31, using the main processing device to generate a signal description word; the signal description word includes an inter-pulse carrier frequency component, an inter-pulse amplitude component and a frequency modulation slope; The main processing devices include X86 / AMD64 architecture processing devices, ARM architecture processing devices, LongArch architecture processing devices, RISC-V architecture processing devices and artificial intelligence processing devices; S32, using the slave processing device to process the signal description word to obtain a reconstructed signal, and sending the reconstructed signal to the master processing device, including: S321, using a slave processing device to process the signal description word to obtain a synthesized signal; The synthetic signal is: Where p(t) is the synthetic signal, f i is the pulse-to-pulse carrier frequency component of the radiation signal description word within the i-th step, A i is the pulse-to-pulse amplitude component of the radiation signal description word within the i-th step, r i The frequency modulation slope of the radiation signal description word within the i-th step, t represents time; S322, using a reconstruction model, processing the synthesized signal to obtain a reconstructed signal; The reconstruction model expression is: s(t)=p(t)x(t) Where s(t) is the reconstructed signal and p(t) is the synthesized signal. rect() represents the rectangular function, δ(t) is the unit impulse signal, T s is the preset sampling period, T p is the time length of each step, and t is the time variable; The slave processing devices include graphics processor devices, general purpose computing graphics processor devices, neural network processor devices, digital signal processor devices, field programmable array devices, and co-processing units; S33, the main processing device sends the reconstructed signal to the optimized signal processing digital prototype; S34, using the optimized signal processing digital prototype to process the reconstructed signal to obtain a signal processing result, and displaying the signal processing result on the external device, including: S341, segmenting the reconstructed signal to obtain a first reconstructed signal, a second reconstructed signal and a third reconstructed signal; S342, extracting features from the first reconstructed signal to obtain first feature information, including: Using a first feature extraction model, processing the first reconstructed signal to obtain first feature information; The first feature extraction model expression is: Wherein, C1(i,j) is the first characteristic information, i=1,2,…,M, j=1,2,…,M, x1(n) is the first reconstructed signal, and M is the length of the first reconstructed signal; S343, performing feature extraction on the second reconstructed signal to obtain second feature information; S344, performing feature extraction on the third reconstructed signal to obtain third feature information; S345, fusing the first feature information, the second feature information, and the third feature information to obtain fused feature information, including: S3451, using an information synthesis model, fusing the first feature information, the second feature information, and the third feature information to obtain comprehensive feature information; The information integration model expression is: Where C(i,j) is the comprehensive feature information, i = 1, 2, ..., M, j = 1, 2, ..., M, C i (i,j) is the i-th feature information; S3452, using a spectral decomposition model, processing the comprehensive feature information to obtain fused feature information; The spectrum decomposition model expression is: Where F(u,v) is the fusion feature information, u,v are frequency variables, H(i,j) is the preset two-dimensional lag function, and M is the length of the reconstructed signal; S346, using the fused feature information, training a preset signal recognition model to obtain an optimized signal recognition model; S347, using the optimized signal recognition model, processing the reconstructed signal to be processed to obtain a signal processing result.

2. A signal processing device based on a heterogeneous computing platform, characterized in that: The device comprises: A function division module is used to divide the functions of the signal processing digital prototype to obtain an atomic module set; the atomic module set includes N atomic modules, where N is a positive integer; The signal processing digital prototype building module is used to process the atomic module set to obtain an optimized signal processing digital prototype, including: S21, generating an algorithm integration template of any atomic module according to the function of the atomic module, and obtaining algorithm integration templates of N atomic modules; The algorithm integration template includes algorithm codes adapted to run on different processing devices; S22, obtaining signal processing requirement information; S23, acquiring K atomic modules from the atomic module set according to the signal processing requirement information, where K is a positive integer; S24, performing dual directed acyclic graph assembly on the K atomic modules to obtain an optimized signal processing digital prototype; The signal processing module is used to perform signal processing using the main processing device, the slave processing device, the external device and the optimized signal processing digital prototype to obtain a signal processing result, including: S31, using the main processing device to generate a signal description word; the signal description word includes an inter-pulse carrier frequency component, an inter-pulse amplitude component and a frequency modulation slope; The main processing devices include X86 / AMD64 architecture processing devices, ARM architecture processing devices, LongArch architecture processing devices, RISC-V architecture processing devices and artificial intelligence processing devices; S32, using the slave processing device to process the signal description word to obtain a reconstructed signal, and sending the reconstructed signal to the master processing device, including: S321, using a slave processing device to process the signal description word to obtain a synthesized signal; The synthetic signal is: Where p(t) is the synthetic signal, f i is the pulse-to-pulse carrier frequency component of the radiation signal description word within the i-th step, A i is the pulse-to-pulse amplitude component of the radiation signal description word within the i-th step, r i The frequency modulation slope of the radiation signal description word within the i-th step, t represents time; S322, using a reconstruction model, processing the synthesized signal to obtain a reconstructed signal; The reconstruction model expression is: s(t)=p(t)x(t) Where s(t) is the reconstructed signal and p(t) is the synthesized signal. rect() represents the rectangular function, δ(t) is the unit impulse signal, T s is the preset sampling period, T p is the time length of each step, and t is the time variable; The slave processing devices include graphics processor devices, general purpose computing graphics processor devices, neural network processor devices, digital signal processor devices, field programmable array devices, and co-processing units; S33, the main processing device sends the reconstructed signal to the optimized signal processing digital prototype; S34, using the optimized signal processing digital prototype to process the reconstructed signal to obtain a signal processing result, and displaying the signal processing result on the external device, including: S341, segmenting the reconstructed signal to obtain a first reconstructed signal, a second reconstructed signal and a third reconstructed signal; S342, extracting features from the first reconstructed signal to obtain first feature information, including: Using a first feature extraction model, processing the first reconstructed signal to obtain first feature information; The first feature extraction model expression is: Wherein, C1(i,j) is the first characteristic information, i=1,2,…,M, j=1,2,…,M, x1(n) is the first reconstructed signal, and M is the length of the first reconstructed signal; S343, performing feature extraction on the second reconstructed signal to obtain second feature information; S344, performing feature extraction on the third reconstructed signal to obtain third feature information; S345, fusing the first feature information, the second feature information, and the third feature information to obtain fused feature information, including: S3451, using an information synthesis model, fusing the first feature information, the second feature information, and the third feature information to obtain comprehensive feature information; The information integration model expression is: Where C(i,j) is the comprehensive feature information, i = 1, 2, ..., M, j = 1, 2, ..., M, C i (i,j) is the i-th feature information; S3452, using a spectral decomposition model, processing the comprehensive feature information to obtain fused feature information; The spectrum decomposition model expression is: Where F(u,v) is the fusion feature information, u,v are frequency variables, H(i,j) is the preset two-dimensional lag function, and M is the length of the reconstructed signal; S346, using the fused feature information, training a preset signal recognition model to obtain an optimized signal recognition model; S347, using the optimized signal recognition model, processing the reconstructed signal to be processed to obtain a signal processing result.

3. A signal processing device based on a heterogeneous computing platform, characterized in that: The device comprises: A memory storing executable program code; a processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the signal processing method based on a heterogeneous computing platform as described in claim 1.

4. A computer storable medium, characterized in that: The computer storable medium stores computer instructions, and when the computer instructions are called, they are used to execute the signal processing method based on a heterogeneous computing platform as claimed in claim 1.

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