Nanometer quantum cellular automaton circuit with programmable clock and design method thereof

Abstract

The invention discloses a nanometer quantum cellular automaton circuit with a programmable clock and a design method of the nanometer quantum cellular automaton circuit, and relates to the field of nanometer quantum cellular automaton circuit design. The device comprises a clock signal source, and a programmable clock generation circuit layer, a quantum cellular automaton cellular layer and a metal sheet layer which are sequentially arranged from bottom to top, the clock signal source serves as an external clock signal source of a programmable clock of the quantum cellular automaton circuit, the clock signal source is used for transmitting special clock signals and four paths of common clock signals, and the special clock signals comprise one kind of polarized clock signals and five kinds of cross clock signals. According to the invention, the problem that signal interference occurs when a coplanar cross module of a quantum cellular automaton circuit transmits signals in an existing clock layout scheme can be effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of nanometer quantum cellular automaton circuit design, and in particular to a nanometer quantum cellular automaton circuit with a programmable clock and a design method thereof. Technical Background

[0002] Since 2003, the clock frequency of commercial computers has been limited to 3-4GHz due to the power consumption of chips. Moreover, the high energy consumption of chips has also led to an increasing proportion of electricity consumed in the information and computing fields in global electricity consumption, accounting for about 10% in 2010 and expected to be as high as 30-50% in 2030. Therefore, high power consumption has become one of the key factors restricting the development of integrated circuits. Therefore, how to improve the computing energy efficiency of integrated circuits and reduce energy consumption at the same time is a key topic in academia and industry. With the gradual development of integrated circuits, researchers have gradually begun to pay attention to new devices. For example, among the nano devices listed in the 2021 International Device and System Roadmap, quantum cellular automaton devices are considered to be the next generation of logic computing devices with good development potential due to their high integration, fast computing speed and low power consumption. Among them, the clock signal is the basis for the realization of the circuit logic of quantum cellular automaton devices, and for quantum cellular automata, the clock scheme is essentially the distribution of circuit clocks within the cell layer. At present, the existing clock scheme is inefficient in quantum cellular automaton circuit design. The fundamental reason is that the clock area of ​​the quantum cellular automaton circuit is defined before the circuit design, which requires the arrangement characteristics of the clock area of ​​the clock scheme to be fully matched during circuit design. To this end, the present application provides a nano quantum cellular automaton circuit with a programmable clock and a design method thereof. Summary of the invention

[0003] In view of the defects and shortcomings in the above-mentioned prior art, the present application proposes a nano quantum cellular automaton circuit with a programmable clock and a design method thereof.

[0004] In order to achieve the above-mentioned purpose, the present invention adopts the following technical scheme:

[0005] A nanometer quantum cellular automaton circuit with a programmable clock comprises a clock signal source and a programmable clock generation circuit layer, a quantum cellular automaton cell layer and a metal sheet layer arranged in sequence from bottom to top; the clock signal source can generate a special clock signal and four common clock signals, the special clock signal comprises a polarization clock signal and five cross clock signals, wherein the five cross clock signals comprise four cooperative signals and one time slot signal; the quantum cellular automaton cell layer is divided into n 2 signal area, n 2 The signal areas are arranged in n rows and n columns; the programmable clock generation circuit layer includes n groups of clock signal lines, five types of clock metal lines, n2 Programmable connection circuit modules and n 2 metal plates, n is a natural number; a metal plate is correspondingly arranged below each signal area of ​​the quantum cellular automaton cell layer, a programmable connection circuit module is connected below each metal plate, each column of programmable connection circuit modules is connected to a group of clock signal lines, and the above n groups of clock signal lines are arranged in parallel from left to right below the n columns of metal plates; each group of clock signal lines includes five clock signal lines, and the five clock signal lines correspond to five clock metal lines respectively, and the five clock signal lines are connected to the clock signal source through the five clock metal lines. In the present application, the metal plate is connected to the programmable connection circuit module, so that the present application can control the polarization behavior of the cells in the quantum cellular automaton cell layer by controlling the different electric fields formed between the metal plate and the upper metal sheet layer through the programmable connection circuit module, and the quantum cellular automaton cell layer is divided into different clock areas according to the different electric fields.

[0006] Preferably, the five clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line and a special clock signal line, and the five clock metal lines include a first clock metal line, a second clock metal line, a third clock metal line, a fourth clock metal line and a special clock metal line; all the first clock signal lines are connected to the first clock metal line, all the second clock signal lines are connected to the second clock metal line, all the third clock signal lines are connected to the third clock metal line, all the fourth clock signal lines are connected to the fourth clock metal line, all the special clock signal lines are connected to the special clock metal line, and the five clock metal lines are connected to the clock signal source. In the present application, the first clock metal line is connected to the clock signal source for transmitting the first clock signal, the second clock metal line is connected to the clock signal source for transmitting the second clock signal, the third clock metal line is connected to the clock signal source for transmitting the third clock signal, the fourth clock metal line is connected to the clock signal source for transmitting the fourth clock signal, and the special clock metal line is connected to the clock signal source for transmitting a polarized clock signal and five cross clock signals, wherein the five cross clock signals include four collaborative signals and one time slot signal.

[0007] Preferably, the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line and the special clock signal line in each group of clock signal lines are arranged from left to right in a step-by-step manner away from the metal plate; the surface of each clock signal line is coated with an insulating layer; the size of any programmable connection circuit module is smaller than its corresponding signal area, and the width between the first clock signal line and the special clock signal line is smaller than the width of the signal area.

[0008] Preferably, the length and width of each signal region in the quantum cellular automaton cell layer are the same, and the size is L×L.

[0009] Preferably, the polarization clock signal is used to achieve fixed polarization of the cell; in a quantum cell state cycle, the Hold state time is relatively long, and the polarization clock signal can use the clock signal of the Hold state to lock the electrons in the cell in a fixed position for a long time, so that the polarization state of the cell is fixed to 1 or 0.

[0010] Preferably, the cross clock signal can be used for coplanar cross module signal distribution, wherein the coplanar cross module refers to a quantum cellular automaton circuit structure in which signal propagation paths in the same plane intersect.

[0011] Preferably, the present application can set a corresponding cell layout in each signal area of ​​the quantum cellular automaton cell layer according to the layout of the designed quantum cellular automaton circuit, and use the corresponding cell layout in each signal area of ​​the quantum cellular automaton cell layer to control the formation of different electric fields between the metal plate and the upper metal sheet layer through the programmable connection circuit module, so as to provide n cells in the quantum cellular automaton cell layer with a certain number of cells. 2 Five clock areas are correspondingly allocated to each signal area; the five clock areas include a first clock area, a second clock area, a third clock area, a fourth clock area and a special clock area; wherein the first clock area is a signal area for allocating a first clock signal, the second clock area is a signal area for allocating a second clock signal, the third clock area is a signal area for allocating a third clock signal, the fourth clock area is a signal area for allocating a fourth clock signal, and the special clock area is a signal area for allocating a special clock signal.

[0012] A design method for a nanometer quantum cellular automaton circuit with a programmable clock comprises the following steps:

[0013] S1, setting five clock metal wires, namely a first clock metal wire, a second clock metal wire, a third clock metal wire, a fourth clock metal wire and a special clock metal wire, and all the five clock metal wires are coated with an insulating layer;

[0014] S2, setting five clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line and a special clock signal line; the five clock signal lines are grouped into a clock signal line in the order of the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line and the special clock signal line, and n groups of clock signal lines are arranged in parallel;

[0015] S3, setting a clock signal source including five clock signals, so that it can send out a special clock signal and four common clock signals, wherein the special clock signal includes a polarization clock signal and five cross clock signals, and the five cross clock signals include four coordination signals and one time slot signal;

[0016] S4, connecting the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line and the special clock signal line to the clock signal source through five clock metal lines respectively;

[0017] S5, n 2 The programmable connection circuit modules are arranged in the form of n rows and n columns, and then a column of programmable connection circuit modules is connected to a group of clock signal lines, and then n 2 The metal plates are located at n 2 The bit lines of the programmable connection circuit modules are connected, n 2 The metal plates are respectively set on n 2 Above a programmable connection circuit module;

[0018] S6, in n 2 The upper part of the metal plate is provided with n 2 A quantum cellular automaton cell layer for each signal region;

[0019] S7. According to the layout of the designed quantum cellular automaton circuit, a corresponding cell layout is set in each signal region of the quantum cellular automaton cell layer;

[0020] S8, covering the quantum cellular automaton cell layer with a metal sheet layer, and controlling the formation of different electric fields between the metal plate and the upper metal sheet layer through a programmable connection circuit module, thereby providing n electric fields for the quantum cellular automaton cell layer. 2 Five clock regions are correspondingly allocated to each signal region to obtain a quantum cellular automaton circuit; wherein the five clock regions include a first clock region, a second clock region, a third clock region, a fourth clock region and a special clock region; wherein the first clock region is a signal region for allocating a first clock signal, the second clock region is a signal region for allocating a second clock signal, the third clock region is a signal region for allocating a third clock signal, the fourth clock region is a signal region for allocating a fourth clock signal, and the special clock region is a signal region for allocating a special clock signal.

[0021] Preferably, in step S2, n groups of clock signal lines are arranged in parallel from left to right, and five clock signal lines in a group of clock signal lines are arranged in parallel and arranged from left to right in the order of a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line and a special clock signal line in a step-by-step manner away from the metal plate; the size of any programmable connection circuit module is smaller than its corresponding signal area, and the width between the first clock signal line and the special clock signal line is smaller than the width of the signal area.

[0022] Preferably, in step S4, the first clock metal line is connected to the clock signal source for transmitting the first clock signal, and the first clock metal line is also connected to all the first clock signal lines; the second clock metal line is connected to the clock signal source for transmitting the second clock signal, and the second clock metal line is also connected to all the second clock signal lines; the third clock metal line is connected to the clock signal source for transmitting the third clock signal, and the third clock metal line is also connected to all the third clock signal lines; the fourth clock metal line is connected to the clock signal source for transmitting the fourth clock signal, and the fourth clock metal line is also connected to all the fourth clock signal lines; the special clock metal line is connected to the clock signal source for transmitting the special clock signal, and the special clock metal line is also connected to all the special clock signal lines.

[0023] Preferably, in step S6, the length and width of each signal area are the same, and the size is L×L.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present application provides a nano quantum cellular automaton circuit with a programmable clock and a design method thereof, which can customize the clock area arrangement that matches it through a programmable connection circuit module according to the actual needs of the circuit design, thereby improving the flexibility and efficiency of the circuit design. Specifically, the present application can allocate the clock signal types of different clock areas in the quantum cellular automaton cell layer through a programmable clock generation circuit according to the actual needs of the circuit design. In other words, the programmable clock generation circuit described in the present application can be used to flexibly build various nano quantum cellular automaton circuits, such as combinational logic circuits and sequential logic circuits. Moreover, from the test results, the full adder circuit designed using the nano quantum cellular automaton circuit with a programmable clock described in the present application has achieved better test results in terms of the number of logic gates, the number of cells, the area, the delay, the cost, and the total power consumption.

[0026] In addition, when distributing signals to a quantum cellular automaton circuit structure in which signal propagation paths in the same plane have coplanar intersections, the present application can also use the clock extension area to adjust the phase difference between the main signal to be multiplexed and the secondary signal to be multiplexed to ensure that the transmission of the main signal to be multiplexed and the secondary signal to be multiplexed do not interfere with each other, and use the clock adjustment area to adjust and shorten the transmission phase difference of the two signals to ensure the clock synchronization of the output signal. The present application can effectively solve the problem that clock signal distribution is affected when there is a coplanar intersection in the clock signal propagation path in the existing clock layout scheme; therefore, compared with the traditional clock layout scheme, the programmable clock described in the present application can not only effectively improve the utilization rate of the signal area of ​​the quantum cellular automaton cell layer, but also effectively reduce the design difficulty of the feedback path, while reducing the complexity of automatic layout and wiring, providing greater design freedom and flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure of a quantum cellular automaton circuit with a programmable clock according to the present invention;

[0028] Figure 2 This is a relationship diagram of four common clocks of the present invention;

[0029] Figure 3 A schematic diagram of a polarized clock signal and a cross-clock signal emitted by a clock signal source;

[0030] Figure 4 This is a schematic diagram of the arrangement of the clock metal wires of the present invention;

[0031] Figure 5 A schematic diagram of connection between any set of clock signal lines and a programmable connection circuit module;

[0032] Figure 6 The clock signal distribution of different clock regions of a nano quantum cellular automaton circuit with a programmable clock and a coplanar crossbar module;

[0033] Figure 7 A digital logic diagram, a logic decomposition diagram and a clock distribution diagram of a quantum cellular automaton circuit in a full adder based on the quantum cellular automaton circuit with a programmable clock according to the present invention;

[0034] Figure 8 This is the layout of the full adder; Fig. 9 This is the simulation result of the full adder. DETAILED DESCRIPTION

[0035] A nano quantum cellular automaton circuit with a programmable clock, such as Figure 1As shown, it includes a clock signal source and a programmable clock generation circuit layer, a quantum cellular automaton cell layer and a metal sheet layer arranged in sequence from bottom to top; wherein the quantum cellular automaton cell layer is divided into n 2 signal area, n 2 The signal areas are distributed in n rows and n columns, and the length and width of each signal area are the same, and the size is L×L, such as Figure 4 As shown, Figure 4 In the figure, each small square area indicated by a black solid line is a signal area; the programmable clock generation circuit layer includes n groups of clock signal lines, five types of clock metal lines, n 2 Programmable connection circuit modules and n 2 metal plates, n is a natural number; a metal plate is correspondingly arranged below each signal region of the quantum cellular automaton cell layer, a programmable connection circuit module is connected below each metal plate, the programmable connection circuit module is arranged in a vertical direction, and the metal plate is connected to the bit line of the programmable connection circuit module, each column of programmable connection circuit modules is connected to a group of clock signal lines, the above-mentioned n groups of clock signal lines are arranged in parallel from left to right below the n columns of metal plates, and the connection mode between each programmable connection circuit module and a group of clock signal lines is as follows Figure 5 As shown; the five clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line and a special clock signal line, and the five clock metal lines include a first clock metal line, a second clock metal line, a third clock metal line, a fourth clock metal line and a special clock metal line;

[0036] The structure of the programmable connection circuit module used in this application is as follows: Figure 5 As shown, the programmable connection circuit module described in the present application is obtained by connecting five programmable units together, and the programmable unit is a prior art, which is different from the one disclosed in "A16-kb Antifuse One-Time-Programmable Memory in 5-nm High-K Metal-Gate FinFETCMOS Featuring Bootstrap High-Voltage Scheme, Read Endpoint Detection, and Pseudodifferential Sensing". Figure 2 The circuit structure is the same as that shown in the pink rectangle in the upper left corner;

[0037] In the present application, the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line and the special clock signal line in each group of clock signal lines are arranged from left to right in a step-by-step manner away from the metal plate, and the surface of each clock signal line is coated with an insulating layer; the size of any programmable connection circuit module is smaller than its corresponding signal area, and the width between the first clock signal line and the special clock signal line is smaller than the width of the signal area;

[0038] In the present application, a first clock metal line is connected to all first clock signal lines, and the first clock metal line is also connected to a clock signal source for transmitting a first clock signal; a second clock metal line is connected to all second clock signal lines, and the second clock metal line is also connected to a clock signal source for transmitting a second clock signal; a third clock metal line is connected to all third clock signal lines, and the third clock metal line is also connected to a clock signal source for transmitting a third clock signal; a fourth clock metal line is connected to all fourth clock signal lines, and the fourth clock metal line is also connected to a clock signal source for transmitting a fourth clock signal; a special clock metal line is connected to all special clock signal lines, and the special clock metal line is also connected to a clock signal source for transmitting a polarized clock signal and five cross clock signals, wherein the polarized clock signal is such as Figure 3 As shown in Figure (a), the five cross-clock signals include four cooperative signals and one time slot signal. Figure 3 As shown in the middle figure (b).

[0039] In the present application, the clock signal source serves as an external clock signal source for a quantum cellular automaton circuit with a programmable clock. The clock signal source in the present application uses a signal generator from Keysight Technologies as the clock signal source. The present application adjusts parameters such as frequency, amplitude, bias and phase by adjusting the knob of the signal generator. At the same time, the arbitrary waveform function of the signal generator can also be used to enable the clock signal source used in the present application to transmit a special clock signal and four ordinary clock signals. The special clock signal includes a polarization clock signal and five cross clock signals. Taking the arbitrary waveform function of the signal generator as an example, first select the "arbitrary waveform" mode, enter the editing interface, and draw a trapezoidal waveform in the waveform editor; then, you can use graphic tools to design the rise time, hold time, fall time and period, and then save the created waveform and load it into the signal generator for output.

[0040] In the present application, the four common clock signals are four existing common clock signals commonly used in quantum cellular automata, each consisting of a sinusoidal pulse signal with a phase difference of 90°, and are used for signal shaping and signal synchronization in quantum cellular automata circuits; Figure 2As shown, the four common clock signals in the present application correspond to the four states of the quantum cell, which are Switch, Hold, Release and Relax. The state of the quantum cell is controlled by the clock signal, and the state of the quantum cell is sequentially changed in the order of Switch, Hold, Release and Relax, and each common clock signal also cyclically jumps in the four states of Switch, Hold, Release and Relax. For example, when the signal change state of the first clock signal is Switch, Hold, Release, Relax, Switch, Hold..., the signal change state of the second clock signal is Hold, Release, Relax, Switch, Hold, Release..., the signal change state of the third clock signal is Release, Relax, Switch, Hold, Release, Relax..., and the signal change state of the fourth clock signal is Relax, Switch, Hold, Release, Relax, Switch...;

[0041] In the present application, the polarization clock signal is used to realize the fixed polarization of the cell. Specifically, in a quantum cell state cycle, the Hold state time is relatively long. The polarization clock signal can use the clock signal of the Hold state to lock the electrons in the cell in a fixed position for a long time, so that the polarization state of the cell is fixed to 1 or 0.

[0042] The cross clock signal is used to distribute signals to the coplanar cross modules in the quantum cellular automaton circuit, wherein the coplanar cross modules refer to modules in the quantum cellular automaton circuit structure where the signal propagation paths in the same plane have coplanar crosses.

[0043] The present application can set a corresponding cell layout in each signal area of ​​the quantum cellular automaton cell layer according to the layout of the designed quantum cellular automaton circuit, and control the formation of different electric fields between the metal plate and the upper metal sheet layer through a programmable connection circuit module, so as to provide a signal for n cells in the quantum cellular automaton cell layer. 2 Five clock areas are correspondingly allocated to each signal area; the five clock areas include a first clock area, a second clock area, a third clock area, a fourth clock area and a special clock area; wherein the first clock area is a signal area for allocating a first clock signal, the second clock area is a signal area for allocating a second clock signal, the third clock area is a signal area for allocating a third clock signal, the fourth clock area is a signal area for allocating a fourth clock signal, and the special clock area is a signal area for allocating a special clock signal.

[0044] This application is Figure 6 As an example, when two input signals are transmitted to the coplanar cross module of the quantum cellular automaton circuit, the changes of the clock signals in each clock area in the coplanar cross module are introduced, wherein the clock areas where the input signals are located in the coplanar cross module of the quantum cellular automaton circuit are defined as the first clock area 1 and the second clock area 2; the overlapping clock area of ​​the two transmission paths in the coplanar cross module is defined as the clock multiplexing area 3; the clock area connecting the clock multiplexing area and the input signal is defined as the clock extension area. In this application, there are two clock extension areas, one of which is as follows Figure 6 As shown in area 2 in (a) of the figure, it is called the first clock extension area 2, and the other clock extension area is shown in area 7 in (a) of the figure in 6, which is called the second clock extension area 7; in this application, the clock extension area is used to adjust the phase difference of the two signals to ensure that the transmission of the main to-be-multiplexed signal is not affected by the secondary to-be-multiplexed signal; the area connecting the clock multiplexing area and the clock area where the output signal is located is defined as the clock adjustment area. In this application, the clock adjustment area includes two, one of which is as shown in Figure 6 As shown in the area 8 in the figure (a), it is called the first clock adjustment area 8, and the other clock adjustment area is as follows Figure 6 As shown in area 4 in the figure (a), it is called the second clock adjustment area 4; in the present application, the clock adjustment area is used to adjust and shorten the transmission phase difference of the two signals to ensure the clock synchronization of the output signal; the clock signal in the clock multiplexing area is defined as a time slot signal, and the clock signals in the clock extension area and the clock adjustment area are defined as cooperative signals; the two input signals are defined as the main to-be-multiplexed signal and the secondary to-be-multiplexed signal, respectively, wherein the main to-be-multiplexed signal and the secondary to-be-multiplexed signal are two sinusoidal pulse signals with the same frequency and amplitude but different phases that need to be transmitted; in the present application, Figure 6 In the middle (a) figure, the special clock region includes two clock adjustment regions, two clock extension regions and one clock multiplexing region;

[0045] from Figure 6 As can be seen from Figure (b), the present application can realize that the primary to-be-multiplexed signal and the secondary to-be-multiplexed signal can be transmitted from the cells in the clock region 1 to the cells in the clock region 5 and from the cells in the clock region 6 to the cells in the clock region 9 without interfering with each other, effectively solving the problem of coplanar cross-module interference signal transmission that is difficult to solve in conventional clock schemes. The present application uses the clock extension area to adjust the phase difference between the primary to-be-multiplexed signal and the secondary to-be-multiplexed signal to ensure that the transmission of the primary to-be-multiplexed signal and the secondary to-be-multiplexed signal does not interfere with each other, and the clock adjustment area is used to adjust and shorten the transmission phase difference of the two signals to ensure the clock synchronization of the output signal; specifically:

[0046] from Figure 6 As shown in Figure (a), the main multiplexed signal is input to the first clock region 1, and the secondary multiplexed signal is input to the second clock region 6. When the main multiplexed signal and the secondary multiplexed signal are transmitted to the coplanar cross module, the changes of the clock signals in the coplanar cross module are as follows: Figure 6 As shown in Figure (b); Figure 6 As shown in Figure (b), when the cells in the first clock region 1 are in the Hold state, they transmit signals to the cells in the first clock extension region 2 in the Switch state; after receiving the signals, the cells in the first clock extension region 2 enter the Hold stage, affecting the cells in the adjacent clock multiplexing region 3 in the Switch stage; then, the cells in the clock multiplexing region 3 transmit the signals to the cells in the first clock adjustment region 4, and the cells in the first clock adjustment region 4 transmit the signals to the cells in the third clock region. Since the Hold stages of the cells in the first clock region 1 and the second clock region 6 differ by a quarter of a cycle, and the Switch stages of the cells in the second clock extension region 7 and the first clock extension region 2 in the same cycle are also in different time periods, when the cells in the second clock region 6 transmit the secondary waiting multiplexing signal to the clock multiplexing region 3, they will be 1 / 2 cycle later than the cells in the first clock region 1 transmit the primary waiting multiplexing signal to the cells in the clock multiplexing region 3. The difference between the main multiplexed signal after being transmitted from the cells of the first clock adjustment area 4 to the cells of the third clock area 5 and the secondary multiplexed signal after being transmitted from the cells of the second clock adjustment area 8 to the cells of the fourth clock area 9 is only 1 / 4 cycle. In addition, when the cells in the first clock extension area 2 transmit signals to the cells in the clock multiplexing area 3, the cells in the second clock extension area 7 and the second clock adjustment area 8 are in the Relax stage, which will not affect the polarization state of the cells in the clock multiplexing area 3; when the cells in the second clock extension area 7 transmit polarized signals to the cells in the clock multiplexing area 3, the cells in the first clock extension area 2 and the first clock adjustment area 4 are in the Relax stage, which will not affect the polarization state of the cells in the clock multiplexing area 3; the cells in the clock multiplexing area 3 transmit polarized signals to the cells in the second clock adjustment area 8. When the inner cells transmit signals, the cells in the clock extension area 2 and the first clock adjustment area 4 are in the Relax stage, which will not affect the polarization state of the cells in the second clock adjustment area 8; when the cells in the clock multiplexing area 3 transmit signals to the cells in the first clock adjustment area 4, the cells in the second clock extension area 7 and the second clock adjustment area 8 are in the Relax stage, which will not affect the polarization state of the cells in the first clock adjustment area 4; therefore, the present application ensures that the main signal to be multiplexed and the secondary signal to be multiplexed are transmitted without interfering with each other in the coplanar cross module of the quantum cellular automaton circuit.

[0047] A design method for a nanometer quantum cellular automaton circuit with a programmable clock comprises the following steps:

[0048] S1, setting five clock metal wires, namely a first clock metal wire, a second clock metal wire, a third clock metal wire, a fourth clock metal wire and a special clock metal wire, and all the five clock metal wires are coated with an insulating layer;

[0049] S2. Set five clock signal lines as the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line and the special clock signal line; group the above five clock signal lines into a group of clock signal lines in the order of the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line and the special clock signal line; set four groups of clock signal lines in parallel, and the four groups of clock signal lines are arranged in parallel from left to right, and five clock signal lines in a group of clock signal lines are arranged in parallel and away from the metal plate step by step from left to right in the order of the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line and the special clock signal line, the size of any programmable connection circuit module is smaller than its corresponding signal area, and the width between the first clock signal line and the special clock signal line is smaller than the width of the signal area;

[0050] S3, setting a clock signal source including five clock signals, so that it can send out a special clock signal and four common clock signals, wherein the special clock signal includes a polarization clock signal and five cross clock signals, wherein the five cross clock signals include four coordination signals and one time slot signal;

[0051] S4, connecting five clock metal lines to the clock signal source respectively, wherein the first clock metal line is connected to the clock signal source for transmitting the first clock signal, and the first clock metal line is also connected to all the first clock signal lines; the second clock metal line is connected to the clock signal source for transmitting the second clock signal, and the second clock metal line is also connected to all the second clock signal lines; the third clock metal line is connected to the clock signal source for transmitting the third clock signal, and the third clock metal line is also connected to all the third clock signal lines; the fourth clock metal line is connected to the clock signal source for transmitting the fourth clock signal, and the fourth clock metal line is also connected to all the fourth clock signal lines; the special clock metal line is connected to the clock signal source for transmitting the special clock signal, and the special clock metal line is also connected to all the special clock signal lines;

[0052] S5, n 2 The programmable connection circuit modules are arranged in the form of n rows and n columns, and then a column of programmable connection circuit modules is connected to a group of clock signal lines, and then n 2 The metal plates are located at n2 The bit lines of the programmable connection circuit modules are connected, n 2 The metal plates are respectively set on n 2 Above a programmable connection circuit module;

[0053] S6, in n 2 The upper part of the metal plate is provided with n 2 A quantum cellular automaton cell layer for each signal region;

[0054] S7. According to the layout of the designed quantum cellular automaton circuit, a corresponding cell layout is set in each signal region of the quantum cellular automaton cell layer;

[0055] S8, covering the quantum cellular automaton cell layer with a metal sheet layer, and controlling the formation of different electric fields between the metal plate and the upper metal sheet layer through a programmable connection circuit module, thereby providing n electric fields for the quantum cellular automaton cell layer. 2 Five clock regions are correspondingly allocated to each signal region to obtain a quantum cellular automaton circuit; wherein the five clock regions include a first clock region, a second clock region, a third clock region, a fourth clock region and a special clock region; the first clock region is a signal region for allocating a first clock signal, the second clock region is a signal region for allocating a second clock signal, the third clock region is a signal region for allocating a third clock signal, the fourth clock region is a signal region for allocating a fourth clock signal, and the special clock region is a signal region for allocating a special clock signal.

[0056] Applications of Quantum Cellular Automata Circuits with Programmable Clocks:

[0057] According to the designed digital circuit logic, the various logic gates and their connection relationships in the digital circuit structure are decomposed into n quantum cellular automaton cell layers. 2 In each signal area, a circuit layout corresponding to the digital circuit logic is designed according to logic gates and their connection relationships (i.e., line logic), and a suitable clock is allocated to the signal area to form a circuit layout corresponding to the digital circuit logic, wherein ordinary clock signals are used for ordinary logic units in the circuit layout corresponding to the digital circuit logic, polarized clock signals are used for cells that need to be fixedly polarized in the circuit layout corresponding to the digital circuit logic, and the polarized clock signals utilize a clock signal with a long Hold phase to lock the electrons in the cells in a fixed position for a long time without affecting the cells in the required clock area, and cross clock signals are used for coplanar cross modules in the circuit layout corresponding to the digital circuit logic, so as to effectively solve the problem of coplanar cross modules interfering with signal transmission, which is difficult to solve with conventional clock schemes.

[0058] A full adder using the nano quantum cellular automaton circuit design with a programmable clock according to the present invention, such as Figure 7 , Figure 8 and Fig. 9 As shown; Figure 7 In the figure, (a) shows the digital logic schematic diagram of the full adder, and the digital logic relationship shown in (a) is: Sum = A⊕B⊕Cin, Cout = (A∧B)∨(Cin∧(A⊕B)), where the symbol ⊕ represents an XOR operation, the symbol ∧ represents an AND operation, and the symbol ∨ represents an OR operation; (b) shows the clock region allocated to the quantum cellular automaton cell layer corresponding to the digital logic of the full adder, and (c) shows the clock signal allocation result of the clock region allocated to the quantum cellular automaton cell layer corresponding to the digital logic of the full adder; Figure 8 Represents the layout of a full adder, Fig. 9 This is the simulation result of the full adder.

[0059] In this application, the digital logic of the full adder is decomposed into n quantum cellular automata cell layers. 2 The quantum cellular automaton cell layer is then designed according to the logic gates and the connection relationship between the logic gates, and the clock area corresponding to the digital logic relationship is allocated to form a full adder. Figure 7 (b) is the clock signal distribution result in each clock area of ​​the quantum cellular automation circuit.

[0060] Table 1 shows the test performance of the full adder designed based on nano-quantum cellular automata with different clock schemes in terms of the number of logic gates, the number of cells, the occupied area A, the delay time L, the cost Cost and the overall energy consumption. Among them, the 2DD clock scheme in Table 1 comes from "Two-Dimensional Schemes for Clocking / Timing of QCA Circuits", the pulse clock scheme comes from "Ripple clock schemes for quantum-dot cellular automata circuits", the USE clock scheme comes from "USE: AUniversal, Scalable, and Efficient Clocking Scheme for QCA", the two-dimensional clock optimization scheme comes from "An optimized clocking scheme for nanoscale quantum-dot cellular automata circuit", the RES clock scheme comes from "An efficient clocking scheme for quantum-dot cellular Automata", and the GE clock scheme comes from "A general and efficient clocking scheme for majority logic in quantum-dot cellular automata". The structure described in the present invention refers to the nano-quantum cellular automata circuit with programmable clock described in the present invention;

[0061] Table 1 Test results of full adders designed based on nano quantum cellular automata with different clock schemes in terms of number of logic gates, number of cells, area, delay, cost, and total power consumption

[0062]

[0063] It can be seen from Table 1 that the full adder obtained by using the nanometer quantum cellular automaton circuit with programmable clock of the present invention consumes less logic gates, number of cells, area A, delay L, cost Cost and total power consumption. Specifically, the full adder obtained by using the nanometer quantum cellular automaton circuit with programmable clock of the present invention uses 71 cells and occupies an area of ​​0.13 μm 2 , delay is 0.75 cycles, cost is 0.07μm 2 ×(ps) 2 , the total power consumption is 2.55×10 -2eV. From the test results of the six full adders designed based on nano quantum cellular automata with different clock schemes recorded in Table 1 in terms of the number of logic gates, the number of cells, the area, delay, cost and total power consumption, the full adder designed based on the nano quantum cellular automata with GE-type clock scheme has better test results in terms of the number of logic gates, the number of cells, the area, delay, cost and total power consumption. Therefore, this application focuses on comparing the test results of the full adder designed based on the nano quantum cellular automata with GE-type clock scheme and the test results of the full adder designed based on the nano quantum cellular automata with programmable clock described in this application. The comparison results are as follows: Compared with the full adder designed based on the nano quantum cellular automata with GE-type clock scheme, the full adder designed based on the nano quantum cellular automata with programmable clock described in this application has a 1.4% reduction in the number of cells, 18.8% savings in area A, 40.0% shortened delay, 65.0% reduction in cost, and 10.8% reduction in total power consumption.

Claims

1. A nanometer quantum cellular automaton circuit with a programmable clock, characterized in that: The invention comprises a clock signal source and a programmable clock generation circuit layer, a quantum cellular automaton cell layer and a metal sheet layer arranged in sequence from bottom to top; the clock signal source can generate a special clock signal and four common clock signals, the special clock signal includes a polarization clock signal and five cross clock signals; the quantum cellular automaton cell layer is divided into n 2 signal area, n 2 The signal areas are arranged in n rows and n columns; the programmable clock generation circuit layer includes n groups of clock signal lines, five types of clock metal lines, n 2 Programmable connection circuit modules and n 2 metal plates, n is a natural number; A metal plate is correspondingly arranged below each signal area of ​​the quantum cellular automaton cell layer, a programmable connection circuit module is connected below each metal plate, each column of programmable connection circuit modules is connected to a group of clock signal lines, and the above-mentioned n groups of clock signal lines are arranged in parallel from left to right below the n columns of metal plates; each group of clock signal lines includes five clock signal lines, the five clock signal lines correspond to five clock metal lines respectively, and the five clock signal lines are connected to the clock signal source through the five clock metal lines respectively.

2. The nanometer quantum cellular automaton circuit with a programmable clock according to claim 1, characterized in that: The five clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line and a special clock signal line, and the five clock metal lines include a first clock metal line, a second clock metal line, a third clock metal line, a fourth clock metal line and a special clock metal line; All first clock signal lines are connected to the first clock metal line, all second clock signal lines are connected to the second clock metal line, all third clock signal lines are connected to the third clock metal line, all fourth clock signal lines are connected to the fourth clock metal line, all special clock signal lines are connected to the special clock metal line, and all five clock metal lines are connected to the clock signal source. In the present application, the first clock metal line is connected to the clock signal source for transmitting the first clock signal, the second clock metal line is connected to the clock signal source for transmitting the second clock signal, the third clock metal line is connected to the clock signal source for transmitting the third clock signal, the fourth clock metal line is connected to the clock signal source for transmitting the fourth clock signal, and the special clock metal line is connected to the clock signal source for transmitting a polarized clock signal and five cross clock signals, and the five cross clock signals include four cooperative signals and one time slot signal.

3. The nanometer quantum cellular automaton circuit with a programmable clock according to claim 1, characterized in that: The first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line and the special clock signal line in each group of clock signal lines are arranged from left to right in a stepped manner and away from the metal plate; the surface of each clock signal line is coated with an insulating layer; the size of any programmable connection circuit module is smaller than its corresponding signal area, and the width between the first clock signal line and the special clock signal line is smaller than the width of the signal area.

4. The nanometer quantum cellular automaton circuit with a programmable clock according to claim 1, characterized in that: The length and width of each signal area in the quantum cellular automation cell layer are the same, and the size is L×L.

5. The nanometer quantum cellular automaton circuit with a programmable clock according to claim 2, characterized in that: The polarization clock signal is used to achieve fixed polarization of the cell; in a quantum cell state cycle, the Hold state time is relatively long, and the polarization clock signal can use the Hold state clock signal to lock the electrons in the cell in a fixed position for a long time, so that the polarization state of the cell is fixed to 1 or 0.

6. The nanometer quantum cellular automaton circuit with a programmable clock according to claim 2, characterized in that: The cross clock signal can be used to distribute signals in a coplanar cross module, wherein the coplanar cross module refers to a quantum cellular automaton circuit structure in which signal propagation paths in the same plane have coplanar crosses.

7. The nanometer quantum cellular automaton circuit with a programmable clock according to claim 1, characterized in that: According to the layout of the designed quantum cellular automaton circuit, a corresponding cell layout is set in each signal area of ​​the quantum cellular automaton cell layer, and the different electric fields are controlled between the metal plate and the upper metal sheet layer through the programmable connection circuit module, so as to generate different electric fields for the n cells in the quantum cellular automaton cell layer. 2 Five clock areas are correspondingly allocated to each signal area; the five clock areas include a first clock area, a second clock area, a third clock area, a fourth clock area and a special clock area; wherein the first clock area is a signal area for allocating a first clock signal, the second clock area is a signal area for allocating a second clock signal, the third clock area is a signal area for allocating a third clock signal, the fourth clock area is a signal area for allocating a fourth clock signal, and the special clock area is a signal area for allocating a special clock signal.

8. A design method for a nano quantum cellular automaton circuit with a programmable clock, characterized in that: The nanometer quantum cellular automaton circuit with a programmable clock is the nanometer quantum cellular automaton circuit with a programmable clock according to any one of claims 1 to 7. The design method of the nanometer quantum cellular automaton circuit with a programmable clock comprises the following steps: S1, setting five clock metal wires, namely a first clock metal wire, a second clock metal wire, a third clock metal wire, a fourth clock metal wire and a special clock metal wire, and all the five clock metal wires are coated with an insulating layer; S2, setting five clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line and a special clock signal line; the five clock signal lines are grouped into a clock signal line in the order of the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line and the special clock signal line, and n groups of clock signal lines are arranged in parallel; S3, setting a clock signal source including five clock signals, so that it can send out a special clock signal and four common clock signals, wherein the special clock signal includes a polarization clock signal and five cross clock signals, and the five cross clock signals include four coordination signals and one time slot signal; S4, connecting the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line and the special clock signal line to the clock signal source through five clock metal lines respectively; S5, n 2 The programmable connection circuit modules are arranged in the form of n rows and n columns, and then a column of programmable connection circuit modules is connected to a group of clock signal lines, and then n 2 The metal plates are respectively 2 The bit lines of the programmable connection circuit modules are connected, n 2 The metal plates are respectively set on n 2 Above a programmable connection circuit module; S6, in n 2 The upper part of the metal plate is provided with n 2 A quantum cellular automaton cell layer for each signal region; S7. According to the layout of the designed quantum cellular automaton circuit, a corresponding cell layout is set in each signal region of the quantum cellular automaton cell layer; S8, covering the quantum cellular automaton cell layer with a metal sheet layer, and controlling the formation of different electric fields between the metal plate and the upper metal sheet layer through a programmable connection circuit module, thereby providing n electric fields for the quantum cellular automaton cell layer. 2 Five clock regions are correspondingly allocated to each signal region to obtain a quantum cellular automaton circuit; wherein the five clock regions include a first clock region, a second clock region, a third clock region, a fourth clock region and a special clock region; the first clock region is a signal region for allocating a first clock signal, the second clock region is a signal region for allocating a second clock signal, the third clock region is a signal region for allocating a third clock signal, the fourth clock region is a signal region for allocating a fourth clock signal, and the special clock region is a signal region for allocating a special clock signal.

9. The design method of a nano quantum cellular automaton circuit with a programmable clock according to claim 7, characterized in that: In step S2, n groups of clock signal lines are arranged in parallel from left to right, and five clock signal lines in a group of clock signal lines are arranged in parallel and arranged from left to right in the order of a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line and a special clock signal line in a step-by-step manner away from the metal plate; the size of any programmable connection circuit module is smaller than its corresponding signal area, and the width between the first clock signal line and the special clock signal line is smaller than the width of the signal area.

10. The design method of a nano quantum cellular automaton circuit with a programmable clock according to claim 7, characterized in that: In step S4, the first clock metal line is connected to the clock signal source for transmitting the first clock signal, and the first clock metal line is also connected to all the first clock signal lines; the second clock metal line is connected to the clock signal source for transmitting the second clock signal, and the second clock metal line is also connected to all the second clock signal lines; the third clock metal line is connected to the clock signal source for transmitting the third clock signal, and the third clock metal line is also connected to all the third clock signal lines; the fourth clock metal line is connected to the clock signal source for transmitting the fourth clock signal, and the fourth clock metal line is also connected to all the fourth clock signal lines; The special clock metal line is connected to a clock signal source for transmitting a special clock signal, and the special clock metal line is also connected to all special clock signal lines.

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