Adaptive rate decoding method, system and device for power line host communication core

Abstract

The present invention relates to the technical field of power line setting, and more specifically, to an adaptive rate decoding method, system and device for a power line host communication core. The scheme includes performing online current starting point analysis based on high-precision ADC data; performing online current ending point analysis; storing effective current signals in a quantization data cache module based on current starting point and effective current ending point; counting effective sampling point lengths based on current ending sampling points; calculating average single BIT sampling points based on effective sampling point lengths; and performing comprehensive verification based on quantization data cache modules, average single BIT sampling points and effective sampling point lengths. The scheme provides an adaptive rate decoding method for a power line host communication core, which can adaptively solve current waveform distortion of different slaves, current waveform changes caused by different temperature drift clocks, and current waveforms of different rates, and also uses statistical average characteristics to filter interference of external electromagnetic environment on current signals.

Description

Technical Field

[0001] The present invention relates to the technical field, and more specifically, to an adaptive rate decoding method, system and device for a power line host communication core. Background Art

[0002] Power line technology is a technology that combines two power lines and two signal lines into two lines to achieve signal and power sharing. It saves construction and cable costs and brings great convenience to on-site construction and later maintenance. It has been widely used in fire protection, instrumentation, sensors, industrial control and other fields. It uses voltage pulse width modulation technology for downlink and current loop modulation technology for uplink.

[0003] Prior to the technology of the present invention, the prior art gradually developed towards intelligence, networking, and multifunctionality with the development of equipment terminals and overall solution products. It was required that a power line loop could communicate up to 1-3 kilometers, a power line loop could carry up to 256 slave devices, and a host chip could manage and control up to 8 power line loops. In this case, it was difficult for the prior art to simultaneously ensure communication stability and reliability. Due to the main reasons such as parasitic line resistance, line capacitance, line sense, and irregular construction of the power line, it is very easy to cause the upstream current signal to be distorted during the transmission process, which greatly affects the reliable reception of the current modulation signal of the upstream host device. In addition, the distances between the locations of different slave devices and the location of the host device are different, resulting in different degrees of distortion of the current waveform; different slave devices use low-cost internal clocks with large temperature drift chips, resulting in different widths of the effective current waveforms sent by different slaves, or becoming longer or shorter. These problems can easily lead to errors in the host decoding of the current waveform. Summary of the invention

[0004] In view of the above problems, the present invention proposes an adaptive rate decoding method, system and device for the power line host communication core, and provides an adaptive rate decoding method for the power line host communication core, which can adaptively solve the current waveform distortion of different slaves, the current waveform changes caused by different temperature drift clocks, and the current waveforms of different rates. In addition, the statistical averaging characteristics are used to filter out the interference of the external electromagnetic environment on the current signal.

[0005] According to a first aspect of an embodiment of the present invention, an adaptive rate decoding method for a power line host communication core is provided.

[0006] In one or more embodiments, preferably, the adaptive rate decoding method of the power line host communication core includes:

[0007] Perform online current starting point analysis based on high-precision ADC data;

[0008] Perform online current end point analysis based on high-precision ADC data;

[0009] Storing the effective current signal in the quantization data cache module according to the current starting point and the effective current ending point;

[0010] Count the effective sampling point length according to the current end sampling point;

[0011] Calculate the average single BIT sampling point based on the effective sampling point length;

[0012] A comprehensive check is performed based on the quantized data cache module, the average single BIT sampling point and the effective sampling point length.

[0013] In one or more embodiments, preferably, the online current starting point analysis based on the high-precision ADC data specifically includes:

[0014] The high-precision ADC data processed by the previous stage is sent to the receiving decoding module;

[0015] Searching for the starting sampling point of the effective current in the input ADC data processed by the previous stage;

[0016] When it is found that there are a continuous preset number of current digital signal values ​​that satisfy the first calculation formula, it is considered to be a valid current starting point, and the position of this sampling point is recorded;

[0017] The first calculation formula is:

[0018] L≥Y1

[0019] Wherein, L is a preset number of continuous current digital signal values, and Y1 is a preset background starting current threshold.

[0020] In one or more embodiments, preferably, the online current end point analysis based on the high-precision ADC data specifically includes:

[0021] When the effective current starting point is searched, the effective current end point search module also starts to process the ADC data in the input front stage;

[0022] When the valid current end point search module finds a certain number of continuous current digital signal values ​​satisfying the second calculation formula in the ADC data sequence stream, it is considered to be a valid current end point and the sampling point position is recorded;

[0023] The second calculation formula is:

[0024] L≥Y2

[0025] Among them, Y2 is the preset background end current threshold.

[0026] In one or more embodiments, preferably, storing the effective current signal in the quantization data cache module according to the current starting point and the effective current ending point specifically includes:

[0027] When the effective current starting point is found, the module for quantifying the effective current value starts;

[0028] The quantized effective current value module judges the input current value signal value according to the third calculation formula, and the value is 1 if it satisfies the third calculation formula, and 0 if it does not, and stores it in the quantized data cache module until the effective current end point is searched;

[0029] The third calculation formula is:

[0030] W>F

[0031] Wherein, W is the current digital signal value, and F is the 0 / 1 value dividing threshold.

[0032] In one or more embodiments, preferably, the counting of effective sampling point lengths according to the current end sampling point specifically includes:

[0033] Obtaining the current starting point and the current ending sampling point;

[0034] Calculate the effective sampling point length using the fourth calculation formula;

[0035] The fourth calculation formula is:

[0036] XL=(JS-QD)÷PL

[0037] Among them, XL is the effective sampling point length, JS is the current end sampling point, QD is the current starting point, and PL is the sampling frequency.

[0038] In one or more embodiments, preferably, the calculating the average single BIT sampling point according to the effective sampling point length specifically includes:

[0039] Counting the number of valid sampling points that satisfy a third calculation formula according to the current starting point and the current ending sampling point;

[0040] Get the preset number of bits;

[0041] The fifth calculation formula is used to calculate the average single BIT sampling point;

[0042] The fifth calculation formula is:

[0043] DB=YX÷YBIT

[0044] Among them, DB is the average single BIT sampling point, YX is the number of valid sampling points, and YBIT is the preset number of bits.

[0045] In one or more embodiments, preferably, the comprehensive verification based on the quantized data cache module, the average single BIT sampling point and the effective sampling point length specifically includes:

[0046] Quantify the storage content of the data cache module to count the number of 0s or 1s in each bit segment;

[0047] Determine the number of 1 / 0 in each bit segment and compare it with the preset 1 / 0 number threshold. When the number of 1 / 0 in each bit segment is greater than the preset 1 / 0 number threshold, it is recorded as 1, otherwise it is recorded as 0 and stored as the decoding output result;

[0048] The average single BIT sampling point, decoding output result and effective sampling point length are compared with the preset data. If they are consistent, it is considered that the verification has passed. Otherwise, it is considered that there is a problem and the verification cannot pass.

[0049] According to a second aspect of an embodiment of the present invention, an adaptive rate decoding system for a power line host communication core is provided.

[0050] In one or more embodiments, preferably, the adaptive rate decoding system of the power line host communication core includes:

[0051] Current starting point analysis module, used to perform online current starting point analysis based on high-precision ADC data;

[0052] Current end sampling point analysis module, used to perform online current end point analysis based on high-precision ADC data;

[0053] A quantized effective storage module, used for storing effective current signals into a quantized data cache module according to a current starting point and an effective current ending point;

[0054] An effective current calculation module is used to count the effective sampling point length according to the current end sampling point;

[0055] An average single BIT sampling point calculation module is used to calculate the average single BIT sampling point according to the effective sampling point length;

[0056] The comprehensive decoding output module is used to perform comprehensive verification according to the quantized data cache module, the average single BIT sampling point and the effective sampling point length.

[0057] According to a third aspect of an embodiment of the present invention, there is provided a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method as described in any one of the first aspect of the embodiment of the present invention is implemented.

[0058] According to a fourth aspect of an embodiment of the present invention, there is provided an electronic device, comprising a memory and a processor, wherein the memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement any one of the methods described in the first aspect of the embodiment of the present invention.

[0059] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:

[0060] In the scheme of the present invention, the starting point of the effective current signal is searched for with high reliability on the input pre-processing ADC data, and a certain number of current digital signals that continuously count and exceed the background current starting threshold are considered as the starting point, so as to reduce the probability of misjudging the starting point.

[0061] In the scheme of the present invention, the end point search of the effective current signal is performed on the ADC data processed by the input pre-stage with high reliability. The end point is considered to be the current digital signal when a certain number of current digital signals are continuously counted to be less than the background current end threshold, so as to reduce the probability of misjudging the end point. In addition, the total length of the actual effective current sampling points is counted at the same time.

[0062] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0063] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 It is a flow chart of an adaptive rate decoding method of a power line host communication core according to an embodiment of the present invention.

[0066] Figure 2 The present invention is a flowchart of an adaptive rate decoding method for a power line host communication core, which performs online current starting point analysis based on high-precision ADC data.

[0067] Figure 3 The present invention is a flowchart of an adaptive rate decoding method for a power line host communication core according to an embodiment of the present invention for performing online current end point analysis based on high-precision ADC data.

[0068] Figure 4 The present invention is a flowchart of storing effective current signals in a quantized data cache module according to a current starting point and an effective current ending point in an adaptive rate decoding method of a power line host communication core according to an embodiment of the present invention.

[0069] Figure 5 The present invention is a flowchart of counting effective sampling point lengths according to current end sampling points in an adaptive rate decoding method of a power line host communication core according to an embodiment of the present invention.

[0070] Figure 6 The present invention is a flowchart of calculating an average single BIT sampling point according to the effective sampling point length in an adaptive rate decoding method of a power line host communication core according to an embodiment of the present invention.

[0071] Figure 7 It is a flow chart of performing comprehensive verification according to the quantized data cache module, the average single BIT sampling point and the effective sampling point length in the adaptive rate decoding method of the power line host communication core of an embodiment of the present invention.

[0072] Figure 8 It is a structural diagram of an adaptive rate decoding system of a power line host communication core according to an embodiment of the present invention.

[0073] Fig. 9 It is a structural diagram of an electronic device in one embodiment of the present invention.

[0074] Fig.10 A power line communication system.

[0075] Fig.11 This is the structure diagram of the adaptive decoding circuit. DETAILED DESCRIPTION

[0076] In some of the processes described in the specification and claims of the present invention and the above-mentioned figures, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or executed in parallel. The serial numbers of the operations, such as 101, 102, etc., are only used to distinguish different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0077] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0078] Power line technology is a technology that combines two power lines and two signal lines into two lines to achieve signal and power sharing. It saves construction and cable costs and brings great convenience to on-site construction and later maintenance. It has been widely used in fire protection, instrumentation, sensors, industrial control and other fields. It uses voltage pulse width modulation technology for downlink and current loop modulation technology for uplink. Power line communication system such as Fig.10 shown.

[0079] Prior to the technology of the present invention, the prior art gradually developed towards intelligence, networking, and multifunctionality with the development of equipment terminals and overall solution products. It was required that a power line loop could communicate up to 1-3 kilometers, a power line loop could carry up to 256 slave devices, and a host chip could manage and control up to 8 power line loops. In this case, it was difficult for the prior art to simultaneously ensure communication stability and reliability. Due to the main reasons such as parasitic line resistance, line capacitance, line sense, and irregular construction of the power line, it is very easy to cause the upstream current signal to be distorted during the transmission process, which greatly affects the reliable reception of the current modulation signal of the upstream host device. In addition, the distances between the locations of different slave devices and the location of the host device are different, resulting in different degrees of distortion of the current waveform; different slave devices use low-cost internal clocks with large temperature drift chips, resulting in different widths of the effective current waveforms sent by different slaves, or becoming longer or shorter. These problems can easily lead to errors in the host decoding of the current waveform.

[0080] In an embodiment of the present invention, an adaptive rate decoding method, system and device for a power line host communication core are provided. The scheme provides an adaptive rate decoding method for a power line host communication core, which can adaptively solve the current waveform distortion of different slaves, the current waveform change caused by different temperature drift clocks, and the current waveform of different rates. In addition, the statistical average characteristic is used to filter the interference of the external electromagnetic environment on the current signal.

[0081] According to a first aspect of an embodiment of the present invention, an adaptive rate decoding method for a power line host communication core is provided.

[0082] Figure 1 It is a flow chart of an adaptive rate decoding method of a power line host communication core according to an embodiment of the present invention.

[0083] In one or more embodiments, preferably, the adaptive rate decoding method of the power line host communication core includes:

[0084] S101, performing online current starting point analysis according to high-precision ADC data;

[0085] S102, performing online current end point analysis according to high-precision ADC data;

[0086] S103, storing the effective current signal in a quantization data cache module according to the current starting point and the effective current ending point;

[0087] S104, counting the effective sampling point length according to the current end sampling point;

[0088] S105, calculating the average single BIT sampling point according to the effective sampling point length;

[0089] S106 , performing a comprehensive check according to the quantized data cache module, the average single BIT sampling point and the effective sampling point length.

[0090] In the embodiment of the present invention, the high-precision ADC data input to the pre-processing stage is quantized into a single-bit value to save data cache overhead; the average number of effective current sampling points per bit is counted to facilitate the segmentation of the quantized data cache corresponding to each bit interval by each bit; the number of 0 or 1 in the value in the quantized data cache corresponding to each bit interval is counted, and the real value of this bit is determined according to the larger number of 0 or 1 to reduce the probability of misjudgment. The structure diagram of the adaptive decoding circuit is shown in FIG. Fig.11 shown.

[0091] Figure 2 The present invention is a flowchart of an adaptive rate decoding method for a power line host communication core, which performs online current starting point analysis based on high-precision ADC data.

[0092] like Figure 2 As shown, in one or more embodiments, preferably, the online current starting point analysis based on the high-precision ADC data specifically includes:

[0093] S201, the high-precision ADC data processed by the previous stage is sent to the receiving decoding module;

[0094] S202, searching for a starting sampling point of effective current in the input ADC data processed by the previous stage;

[0095] S203, when it is found that there are a continuous preset number of current digital signal values ​​that satisfy the first calculation formula, it is considered to be a valid current starting point, and the position of this sampling point is recorded;

[0096] The first calculation formula is:

[0097] L≥Y1

[0098] Wherein, L is a preset number of continuous current digital signal values, and Y1 is a preset background starting current threshold.

[0099] In the embodiment of the present invention, it is specifically about how to perform online current starting point analysis based on high-precision ADC (analog-to-digital converter) data. First of all, it should be clear that ADC is a device that converts analog signals into digital signals. Its accuracy determines the degree of restoration of the digital signal to the original analog signal, and high-precision ADC means a higher signal restoration degree. In the implementation process of the present invention, the high-precision ADC data after pre-processing is sent to the receiving decoding module. These data represent the real-time current signal on the power line, but due to factors such as line impedance, capacitance, inductance and irregular construction, these signals may have been distorted. Therefore, it is necessary to further process these data to accurately identify the starting point of the effective current signal. In order to achieve this goal, the present invention adopts a search algorithm. The algorithm searches for the starting sampling point of the effective current in the input pre-processed ADC data. Specifically, the algorithm continuously checks whether the preset number of current digital signal values ​​meets the first calculation formula. This formula can be expressed as: L≥Y1, where L is the continuous preset number of current digital signal values, and Y1 is the preset background starting current threshold. In this formula, L is a variable, which represents the number of current digital signal values ​​that are continuously checked. Y1 is a fixed value, which represents the threshold of the background starting current. When the value of L is greater than or equal to Y1, it means that a valid current starting point has been found, and the position of this sampling point is recorded. For example, suppose the value of L is set to 5 and the value of Y1 is set to 3. Then, when 5 consecutive current digital signal values ​​are found in the ADC data that are greater than or equal to 3, it is considered to be a valid current starting point and this position is recorded. In this way, the starting point of the effective current signal can be accurately determined, thereby providing accurate data support for subsequent signal decoding and processing.

[0100] Figure 3 The present invention is a flowchart of an adaptive rate decoding method for a power line host communication core according to an embodiment of the present invention for performing online current end point analysis based on high-precision ADC data.

[0101] like Figure 3 As shown, in one or more embodiments, preferably, the online current end point analysis based on the high-precision ADC data specifically includes:

[0102] S301, after searching for the effective current starting point, the effective current ending point searching module also starts inputting the ADC data processed by the previous stage;

[0103] S302, when the valid current end point search module finds a certain number of consecutive current digital signal values ​​satisfying the second calculation formula in the ADC data sequence stream, it is considered as a valid current end point, and the position of this sampling point is recorded;

[0104] The second calculation formula is:

[0105] L≥Y2

[0106] Among them, Y2 is the preset background end current threshold.

[0107] In an embodiment of the present invention, in a power line communication system, in order to ensure the accuracy and reliability of signal transmission, it is necessary to accurately identify the starting point and the end point of the signal. This embodiment provides an online current end point analysis method based on high-precision analog-to-digital converter (ADC) data. The method first searches for the starting point of the effective current in the ADC data after the pre-stage processing. Once a valid starting point is found, the system will start the effective current end point search module, which continues to search for a valid end point in the input pre-stage processed ADC data stream. When the search module finds that a certain number of continuous current digital signal values ​​in the ADC data sequence satisfy the second calculation formula, it is considered that a valid current end point is found, and the position of this sampling point is recorded. Among them, the second calculation formula is L≥Y2, L represents a continuous preset number of current digital signal values, and Y2 is a preset background end current threshold. In this way, the system can accurately determine the end point of the current signal, thereby ensuring the integrity of the signal and the stability of communication.

[0108] Figure 4 The present invention is a flowchart of storing effective current signals in a quantized data cache module according to a current starting point and an effective current ending point in an adaptive rate decoding method of a power line host communication core according to an embodiment of the present invention.

[0109] like Figure 4 As shown, in one or more embodiments, preferably, storing the effective current signal in the quantization data cache module according to the current starting point and the effective current ending point specifically includes:

[0110] S401, when the effective current starting point is found, the module for quantifying the effective current value is started;

[0111] S402, the quantized effective current value module judges the value of the input current numerical signal according to the third calculation formula, and the value is 1 if it satisfies the third calculation formula, and 0 if it does not, and stores it in the quantized data cache module until the effective current end point is searched;

[0112] The third calculation formula is:

[0113] W>F

[0114] Wherein, W is the current digital signal value, and F is the 0 / 1 value dividing threshold.

[0115] In an embodiment of the present invention, how to store the effective current signal into the quantization data cache module according to the current starting point and the effective current ending point. When the system detects the effective current starting point, the quantization effective current value module is started. The task of this module is to judge the input current numerical signal according to the third calculation formula, and store the signal that meets the conditions into the quantization data cache module until the effective current ending point is found. In this embodiment, the third calculation formula is W>F, where W represents the current value of 1bit, and F is the 0 / 1 value demarcation threshold. This means that if the input current numerical signal is greater than the demarcation threshold F, then the signal is judged to be 1, otherwise it is 0. These binary signals are then stored in the quantization data cache module. This process will continue until the system detects the effective current ending point, at which time the quantization effective current value module will stop working. For example, assume that there is a current numerical signal sequence [0.2, 0.5, 0.8, 1.1, 1.4], and the demarcation threshold F is set to 1. Then, according to the third calculation formula, this sequence can be quantized to [0, 0, 1, 1, 1], and the quantized data can be stored in the quantized data cache module. In this way, the effective current signal is successfully stored for subsequent processing and analysis. In this way, the present invention can determine the starting point and the end point of the effective current signal with high reliability and store these signals accurately. This not only improves the stability and reliability of the power line communication system, but also provides accurate data support for subsequent signal processing and analysis.

[0116] Figure 5 The present invention is a flowchart of counting effective sampling point lengths according to current end sampling points in an adaptive rate decoding method of a power line host communication core according to an embodiment of the present invention.

[0117] like Figure 5 As shown, in one or more embodiments, preferably, the counting of effective sampling point lengths according to the current end sampling point specifically includes:

[0118] S501, obtaining the current starting point and the current ending sampling point;

[0119] S502, calculating the effective sampling point length using the fourth calculation formula;

[0120] The fourth calculation formula is:

[0121] XL=(JS-QD)÷PL

[0122] Among them, XL is the effective sampling point length, JS is the current end sampling point, QD is the current starting point, and PL is the sampling frequency.

[0123] In an embodiment of the present invention, the starting point and the ending point of the current signal are first obtained, and these two points represent the starting and ending positions of the effective current signal, respectively. Then, the length of the effective sampling point is calculated using the fourth calculation formula. This formula can be expressed as: XL=(JS-QD)÷PL, where XL represents the length of the effective sampling point, JS represents the position of the current end sampling point, QD represents the position of the current starting point, and PL represents the sampling frequency of the system, that is, the number of samples collected per second. In this way, an accurate and quantified effective sampling point length value can be obtained, which reflects the length of the effective current signal actually transmitted. For example, if the current end sampling point JS is 100, the current starting point QD is 20, and the sampling frequency PL is 50Hz (i.e., 50 samples per second), then the effective sampling point length XL is equal to (100-20)÷50=1.6 seconds. This means that in this example, the effective current signal lasts for 1.6 seconds. In this way, the length of the effective current signal transmitted on the power line can be accurately measured, thereby providing accurate data support for subsequent signal processing and analysis. This method of counting the effective sampling point length based on the current end sampling point not only improves the measurement accuracy, but also provides an important reference for the optimization of the power line communication system.

[0124] Figure 6 The present invention is a flowchart of calculating an average single BIT sampling point according to the effective sampling point length in an adaptive rate decoding method of a power line host communication core according to an embodiment of the present invention.

[0125] like Figure 6 As shown, in one or more embodiments, preferably, the calculating the average single BIT sampling point according to the effective sampling point length specifically includes:

[0126] S601, counting the number of valid sampling points that satisfy a third calculation formula according to the current starting point and the current ending sampling point;

[0127] S602, obtaining a preset number of bits;

[0128] S603, calculating the average single BIT sampling point using the fifth calculation formula;

[0129] The fifth calculation formula is:

[0130] DB=YX÷YBIT

[0131] Among them, DB is the average single BIT sampling point, YX is the number of valid sampling points, and YBIT is the preset number of bits.

[0132] In the embodiment of the present invention, it should be clear that the "bit" in this embodiment refers to a binary number, that is, 0 or 1. In a digital circuit, a bit is the smallest unit of data. And "BIT" is a specific term here, which is used to refer to a binary bit. In this embodiment, a bit number (YBIT) is preset, and this number will be used for the subsequent calculation of the average single BIT sampling point. Specifically, the method of this embodiment includes the following steps: Count the number of valid sampling points: According to the current starting point and the current ending sampling point, count the number of valid sampling points (YX) that meet the third calculation formula inside. Here, "inside" refers to the area between the current starting point and the current ending sampling point, that is, the length of the effective current signal. Obtain the preset number of bits: This step is pre-set, and a suitable number of bits (YBIT) is determined according to the specific application scenario and requirements. This number will be used for subsequent calculations. Calculate the average single BIT sampling point: Use the fifth calculation formula DB=YX÷YBIT to calculate the average single BIT sampling point (DB). Here, YX is the number of valid sampling points previously counted, and YBIT is the preset number of bits. Through this formula, the average number of sampling points corresponding to each bit can be obtained. For example, if the number of effective sampling points YX is 100 and the preset number of bits YBIT is 10, then according to the fifth calculation formula, the average single BIT sampling point DB is 10. This means that in this effective current signal, each bit corresponds to 10 sampling points on average. In this way, the present embodiment can accurately calculate the average single BIT sampling point, thereby providing important reference information for signal decoding in the power line communication system. This calculation method not only improves the accuracy of signal processing, but also enhances the system's adaptability to various complex situations.

[0133] Figure 7 It is a flow chart of performing comprehensive verification according to the quantized data cache module, the average single BIT sampling point and the effective sampling point length in the adaptive rate decoding method of the power line host communication core of an embodiment of the present invention.

[0134] like Figure 7As shown, in one or more embodiments, preferably, the comprehensive verification is performed according to the quantized data cache module, the average single BIT sampling point and the effective sampling point length, specifically including:

[0135] S701, counting the number of 0s or 1s in each bit segment of the storage content of the quantized data cache module;

[0136] S702, comparing the number of 1 / 0 in each bit segment with a preset 1 / 0 number threshold, when the number of 1 / 0 in each bit segment is greater than the preset 1 / 0 number threshold, it is recorded as 1, otherwise it is recorded as 0 and stored as a decoding output result;

[0137] S703, comparing the average single BIT sampling point, the decoding output result and the effective sampling point length with the preset data, if they are consistent, it is considered that the verification has passed, otherwise, it is considered that there is a problem and the verification cannot pass.

[0138] In the embodiment of the present invention, first of all, it should be clear that the quantization data cache module is a storage unit for storing data after quantization processing. In this embodiment, the storage content of the module is used to count the number of 0 or 1 in each bit segment. Specifically, the system will traverse each bit segment in the quantization data cache module and calculate the number of 0 and 1 therein respectively. Next, the system will compare the number of 1 / 0 in each bit segment with the preset 1 / 0 number threshold. If the number of 1 / 0 in a bit segment is greater than the preset 1 / 0 number threshold, then the segment is recorded as 1; otherwise, it is recorded as 0. The result of this step will be stored as the decoding output result. Then, the system will compare the average single BIT sampling point, the decoding output result and the effective sampling point length with the preset data. If all three are consistent, then it is considered that the verification has passed; otherwise, it is considered that there is a problem and the verification cannot pass.

[0139] According to a second aspect of an embodiment of the present invention, an adaptive rate decoding system for a power line host communication core is provided.

[0140] Figure 8 It is a structural diagram of an adaptive rate decoding system of a power line host communication core according to an embodiment of the present invention.

[0141] In one or more embodiments, preferably, the adaptive rate decoding system of the power line host communication core includes:

[0142] A current starting point analysis module 801 is used to perform online current starting point analysis based on high-precision ADC data;

[0143] A current end sampling point analysis module 802 is used to perform online current end point analysis based on high-precision ADC data;

[0144] A quantized effective storage module 803 is used to store effective current signals into a quantized data cache module according to a current starting point and an effective current ending point;

[0145] An effective current calculation module 804 is used to count the effective sampling point length according to the current end sampling point;

[0146] The average single BIT sampling point calculation module 805 is used to calculate the average single BIT sampling point according to the effective sampling point length;

[0147] The comprehensive decoding output module 806 is used to perform comprehensive verification according to the quantized data cache module, the average single BIT sampling point and the effective sampling point length.

[0148] In the embodiment of the present invention, a system suitable for different structures is realized through a series of modular designs. The system can achieve closed-loop, reliable and efficient execution through collection, analysis and control.

[0149] According to a third aspect of an embodiment of the present invention, there is provided a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method as described in any one of the first aspect of the embodiment of the present invention is implemented.

[0150] According to a fourth aspect of an embodiment of the present invention, an electronic device is provided. Fig. 9 It is a structural diagram of an electronic device in one embodiment of the present invention. Fig. 9 The electronic device shown is an adaptive rate decoding device for a universal power line host communication core. Fig. 9 , the electronic device includes a plurality of acquisition devices 901 and a processing device 902; wherein different acquisition devices 901 monitor different areas of a target scene, and the monitoring areas of the plurality of acquisition devices cover the target scene;

[0151] Each acquisition device 901 is used to acquire an image of a target scene and identify the position information of a moving target in the acquired image;

[0152] The processing device 902 includes a processor 903, a communication interface 904, a memory 905 and a communication bus 906, wherein the processor 903, the communication interface 904 and the memory 905 communicate with each other via the communication bus 906.

[0153] Memory 905, used for storing computer programs;

[0154] The processor 903 is used to implement the adaptive rate decoding method steps of any of the above-mentioned universal power line host communication cores provided by the embodiments of the present invention when executing the computer program stored in the memory 905.

[0155] The communication bus 906 mentioned in the above processing device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus 906 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0156] The communication interface 904 is used for communication between the above processing device and other devices.

[0157] The memory 905 may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory 905 may also be at least one storage device located away from the processor 903 .

[0158] The above-mentioned processor 903 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0159] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:

[0160] In the scheme of the present invention, the starting point of the effective current signal is searched for with high reliability on the input pre-processing ADC data, and a certain number of current digital signals that continuously count and exceed the background current starting threshold are considered as the starting point, so as to reduce the probability of misjudging the starting point.

[0161] In the scheme of the present invention, the end point search of the effective current signal is performed on the ADC data processed by the input pre-stage with high reliability. The end point is considered to be the current digital signal when a certain number of current digital signals are continuously counted to be less than the background current end threshold, so as to reduce the probability of misjudging the end point. In addition, the total length of the actual effective current sampling points is counted at the same time.

[0162] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program codes.

[0163] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0164] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0165] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0166] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An adaptive rate decoding method for a power line host communication core, characterized in that: The method includes: Perform online current starting point analysis based on high-precision ADC data; Perform online current end point analysis based on high-precision ADC data; Storing the effective current signal in the quantization data cache module according to the current starting point and the effective current ending point; Count the effective sampling point length according to the current end sampling point; Calculate the average single BIT sampling point based on the effective sampling point length; Performing a comprehensive check based on the quantized data cache module, the average single BIT sampling point and the effective sampling point length; The step of storing the effective current signal in the quantization data cache module according to the current starting point and the effective current ending point specifically includes: When the effective current starting point is found, the module for quantifying the effective current value starts; The quantized effective current value module judges the input current value signal value according to the third calculation formula, and stores the value of the current value signal in the quantized data cache module until the effective current end point is found. The third calculation formula is: W>F Where W is the current digital signal value, and F is the 0 / 1 value demarcation threshold; The counting of effective sampling point lengths according to the current end sampling point specifically includes: Obtaining the current starting point and the current ending sampling point; Calculate the effective sampling point length using the fourth calculation formula; The fourth calculation formula is: XL=(JS-QD)÷PL Among them, XL is the effective sampling point length, JS is the current end sampling point, QD is the current starting point, and PL is the sampling frequency; The step of calculating the average single BIT sampling point according to the effective sampling point length specifically includes: Counting the number of valid sampling points that satisfy a third calculation formula according to the current starting point and the current ending sampling point; Get the preset number of bits; The fifth calculation formula is used to calculate the average single BIT sampling point; The fifth calculation formula is: DB=YX÷YBIT Among them, DB is the average single BIT sampling point, YX is the number of valid sampling points, and YBIT is the preset number of bits; The comprehensive verification based on the quantized data cache module, the average single BIT sampling point and the effective sampling point length specifically includes: Quantify the storage content of the data cache module to count the number of 0s or 1s in each bit segment; Determine the number of 1 / 0 in each bit segment and compare it with the preset 1 / 0 number threshold. When the number of 1 / 0 in each bit segment is greater than the preset 1 / 0 number threshold, it is recorded as 1, otherwise it is recorded as 0 and stored as the decoding output result; The average single BIT sampling point, decoding output result and effective sampling point length are compared with the preset data. If they are consistent, it is considered that the verification has passed. Otherwise, it is considered that there is a problem and the verification cannot pass.

2. The adaptive rate decoding method of the power line host communication core according to claim 1, characterized in that: The online current starting point analysis based on the high-precision ADC data specifically includes: The high-precision ADC data processed by the previous stage is sent to the receiving decoding module; Searching for the starting sampling point of the effective current in the input ADC data processed by the previous stage; When it is found that there are a continuous preset number of current digital signal values ​​that satisfy the first calculation formula, it is considered to be a valid current starting point, and the position of this sampling point is recorded; The first calculation formula is: L≥Y1 Wherein, L is a preset number of continuous current digital signal values, and Y1 is a preset background starting current threshold.

3. The adaptive rate decoding method of the power line host communication core as claimed in claim 2, characterized in that: The online current end point analysis based on the high-precision ADC data specifically includes: When the effective current starting point is searched, the effective current end point search module also starts to process the ADC data in the input front stage; When the valid current end point search module finds a certain number of continuous current digital signal values ​​satisfying the second calculation formula in the ADC data sequence stream, it is considered to be a valid current end point and the sampling point position is recorded; The second calculation formula is: L≥Y2 Among them, Y2 is the preset background end current threshold.

4. An adaptive rate decoding system for a power line host communication core, characterized in that: The system is used to implement the method according to any one of claims 1 to 3, and the system comprises: Current starting point analysis module, used to perform online current starting point analysis based on high-precision ADC data; Current end sampling point analysis module, used to perform online current end point analysis based on high-precision ADC data; A quantized effective storage module, used for storing effective current signals into a quantized data cache module according to a current starting point and an effective current ending point; An effective current calculation module is used to count the effective sampling point length according to the current end sampling point; An average single BIT sampling point calculation module is used to calculate the average single BIT sampling point according to the effective sampling point length; The comprehensive decoding output module is used to perform comprehensive verification according to the quantized data cache module, the average single BIT sampling point and the effective sampling point length.

5. A computer-readable storage medium storing computer program instructions, characterized in that: The computer program instructions implement the method according to any one of claims 1 to 3 when executed by a processor.

6. An electronic device comprising a memory and a processor, characterized in that: The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method according to any one of claims 1-3.

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