Monoclinic ADC and CIS chip based on look-ahead adaptive CMS technology

Abstract

The invention belongs to the field of CMOS (Complementary Metal Oxide Semiconductor) devices, and particularly relates to a monoclinic ADC (Analog to Digital Converter) and CIS (Contact Image Sensor) chip based on a look-ahead adaptive CMS ( The CMS quantization module comprises each CMS quantization module connected to each column in a pixel array and a dynamic slope generation module; the CMS quantization module comprises a comparator, a counter, a column level judgment module and an adder-subtractor. The dynamic slope generation module comprises a slope generator, a slope modulation module and a global judgment module. The ramp generator is used for generating a ramp signal corresponding to a standard ramp, a full-scale ramp or a self-adaptive ramp according to the received modulation signal, and sending the ramp signal to the comparator in the corresponding row. And the global judgment module is used for identifying the maximum value and the minimum value of the primary quantization results of the pixel units in the same row, and further determining the swing interval of the adaptive slope in the secondary quantization. The slope modulation module is used for outputting modulation signals capable of generating three types of slopes. According to the invention, the problem that an existing monoclinic ADC is difficult to give consideration to quantization precision and quantization time at the same time is solved.

Description

Technical Field

[0001] The invention belongs to the field of CMOS devices, and in particular relates to a single-slope ADC based on a forward-looking adaptive CMS technology and a corresponding CIS chip. Background Art

[0002] CMOS image sensors (CIS) are widely used in smart phones, security monitoring, medical imaging and other fields due to their small size and easy integration. In recent years, with the continuous advancement of CMOS integrated circuit technology, some advanced application scenarios have higher and higher performance requirements for CIS, especially in low-light environments, which require it to have extremely high noise suppression capabilities to ensure image quality. However, in low-light conditions, the random noise generated by the readout circuit contributes greatly to the total noise. Therefore, how to reduce random noise has become the key to improving the signal-to-noise ratio.

[0003] The traditional correlated multiple sampling (CMS) technology suppresses circuit noise by sampling the circuit output signal multiple times. Generally speaking, after M samplings, the random noise of the readout circuit can be reduced to 1 / M of the original. However, in the traditional CMS working process, each additional sampling time will double the ADC conversion time, resulting in a significant decrease in the frame rate of the image sensor. On this basis, the conditional correlated multiple sampling (CCMS) technology was proposed. The main idea of ​​CCMS is to judge the brightness of the pixel output voltage and use a small voltage range ramp to quantize the small swing dark pixel output multiple times to reduce random noise and A / D conversion time. Since the large swing two-pixel output is mainly photon shot noise, it cannot be reduced by multiple sampling within one frame time. Therefore, when the pixel output voltage swing exceeds a certain value, a full voltage range ramp is used for single quantization. However, the CCMS technology requires the addition of an additional ramp generator, which will cause the problem of mismatch between the ramp generators and increase the power consumption of the SS ADC (single-slope analog-to-digital converter).

[0004] In addition, a method of applying CMS technology to a two-step ADC has also been proposed, which shortens the overall quantization time by using two different quantization methods, coarse and fine. However, this method requires temporary storage of the voltage of the ramp generator in the analog domain or digital domain, which requires additional circuits, and the accuracy of the temporary stored voltage value is difficult to guarantee; at the same time, sufficient redundancy must be designed to avoid the occurrence of false locks, which increases the complexity of the circuit. Summary of the invention

[0005] In order to overcome the problem that the existing SS ADC is difficult to simultaneously take into account higher quantization accuracy and shorter quantization time, the present invention provides a single slope ADC based on a forward-looking adaptive CMS technology and a corresponding CIS chip.

[0006] The technical solution provided by the present invention is:

[0007] A single slope ADC based on forward-looking adaptive CMS technology includes CMS quantization modules connected to each column in a pixel array; the CMS quantization module completes the unit signal V output by each pixel unit in the pixel array based on correlated multi-sampling technology and through a row-by-row scanning method. sig Each CMS quantization module includes a comparator, a counter, a column-level judgment module, and an adder-subtractor.

[0008] In particular, the single slope ADC based on the forward-looking adaptive CMS technology provided by the present invention also includes a dynamic slope generation module; the dynamic slope generation module is used to output a slope signal with different starting points and swing amplitudes at different stages within a full quantization cycle. The dynamic slope generation module includes a slope generator, a slope modulation module and a global judgment module.

[0009] The ramp generator is used to generate a ramp signal V corresponding to a standard ramp, a full-scale ramp or an adaptive ramp according to the received modulation signal. ramp , and sent to the comparator of the corresponding row.

[0010] The global judgment module is used to obtain the primary quantization results of each pixel unit in the same row and identify the maximum value V max and minimum value V min , and according to the preset light threshold V lt Make the following decisions: (1) When V lt ≤V min , an end instruction is generated to terminate the secondary quantization process of the current row. (2) When V min ≤V lt ≤V max , then (V min, , V lt ) is used as the swing range of the adaptive ramp in the secondary quantization and sent to the ramp modulation module. (3) When V max ≤V lt , then (V min, , V max ) is used as the swing range of the adaptive slope in the secondary quantization and is sent to the slope modulation module.

[0011] The slope modulation module is used to: output a first modulation signal for generating a standard slope in the reset signal quantization stage; output a second modulation signal for generating a full-scale slope in the pixel primary quantization stage; and output a third modulation signal for generating an adaptive slope with a specified swing amplitude in the illumination judgment stage.

[0012] As a further improvement of the present invention, the standard ramp includes a plurality of continuous ramps within a specified swing range and is used to quantize the reset signal V output by the pixel unit. rst The full-scale slope includes the upper limit corresponding to the range voltage V FS A slope, and used to output the pixel signal V of each pixel unit pixel The adaptive ramp includes a plurality of continuous ramps located in the adaptive swing range and is used to adjust the pixel unit output below the illumination threshold V lt The pixel signal V pixel Multiple rounds of secondary quantification were performed.

[0013] As a further improvement of the present invention, the ramp generator includes a current steering DAC that uses a thermometer code combined with a binary code, a negative feedback circuit, and a unity gain buffer. The current steering DAC is composed of multiple current sources, a switch array, a positive resistor R1, and a negative resistor R2; the negative feedback circuit is connected at the intersection of R1 and R2, thereby clamping the initial voltage of the ramp to a fixed value V x The unity gain buffer is connected between the negative terminal resistor and the current source of the final stage, and then the output is V x The ramp signal V ramp .

[0014] In the ramp generator, by adjusting the preset fixed value V in the negative feedback circuit x The switching state of the switch array in the current steering DAC can realize the ramp signal V output by the ramp generator. ramp The swing range can be adjusted.

[0015] As a further improvement of the present invention, in the current steering DAC, there are M current sources; the switch array is composed of 2M transmission gates; M of the transmission gates are used to connect the output end of each current source with the upper end of R1, and the other M transmission gates are used to connect the output end of each current source with the upper end of R2. The lower ends of R1 and R2 are connected.

[0016] As a further improvement of the present invention, the negative feedback circuit is composed of an operational amplifier A1, an NMOS tube N0 and a capacitor C0. The negative input terminal of A1 is connected to V xThe positive input terminal of A1, the drain of N0 and one end of C0 are connected to the lower ends of R1 and R2. The output terminal of A1 is connected to the other end of C0 and the gate of N0; the source of N0 is grounded.

[0017] As a further improvement of the present invention, the unit gain buffer uses an operational amplifier A2; the positive input terminal of A2 is connected to the upper end of R2; the negative input terminal of A2 is connected to the output terminal and is used to output the ramp signal V ramp .

[0018] As a further improvement of the present invention, the ramp modulation module includes three counters Counter1 to Counter3, N three-to-one selectors MUX <1> ~MUX <n>, and an N-bit decoder, where N corresponds to the quantization accuracy of the single slope ADC.

[0019] Counter1 is used to store and output the first code QZ0~QZ corresponding to the standard slope N-1 Counter2 is used to store and output the second code QX0~QX corresponding to the full-scale slope. N-1 Counter3 is used to store and output the third code QY0~QY corresponding to the adaptive slope. N-1 The N three-to-one selectors are used to select any one of the N-bit codes in Counter1 to Counter3 and input it into the N-bit decoder. The N-bit decoder is used to decode the received N-bit code and generate a control signal for controlling the switch state of the 2M transmission gates in the switch array.

[0020] As a further improvement of the present invention, the three-to-one selector is composed of two two-to-one selectors mux1 and mux2. Each three-to-one selector is used to select one of the first code, the second code or the third code. Among them, the two input ends of mux1 are connected to QXi and QYi respectively, and the output end is connected to an input end of mux2; the other input end of mux2 is connected to QZi; i=1...N; the control end signal of mux1 is recorded as CTRL, and the control end of mux2 is connected to the selection signal Q.

[0021] As a further improvement of the present invention, the global judgment module includes a maximum value query unit and a minimum value query unit. The maximum value query unit is composed of an N-level AND gate AND, an N-bit counter CounterX and a subtractor Sub. The N input ends of AND are respectively connected to the outputs C0~C1 of the comparator in the CMS quantization module of each column. n-1 , n represents the number of CMS quantization modules; the output end of AND is connected to the input end of CounterX, and the input end of CounterX is connected to the input end of Sub; the output end of Sub is used to output the maximum value of the primary quantization results of each pixel unit in the same row.

[0022] Correspondingly, the minimum value query unit is composed of an N-level OR gate and an N-bit counter CounterY. The N input terminals of OR are respectively connected to the outputs C0~C1 of the comparator in the CMS quantization module of each column. n-1 The output end of OR is connected to the input end of CounterY, and the output end of CounterY is used to output the minimum value of the primary quantization results of each pixel unit in the same row.

[0023] As a further improvement of the present invention, the single slope ADC also includes a process management module, which is used to switch different stages in the full quantization cycle of the pixel array. The process management module includes a two-to-one selector mux0 and a T trigger T0. The two input terminals of mux0 are respectively connected to the end signal p of the reset signal quantization stage and the end signal q of the pixel secondary quantization stage. The output terminal of mux0 is connected to the clock port of T0; the control terminal of mux0 is connected to the Q terminal of T0; and the T terminal of T0 is connected to a high level signal. In the process management module, p and q jointly generate a selection signal Q output to the ramp modulation unit.

[0024] As a further improvement of the present invention, the unit signal V sig By the reset signal V rst and pixel signal V pixel Composition: Single slope ADC realizes the unit signal V output to the pixel array sig The quantification process is as follows:

[0025] 1. Reset signal quantization stage

[0026] The ramp modulation module controls the ramp generator to generate a ramp signal V with a standard ramp. ramp ; The comparators in each CMS quantization module on the same row use V ramp V for pixel unit output rst Multiple rounds of prequantization are performed and the prequantization results are stored in a counter.

[0027] 2. Primary pixel quantization stage

[0028] The ramp modulation module controls the ramp generator to generate a ramp signal V with a full-scale ramp. ramp ; The comparators in each CMS quantization module on the same row use V ramp V for pixel unit output pixel Perform primary quantization; the primary quantization result is stored in the counter.

[0029] 3. Light intensity judgment stage

[0030] The global judgment module determines V according to the primary quantization results. max and V min , and then combined with the preset light threshold V lt Make the following decisions:

[0031] (1) When V lt ≤V min , the quantization process of the current row is terminated, and the adder-subtractor generates the output value of each pixel unit according to the pre-quantization and primary quantization results in the counter.

[0032] (2) When V min ≤V lt ≤V max , then enter the pixel secondary quantization stage; at the same time (V min, , V lt ) is used as the swing interval of the adaptive slope in the secondary quantization and is sent to the slope modulation module.

[0033] (3) When V max ≤V lt , then enter the pixel secondary quantization stage; at the same time (V min, , V max ) is used as the swing interval of the adaptive slope in the secondary quantization and is sent to the slope modulation module.

[0034] 4. Pixel sub-quantization stage

[0035] The ramp modulation module controls the ramp generator to generate a ramp signal V with an adaptive ramp. ramp The column-level judgment module determines in turn whether the primary quantization results of each column of pixel units in the current row exceed the illumination threshold V lt :

[0036] (I) If yes, the primary quantization result is used as the secondary quantization result;

[0037] (Ⅱ) Otherwise, the comparator uses V ramp V for pixel unit output pixel Perform multiple rounds of secondary quantification;

[0038] The adder-subtractor takes the average of multiple rounds of secondary quantization as the final result of secondary quantization;

[0039] Finally, the adder-subtractor generates the output value of each pixel unit according to the pre-quantization and sub-quantization results in the counter.

[0040] The present invention also includes a CIS chip, which includes a pixel array and also adopts the single slope ADC based on the forward-looking adaptive CMS technology as mentioned above.

[0041] The technical solution provided by the present invention has the following beneficial effects:

[0042] The present invention combines the forward-looking analysis of signal distribution with the digital correlated multi-sampling technology, and designs a single-slope ADC based on the forward-looking adaptive CMS technology. The single-slope ADC first performs reset signal quantization, then performs preliminary quantization of the full-scale pixel signal, and then performs forward-looking analysis on the results of the preliminary quantization, and is used to make a decision on whether CMS quantization is needed. In the present invention, the swing amplitude of the adaptive slope used in the CMS quantization stage is adaptively regulated according to the voltage distribution of each pixel unit obtained by the forward-looking analysis. In this way, the quantization time is shortened under the premise of ensuring the quantization accuracy and reducing the random noise.

[0043] The technical solution provided by the present invention can effectively improve the conversion speed of ADC in CIS based on LA-ACMS technology, especially when the pixel signals of each pixel in the same row are accumulated within a very small voltage range. The present invention can use very few clock cycles to complete the quantization of the pixel signals. Even when the row pixel signals are uniformly distributed within the full-scale range, the present invention can effectively shorten the quantization time.

[0044] In addition, compared with CCMS technology, the present invention only includes a dynamically adjustable ramp generator, which has a simple structure and avoids the problem of slope mismatch when using multiple ramp generators. Compared with the two-step ADC, the present invention does not need to temporarily store the coarse quantization voltage, avoiding the problem of insufficient precision of the temporarily stored voltage value. In addition, the present invention can distinguish the intensity of the light environment in which the pixel unit is located at one time in the initial quantization stage of the pixel signal, without the need to introduce an additional judgment module or perform multiple rounds of judgment, which can reduce the complexity of the circuit and the operating power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a circuit schematic diagram of a single slope ADC based on the look-ahead adaptive CMS technology provided in Example 1 of the present invention.

[0046] Figure 2 1 is a waveform diagram of the ramp signal used in three typical signal voltage distribution conditions in Example 1 of the present invention.

[0047] Figure 3 4 is a circuit diagram of the ramp generator used in Example 1 of the present invention.

[0048] Figure 4 4 is a circuit diagram of the ramp modulation module used in Example 1 of the present invention.

[0049] Figure 5 The circuit diagram and functional principle of the maximum value query unit and the minimum value query unit in the global judgment module used in Example 1 of the present invention.

[0050] Figure 6 This is a circuit diagram of the process management module used in Example 1 of the present invention.

[0051] Figure 7 To adopt Figure 1 The circuit performs a quantization strategy image on the unit signal output by each pixel unit in the pixel array.

[0052] Figure 8 for Figure 2 Signal flow diagram of the quantization process in three corresponding typical scenarios. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0054] Example 1

[0055] This embodiment provides a single slope ADC based on the forward-looking adaptive CMS technology. The single slope ADC is obtained by improving the traditional SS ADC based on the CCMS technology. The traditional SS ADC is composed of each CMS quantization module connected to each column in the pixel array; the CMS quantization module can complete the unit signal V output by each pixel unit in the pixel array by scanning row by row. sig Quantify.

[0056] Each CMS quantization module includes a comparator, a counter, a column level judgment module and an adder-subtractor. The comparator is used to calculate the value of the ramp signal V according to the preset ramp signal V. ramp The unit signal V outputted by the pixel unit on each column in the pixel array sig The quantization is performed and the quantization result is stored in the counter. The column-level judgment module obtains the quantization result stored in the counter and judges the unit signal V sig The corresponding ambient light is strong or weak. If it is weak, the same ramp signal is used to repeatedly sample and quantize the unit signal for multiple rounds, and the adder-subtractor uses the preset operation rules to calculate the final quantization value based on the results of multiple rounds of quantization. It should be noted that the unit signal V output by the CMOS sig By the reset signal V rst and pixel signal V pixel The SS ADC needs to reset the signal V rst and pixel signal V pixel Quantize them, and then synthesize the final quantized value based on the quantization results of the two.

[0057] On the basis of the traditional SS ADC, the improved single slope ADC based on the forward-looking adaptive CMS technology in this embodiment introduces a strategy for forward-looking analysis of the distribution state of the quantization values ​​of the pixel units in each row in the pixel array, adaptively adjusting the subsequent quantization strategy according to the forward-looking analysis results, and dynamically regulating the ramp signal in the quantization stage.

[0058] Specifically, the single slope ADC based on the forward-looking adaptive CMS technology designed in this embodiment adopts asynchronous timing. Through the row-by-row exposure of the CMOS image sensor, adaptive correlated multi-sampling is implemented for each pixel unit with each row of the pixel array as a whole. Different from the existing scheme, the adaptive process of this embodiment includes the adjustment of the number of correlated multi-sampling and the adjustment of the quantization range of the ADC; the single slope ADC uses the size of the pixel voltage value as a reference to realize the overall and local logical judgment. In this scheme, "forward-looking" means that in the quantized pixel signal V pixel When the ramp generator generates a voltage corresponding to the full voltage range V FS The comparator of each column performs primary quantization on the pixel signal and latches the result. Since the voltage distribution of the entire row of pixel signals is obtained in this stage, this ramp can also be called a forward-looking ramp compared to the subsequent CMS stage.

[0059] Different from the method of predicting voltage values ​​through algorithm design, the forward-looking analysis of the voltage distribution of pixel signals in this embodiment is implemented at the circuit level. The circuit module for implementing the forward-looking analysis in this embodiment can predict the maximum value V of the pixel voltage in a row. max and minimum value V min The latching is performed, and the latching result can be used to adjust the ramp signal in the subsequent CMS stage, thereby effectively reducing the ramp range of the CMS stage without affecting the quantization accuracy, so as to shorten the quantization time.

[0060] Specifically, Figure 1 As shown, in addition to using multiple CMS quantization modules in the traditional SS ADC, the single slope ADC based on the forward-looking adaptive CMS technology provided in this embodiment also designs a dynamic slope generation module. The dynamic slope generation module is used to output adaptive slope signals with different starting points and swings at different stages within the full quantization cycle. The dynamic slope generation module includes a slope generator, a slope modulation module and a global judgment module. Among them, the slope generator adopts a new circuit that can flexibly adjust the starting point and swing of the output ramp signal. The global judgment module is mainly used to realize the aforementioned "forward-looking analysis" after the primary quantization of the pixel signal, and the slope control module generates the adaptive slope signal required by the pixel signal in the secondary quantization stage according to the forward-looking analysis results of the global judgment module.

[0061] In this embodiment, the ramp generator is used to generate a ramp signal V corresponding to a standard ramp, a full-scale ramp or an adaptive ramp according to the received modulation signal. ramp , and sent to the comparator of the corresponding row. Figure 2 As shown, the standard ramp includes a plurality of continuous ramps within a specified swing range and is used to quantize the reset signal V output by the pixel unit. rst For the same type of pixel array, the starting point and swing amplitude of the standard ramp are usually fixed. In this embodiment, the standard ramp is located in the lower amplitude range of (0, V1) and includes four identical continuous ramps, thereby realizing four rounds of quantization of the reset signal.

[0062] The full-scale slope includes the upper limit corresponding to the range voltage V FS The full-scale slope range is recorded as (0, V FS ). Since the ramp signal of the full-scale ramp contains all possible signal voltage locations of the pixel signal output by the pixel unit, the pixel signal V output by each pixel unit in the same row of the pixel array is calculated by using the full-scale ramp. pixel After partial primary quantization, the distribution range of the quantization results of all pixel signals can be obtained.

[0063] The adaptive slope is a ramp signal used by the comparator when it is determined that there are low-light pixels in the current row and it is necessary to repeatedly sample and quantize several pixel units in the row in the low-light state. In practical applications, the adaptive slope includes multiple continuous slopes located in the adaptive swing range, and the number of continuous slopes in the adaptive slope is flexibly designed according to the preset number of repeated sampling times. For example, in the present embodiment, the number of repeated samplings in the secondary quantization stage is set to 4, and the adaptive slope includes 4 continuous slopes. In particular, unlike traditional schemes that mostly use a ramp signal with a fixed swing amplitude at this stage, the present embodiment selects the maximum value V of the quantization result of the pixel unit determined in the primary quantization stage according to the current row. max and minimum value V min ; Then combine V max 、V min With the light threshold V lt The starting point and swing amplitude of the ramp signal can be flexibly adjusted based on the size relationship of the pixels. This allows the ramp signal to perfectly cover the quantization interval corresponding to the low-light pixels and significantly shorten the duration of the ramp signal.

[0064] In this embodiment, if Figure 2 As shown, the global judgment module is used to obtain the primary quantization results of each pixel unit in the same row and identify the maximum value V max and minimum value V min , and according to the preset light threshold V lt Make the following decisions:

[0065] (1) When V lt ≤V min , an end instruction is generated to terminate the secondary quantization process of the current row.

[0066] In this embodiment, according to the result identified by the global judgment module, an interval reflecting the distribution range of the pixel signal quantization results of all pixel units in the same row can be obtained, that is: min , V max ). Light threshold V lt Usually set to full-scale voltage V FS Half of V lt =V FS / 2. In this case, the light threshold V lt In fact, it can be used as a basis for judging the lighting environment of each pixel unit. When the quantization result of a pixel unit is lower than the lighting threshold V lt , the pixel unit can be considered to be in a weak light state. On the contrary, when the quantization result of a pixel unit is higher than the light threshold V lt , it can be considered that the pixel unit is in a strong light state.

[0067] If the present embodiment determines that the primary quantization results of each pixel unit in the same row satisfy: V lt ≤V min , it means that the primary quantization results of all pixel units are higher than the illumination threshold V lt , at this time, all pixel units are in a strong light state. According to the quantization principle of CMMS technology, the primary quantization results of each pixel unit in this row can be used as the final quantization result, without the need to suppress random noise through repeated sampling. lt ≤V min When the primary quantization is completed, the embodiment directly generates an end instruction for terminating the secondary quantization process of the current row. The quantization task of each pixel unit in the row ends after the primary quantization is completed, and the secondary quantization is not performed.

[0068] (2) When V min ≤V lt ≤V max , then (V min, , V lt ) is used as the swing range of the adaptive slope in the secondary quantization and is sent to the slope modulation module.

[0069] Assume that the result of the primary quantization shows that the illumination threshold V lt The maximum value V of the primary quantization result in the current row max and minimum value V min In the middle of the primary quantization result is said to be (V min, , V lt ) interval is in a weak light state, and these pixel units need to complete secondary quantization in the subsequent CMS stage; while the primary quantization result is in [V lt , V max ) interval is in a strong light state, and these pixel units do not need to be secondary quantized.

[0070] Therefore, in order to shorten the swing of the ramp signal while ensuring that the signal voltage distribution of each pixel unit is covered, it is only necessary to set the voltage swing of the adaptive ramp used in the secondary quantization process to (V min, , V lt ) interval.

[0071] (3) When V max ≤V lt , then (V min, , V max ) is used as the swing range of the adaptive slope in the secondary quantization and is sent to the slope modulation module.

[0072] Assume that the result of the primary quantization shows that the illumination threshold V lt Greater than the maximum value V of the primary quantization result max , then the primary quantization results of all pixel units in the current row are less than the illumination threshold V lt , each pixel unit is in a weak light state. At this time, all pixel units in the current row need to complete secondary quantization in the subsequent CMS stage.

[0073] In this state, the preliminary quantization results of the entire row of pixel units are distributed in (V min, , V max ) interval; in order to ensure that the signal voltage distribution of each pixel unit is covered, the swing of the ramp signal is shortened; it is only necessary to set the voltage swing of the adaptive ramp used in the secondary quantization process to (V min, , V max ) interval.

[0074] The ramp modulation module is used to generate a first modulation signal, a second modulation signal and a third modulation signal. The first modulation signal is used to control the ramp generator to generate a standard ramp in the reset signal quantization stage. The second modulation signal is used to control the ramp generator to generate a full-scale ramp in the pixel primary quantization stage. The third modulation signal is used to control the ramp generator to generate an adaptive ramp with a specified swing amplitude in the illumination judgment stage.

[0075] Based on the above, it can be seen that the single slope ADC based on the forward-looking adaptive CMS technology designed in this embodiment retains the effect of selectively repeating the sampling of pixel signals under low-light conditions by the traditional SS ADC, thereby suppressing the random noise of the quantization result and improving the quantization accuracy. The forward-looking adaptive technology is also applied to analyze the signal distribution of each pixel unit in the same row, and adaptively modulate the swing amplitude of the ramp signal used by the pixel unit in the low-light state in the secondary quantization process based on the analysis results.

[0076] Compared with the existing solutions: the new single slope ADC provided by this embodiment has two main advantages: first, the solution can determine at one time that all pixel units are in a strong light state, and directly terminate the subsequent CMS operation of the current row in this state; without the need to analyze the primary quantization results of each pixel unit in the row in sequence. Second, when all or part of the pixel units in any row need to be secondary quantized, if the voltage distribution of the primary quantization results of the pixel units in a whole row is relatively close (in the actual application of CMOS, this is a high-probability event), the swing amplitude of the adaptive ramp signal generated by the solution of this embodiment in the secondary quantization stage will also be distributed in a narrower range, which can greatly reduce the A / D conversion time of each pixel unit in the same row.

[0077] It should be emphasized that: in the second advantage of the solution of this embodiment, considering that the secondary quantization stage may involve multiple pixel units, and each pixel unit needs to be repeatedly sampled multiple times in the CMS technology, even if the quantization time shortened by the adaptive slope designed in this embodiment is relatively short, after it is applied to the quantization task of all pixels in the pixel array, the global quantization time saved is still very considerable.

[0078] The above content introduces the basic architecture and functional principle of the single slope ADC based on the forward-looking adaptive CMS technology designed in this embodiment. Figure 1 In the circuit architecture, the specific hardware solution of the CMS quantization module can adopt multiple existing solutions, and this embodiment neither limits nor elaborates on it. As for the hardware solution of the dynamic slope generation module, it can be developed by technical personnel based on the logical functions introduced in the previous article. This embodiment provides a single slope ADC based on the forward-looking adaptive CMS technology, which is not limited to a specific hardware circuit implementation. As long as the corresponding logical functions pointed out by Qianwen can be met, the ramp generator, ramp modulation module and global judgment module can adopt a variety of circuit solutions designed with different components.

[0079] Hereinafter, this embodiment introduces a typical circuit design of main circuit modules such as a ramp generator, a ramp modulation module and a global judgment module provided by technicians of this case.

[0080] 1. Ramp Generator

[0081] The ramp generator provided in this embodiment is characterized in that it can generate a required ramp signal of any length according to a specified starting point and swing amplitude.

[0082] Specifically, Figure 3 As shown in the figure, the ramp generator includes a current steering DAC that uses a combination of thermometer code and binary code, a negative feedback circuit, and a unity gain buffer. The current steering DAC is composed of multiple current sources, a switch array, a positive resistor R1, and a negative resistor R2; the negative feedback circuit is connected at the intersection of R1 and R2, thereby clamping the initial voltage of the ramp to a fixed value V x The unity gain buffer is connected between the negative terminal resistor and the current source of the final stage, and then the output is V x The ramp signal V ramp .

[0083] exist Figure 3 In the current steering DAC, there are M current sources; the switch array is composed of 2M transmission gates; M of the transmission gates are used to connect the output of each current source with the upper end of R1, and the other M transmission gates are used to connect the output of each current source with the upper end of R2. The lower ends of R1 and R2 are connected. The number of current sources and transmission gates in the current steering DAC mainly depends on the number of bits of the thermometer code and binary code used.

[0084] For example, in a typical scheme, assuming that the quantization accuracy of the ramp signal is 10 bits, the lower 4 bits are in the form of binary coding, and the upper 6 bits are in the form of thermometer coding, the number of current sources required is: M = 4 + 2 6 -1 = 67. Among them, the output current ratio of the 4 current sources corresponding to the binary code is 1:2:4:8, and the 63 current sources corresponding to the thermometer code are all twice the maximum current source corresponding to the binary code. Accordingly, the number of transmission tubes in the switch array is 134.

[0085] In the current steering ADC, the number of bits of the thermometer code and binary code can be flexibly set as needed. Among them, the binary code can reduce the number of bits of the thermometer code, thereby reducing the area of ​​the thermometer code circuit. The thermometer code can reduce the noise generated by too many flip bits during the carry process. Ideally, the positive output voltage of the current steering DAC starts from 0V.

[0086] The negative feedback circuit is composed of an operational amplifier A1, an NMOS tube N0 and a capacitor C0. The negative input terminal of A1 is connected to V x ; The positive input terminal of A1, the drain of N0 and one end of C0 are connected to the lower ends of R1 and R2. The output terminal of A1 is connected to the other end of C0 and the gate of N0; the source of N0 is grounded;

[0087] The unity gain buffer uses an operational amplifier A2; the non-inverting input of A2 is connected to the upper end of R2; the inverting input of A2 is connected to the output and is used to output the ramp signal V ramp .

[0088] exist Figure 3 In the ramp generator shown, by adjusting the preset fixed value V in the negative feedback circuit x The switching state of the switch array in the current steering DAC can realize the ramp signal V output by the ramp generator. ramp The swing range can be adjusted.

[0089] 2. Ramp Modulation Module

[0090] The function of the ramp modulation module provided in this embodiment is to adaptively control the switch state of the switch array in the current steering DAC of the ramp generator according to the type of ramp signal required in different quantization stages.

[0091] Specifically, Figure 4 As shown, the ramp modulation module provided in this embodiment includes three counters Counter1 to Counter3, N three-to-one selectors MUX <1> ~MUX <n>, and an N-bit decoder, where N corresponds to the quantization accuracy of the single slope ADC.

[0092] Counter1 is used to store and output the first code QZ0~QZ corresponding to the standard slope N-1 Counter2 is used to store and output the second code QX0~QX corresponding to the full-scale slope. N-1 Counter3 is used to store and output the third code QY0~QY corresponding to the adaptive slope. N-1 The N three-to-one selectors are used to select any one of the N-bit codes in Counter1 to Counter3 and input it into the N-bit decoder. The N-bit decoder is used to decode the received N-bit code and generate a control signal for controlling the switch state of the 2M transmission gates in the switch array.

[0093] In the solution of this embodiment, for a specified CMOS chip, the standard slope and full-scale slope used are actually predetermined according to design parameters. Therefore, the N-bit first codes QZ0 to QZ1 stored in counters Counter1 and Counter2 are N-1 And the second code QX0~QX N-1 In fact, they are fixed codes, and they remain unchanged during the circuit application process. Counter3 stores the third code QY0~QY N-1 The global judgment module needs to make dynamic adjustments based on the determined swing range of the adaptive slope.

[0094] Specifically, the global judgment module determines whether secondary quantization is required after each completion of primary quantization, and determines the amplitude range of the ramp signal used for secondary quantization. At this time, the global judgment unit rewrites the third codes QY0~QY0 stored in Counter3 according to the amplitude range. N-1 The N-bit decoder then decodes the control code for switching the switch state of the switch array according to the rewritten third code; after the switch array in the ramp generator is switched, the required adaptive ramp can be generated.

[0095] exist Figure 4 The ramp modulation module, each three-to-one selector is composed of two two-to-one selectors mux1 and mux2. Each three-to-one selector is used to select one of the first code, the second code or the third code. Among them, the two input ends of mux1 are connected to QXi and QYi respectively, and the output end is connected to an input end of mux2; the other input end of mux2 is connected to QZi; i=1...N; the control end signal of mux1 is recorded as CTRL, and the control end of mux2 is connected to the selection signal Q.

[0096] It can be seen that the slope modulation module controls two groups of three-to-one selectors connected to the output ends of three counters through two control signals Q and CTRL, respectively generating a standard slope, a full-scale slope, and an adaptive slope for the CMS stage. Among them, when Q=1, the counter corresponding to the standard slope required for the reset signal quantization is selected, and when Q=0, the counter corresponding to the full-scale slope or adaptive slope required for the pixel signal quantization stage is selected. Further, when Q=0 and CTRL=1, the counter corresponding to the adaptive slope in the CMS stage is selected. When Q=0 and CTRL=0, the counter corresponding to the full-scale slope required for the primary quantization stage is selected.

[0097] 3. Global judgment module

[0098] In this embodiment, the global judgment module is used, on the one hand, to judge the maximum and minimum values ​​of the primary quantization results of the current row based on the outputs of each comparator; on the other hand, it is used to generate a flag signal indicating whether the CMS stage needs to be executed, and to generate a third code of the adaptive slope to be used in the CMS stage.

[0099] Specifically, Figure 5 As shown in FIG. 1 , the global judgment module includes a maximum value query unit and a minimum value query unit. The maximum value query unit is composed of an N-level AND gate, an N-bit counter CounterX, and a subtractor Sub. The N input terminals of AND are respectively connected to the outputs C0 to C1 of the comparator in the CMS quantization module of each column. n-1 The output of AND is connected to the input of CounterX, and the input of CounterX is connected to the input of Sub; the output of Sub is used to output the maximum value of the primary quantization results of each pixel unit in the same row. The output of the N-stage AND gate AND is recorded as the enable signal EN1.

[0100] Correspondingly, the minimum value query unit is composed of an N-level OR gate and an N-bit counter CounterY. The N input terminals of OR are respectively connected to the outputs C0~C1 of the comparator in the CMS quantization module of each column. n-1 The output of OR is connected to the input of CounterY, and the output of CounterY is used to output the minimum value of the primary quantization results of each pixel unit in the same row. The output of the N-stage OR gate OR is recorded as the enable signal EN2.

[0101] The output of the N-level AND gate is the output of the column-level comparator corresponding to the smallest pixel signal in a row, and the output of the N-input OR gate is the output of the column-level comparator corresponding to the largest pixel signal in a row. At the same time, the outputs of these two logic gates will serve as the enable signals EN1 and EN2 of two independent counters Counter X and Counter Y in the circuit. At the beginning of the primary quantization stage, Counter X and Counter Y start counting synchronously from 0. When EN1 and EN2 change from high level to low level, the output of the counter is latched and recorded as the digital code corresponding to the minimum and maximum values ​​of the pixel signal in a row. These two digital code values ​​can determine the starting and end points of the adaptive slope through a certain logic circuit, and then generate the corresponding third code.

[0102] 4. Column-level judgment module

[0103] In the CMS quantization module, the column-level judgment module is composed of the output of the counter of each column and the corresponding combinational logic circuit. lt Set to V FS / 2, the primary quantization voltage is lower than V FS / The illumination in area 2 is low and the voltage value is higher than V FS After the primary quantization stage is completed, the column-level judgment model determines the interval to which the quantization voltage of the pixel unit belongs to determine whether it needs to perform a CMS operation.

[0104] In practical applications, taking 10-bit quantization accuracy as an example, the column-level judgment module determines whether each column needs to perform a CMS operation on the pixel signal by analyzing the value of the highest bit D9 of the counter of each column, and determines the number of sampling and quantization. The process includes:

[0105] The highest bit of each column counter is defined as D9. When Vsig>V FS / 2, that is, when D9=1, it can be determined that the quantized signal voltage is large at this time, and the sensor is in a high illumination, so only primary quantization sampling is performed, and CMS operation is not performed. FS / 2, that is, when D9=0, it can be determined that the quantized signal voltage is small at this time, the current column of the sensor is in a low illumination, and multiple rounds of CMS operations are required. In this embodiment, the iteration rounds of the CMS operation are uniformly set to 4.

[0106] In this embodiment, the global judgment module and the column-level judgment module jointly determine the waveform of the ramp and the timing of the circuit. When the highest bit D9 of the counter of a column in a row is 0, it not only indicates that the current column is in a low illumination and needs to be correlated multi-sampling, but also means that at least one pixel unit in this row is in a low illumination, that is, the pixel signal in a row must have a minimum voltage value MIN<V FS / 2, so the ramp generator will generate an adaptive ramp in the CMS phase after the primary quantization phase of the full-scale ramp is completed. When the highest bit D9 of each counter in the same row is 1, it means that every pixel unit in this row is at a high illumination, that is: MIN>VFS / 2, so only the primary quantization needs to be completed.

[0107] 5. Process Management Module

[0108] In a further optimized solution of this embodiment, the single slope ADC also includes a process management module. Figure 6 As shown, the process management module is used to switch different stages in the full quantization cycle of the pixel array. The process management module includes a two-to-one selector mux0 and a T trigger T0. The two input terminals of mux0 are respectively connected to the end signal p of the reset signal quantization stage and the end signal q of the pixel secondary quantization stage. The output terminal of mux0 is connected to the clock port of T0; the control terminal of mux0 is connected to the Q terminal of T0; and the T terminal of T0 is connected to a high level signal. In the process management module, p and q jointly generate the selection signal Q output to the ramp modulation unit.

[0109] Figure 6 The process management module shown is Figure 1 The process management strategy of the full quantization stage of the single slope ADC based on the forward-looking adaptive CMS technology is as follows:

[0110] Under the initial condition, the clock terminal is connected to p. At the end of the reset signal quantization stage, p jumps from 0 to 1, and then jumps to 0 after a certain delay, generating a rising edge as the trigger signal of TFF. Since the value of the output terminal flips when T=1, the control clock terminal changes from connection p to connection q. Similarly, when the pixel signal quantization stage ends, q jumps from 0 to 1, and then jumps to 0 after a certain delay, generating the same rising edge, and the value of the output terminal flips again, that is, the control clock terminal returns to the state of connection p. At this time, the reset signal and pixel signal in a row have completed quantization, which means that a complete quantization cycle of each pixel unit in one row of the pixel array has ended, and the reset signal quantization stage of the next row of pixel units in the pixel array will enter.

[0111] In CMOS, each pixel unit outputs a unit signal V sig By the reset signal V rst and pixel signal V pixel It consists of two parts; when SS ADC quantizes, it needs to quantize the reset signal first, then quantize the pixel signal, and then determine the final quantization value of each pixel unit based on the quantization results of the two.

[0112] Therefore, based on the hardware solution of the single slope ADC based on the forward-looking adaptive CMS technology designed in this embodiment, as shown in FIG. Figure 7 Shown and Figure 8 As shown, it realizes the unit signal V output by each pixel unit in the pixel array. sig The quantification process is as follows:

[0113] 1. Reset signal quantization stage

[0114] The ramp modulation module controls the ramp generator to generate a ramp signal V with a standard ramp. ramp ; The comparators in each CMS quantization module on the same row use V ramp V for pixel unit output rst Multiple rounds of prequantization are performed and the prequantization results are stored in a counter.

[0115] 2. Primary pixel quantization stage

[0116] The ramp modulation module controls the ramp generator to generate a ramp signal V with a full-scale ramp. ramp ; The comparators in each CMS quantization module on the same row use V ramp V for pixel unit output pixel Perform primary quantization; the primary quantization result is stored in the counter.

[0117] 3. Light intensity judgment stage

[0118] The global judgment module determines V according to the primary quantization results. max and V min , and then combined with the preset light threshold V lt Make the following decisions:

[0119] (1) When V lt ≤V min , the quantization process of the current row is terminated, and the adder-subtractor generates the output value of each pixel unit according to the pre-quantization and primary quantization results in the counter.

[0120] (2) When V min ≤V lt ≤V max , then enter the pixel secondary quantization stage; at the same time (V min, , V lt ) is used as the swing interval of the adaptive slope in the secondary quantization and is sent to the slope modulation module.

[0121] (3) When V max ≤V lt , then enter the pixel secondary quantization stage; at the same time (V min, , V max ) is used as the swing interval of the adaptive slope in the secondary quantization and is sent to the slope modulation module.

[0122] 4. Pixel sub-quantization stage

[0123] The ramp modulation module controls the ramp generator to generate a ramp signal V with an adaptive ramp. ramp The column-level judgment module determines in turn whether the primary quantization results of each column of pixel units in the current row exceed the illumination threshold V lt :

[0124] (I) If yes, the primary quantization result is used as the secondary quantization result;

[0125] (Ⅱ) Otherwise, the comparator uses V ramp V for pixel unit output pixel Perform multiple rounds of secondary quantification;

[0126] The adder-subtractor takes the average of multiple rounds of secondary quantization as the final result of secondary quantization;

[0127] Finally, the adder-subtractor generates the output value of each pixel unit according to the pre-quantization and sub-quantization results in the counter.

[0128] Example 2

[0129] The solution of Example 1 is mainly used to quantize and output the detection signal of the CMOS sensor. The single-slope ADC based on the forward-looking adaptive CMS technology is usually integrated into the corresponding CIS chip in practical applications. Therefore, this embodiment further provides a CIS chip, which includes a CMOS pixel array. In particular, the CIS chip adopts the single-slope ADC based on the forward-looking adaptive CMS technology as in Example 1, and works according to the specified quantization strategy.

[0130] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.< / n> < / n>

Claims

1. A single slope ADC based on forward-looking adaptive CMS technology, comprising CMS quantization modules connected to each column in a pixel array; the CMS quantization modules complete the unit signal V output by each pixel unit in the pixel array based on correlated multi-sampling technology and through a row-by-row scanning method. sig Quantization is performed; each of the CMS quantization modules includes a comparator, a counter, a column-level judgment module and an adder-subtractor; It is characterized in that It also includes a dynamic slope generation module; the dynamic slope generation module includes a slope generator, a slope modulation module and a global judgment module; The ramp generator is used to generate a ramp signal V corresponding to a standard ramp, a full-scale ramp or an adaptive ramp according to the received modulation signal. ramp , and sent to the comparator of the corresponding row; The global judgment module is used to obtain the primary quantization results of each pixel unit in the same row and identify the maximum value V max and minimum value V min , and according to the preset light threshold V lt Make the following decisions: (1) When V lt ≤V min , then an end instruction is generated to terminate the secondary quantization process of the current row; (2) when V min ≤V lt ≤V max , then (V min, , V lt ) as the swing interval of the adaptive ramp in the secondary quantization and sent to the ramp modulation module; (3) when V max ≤V lt , then (V min, , V max ) as the swing interval of the adaptive slope in the secondary quantization, and sent to the ramp modulation module; The slope modulation module is used to: output a first modulation signal for generating the standard slope in the reset signal quantization stage, output a second modulation signal for generating the full-scale slope in the pixel primary quantization stage, and output a third modulation signal for generating an adaptive slope with a specified swing amplitude in the illumination judgment stage.

2. The single slope ADC based on the forward-looking adaptive CMS technology according to claim 1, characterized in that: The standard ramp includes a plurality of continuous ramps within a specified swing range and is used to quantize the reset signal V output by the pixel unit. rst The full-scale slope includes an upper limit corresponding to the range voltage V FS A slope, and used to output the pixel signal V of each pixel unit pixel The adaptive slope includes a plurality of continuous slopes located in the adaptive swing range, and is used to adjust the pixel unit output below the illumination threshold V lt The pixel signal V pixel Multiple rounds of secondary quantification were performed.

3. The single slope ADC based on the forward-looking adaptive CMS technique as claimed in claim 1, characterized in that: The ramp generator includes a current steering DAC that uses a combination of thermometer code and binary code, a negative feedback circuit and a unity gain buffer; the current steering DAC is composed of multiple current sources, a switch array, a positive terminal resistor R1, and a negative terminal resistor R2; the negative feedback circuit is connected at the intersection of R1 and R2, thereby clamping the initial voltage of the ramp to a fixed value V x The unit gain buffer is connected between the negative terminal resistor and the current source of the final stage, and then outputs V x The ramp signal V ramp ; By adjusting the preset fixed value V in the negative feedback circuit x and the switch state of the switch array in the current steering DAC, so as to realize the output of the ramp signal V to the ramp generator. ramp The swing range can be adjusted.

4. The single slope ADC based on the forward-looking adaptive CMS technique as claimed in claim 3, characterized in that: In the current steering DAC, there are M current sources; the switch array is composed of 2M transmission gates, M of which are used to connect the output end of each current source with the upper end of R1, and the other M transmission gates are used to connect the output end of each current source with the upper end of R2; the lower ends of R1 and R2 are connected; and / or The negative feedback circuit is composed of an operational amplifier A1, an NMOS tube N0 and a capacitor C0; wherein the negative input terminal of A1 is connected to V x ; The positive input terminal of A1, the drain of N0 and one end of C0 are connected to the lower ends of R1 and R2; the output terminal of A1 is connected to the other end of C0 and the gate of N0; the source of N0 is grounded; and / or The unit gain buffer uses an operational amplifier A2; the positive input terminal of A2 is connected to the upper end of R2; the negative input terminal of A2 is connected to the output terminal and is used to output a ramp signal V ramp .

5. The single slope ADC based on the forward-looking adaptive CMS technique as claimed in claim 4, characterized in that: The ramp modulation module includes three counters Counter1 to Counter3, N three-to-one selectors MUX <1> ~MUX <n> , and an N-bit decoder; wherein N corresponds to the quantization accuracy of the single slope ADC;< / n> Counter1 is used to store and output the first code QZ0~QZ corresponding to the standard slope N-1 ; Counter2 is used to store and output the second code QX0~QX corresponding to the full-scale slope N-1 ; Counter3 is used to store and output the third code QY0~QY corresponding to the adaptive slope N-1 ; N three-to-one selectors are used to select any one of the N-bit codes in Counter1~Counter3 and input it into the N-bit decoder; the N-bit decoder is used to decode the received N-bit code and then generate a control signal for controlling the switch state of the 2M transmission gates in the switch array.

6. The single slope ADC based on the forward-looking adaptive CMS technique as claimed in claim 5, characterized in that: The three-to-one selector is composed of two two-to-one selectors mux1 and mux2; each three-to-one selector is used to select one of the first code, the second code or the third code; wherein, the two input ends of mux1 are respectively connected to QXi and QYi, and the output end is connected to an input end of mux2; the other input end of mux2 is connected to QZi; i=1…N; the control end signal of mux1 is recorded as CTRL, and the control end of mux2 is connected to the selection signal Q.

7. The single slope ADC based on the forward-looking adaptive CMS technique as claimed in claim 6, characterized in that: The global judgment module includes a maximum value query unit and a minimum value query unit; The maximum value query unit is composed of an N-level AND gate, an N-bit counter CounterX and a subtractor Sub; the N input ends of the AND are respectively connected to the outputs C0 to C1 of the comparator in the CMS quantization module of each column. n-1 , n represents the number of CMS quantization modules; the output terminal of AND is connected to the input terminal of CounterX, and the input terminal of CounterX is connected to the input terminal of Sub; the output terminal of Sub is used to output the maximum value of the primary quantization results of each pixel unit in the same row; The minimum value query unit is composed of an N-level OR gate and an N-bit counter CounterY; the N input ends of the OR are respectively connected to the outputs C0 to C1 of the comparator in the CMS quantization module of each column. n-1 The output end of OR is connected to the input end of CounterY, and the output end of CounterY is used to output the minimum value of the primary quantization results of each pixel unit in the same row.

8. The single slope ADC based on the forward-looking adaptive CMS technique as claimed in claim 7, characterized in that: The single slope ADC further comprises a process management module, the process management module is used to switch different phases in the full quantization cycle of the pixel array; the process management module comprises a two-to-one selector mux0 and a T trigger T0; The two input terminals of mux0 are respectively connected to the end signal p of the reset signal quantization stage and the end signal q of the pixel secondary quantization stage; the output terminal of mux0 is connected to the clock port of T0; the control terminal of mux0 is connected to the Q terminal of T0; the T terminal of T0 is connected to the high level signal; in the process management module, p and q jointly generate the selection signal Q output to the ramp modulation unit.

9. The single slope ADC based on the forward-looking adaptive CMS technique according to any one of claims 1 to 8, characterized in that: Unit signal V sig By the reset signal V rst and pixel signal V pixel The single slope ADC realizes the output of the unit signal V of the pixel array sig The quantification process is as follows:

1. Reset signal quantization stage The ramp modulation module controls the ramp generator to generate a ramp signal V with a standard ramp. ramp ; The comparators in each CMS quantization module on the same row use V ramp V for pixel unit output rst Perform multiple rounds of pre-quantization, and store the pre-quantization results in a counter; 2. Primary pixel quantization stage The ramp modulation module controls the ramp generator to generate a ramp signal V with a full-scale ramp. ramp ; The comparators in each CMS quantization module on the same row use V ramp V for pixel unit output pixel Perform primary quantization; store the primary quantization result in a counter; 3. Light intensity judgment stage The global judgment module determines V according to the primary quantization results. max and V min , and then combined with the preset light threshold V lt Make the following decisions: (1) When V lt ≤V min , the quantization process of the current row is terminated, and the adder-subtractor generates the output value of each pixel unit according to the pre-quantization and primary quantization results in the counter; (2) When V min ≤V lt ≤V max , then enter the pixel secondary quantization stage; at the same time (V min, , V lt ) as the swing interval of the adaptive ramp in the secondary quantization and sent to the ramp modulation module; (3) When V max ≤V lt , then enter the pixel secondary quantization stage; at the same time (V min, , V max ) as the swing interval of the adaptive slope in the secondary quantization, and sent to the ramp modulation module; 4. Pixel sub-quantization stage Determine whether the primary quantization results of each column of pixel units in the current row exceed the light threshold V lt : If yes, the primary quantification result is used as the secondary quantification result; Otherwise, the comparator uses V ramp V for pixel unit output pixel Perform multiple rounds of secondary quantization, and use the average of the multiple rounds of secondary quantization as the final result of the secondary quantization; The adder-subtractor generates the output value of each pixel unit according to the pre-quantization and sub-quantization results in the counter.

10. A CIS chip comprising a pixel array, characterized in that: It also adopts a single slope ADC based on the look-ahead adaptive CMS technology as described in any one of claims 1-9.

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