Interrupt management method and device, computer equipment and computer readable storage medium
By configuring multi-bit interrupt masking registers and spliced signals for interrupt sources for logical operations, the redundant logic and fixed mode of interrupt numbers are solved, and flexible selection of interrupt sources and efficient utilization of resources are achieved.
Patent Information
- Application Number
- CN202410990992.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-23
- Publication Date
- 2024-12-24
AI Technical Summary
In the existing design, interrupts of interrupt numbers may come from multiple interrupt sources, and the same interrupt source needs to be sent to different interrupt numbers, resulting in an increase in redundant logic, making it impossible to achieve flexible selection of interrupt sources, and the design tends to be fixed mode and cannot adapt. Efficient utilization of resource requirements.
By configuring multi-bit interrupt mask registers for N interrupt sources, the N bits of each interrupt mask register correspond to N interrupt sources, the interrupt request is filtered based on the interrupt mask register to form a multi-bit splicing signal for Logic and operation realize the flexible selection of interrupt numbers for any interrupt source.
It reduces redundant logic, realizes flexible selection of interrupt sources, adapts to different systems and ecology, reduces resource overhead, and simplifies logical design.
Smart Images
Figure CN119179556A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of interrupt management, and in particular to an interrupt management method, apparatus, computer device, and computer-readable storage medium. Background Art
[0002] In many designs, each interrupt number may come from multiple interrupt sources. In some designs, the same interrupt source needs to be sent to different interrupt numbers, which requires targeted processing of each interrupt. At this time, a lot of redundant logic is often added to implement it. In the context of increasing resource requirements, how to reduce resource overhead is particularly important. In addition, existing designs usually tend to be fixed modes and cannot achieve flexible selection of interrupt sources. Summary of the invention
[0003] The embodiments of the present application provide an interrupt management method, apparatus, computer device, computer-readable storage medium, and computer program product, which can solve the above-mentioned problem of excessive redundant logic and easily realize flexible selection of interrupt sources.
[0004] In view of this, in a first aspect, an embodiment of the present application provides an interrupt management method, including:
[0005] Creating a multi-bit interrupt mask register for each of the multiple interrupt numbers configured for the N interrupt sources, wherein the N bits of each interrupt mask register correspond to the N interrupt sources, where N is a plurality;
[0006] Interrupt requests are screened based on each of the interrupt mask registers to obtain a valid interrupt request for each of the interrupt numbers.
[0007] In one embodiment, the method further comprises:
[0008] Splicing the N interrupt sources to form a multi-bit splicing signal, wherein each of the interrupt sources corresponds to a bit of the splicing signal;
[0009] The screening of the interrupt request based on each of the interrupt mask registers to obtain a valid interrupt request for each of the interrupt numbers comprises:
[0010] The N bits of each interrupt mask register are respectively subjected to a logic AND operation with the corresponding N bits of the splicing signal, and a valid interrupt request of each interrupt number is obtained based on the result of the logic AND operation.
[0011] In one embodiment, the N interrupt sources are of the same type.
[0012] In one embodiment, the N interrupt sources are level-type interrupt sources or pulse-type interrupt sources.
[0013] In one embodiment, the N interrupt sources are high-level effective level-type interrupt sources, low-level effective level-type interrupt sources, rising-edge triggered pulse-type interrupt sources, or falling-edge triggered pulse-type interrupt sources.
[0014] In one embodiment, before splicing the N interrupt sources, the method further includes:
[0015] The interrupt sources belonging to different types are normalized to obtain the N interrupt sources of the same type.
[0016] In one embodiment, before splicing the N interrupt sources, the method further includes:
[0017] The N interrupt sources of level type and the N interrupt sources of pulse type are obtained by processing the N interrupt sources.
[0018] In one embodiment, the logical AND operation is a bitwise AND operation.
[0019] In one embodiment, obtaining a valid interrupt request for each interrupt number based on the result of the logic AND operation includes:
[0020] performing a logical OR operation on the results of the logical AND operation;
[0021] A valid interrupt request corresponding to the interrupt number is obtained based on the result of the logic OR operation.
[0022] In one embodiment, the method further comprises:
[0023] Establishing a resource pool, wherein a plurality of interruption events are stored in the resource pool;
[0024] The interrupt source is updated based on the interrupt event in the resource pool.
[0025] In a second aspect, an embodiment of the present application further provides an interrupt management device, including:
[0026] A creation module, used for creating a multi-bit interrupt mask register for each of the multiple interrupt numbers configured for the N interrupt sources, wherein the N bits of each of the interrupt mask registers correspond to the N interrupt sources, and N is multiple;
[0027] The screening module is used to screen the interrupt request based on each of the interrupt mask registers to obtain a valid interrupt request of each of the interrupt numbers.
[0028] In a third aspect, an embodiment of the present application further provides a computer device, including a memory and a processor;
[0029] The memory is connected to the processor, the memory is used to store a computer program, and the processor is used to call the computer program so that the computer device executes the interrupt management method described in any one of the first aspects.
[0030] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is suitable for being loaded by a processor and executing the interrupt management method described in any one of the first aspects.
[0031] In a fifth aspect, an embodiment of the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of any one of the methods described in the first aspect.
[0032] The above-mentioned interrupt management method, device, computer equipment, computer-readable storage medium and computer program product create a multi-bit interrupt mask register for each of the multiple interrupt numbers configured for N interrupt sources, and the N bits of each interrupt mask register correspond to the N interrupt sources, so that each interrupt number can correspond to all interrupt sources, and each interrupt source can correspond to all interrupt numbers. On the basis of pre-configuring each interrupt mask register as needed, the interrupt request is screened based on each interrupt mask register, so that each interrupt number can easily select any at least one interrupt source, which is conducive to adapting to different systems / ecosystems. Moreover, whether the interrupt of each interrupt number comes from multiple interrupt sources, or the same interrupt source needs to be sent to different interrupt numbers, it is easy to filter the respective interrupt requests based on each interrupt mask register, so that the implementation logic is simple, which is conducive to avoiding excessive redundant logic and reducing resource overhead. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 Schematic diagram of the interrupt management method provided in the embodiment of the present application Figure 1 .
[0034] Figure 2 This is a flow diagram of the interrupt management method provided in the embodiment of the present application. Figure 2 .
[0035] Figure 3 It is a schematic diagram of performing a logical AND operation on the interrupt mask register and the splicing signal and then performing a logical OR operation in an embodiment of the present application.
[0036] Figure 4 This is a schematic diagram of an interrupt management method based on a pulse interrupt source in an embodiment of the present application. Figure 1 .
[0037] Figure 5 This is a schematic diagram of an interrupt management method based on a level-type interrupt source in an embodiment of the present application. Figure 1 .
[0038] Figure 6 This is a flow diagram of the interrupt management method provided in the embodiment of the present application. Figure 3 .
[0039] Figure 7 This is a schematic diagram of an interrupt management method based on a pulse interrupt source in an embodiment of the present application. Figure 2 .
[0040] Figure 8 This is a schematic diagram of an interrupt management method based on a level-type interrupt source in an embodiment of the present application. Figure 2 .
[0041] Fig. 9 This is a flow diagram of the interrupt management method provided in the embodiment of the present application. Figure 4 .
[0042] Fig.10 It is a schematic diagram of an embodiment of the present application in which an interrupt management method is executed based on a level-type interrupt source and a pulse-type interrupt source respectively.
[0043] Fig.11 Schematic diagram of the interrupt management device provided in the embodiment of the present application Figure 1 .
[0044] Fig.12 Schematic diagram of the interrupt management device provided in the embodiment of the present application Figure 2 .
[0045] Fig.13 Schematic diagram of the interrupt management device provided in the embodiment of the present application Figure 3 .
[0046] Fig.14 Schematic diagram of the interrupt management device provided in the embodiment of the present application Figure 4 .
[0047] Fig.15 A schematic diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0048] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0049] Interrupt handling refers to a mechanism in a computer system that responds to external events or hardware exceptions. When an interrupt occurs in the system, the CPU will pause the currently executed command and execute the interrupt-related handler instead. Interrupt handling can be applied to handle various events, such as hardware failures, input / output requests, etc. Interrupt handling helps improve the system's responsiveness and processing complexity.
[0050] Especially in fields such as cloud computing, interrupt design is particularly important. As an important part of the RAS mechanism, it is crucial to the reliability, stability and maintainability of the entire system.
[0051] The interrupt number plays a key role in the interrupt processing of the computer system. It is a number used by the system to identify and distinguish different interrupt sources. When a hardware device or software requires the CPU's immediate attention to handle certain events, such as completing an input / output operation, an error, or reaching a timer setting value, an interrupt request with a specific interrupt number is sent to the CPU.
[0052] At present, in many designs, the interrupt of each interrupt number may come from multiple interrupt sources, and in some designs, the same interrupt source needs to be sent to different interrupt numbers, which requires targeted processing of each interrupt, and at this time, a lot of redundant logic is often added to implement it. In the context of increasing resource requirements, how to reduce resource overhead is particularly important. Furthermore, existing designs usually tend to be fixed modes, and it is impossible to achieve flexible selection of interrupt sources. To this end, an embodiment of the present application provides an interrupt management solution that can solve the above-mentioned problems of more redundant logic and inability to flexibly select interrupt sources.
[0053] See also Figure 1 , the embodiment of the present application discloses an interrupt management method, including:
[0054] S103, creating a multi-bit interrupt mask register for each of the multiple interrupt numbers configured for the N interrupt sources, wherein the N bits of each interrupt mask register correspond to the N interrupt sources, where N is a plurality.
[0055] Assume that 10 interrupt numbers are configured for N interrupt sources, and a multi-bit interrupt mask register is created for each of the 10 interrupt numbers, which means that there are 10 interrupt mask registers corresponding to the 10 interrupt numbers.
[0056] It is understandable that the interrupt mask register may be an N-bit interrupt mask register or an interrupt mask register greater than N bits. When the interrupt mask register is an interrupt mask register greater than N bits, optionally, the consecutive N bits of the interrupt mask register correspond to N interrupt sources respectively, but are not limited to this.
[0057] S104, screening the interrupt requests based on each interrupt mask register to obtain a valid interrupt request for each interrupt number.
[0058] Regarding how to use the interrupt mask register to filter interrupt requests, the method in the embodiment detailed below in this application can be used, that is, first splicing N interrupt sources, and then performing logical AND operations based on the N bits of the interrupt mask register and the corresponding N bits of the splicing signal, etc. Of course, it is not limited to this, and other methods can be used for filtering, which can be based on existing filtering methods. For example, according to the situation, logical AND operations can be directly performed with each independent interrupt source respectively, which will not be described in detail here.
[0059] The "interrupt request" here refers to all interrupt requests from N interrupt sources. For example, if there are 4 interrupt sources corresponding to 4 bits of the interrupt mask register, the first interrupt source and the fourth interrupt source are triggered, forming two interrupt requests, and after screening by the interrupt mask register, one interrupt request is passed. It can be understood that after screening by the interrupt mask register, all interrupt requests may be masked, that is, there is no valid interrupt request.
[0060] The hardware can set the default interrupt mask register value. If different software or ecosystems need to change the interrupt information on each interrupt number, the interrupt mask register can be set as needed before the system starts.
[0061] Application examples:
[0062] Scenario: If a system has 100 interrupt sources, but only 10 interrupt numbers can be used, and after the interrupt numbers are applied to different devices, the information about the expected interrupt numbers of different devices is not fixed.
[0063] Implementation: For any device, you can select the desired interrupt source by configuring the interrupt mask register of each interrupt number according to your needs. For example, if interrupt number M[0] only wants to see events from interrupt source 99, you can set the 99th bit of its corresponding interrupt mask register to 0, and the remaining bits are set to 1 by default. If in other application scenarios, interrupt number M[0] only wants to see events from interrupt source 9, you can set the 9th bit of its corresponding interrupt mask register to 0, and the remaining bits are set to 1 by default.
[0064] In the embodiment of the present application, a multi-bit interrupt mask register is created for each of the multiple interrupt numbers configured for N interrupt sources. The N bits of each interrupt mask register correspond to the N interrupt sources, so that each interrupt number can correspond to all interrupt sources, and each interrupt source can correspond to all interrupt numbers. On the basis of pre-configuring each interrupt mask register as needed, the interrupt requests are screened based on each interrupt mask register, so that each interrupt number can easily select any at least one interrupt source flexibly, which is conducive to adapting to different systems / ecosystems. Moreover, whether the interrupt of each interrupt number comes from multiple interrupt sources or the same interrupt source needs to be sent to different interrupt numbers, it is easy to filter the respective interrupt requests based on each interrupt mask register, which makes the implementation logic simple, which is conducive to avoiding excessive redundant logic and reducing resource overhead.
[0065] Please combine Figure 2 In one embodiment, the interrupt management method further includes:
[0066] S102, splicing N interrupt sources to form a multi-bit splicing signal, wherein each interrupt source corresponds to a bit of the splicing signal. That is, there is a one-to-one correspondence between the N bits of the splicing signal corresponding to the N interrupt sources and the N bits of the interrupt mask register.
[0067] It can be understood that, in this embodiment, the execution order of step S102 and step S103 is not limited, and the accompanying drawings only show an example for the convenience of intuitive display.
[0068] It is understandable that the spliced signal may have more than N bits, in which case the N interrupt sources may occupy N consecutive bits, but is not limited thereto. For example, the real-time value of the N consecutive bits occupied by the N interrupt sources in the spliced signal formed by splicing 8 interrupt sources is 10010010.
[0069] Specifically, the spliced signal is a bus signal.
[0070] Specifically, the N interrupt sources are of the same type, so as to facilitate splicing and subsequent logic calculation, but the present invention is not limited thereto. The N interrupt sources of the same type may be level interrupt sources or pulse interrupt sources.
[0071] Specifically, the N interrupt sources are high-level effective level interrupt sources. Since the N interrupt sources are all high-level effective level interrupt sources, it is convenient to perform a logical AND operation on the subsequent splicing signal and the corresponding interrupt mask register.
[0072] Specifically, the N interrupt sources are low-level effective level interrupt sources. Since the N interrupt sources are low-level effective level interrupt sources, it is convenient to perform a logical AND operation on the subsequent splicing signal and the corresponding interrupt mask register.
[0073] Specifically, the N interrupt sources are pulse interrupt sources triggered by a rising edge. Since the N interrupt sources are all pulse interrupt sources triggered by a rising edge, it is convenient to perform a logic AND operation on the subsequent splicing signal and the corresponding interrupt mask register.
[0074] Specifically, the N interrupt sources are pulse interrupt sources triggered by falling edges. Since the N interrupt sources are all pulse interrupt sources triggered by falling edges, it is convenient to perform a logic AND operation on the subsequent splicing signal and the corresponding interrupt mask register.
[0075] Interrupt requests are screened based on each interrupt mask register, and valid interrupt requests for each interrupt number include:
[0076] S1041, performing a logic AND operation on the N bits of each interrupt mask register and the corresponding N bits of the splicing signal, and obtaining a valid interrupt request for each interrupt number based on the result of the logic AND operation.
[0077] Specifically, the logical AND operation is a bitwise AND operation. On the basis of pre-configuring each interrupt mask register as needed, after performing a bitwise AND operation based on each interrupt mask register and the splicing signal, it is easy to realize the flexible selection of at least one interrupt source for each interrupt number, and whether the interrupt of each interrupt number comes from multiple interrupt sources, or the same interrupt source needs to be sent to different interrupt numbers, the bitwise AND operation based on each interrupt mask register and the splicing signal can be more easily realized, and the realization logic is simple.
[0078] Optionally, the interrupt mask register and the splicing signal can be bitwise ANDed without any processing, but it is not limited to this. For example, the interrupt mask register or the splicing signal can be bitwise ANDed after being inverted, etc.
[0079] It can be understood that, in this embodiment, the logical AND operation is not limited to a bitwise AND operation.
[0080] Specifically, obtaining a valid interrupt request for each interrupt number based on the result of the logic AND operation includes:
[0081] Perform a logical OR operation on the results of the logical AND operation;
[0082] Based on the result of the logical OR operation, a valid interrupt request of the corresponding interrupt number is obtained.
[0083] Please combine Figure 3, which provides a schematic diagram of performing a logical AND operation on an interrupt mask register and a splicing signal and then performing a logical OR operation. It is understandable that after performing a logical AND operation, it is not limited to performing a logical OR operation to obtain a valid interrupt request corresponding to the interrupt number.
[0084] Exemplarily, the data 1010 of the real-time splicing signal int_s[3:0] and the data 1001 of the interrupt mask register mask[3:0] are bitwise ANDed to obtain 1000, and then logically ORed to obtain a valid interrupt request from the interrupt source int_s0, that is, the interrupt corresponding to the corresponding interrupt number at this moment that needs to be processed comes from the interrupt source int_s0.
[0085] In order to better understand the above embodiments, Figure 4 and Figure 5 Further exemplary description is given.
[0086] Figure 4 In the example, N pulse interrupt sources int_s0, int_s1, int_s2, ... int_sN are spliced to form a multi-bit spliced signal primary_pulse_ints[N-1:0], where each interrupt source corresponds to a bit of the spliced signal primary_pulse_ints[N-1:0]. The interrupt number M configured for the N pulse interrupt sources int_s0, int_s1, int_s2, ... int_sN is p [0], M p [1] M p [2]……M p [M-1] creates a multi-bit interrupt mask register mask[0][N-1:0], mask[1][N-1:0], mask[2][N-1:0]...mask[M-1][N-1:0]. The N bits of each interrupt mask register correspond to the bits of the splicing signal primary_pulse_ints[N-1:0] corresponding to the pulse interrupt sources int_s0, int_s1, int_s2...int_sN. Then each interrupt mask register is logically ANDed with the splicing signal primary_pulse_ints[N-1:0], and then the valid interrupt request of each interrupt number can be obtained based on the result of the logical AND operation, for example, the valid interrupt request is the interrupt request from the pulse interrupt sources int_s0 and int_s5.
[0087] Figure 5In the example, N level interrupt sources int_s0, int_s1, int_s2, ... int_sN are spliced to form a multi-bit splicing signal primary_level_ints[N-1:0], where each interrupt source corresponds to a bit of the splicing signal primary_level_ints[N-1:0]. The interrupt number M configured for N level interrupt sources int_s0, int_s1, int_s2, ... int_sN l [0], M l [1] M l [2]……M l [M-1] creates a multi-bit interrupt mask register mask[0][N-1:0], mask[1][N-1:0], mask[2][N-1:0]...mask[M-1][N-1:0]. The N bits of each interrupt mask register correspond to the bits of the splicing signal primary_level_ints[N-1:0] corresponding to the level-type interrupt sources int_s0, int_s1, int_s2...int_sN. Then, each interrupt mask register is logically ANDed with the splicing signal primary_level_ints[N-1:0], and then the valid interrupt request of each interrupt number can be obtained based on the result of the logical AND operation, for example, the valid interrupt request is the interrupt request from the level-type interrupt sources int_s1 and int_s6.
[0088] In a system, a group of level interrupt sources int_s0, int_s1, int_s2...int_sN and a group of pulse interrupt sources int_s0, int_s1, int_s2...int_sN that represent events that are completely consistent can be formed through conversion. Figure 1 and Figure 2 Perform interrupt management.
[0089] See also Figure 6 Specifically, before splicing the N interrupt sources, the interrupt management method further includes:
[0090] S101, normalizing interrupt sources of different types to obtain N interrupt sources of the same type.
[0091] In actual situations, the types of interrupt sources in a system are usually different. To facilitate subsequent processing, the types of interrupt sources may be unified before splicing, but the present invention is not limited thereto.
[0092] When both level-type interrupt sources and pulse-type interrupt sources are included, each level-type interrupt source can be converted into a pulse-type interrupt source so that each interrupt source is unified into a pulse-type interrupt source, or each pulse-type interrupt source can be converted into a level-type interrupt source so that each interrupt source is unified into a level-type interrupt source. Of course, as needed, each interrupt source can also be unified into a group of level-type interrupt sources and a group of pulse-type interrupt sources, and operations such as splicing can be performed on a group of level-type interrupt sources and a group of pulse-type interrupt sources respectively.
[0093] For example, assuming there are 4 level-type interrupt sources and 4 pulse-type interrupt sources, the 4 level-type interrupt sources can be converted into pulse-type interrupt sources, so that all 8 interrupt sources are unified as pulse-type interrupt sources. The 4 pulse-type interrupt sources can also be converted into level-type interrupt sources, so that all 8 interrupt sources are unified as level-type interrupt sources. It is also possible to obtain 8 pulse-type interrupt sources and 8 level-type interrupt sources at the same time.
[0094] How to convert the interrupt source is known to those skilled in the art and will not be described in detail here. For example, when converting a pulse type interrupt source into a level type interrupt source, an edge detection circuit can be used. The edge detection circuit can detect the signal edge and generate a corresponding level signal based on the detected level.
[0095] In order to facilitate the subsequent logical AND operation of splicing signals and interrupt mask registers, each interrupt source can be unified as a high-level valid level interrupt source, a low-level valid level interrupt source, a rising edge triggered pulse interrupt source, or a falling edge triggered pulse interrupt source.
[0096] When only level-type interrupt sources are included, if both high-level valid level-type interrupt sources and low-level valid level-type interrupt sources are included, in order to facilitate the subsequent splicing signal and the interrupt mask register to perform logical AND operations, the high-level valid level-type interrupt source can be converted to a low-level valid level-type interrupt source, or the low-level valid level-type interrupt source can be converted to a high-level valid level-type interrupt source, so as to be unified into a high-level valid level-type interrupt source or a low-level valid level-type interrupt source.
[0097] When only pulse type interrupt sources are included, if both rising edge triggered pulse type interrupt sources and falling edge triggered pulse type interrupt sources are included, in order to facilitate the subsequent splicing signal and interrupt mask register logical AND operation, the rising edge triggered pulse type interrupt source can be converted to a falling edge triggered pulse type interrupt source, or the falling edge triggered pulse type interrupt source can be converted to a rising edge triggered pulse type interrupt source, so as to be unified as a rising edge triggered pulse type interrupt source or a falling edge triggered pulse type interrupt source.
[0098] When there is only one type of interrupt source, for example, all high-level valid level interrupt sources, the high-level valid level interrupt sources can be used for splicing operations. Of course, they can also be uniformly converted to another type of interrupt source and then spliced as needed.
[0099] When different types of interrupt sources exist in a system at the same time, it is not limited to normalizing the interrupt sources, that is, unifying them into the same type of interrupt sources, and at least part of any type of interrupt sources can be selected as a basis for performing operations such as splicing.
[0100] It is understandable that, in this embodiment, before splicing, it is not limited to unifying each interrupt source into a high-level effective level interrupt source, a low-level effective level interrupt source, a rising edge triggered pulse interrupt source, or a falling edge triggered pulse interrupt source, etc., as long as the technicians in this field can perform splicing and subsequent logical and operations. For example, it is not excluded that the interrupt mask register can have two processing logics, for example, the processing logic of the first part of the bits is "0" to allow, "1" to mask, and the processing logic of the latter part of the bits is "1" to allow, "0" to mask, and the high-level effective level interrupt source and the low-level effective level interrupt source correspond to different parts of the interrupt mask register. Before splicing, it is not limited to being unified into a level interrupt source or a pulse interrupt source, as long as the splicing can be achieved after processing, and the interrupt mask register can be compatible with different processing logics.
[0101] In order to better understand this embodiment, Figure 7 and Figure 8 Provide further explanation.
[0102] Figure 7 In the example, N interrupt sources int_s0, int_s1, int_s2, ... int_sN are normalized to form N pulse interrupt sources int_s0, int_s1, int_s2, ... int_sN. Figure 4 Further interrupt management is performed and will not be described in detail here.
[0103] Figure 8 In the example, N interrupt sources int_s0, int_s1, int_s2, ... int_sN are normalized to form N level interrupt sources int_s0, int_s1, int_s2, ... int_sN. Figure 5 Further interrupt management is performed and will not be described in detail here.
[0104] See also Fig. 9 Specifically, before splicing the N interrupt sources, the interrupt management method further includes:
[0105] S100, obtaining N level-type interrupt sources and N pulse-type interrupt sources by processing N interrupt sources.
[0106] In this way, subsequent interrupt management can be performed for a group of level interrupt sources and a group of pulse interrupt sources that represent completely consistent event types. In this way, in the scenario where there are both pulse interrupt processors and level interrupt processors, it is convenient to use both pulse interrupt processors and level interrupt processors to perform corresponding interrupt processing. It should be noted that before processing, the N interrupt sources may include level interrupt sources and pulse interrupt sources, or may only include level interrupt sources or pulse interrupt sources.
[0107] In order to better understand this embodiment, Fig.10 Provide further explanation.
[0108] Fig.10 In the example, N interrupt sources int_s0, int_s1, int_s2, ... int_sN are normalized to form N pulse interrupt sources int_s0, int_s1, int_s2, ... int_sN and N level interrupt sources int_s0, int_s1, int_s2, ... int_sN. Figure 4 and Figure 5 Further interrupt management is performed and will not be described in detail here.
[0109] In one embodiment, the interrupt management method further includes:
[0110] A resource pool is established, in which several interruption events are stored;
[0111] Update interrupt sources based on interrupt events within the resource pool.
[0112] You can add as many possible interruption events as possible, such as exceptions and regular business, and make them into a resource pool to provide more possibilities to adapt to unclear scenarios. When a new scenario appears, you can extract the interruption file from the resource pool to update the interruption source, increase the fault tolerance mechanism of the design, and enhance maintainability, which is especially important for the stability of the server.
[0113] It should be noted that the interrupt management method in the embodiment of the present application is not limited to being executed based on all interrupt sources in the system. Some interrupt sources can be selected as needed, and the selected interrupt sources can be of the same type or different types.
[0114] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.
[0115] Based on the same inventive concept, the embodiment of the present application also provides an interrupt management device for implementing the interrupt management method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations / descriptions in the interrupt management device embodiment provided below can refer to the limitations / descriptions of the interrupt management method above, and will not be repeated here.
[0116] See also Fig.11 , the interrupt management device of the embodiment of the present application includes:
[0117] The creation module 203 is used to create a multi-bit interrupt mask register for each of the multiple interrupt numbers configured for the N interrupt sources. The N bits of each interrupt mask register correspond to the N interrupt sources, where N is a plurality.
[0118] The screening module 204 is used to screen the interrupt requests based on each interrupt mask register to obtain a valid interrupt request for each interrupt number.
[0119] Please combine Fig.12 In one embodiment, the interrupt management device further includes:
[0120] The splicing module 202 is used to splice N interrupt sources to form a multi-bit splicing signal, wherein each interrupt source corresponds to a bit of the splicing signal. That is, there is a one-to-one correspondence between the N bits of the splicing signal corresponding to the N interrupt sources and the N bits of the interrupt mask register.
[0121] The screening module 204 is used to perform a logic AND operation on the N bits of each interrupt mask register and the corresponding N bits of the splicing signal, and obtain a valid interrupt request of each interrupt number based on the result of the logic AND operation.
[0122] Specifically, the logical AND operation is a bitwise AND operation.
[0123] Specifically, the screening module 204 is used to:
[0124] Perform a logical OR operation on the results of the logical AND operation;
[0125] Based on the result of the logical OR operation, a valid interrupt request of the corresponding interrupt number is obtained.
[0126] See also Fig.13 Specifically, the interrupt management device also includes:
[0127] The processing module 201 is used to normalize the interrupt sources of different types before splicing the N interrupt sources to obtain N interrupt sources of the same type.
[0128] See also Fig.14 Specifically, the interrupt management device also includes:
[0129] The processing module 200 is used to obtain N level-type interrupt sources and N pulse-type interrupt sources by processing the N interrupt sources before splicing them.
[0130] In one embodiment, the interrupt management device further includes:
[0131] A building module is used to build a resource pool, in which a number of interruption events are stored;
[0132] The update module is used to update the interrupt source based on the interrupt event in the resource pool.
[0133] In the embodiments of the present application, the term "module" refers to a computer program or a part of a computer program with a predetermined function, and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories) or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.
[0134] Fig.15 Schematic diagram of the structure of a computer device provided in an embodiment of the present application. Fig.15As shown, the computer device may include: a processor 301 and a memory 302. The memory 302 is connected to the processor 301, and the memory 302 is used to store a computer program. The processor 301 is used to call the computer program so that the computer device executes the interrupt management method described in the above embodiment. In addition, the above computer device may also include: at least one communication bus 303. Among them, the communication bus 303 is used to realize the connection and communication between components. The memory 302 can be a high-speed RAM memory, or a non-volatile memory, such as at least one disk memory.
[0135] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. The computer program is suitable for being loaded by a processor and executing the interrupt management method described in the above embodiment.
[0136] The embodiment of the present application also provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. The processor of the computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the electronic device executes the interrupt management method described in the above embodiment.
[0137] It should be understood that in the embodiments of the present application, the processor referred to may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0138] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by hardware related to computer program instructions, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.
[0139] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0140] The above disclosure is only a preferred example of the present application and cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are all within the scope covered by the present application.
Claims
1. An interrupt management method, characterized in that: include: Creating a multi-bit interrupt mask register for each of the multiple interrupt numbers configured for the N interrupt sources, wherein the N bits of each interrupt mask register correspond to the N interrupt sources, where N is a plurality; Interrupt requests are screened based on each of the interrupt mask registers to obtain a valid interrupt request for each of the interrupt numbers.
2. The interrupt management method according to claim 1, characterized in that: The method further comprises: Splicing the N interrupt sources to form a multi-bit splicing signal, wherein each of the interrupt sources corresponds to a bit of the splicing signal; The screening of the interrupt request based on each of the interrupt mask registers to obtain a valid interrupt request for each of the interrupt numbers comprises: The N bits of each interrupt mask register are respectively subjected to a logic AND operation with the corresponding N bits of the splicing signal, and a valid interrupt request of each interrupt number is obtained based on the result of the logic AND operation.
3. The interrupt management method according to claim 2, characterized in that: The N interrupt sources are of the same type.
4. The interrupt management method according to claim 2, characterized in that: The N interrupt sources are level type interrupt sources or pulse type interrupt sources.
5. The interrupt management method according to claim 2, characterized in that: The N interrupt sources are high-level effective level-type interrupt sources, low-level effective level-type interrupt sources, rising-edge triggered pulse-type interrupt sources, or falling-edge triggered pulse-type interrupt sources.
6. The interrupt management method according to claim 2, characterized in that: Before splicing the N interrupt sources, the method further includes: The interrupt sources belonging to different types are normalized to obtain the N interrupt sources of the same type.
7. The interrupt management method according to claim 2, characterized in that: Before splicing the N interrupt sources, the method further includes: The N interrupt sources of level type and the N interrupt sources of pulse type are obtained by processing the N interrupt sources.
8. The interrupt management method according to claim 2, characterized in that: The logical AND operation is a bitwise AND operation.
9. The interrupt management method according to claim 2, characterized in that: The obtaining of a valid interrupt request for each interrupt number based on the result of the logic and operation comprises: performing a logical OR operation on the results of the logical AND operation; A valid interrupt request corresponding to the interrupt number is obtained based on the result of the logic OR operation.
10. The interrupt management method according to claim 1, characterized in that: The method further comprises: Establishing a resource pool, wherein a plurality of interruption events are stored in the resource pool; The interrupt source is updated based on the interrupt event in the resource pool.
11. An interrupt management device, characterized in that: include: A creation module, used for creating a multi-bit interrupt mask register for each of the multiple interrupt numbers configured for the N interrupt sources, wherein the N bits of each of the interrupt mask registers correspond to the N interrupt sources, and N is a plurality; The screening module is used to screen the interrupt request based on each of the interrupt mask registers to obtain a valid interrupt request of each of the interrupt numbers.
12. A computer device, characterized in that: including memory and processor; The memory is connected to the processor, the memory is used to store a computer program, and the processor is used to call the computer program so that the computer device executes the interrupt management method according to any one of claims 1 to 10.
13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is suitable for being loaded by a processor and executing the interrupt management method according to any one of claims 1 to 10.