Communication between circuits with different clock frequencies

Abstract

The invention relates to communication between circuits with different clock frequencies. An apparatus includes a clock monitoring circuit and a multiplexing circuit. The clock monitoring circuit includes an output terminal. The clock monitoring circuit is configured to generate a control signal based on monitoring a plurality of clock signals. A multiplexing circuit is coupled to an output terminal of the clock monitoring circuit and configured to receive a control signal, the multiplexing circuit including a first input terminal to receive a first signal generated based on a first clock signal of the plurality of clock signals. The multiplexing circuit includes a second input terminal to receive a second signal generated based on a second clock signal of the plurality of clock signals. The multiplexing circuit includes an output terminal to output one of the first signal or the second signal based on the control signal.

Description

Technical Field

[0001] Embodiments are directed to rapidly transferring data operands between functional blocks of digital logic having different clock frequencies (eg, where the clock signals have a deterministic relationship). Background Art

[0002] Computer platforms and electronic systems often move data between separate functional units of separately clocked digital blocks. If this data movement is slow, a potential bottleneck will occur and system performance will be negatively affected, affecting computers, smartphones and a host of other devices. Summary of the invention

[0003] One aspect of the present disclosure provides an apparatus. The apparatus includes: a clock monitoring circuit including an output terminal, the clock monitoring circuit being configured to generate a control signal based on monitoring a plurality of clock signals; and a multiplexing circuit coupled to the output terminal of the clock monitoring circuit, the multiplexing circuit being configured to receive the control signal, the multiplexing circuit including: a first input terminal for receiving a first signal generated based on a first clock signal among the plurality of clock signals; a second input terminal for receiving a second signal generated based on a second clock signal among the plurality of clock signals; and an output terminal for outputting one of the first signal or the second signal based on the control signal.

[0004] Another aspect of the present disclosure provides a system. The system includes: a memory; and at least one processor coupled to the memory, the at least one processor configured to: receive a first clock signal, the first clock signal being associated with a transmit (Tx) circuit of a computing device; receive a second clock signal, the second clock signal being associated with a receive (Rx) circuit of the computing device; perform a comparison between the first clock signal and the second clock signal; generate a control signal based on the comparison; and encode the control signal to be communicated to at least one circuit within the Rx circuit.

[0005] Another aspect of the present disclosure provides a system. The system includes: means for receiving a first clock signal, the first clock signal being associated with a transmit (Tx) circuit of a computing device; means for receiving a second clock signal, the second clock signal being associated with a receive (Rx) circuit of the computing device; means for performing a comparison of the first clock signal and the second clock signal; means for generating a control signal based on the comparison; and means for encoding the control signal for communication to at least one circuit within the Rx circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the accompanying drawings, like reference numerals may describe the same or similar components or features in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. Some embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which:

[0007] Figure 1 A block diagram illustrating the prior art for generating a continuous acknowledgement loop of strobed data between a transmitting component and a receiving component;

[0008] Figure 2 Illustration of the use Figure 1 A timing diagram of data transmission and reception through a continuous confirmation loop;

[0009] Figure 3 illustrates a block diagram of a clock management circuit according to some embodiments, the circuit including a continuous acknowledgement loop for generating strobe data between a transmitting component and a receiving component using a clock monitoring circuit and a multiplexing circuit;

[0010] Figure 4 Illustrated is the use of some embodiments Figure 3 A timing diagram of data transmission and reception through a continuous confirmation loop;

[0011] Figure 5 is a flow chart of an example method for communicating data between communication domains using different clock frequencies according to some embodiments; and

[0012] Figure 6 Illustrated is a block diagram of an example machine upon which any one or more of the operations / techniques (eg, methodologies) discussed herein may be performed. DETAILED DESCRIPTION

[0013] The following detailed description refers to the accompanying drawings. The same reference numerals may be used in different drawings to identify the same or similar elements. In the following description, specific details such as specific structures, architectures, interfaces, technologies, etc. are recorded for illustrative rather than limiting purposes to provide a thorough understanding of various aspects of various embodiments. However, it will be clear to those skilled in the art who benefit from this disclosure that various aspects of various embodiments may be practiced in other examples that depart from these specific details. In some cases, descriptions of well-known devices, circuits, and methods are omitted to avoid obscuring the description of various embodiments with unnecessary details.

[0014] The following description and the accompanying drawings sufficiently illustrate the specific embodiments to enable those skilled in the art to practice them. Other embodiments may contain structural, logical, electrical, process and other changes. Portions and features of some embodiments may be included in other embodiments, or replace portions and features of other embodiments. The embodiments outlined in the claims encompass all available equivalents of these claims.

[0015] As used herein, the term "chip" (or die) refers to a piece of material, such as semiconductor material, that includes a circuit such as an integrated circuit or a portion of an integrated circuit. The term "memory IP" refers to memory intellectual property. The terms "memory IP," "memory device," "memory chip," and "memory" are interchangeable.

[0016] Many systems-on-a-chip (SoC) and silicon systems synchronize the transfer of data operation objects between communication domains (e.g., a transmit domain associated with the sending of data and a receive domain associated with the receiving of data) that have different clock frequencies. The prior art has addressed this problem using techniques that move data more quickly when the clocks of the functional units have a predictable, pseudo-synchronous (integer or fractional) relationship. For example, the prior art (e.g., as disclosed in U.S. Patent No. 6,067,629 to Murray et al. (hereinafter referred to as "Murray")) uses a token passing mechanism to facilitate such transfers. Contact Figure 1 and Figure 2 The prior art associated with Murray is discussed.

[0017] The disclosed technology provides further improvements on Murray based on the use of a clock management circuit including a clock monitoring circuit and a multiplexing circuit. More specifically, if the clock of the receiving domain is faster than the clock of the sending domain, the disclosed technology (e.g., as shown in FIG. 1 ) Figure 3-Figure 5 The present invention provides a method for eliminating register stages by eliminating register stages. This elimination allows data to be transferred at the rate of the transmit domain, thereby maximizing the maximum available data rate. The disclosed techniques allow performance gains to be achieved in many applications, including interfaces between physical layers (PHY) and media access control layers (MAC), accelerators and fabrics, and other types of interfaces between communication domains associated with different clock frequencies.

[0018] connect Figure 1-Figure 2 A processing technique previously disclosed by Murray is discussed. The essence of Murray is that metastability problems can be alleviated when moving a token from one clock domain to another by using pseudo-synchronous clocks (e.g., two clock signals having an integer relationship to each other). This token can be used to indicate the validity of a multi-bit data operation object, thereby allowing fast data transfer from one domain to another.

[0019] Figure 1 A block diagram 100 of the prior art for generating a continuous acknowledgement loop of strobe data between a transmitting component and a receiving component is illustrated. Figure 1, component 101 operates in a first communication domain (also referred to as a frequency domain or clock domain) and sends data to component 106 operating in a second frequency domain. Component 101 includes logic block 140 and latches (also referred to as registers, register circuits, or flip-flops) 111 and 121 (clocked by clock signal Tx 107). Component 106 includes logic block 145 (generating ACK 146), latches 131 and 142 (clocked by clock signal Rx 108), and inverter 190.

[0020] Component 101 uses strobe 126 and acknowledgement (ACK) 136 to synchronize data transmission between component 101 and component 106. An acknowledgement signal transition on line ACK 136 indicates that component 106 has received an acknowledgement signal with strobe 126 on the communication line. The sending component generates strobe 126 in conjunction with new data. An acknowledgement signal transition on line ACK 136 indicates that component 106 has received new data from component 101. Logic block 140 detects the acknowledgement signal transition on line ACK 136 and gates the new data for transmission between components 101 and 106 via ACK 141. The continuous acknowledgement loop for generating gated data between component 101 and component 106 includes strobe 126, latch 131, inverter 190, line ACK 136, and latch 121.

[0021] Figure 2 Illustration of the use Figure 1 A timing diagram 200 of a continuous confirmation loop for data transmission and reception. Figure 2 , diagram 200 shows that in Murray (e.g., Figure 1 ) to implement the transfer of tokens and associated data operation objects between clock domains. Figure 2 As shown in Figure 1, the receive clock runs faster than the transmit clock, and four data operands are being sent. Sometimes, it takes multiple Tx clocks to move an operand.

[0022] Since the grant of the Murray patent, technology has advanced and variable clock speeds are used in many designs, allowing for reduced power consumption and less heat dissipation. In some aspects, when moving data from one clock domain to another, one technique (e.g., that used by Murray) is to pass a token back and forth between the two communicating domains (e.g., the Tx domain and the Rx domain) to indicate the presence and acceptance of new data. In some aspects, this token is synchronized with the receiving domain. In many cases, this is necessary, but there is a penalty in timing efficiency due to the need for a register stage at the receiver.

[0023] In some embodiments, the disclosed technology includes a clock management circuit with an intelligent clock monitoring circuit that monitors the clock signals of the communication domains (e.g., the Rx clock and the Tx clock associated with the corresponding Rx domain and the Tx domain) and decides to use a clocked or non-clocked path for the token on the Rx side. More specifically, if the Rx clock is faster than the Tx clock, the non-clocked path is selected via a multiplexing circuit and used for the token at Rx. If the Rx clock is slower than the Tx clock, the clocked path is selected via a multiplexing circuit and used for the token. In some aspects, integer clock ratios manage setup and hold time requirements without the need for metastable flip-flops. Contact Figure 3-Figure 5 Example embodiments using clock management circuits are discussed.

[0024] Figure 3 FIG. 3 is a block diagram of a clock management circuit 300 including a continuous acknowledgement loop for generating strobe data between a transmitting component and a receiving component using a clock monitoring circuit and a multiplexing circuit according to some embodiments. Figure 3 , the clock management circuit 300 includes a clock monitoring circuit 302 and a multiplexing circuit 308. The clock management circuit 300 is configured in conjunction with a device that includes one or more circuits operating within a first communication domain (e.g., Tx domain 318) and one or more circuits operating within a second communication domain (e.g., Rx domain 320). As used herein, the term "domain" may refer to circuits associated with a particular clock signal frequency. In this regard, the Tx domain 318 may represent Tx circuits associated with the same clock signal frequency (e.g., one or more circuits coupled via one or more interfaces). Similarly, the Rx domain 320 may represent Rx circuits associated with the same clock signal frequency (e.g., one or more circuits coupled via one or more interfaces).

[0025] The Tx domain 318 includes a register circuit 304 clocked by a clock signal of a first frequency. The Rx domain 320 includes register circuits 306, 310, and 314 clocked by a clock signal of a second frequency. The Rx domain 320 also includes a multiplexing circuit 308, a logic block 312, and an inverter 316. The register circuit 314 is coupled to a data terminal associated with the Tx data 328 and the Rx data 330. The register circuit 314 is coupled to the output of the logic block 312. The multiplexing circuit 308 receives a first input from the register circuit 304 and a second input from the register circuit 306. The inverter 316 receives an input from the output of the multiplexing circuit 308 and generates an output coupled to the register circuit 304 in the Tx domain 318.

[0026] like Figure 3 As shown, register circuits 304, 306 and 310 are connected to Figure 1The latches 121, 131 and 142 of Murray are shown in FIG. 1 . In addition, the logic block 312 and the inverter 316 are similar to those shown in FIG. Figure 1 Murray's logic block 145 and inverter 190 are shown to correspond.

[0027] In some aspects, the clock monitoring circuit 302 receives clock signals used by available communication domains (e.g., a Tx clock signal used by devices in the Tx domain 318 and an Rx clock signal used by devices in the Rx domain 320) as input signals 303. The clock monitoring circuit 302 may perform a comparison on the clock signals received as the input signals 303 and generate a control signal 305 based on the comparison result.

[0028] The control signal 305 may control the input of the multiplexing circuit 308 and select between the Tx token 322 (generated by the register circuit 304 at the Tx domain 318 while using the Tx clock signal) or the buffered signal 324 generated as the output of the register circuit 306 (generated by the register circuit 306 using the Tx token 322 while being clocked by the Rx clock signal associated with the Rx domain 320). For example, as described above, if the Rx clock is faster than the Tx clock, a non-clocked path may be used for the token at the Rx domain 320 (e.g., the control signal 305 enables the first input of the multiplexing circuit 308 so that the Tx token 322 received from the Tx domain 318 is directly used and output by the multiplexing circuit 308 to the inverter 316 without being buffered at the register circuit 306). If the Rx clock is slower than the Tx clock, the clocked path is used for the token (e.g., control signal 305 enables the second input of multiplexing circuit 308 so that buffered signal 324 is received by multiplexing circuit 308 and output to inverter 316). Inverter 316 generates an inverted signal 326 which is communicated to register circuit 304.

[0029] In some embodiments, clock monitoring circuit 302 generates control signal 305 and configures switching between the first input or the second input of multiplexing circuit 308 when the clock is static. In some aspects, on-the-fly switching of multiplexing circuit inputs may also be used.

[0030] about Figure 1 For the processing performed in Murray, regardless of the clock speed (Ptx is the sending clock cycle, Prx is the receiving clock cycle), the average time to transmit an operation object is T=Ptx+(0.5*Prx).

[0031] In contrast, in the case where Prx>Ptx (Rx clock is faster, so there is no Rx register stage), using the disclosed techniques (e.g., as described in connection with Figure 3-Figure 5The average time for transmitting an operation object is T=Ptx. In this regard, the disclosed technology is associated with the delay of waiting for the Rx clock to be eliminated.

[0032] Figure 4 Illustrated is the use of some embodiments Figure 3 A timing diagram 400 of a continuous acknowledgement loop for data transmission and reception. Figure 3 and Figure 4 , when the Rx domain 320 operates in a fast mode (e.g., the frequency of the Rx clock signal is higher than the frequency of the Tx clock signal), the register circuit 306 is bypassed and six operands can be transferred simultaneously. It can be seen from the timing diagram 400 that one operand is moved per Tx clock, which is the fastest possible transfer rate.

[0033] Figure 5 is a flow chart of an example method 500 for communicating data between communication domains using different clock frequencies according to some embodiments. Figure 5 , method 500 includes operations 502, 504, 506, 508, and 510, which may be performed by a clock management circuit or another processor of a computing device (e.g., Figure 6 In some embodiments, the clock monitoring circuit 302 may execute Figure 5 As well as the configuration and management functions discussed in the examples listed below.

[0034] At operation 502, a first clock signal is received. For example, the first clock signal is a Tx token 322 associated with a Tx domain 318 of a computing device received at an Rx domain 320.

[0035] At operation 504, a second clock signal is received. For example, the second clock signal is a buffered signal (e.g., buffered signal 324) generated by register circuit 306 and associated with Rx domain 320 of the computing device. In some aspects, the first clock signal and the second clock signal are also communicated to clock monitoring circuit 302 as input signals 303.

[0036] At operation 506 , a comparison of the first clock signal and the second clock signal is performed (eg, by clock monitoring circuit 302 ).

[0037] At operation 508, a control signal is generated based on the comparison. For example, the clock monitoring circuit 302 generates the control signal 305 based on the comparison.

[0038] At operation 510 , the control signal is encoded for communication to at least one circuit within the Rx domain. For example, the control signal 305 is communicated to the multiplexing circuit 308 where it is used to select one of the Tx token 322 or the buffered signal 324 for further processing at the Rx domain 320 .

[0039] Figure 6 A block diagram of an example machine 600 on which any one or more techniques (e.g., methods) discussed herein may be executed is illustrated. In alternative embodiments, the machine 600 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 600 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, the machine 600 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 600 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a portable communication device, a mobile phone, a smart phone, a web appliance, a network router, a switch or a bridge, or any other computing device capable of executing instructions (sequential or otherwise) specifying the actions to be taken by the machine. In addition, although only a single machine is illustrated, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), and other computer cluster configurations. The terms "machine," "computing device," and "computer system" are used interchangeably.

[0040] The machine (e.g., computer system) 600 may include a hardware processor 602 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination of these), a main memory 604, and a static memory 606, some or all of which may communicate with each other via an interconnection link (e.g., a bus) 608. In some aspects, the main memory 604, the static memory 606, or any other type of memory (including cache memory) used by the machine 600 may be configured based on the disclosed techniques, or may implement the disclosed memory devices.

[0041] Specific examples of main memory 604 include random access memory (RAM), and semiconductor memory devices, which in some embodiments may include storage locations in a semiconductor, such as registers. Specific examples of static memory 606 include non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; RAM; and CD-ROM and DVD-ROM disks.

[0042] The machine 600 may also include a display device 610, an alphanumeric input device 612 (e.g., a keyboard), and a user interface (UI) navigation device 614 (e.g., a mouse). In one example, the display device 610, the input device 612, and the UI navigation device 614 may be a touch screen display. The machine 600 may also include a storage device (e.g., a drive unit or another mass storage device) 616, a signal generating device 618 (e.g., a speaker), a network interface device 620, and one or more sensors 621, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 600 may include an output controller 628, such as a serial (e.g., universal serial bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate with or control one or more peripheral devices (e.g., printers, card readers, etc.). In some embodiments, hardware processor 602 and / or instructions 624 may include processing circuitry and / or transceiver circuitry.

[0043] The storage device 616 may include a machine-readable medium 622 on which is stored one or more sets of data structures or instructions 624 (e.g., software) embodying or utilized by any one or more of the techniques or functionality described herein. The instructions 624 may also reside, completely or at least partially, within the main memory 604, within the static memory 606, or within the hardware processor 602 during execution thereof by the machine 600. In an example, one or any combination of the hardware processor 602, the main memory 604, the static memory 606, or the storage device 616 may constitute a machine-readable medium.

[0044] Specific examples of machine-readable media may include nonvolatile memory, such as semiconductor memory devices (e.g., EPROM or EEPROM) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; RAM; and CD-ROM and DVD-ROM disks.

[0045] Although machine-readable medium 622 is illustrated as a single medium, the term “machine-readable medium” may include a single medium or multiple media (eg, a centralized or distributed database, and / or associated caches and servers) configured to store instructions 624 .

[0046] The apparatus of the machine 600 may be one or more of the following: a hardware processor 602 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 604 and a static memory 606, one or more sensors 621, a network interface device 620, one or more antennas 660, a display device 610, an input device 612, a UI navigation device 614, a storage device 616, instructions 624, a signal generation device 618, and an output controller 628. The apparatus may be configured to perform one or more methods and / or operations disclosed herein. The apparatus may be a component of the machine 600 to perform one or more methods and / or operations disclosed herein, and / or a part of performing one or more methods and / or operations disclosed herein. In some embodiments, the apparatus may include pins or other components to receive power. In some embodiments, the apparatus may include power conditioning hardware.

[0047] The term "machine-readable medium" may include any medium that is capable of storing, encoding or carrying instructions for execution by the machine 600 and causing the machine 600 to perform any one or more techniques of the present disclosure, or capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory, as well as optical and magnetic media. Specific examples of machine-readable media may include non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory devices; disks, such as internal hard disks and removable disks; magneto-optical disks; random access memory (RAM); and CD-ROM and DVD-ROM disks. In some examples, the machine-readable medium may include non-transitory machine-readable media. In some examples, the machine-readable medium may include machine-readable media that is not a transient propagation signal.

[0048] The instructions 624 may also be sent or received over a communication network 626 using a transmission medium via the network interface device 620 using any of a number of transmission protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile phone network (e.g., a cellular network), a Plain Old Telephone (POTS) network, and a wireless data network (e.g., a wireless network known as a WLAN). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards, known as ), IEEE 802.15.4 family of standards, Long Term Evolution (LTE) family of standards, Universal Mobile Telecommunications System (UMTS) family of standards, peer-to-peer (P2P) networks, and the like.

[0049] In one example, the network interface device 620 may include one or more physical jacks (e.g., Ethernet, coaxial or telephone jack) or one or more antennas to connect to the communication network 626. In one example, the network interface device 620 may include one or more antennas 660 to communicate wirelessly using at least one single-input multiple-output (SIMO), multiple-input multiple-output (MIMO) or multiple-input single-output (MISO) technology. In some examples, the network interface device 620 may communicate wirelessly using multi-user MIMO technology. The term "transmission medium" should be understood to include any intangible medium that can store, encode or carry instructions for execution by the machine 600, and includes digital or analog communication signals or other intangible media to facilitate the communication of such software.

[0050] Examples as described herein may include logic or several components, modules or mechanisms, or may operate on logic or several components, modules or mechanisms. A module is a tangible entity (e.g., hardware) that can perform specified operations and can be configured or arranged in a certain manner. In one example, a circuit may be arranged as a module in a specified manner (e.g., internally or with respect to an external entity, such as other circuits). In one example, all or part of one or more computer systems (e.g., stand-alone, client or server computer systems) or one or more hardware processors may be configured as a module by firmware or software (e.g., instructions, application parts or applications), and the module operates to perform specified operations. In one example, the software may reside on a machine-readable medium. In one example, the software causes the hardware to perform specified operations when executed by the underlying hardware of the module.

[0051] Thus, the term "module" is understood to encompass a tangible entity, whether the entity is physically constructed, specifically configured (e.g., hardwired), or temporarily (e.g., temporarily) configured (e.g., programmed) to operate in a specified manner or to perform some, all, or any of the operations described herein. Considering the example of temporarily configured modules, each module need not be instantiated at any one time. For example, where a module includes a general-purpose hardware processor configured using software, the general-purpose hardware processor may be configured as various different modules at different times. The software may accordingly configure the hardware processor to, for example, constitute a particular module at one time and constitute a different module at a different time.

[0052] Some embodiments may be implemented in whole or in part in software and / or firmware. This software and / or firmware may take the form of instructions contained in or on a non-transitory computer-readable storage medium. These instructions may then be read and executed by one or more processors to enable performance of the operations described herein. The instructions may take any suitable form, such as, but not limited to, source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. Such computer-readable media may include any tangible, non-transitory media for storing information in one or more computer-readable forms, such as, but not limited to, read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory, and the like,

[0053] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings illustrate specific embodiments that can be put into practice. These embodiments are also referred to as "examples" in this article. Such examples may include additional elements other than those shown or described. However, examples including the elements shown or described are also contemplated. In addition, examples (or one or more aspects thereof) using any combination or permutation of these elements shown or described are also contemplated, whether for a specific example (or one or more aspects thereof), or for other examples (or one or more aspects thereof) shown or described herein.

[0054] Publications, patents, and patent documents cited in this document are hereby incorporated by reference in their entirety, as if each were incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) supplements that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0055] In this document, the terms "a" or "an" are used to include one or more than one, as is common in patent documents, independent of any other instance or use of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B", "B but not A", and "A and B", unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein". In addition, in the appended claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, or processes that include other elements in addition to those listed after such terms in the claim are still considered to fall within the scope of the claim. In addition, in the appended claims, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to imply a numerical order to their objects.

[0056] The embodiments described above may be implemented in various hardware configurations, which may include a processor for executing instructions that perform the described techniques. Such instructions may be included in a machine-readable medium, such as a suitable storage medium or memory or other processor-executable medium.

[0057] Embodiments as described herein may be implemented in a number of environments, such as as part of a system on a chip, a group of functional blocks in communication with each other, or the like, although the scope of the present disclosure is not limited in this respect.

[0058] Implementations of the described subject matter may include one or more of the features, alone or in combination, as described below by way of example.

[0059] Example 1 is a device comprising: a clock monitoring circuit including an output terminal, the clock monitoring circuit being configured to generate a control signal based on monitoring multiple clock signals; and a multiplexing circuit coupled to the output terminal of the clock monitoring circuit, the multiplexing circuit being configured to receive the control signal, the multiplexing circuit comprising: a first input terminal for receiving a first signal generated based on a first clock signal among the multiple clock signals; a second input terminal for receiving a second signal generated based on a second clock signal among the multiple clock signals; and an output terminal for outputting one of the first signal or the second signal based on the control signal.

[0060] In Example 2, the subject matter of Example 1 includes a first register circuit including a data terminal and an output terminal, the output terminal of the first register circuit coupled to the second input terminal of the multiplexing circuit.

[0061] In Example 3, the subject matter of Example 2 includes the following subject matter: wherein the first register circuit includes a clock terminal configured to receive the second clock signal, and wherein the first register circuit is clocked by the second clock signal.

[0062] In Example 4, the subject matter of Examples 2-3 includes the subject matter wherein a data terminal of the first register circuit is coupled to an output terminal of the second register circuit.

[0063] In Example 5, the subject matter of Example 4 includes the subject matter wherein a data terminal of the first register circuit receives the first signal from an output terminal of the second register circuit.

[0064] In Example 6, the subject matter of Examples 4-5 includes the following subject matter: wherein the second register circuit includes a clock terminal configured to receive the second clock signal, and wherein the second register circuit is clocked by the second clock signal.

[0065] In Example 7, the subject matter of Examples 2-6 includes the following subject matter: wherein the first register circuit is configured to receive the first signal at the data terminal.

[0066] In Example 8, the subject matter of Example 7 includes the following subject matter: wherein the first register circuit buffers the first signal to generate the second signal.

[0067] In Example 9, the subject matter of Examples 1-8 includes the following subject matter: wherein the first signal is a send token generated based on the first clock signal.

[0068] In Example 10, the subject matter of Example 9 includes the following subject matter: wherein the second signal is a buffered version of the send token, and the buffered version of the send token is generated based on the second clock signal.

[0069] In Example 11, the subject matter of Examples 1-10 includes the following subject matter: wherein the clock monitoring circuit is used to perform a comparison of the first clock signal and the second clock signal.

[0070] In Example 12, the subject matter of Example 11 includes the following subject matter: wherein the clock monitoring circuit is used to generate the clock signal based on the comparison.

[0071] In Example 13, the subject matter of Example 12 includes the following subject matter: wherein the multiplexing circuit is used to output the first signal when the control signal indicates that the second clock signal is faster than the first clock signal.

[0072] In Example 14, the subject matter of Examples 12-13 includes the following subject matter: wherein the multiplexing circuit indicates to output the second signal when the control signal indicates that the second clock signal is equal to or slower than the first clock signal.

[0073] In Example 15, the subject matter of Examples 1-14 includes an inverter circuit coupled to an output terminal of the multiplexing circuit, the inverter circuit to generate an inverted signal based on the first signal or the second signal received from the multiplexing circuit.

[0074] In Example 16, the subject matter of Examples 9-15 includes the following subject matter: wherein the transmit token is generated based on transmitting data from a transmit circuit associated with the first clock signal to a receive circuit associated with the second clock signal.

[0075] In Example 17, the subject matter of Examples 1-16 includes the following subject matter: wherein the apparatus includes a processor, and wherein the processor includes the clock monitoring circuit and the multiplexing circuit.

[0076] In Example 18, the subject matter of Example 17 includes one or more interconnects coupling the clock monitoring circuit and the multiplexing circuit.

[0077] Example 19 is a system comprising: a memory; and at least one processor coupled to the memory, the at least one processor being configured to: receive a first clock signal associated with a transmit (Tx) circuit of a computing device; receive a second clock signal associated with a receive (Rx) circuit of the computing device; perform a comparison of the first clock signal and the second clock signal; generate a control signal based on the comparison; and encode the control signal for communication to at least one circuit within the Rx circuit.

[0078] In Example 20, the subject matter of Example 19 includes a first register circuit configured in the Tx circuit, the first register circuit generating a transmit token based on an inverted signal received from the Rx circuit.

[0079] In Example 21, the subject matter of Example 20 includes the following subject matter: wherein the first register circuit includes a clock terminal for receiving the first clock signal.

[0080] In Example 22, the subject matter of Examples 20-21 includes the following subject matter: wherein the first register circuit further generates the transmit token based on the first clock signal.

[0081] In Example 23, the subject matter of Examples 20-22 includes a second register circuit configured in the Rx circuit, the second register circuit coupled to the first register circuit and configured to receive the transmit token.

[0082] In Example 24, the subject matter of Example 23 includes the following subject matter: wherein the second register circuit includes a clock terminal that receives the second clock signal.

[0083] In Example 25, the subject matter of Examples 23-24 includes the following subject matter: wherein the second register circuit is configured to generate a buffered signal based on the second clock signal, the buffered signal corresponding to the send token.

[0084] In Example 26, the subject matter of Example 25 includes a multiplexing circuit coupled to the at least one processor and the second register circuit.

[0085] In Example 27, the subject matter of Example 26 includes the following subject matter: wherein the multiplexing circuit includes a control terminal configured to receive the control signal.

[0086] In Example 28, the subject matter as described in Example 27 includes the following subject matter: wherein the multiplexing circuit also includes: a first input terminal for receiving the sending token; a second input terminal for receiving the buffered signal; and an output terminal for outputting one of the sending token or the buffered signal based on the control signal.

[0087] In Example 29, the subject matter of Example 28 includes the following subject matter: wherein the multiplexing circuit is used to output the transmission token when the control signal indicates that the second clock signal is faster than the first clock signal.

[0088] In Example 30, the subject matter of Examples 28-29 includes the following subject matter: wherein the multiplexing circuit is to output the buffered signal when the control signal indicates that the second clock signal is equal to or slower than the first clock signal.

[0089] In Example 31, the subject matter of Examples 26-30 includes an inverter circuit coupled to the multiplexing circuit within the Rx circuit, the inverter circuit generating an inverted signal based on the transmit token or the buffered signal received from the multiplexing circuit.

[0090] In Example 32, the subject matter as described in Examples 26-31 includes: one or more interfaces, wherein the at least one processor includes the first register circuit, the second register circuit, and the multiplexing circuit, and wherein the first register circuit, the second register circuit, and the multiplexing circuit are communicatively coupled via the one or more interfaces.

[0091] Example 33 is a method comprising: receiving a first clock signal, the first clock signal being associated with a transmit (Tx) circuit of a computing device; receiving a second clock signal, the second clock signal being associated with a receive (Rx) circuit of the computing device; performing a comparison of the first clock signal and the second clock signal; generating a control signal based on the comparison; and encoding the control signal for communication to at least one circuit within the Rx circuit.

[0092] In Example 34, the subject matter of Example 33 includes generating a transmit token based on an inverted signal received from the Rx circuit and further based on availability of data at the Tx circuit.

[0093] In Example 35, the subject matter of Example 34 includes further generating the transmit token based on the first clock signal.

[0094] In Example 36, the subject matter of Examples 34-35 includes generating a buffered signal based on the second clock signal, the buffered signal corresponding to the send token.

[0095] In Example 37, the subject matter of Example 36 includes multiplexing between the transmit token and the buffered signal based on the control signal.

[0096] In Example 38, the subject matter as described in Example 37 includes the following subject matter: wherein the multiplexing includes: outputting the transmission token when the control signal indicates that the second clock signal is faster than the first clock signal.

[0097] In Example 39, the subject matter of Example 38 includes the following subject matter: wherein the multiplexing includes: outputting the buffered signal when the control signal indicates that the second clock signal is equal to or slower than the first clock signal.

[0098] In Example 40, the subject matter of Examples 34-39 includes transmitting the data from the Tx circuit to the Rx circuit based on the generation of the transmit token.

[0099] Example 41 is at least one machine-readable medium comprising instructions that, when executed by a processing circuit, cause the processing circuit to perform operations to implement any of Examples 1-40.

[0100] Example 42 is an apparatus comprising components for implementing any of Examples 1-40.

[0101] Example 43 is a system for implementing any of Examples 1-40.

[0102] Example 44 is a method for implementing any of Examples 1-40.

[0103] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with other examples. Other embodiments may be used, for example, by a person of ordinary skill in the art after viewing the above description. The abstract is used to allow the reader to quickly determine the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description section, various features may be grouped to simplify the present disclosure. However, the claims may not record every feature disclosed herein, because the embodiments may be characterized by a subset of the features. In addition, the embodiments may include fewer features than those disclosed in a particular example. Thus, the attached claims are hereby incorporated into the detailed description section, and a claim is independent as a separate embodiment. The scope of the embodiments disclosed herein should be determined with respect to the attached claims and the full scope of equivalents to which such claims are entitled.

Claims

1. A device comprising: a clock monitoring circuit comprising an output terminal, the clock monitoring circuit being configured to generate a control signal based on monitoring a plurality of clock signals; as well as a multiplexing circuit coupled to an output terminal of the clock monitoring circuit, the multiplexing circuit being configured to receive the control signal, the multiplexing circuit comprising: A first input terminal, used to receive a first signal generated based on a first clock signal among the plurality of clock signals; a second input terminal for receiving a second signal generated based on a second clock signal among the plurality of clock signals; and An output terminal is used to output one of the first signal or the second signal based on the control signal.

2. The apparatus of claim 1, further comprising: A first register circuit includes a data terminal and an output terminal, the output terminal of the first register circuit being coupled to the second input terminal of the multiplexing circuit.

3. The device as claimed in claim 2, wherein: The first register circuit comprises a clock terminal configured to receive the second clock signal, and wherein the first register circuit is clocked by the second clock signal.

4. The device according to claim 2, wherein: A data terminal of the first register circuit is coupled to an output terminal of the second register circuit.

5. The device according to claim 4, wherein: A data terminal of the first register circuit receives the first signal from an output terminal of the second register circuit.

6. The device according to claim 4, wherein: The second register circuit comprises a clock terminal configured to receive the second clock signal, and wherein the second register circuit is clocked by the second clock signal.

7. The device of claim 2, wherein: The first register circuit is configured to receive the first signal at the data terminal.

8. The device according to claim 7, wherein: The first register circuit buffers the first signal to generate the second signal.

9. The device of claim 1, wherein: The first signal is a send token generated based on the first clock signal.

10. The device of claim 9, wherein: The second signal is a buffered version of the send token, the buffered version of the send token being generated based on the second clock signal.

11. The device according to any one of claims 1 to 10, wherein: The clock monitoring circuit is used to perform a comparison between the first clock signal and the second clock signal.

12. The device of claim 9, wherein: The clock monitoring circuit is used to generate the control signal based on the comparison.

13. The device of claim 12, wherein: The multiplexing circuit is used to output the first signal when the control signal indicates that the second clock signal is faster than the first clock signal.

14. The device of claim 12, wherein: The multiplexing circuit is used to output the second signal when the control signal indicates that the second clock signal is equal to or slower than the first clock signal.

15. The apparatus of any one of claims 1 to 10, further comprising: An inverter circuit is coupled to the output terminal of the multiplexing circuit, the inverter circuit being configured to generate an inverted signal based on the first signal or the second signal received by the multiplexing circuit.

16. The device of claim 9, wherein: The transmit token is generated based on transmitting data from a transmit circuit associated with the first clock signal to a receive circuit associated with the second clock signal.

17. A system comprising: Memory; as well as at least one processor coupled to the memory, the at least one processor configured to: receiving a first clock signal associated with a transmit (Tx) circuit of a computing device; receiving a second clock signal associated with a receive (Rx) circuit of the computing device; performing a comparison of the first clock signal and the second clock signal; generating a control signal based on the comparison; and The control signal is encoded to be communicated to at least one circuit within the Rx circuit.

18. The system of claim 17, further comprising: A first register circuit is configured in the Tx circuit, and the first register circuit is used to generate a transmission token based on an inverted signal received from the Rx circuit.

19. The system of claim 18, wherein: The first register circuit includes a clock terminal for receiving the first clock signal.

20. The system of claim 18, wherein: The first register circuit also generates the transmit token based on the first clock signal.

21. The system of claim 18, further comprising: A second register circuit configured in the Rx circuit is coupled to the first register circuit and configured to receive the transmit token.

22. The system of claim 21, wherein: The second register circuit includes a clock terminal receiving the second clock signal.

23. The system of claim 21, wherein: The second register circuit is configured to generate a buffered signal based on the second clock signal, the buffered signal corresponding to the transmit token.

24. A system comprising: means for receiving a first clock signal associated with a transmit (Tx) circuit of a computing device; means for receiving a second clock signal associated with a receive (Rx) circuit of the computing device; means for performing a comparison of said first clock signal and said second clock signal; means for generating a control signal based on said comparison; as well as means for encoding the control signal for communication to at least one circuit within the Rx circuit.

25. The system of claim 24, further comprising: Means for generating a transmit token based on the inverted signal received from the Rx circuit and also based on the availability of data at the Tx circuit.

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