Method for growing low-doped silicon carbide homoepitaxial wafer

Abstract

The invention relates to the technical field of epitaxial wafer growth, in particular to a low-doped silicon carbide homoepitaxial wafer growth method, which comprises the following steps: increasing the temperature in a reaction cavity to be 30-70 DEG C higher than the epitaxial growth temperature and maintaining for 40-50 minutes, carrying out multiple times of cyclic baking and purging, and reducing the background doping concentration in the cavity to 3.0-4.0 E14 atoms / cm < 3 >; then increasing the epitaxial growth rate; the background doping concentration is reduced to 1.0 E14 atoms / cm < 3 >; then reducing the reaction temperature, and reducing the background doping concentration to be less than 1.0 E14 atoms / cm < 3 >; and finally, adjusting the flow of the silicon source and the doping source to realize accurate regulation and control of low doping concentration and uniformity of the target. According to the invention, the requirements of high-voltage power devices of 10 kV and above on uniform, stable and controllable concentration of high-quality low-doped epitaxial wafers are met, and a foundation is laid for batch application of silicon carbide in the high-voltage field in the future.

Description

Technical Field

[0001] The invention relates to the technical field of epitaxial wafer growth, and in particular to a method for growing a low-doped silicon carbide homoepitaxial wafer. Background Art

[0002] At present, as one of the "two heroes" of the third-generation semiconductor materials, silicon carbide has been industrialized in the field of power devices and has even become the hottest "new darling" in the entire industry. Looking at the domestic and international silicon carbide power electronic device industry chain, new projects such as new construction, expansion, and production are emerging in an endless stream in various links.

[0003] Although silicon carbide materials have been applied in batches in medium and low voltage power devices, such as the common 650 V and 1200 V Schottky diodes (SBDs) and metal oxide field effect transistors (MOSFETs), it has not yet been applied in batches in the high and ultra-high voltage fields due to the considerable technical difficulties in various links such as substrates, epitaxy, chips, and packaging and testing.

[0004] The voltage rating of SiC power devices determines the physical properties required of the epitaxial layer. For example, in low-voltage applications of 600 V, the epitaxial layer doping concentration is about 2E16 atmos / cm 3 To ensure sufficient breakdown voltage. For 1200 V and 1700 V medium voltage devices, the doping concentration of the epitaxial layer is about 1E16 atmos / cm 3 and 7E15 atmos / cm 3 At present, the process technology of each epitaxial plant can basically meet the above index requirements. However, in high voltage applications of 10 kV and above, the doping requirement for the epitaxial layer is as low as 4E14 atmos / cm 3 to 7E14 atmos / cm 3 Moreover, as the voltage level increases, the requirements for doping uniformity are becoming more and more stringent. Therefore, for high-voltage and ultra-high-voltage fields, high-quality low-doping epitaxial technology still faces considerable challenges and needs further development and research, and even industrialization.

[0005] The information disclosed in this background technology section is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as acknowledging or suggesting in any form that the information constitutes the prior art known to those skilled in the art. Summary of the invention

[0006] The first object of the present invention is to provide a method for growing a low-doped silicon carbide homoepitaxial wafer with a doping concentration of 1.0E14 atmos / cm 3 To 1.0E15 atmos / cm 3The product is adjustable and controllable within a wide range with good uniformity, meeting the specification requirements for high-quality low-doped epitaxial wafers for power devices with a withstand voltage of 10 kV and above.

[0007] The above technical objectives of the present invention are achieved through the following technical solutions: A method for growing a low-doped silicon carbide homogeneous epitaxial wafer, which meets the requirements of 10 kV and above withstand voltage power devices for high-quality low-doped epitaxial wafers, comprises the following steps: S01: High temperature H2 baking is used to raise the temperature in the reaction chamber to 30~70℃ higher than the epitaxial growth temperature and maintain it for 2500~3000 seconds. Multiple cycles of baking and purging are performed to effectively remove residual impurities and pollutants in the reaction chamber. This treatment significantly reduces the background doping concentration in the reaction chamber to 3.0~4.0E14 atoms / cm 3 , providing a pure environment for subsequent epitaxial growth and ensuring the high purity of the epitaxial layer.

[0008] S02: Gradually increase the epitaxial growth rate; effectively promote the forward reaction of silicon carbide and enhance the growth rate of the crystal. As the growth rate increases, the incorporation of impurities during the epitaxial process is significantly suppressed, thereby reducing the background doping concentration to 1.0E14 atoms / cm 3 ; This process not only improves production efficiency, but also ensures the high quality and low doping level of the epitaxial wafers.

[0009] S03: Gradually reduce the deposition growth reaction temperature to reduce the background doping concentration to <1.0E14 atoms / cm 3 , inhibiting the desorption and incorporation of background impurities; in the process of gradually lowering the reaction temperature, the low temperature is conducive to adsorption and the characteristics are fully utilized, making it more difficult for background impurities to desorb and enter the epitaxial layer. Through this low-temperature growth strategy, the background doping concentration is further reduced, and the desorption and incorporation of impurities into the epitaxial layer are effectively inhibited, thereby ensuring the extremely low intrinsic doping level of the epitaxial wafer.

[0010] S04: Adjust the flow rate of silicon source and doping source to achieve precise control of target low doping concentration and uniformity, ensuring high quality of epitaxial wafers. This step ensures the realization of target low doping concentration, while optimizing the uniformity within the wafer and ensuring the overall quality of the epitaxial wafer. This flow control not only helps to achieve low doping targets, but also improves product consistency and reliability, meeting the strict requirements of high-voltage power devices for epitaxial wafers.

[0011] Preferably, in step S01, the background doping concentration in the reaction chamber is measured in real time during the baking process, and based on the real-time monitoring data, 2 to 3 cycles of baking and purging are performed until the concentration reaches the target value. Real-time monitoring and data-based feedback control can optimize the baking time and number of times, so that each baking and purging is carried out under the most effective conditions. This not only saves time and energy, but also reduces stress and wear in the reaction chamber and extends the service life of the equipment. At the same time, the uncertainty caused by human judgment is avoided, and the stability and reliability of the entire process are significantly improved.

[0012] Preferably, in step S01, the epitaxial growth temperature is 1640°C. Power devices with withstand voltages of 10kV and above have extremely high requirements for the structural stability and uniformity of epitaxial wafers. 1640°C is a proven optimal epitaxial growth temperature, which can effectively avoid lattice stress or defect generation caused by excessive temperature during the baking process, and ensure the crystallization quality of the epitaxial layer. This temperature setting reduces dislocations and defects in the microstructure, thereby improving the performance stability of the epitaxial wafer under high pressure conditions. At the same time, it helps to maintain a uniform temperature distribution throughout the epitaxial layer growth process, ensure the thickness and doping uniformity of the epitaxial layer, and thereby improve the stability and performance consistency of the device under high pressure conditions.

[0013] Under the condition of limiting the epitaxial growth temperature, the pre-baking of step S01 of the present invention is set to 10-20°C above 1640°C, which can significantly enhance the desorption and removal effect of impurities in the reaction chamber. At this higher temperature, the cleaning effect of hydrogen is fully exerted, and it is easier to remove oxides, hydrocarbons and other impurities attached to the walls and surfaces of the reaction chamber. After the impurities are desorbed, as the reaction temperature is later reduced to the epitaxial growth temperature of 1640°C, the risk of re-desorption or deposition incorporation of impurities is significantly reduced. This differential temperature helps to ensure that impurities are completely removed during the baking process, avoiding re-entry into the crystal structure in the subsequent epitaxial growth stage, and further improving the purity of the epitaxial layer.

[0014] Preferably, in step S02, the epitaxial growth rate is gradually increased from the standard of 50 μm / h by 10 μm / h each time until the background doping concentration is reduced to 1.0E14 atoms / cm 3 . By gradually increasing the epitaxial growth rate, the forward reaction rate of silicon carbide can be accelerated. At a higher growth rate, the silicon carbide crystal structure is formed more quickly, reducing the chance of impurities entering the lattice during crystal growth, which is essential for the production of high-purity epitaxial wafers, especially for epitaxial wafers for 10 kV and above withstand voltage power devices. The growth conditions of the epitaxial layer are gradually optimized. This gradual adjustment ensures uniform growth of the crystal, reduces stress concentration and the generation of dislocations, and thus improves the crystal quality of the epitaxial wafer.

[0015] Preferably, in step S02, the epitaxial growth rate is up to 90 μm / h. This rate can significantly shorten the epitaxial growth time, thereby improving production efficiency, meeting the needs of large-scale industrial production, and at the same time ensuring the purity and crystal quality of the epitaxial wafer.

[0016] Preferably, in step S03, the reaction temperature is gradually reduced, and the temperature is reduced in stages, and the temperature reduction in each stage is 5-10°C, and the reaction temperature after reduction is 30-50°C lower than the epitaxial growth temperature. The staged cooling can gradually reduce the temperature in the reaction chamber, making it more difficult for impurities to desorb and enter the epitaxial layer at a lower temperature. In particular, when the temperature is reduced to 30-50°C lower than the epitaxial growth temperature, the low temperature environment can significantly reduce the migration and re-adsorption of background impurities, thereby effectively reducing the background doping concentration of the epitaxial layer and ensuring that the epitaxial wafer has a higher purity. By gradually cooling down by 5-10°C in each stage, the thermal stress concentration caused by the sudden drop in temperature can be avoided. This progressive cooling strategy helps to release the stress in the epitaxial layer, reduce crystal defects caused by thermal stress, such as dislocations and microcracks, and ultimately improve the structural integrity and crystal quality of the epitaxial wafer.

[0017] Preferably, in step S03, the intrinsic doping concentration is reduced to <1E14 atoms / cm 3 , and can be continuously stabilized at 5.0~6.0E13 atoms / cm 3 . The purity of the epitaxial wafer is significantly improved. During the entire epitaxial wafer growth process, maintaining the background doping concentration in a stable range of 5.0~6.0E13 atoms / cm³ helps to improve the uniformity of the epitaxial wafer. The uniform doping distribution ensures the consistency of the epitaxial wafer over a large area, reduces the performance fluctuation caused by uneven doping in device production, and thus improves the overall quality and production yield of the device. This ultra-low doping concentration reduces unnecessary free carriers, thereby optimizing the electrical properties of the epitaxial wafer.

[0018] Preferably, in step S04, when the proportion of the inner circle of TCS is reduced from 18% to 16%, the flow and distribution of the gas during the epitaxy process are more uniform, making the deposition of the silicon source on the surface of the epitaxial wafer more balanced. The deposition rate difference between different regions is reduced, the thickness and doping concentration uniformity of the entire epitaxial wafer are optimized, and the uniformity within the wafer is optimized to <2%. The yield fluctuation caused by the unevenness of the epitaxial wafer during the manufacturing process can be reduced, thereby improving the overall production efficiency and yield rate. This is especially important for the large-scale production of high-voltage power devices and can effectively reduce production costs.

[0019] Preferably, in step S04, by adjusting the N2 flow rate from 0.41 to 1.82 sccm, the doping concentration can be increased from 2.36E14 to 1.06E15 atoms / cm 3 The linear controllability ensures the repeatability and stability of the process. In mass production, the doping concentration can be accurately reproduced according to the set N2 flow, thus reducing performance fluctuations between batches.

[0020] As a preferred embodiment, the concentration target value of the epitaxial wafer is continuously and stably controlled at 6.30~6.40E14 atoms / cm 3 The doping level of the epitaxial wafer is precisely controlled to ensure high consistency of product quality. The concentration uniformity is stable at 1.60%~2.10%. It can avoid local electric field enhancement or uneven current distribution caused by uneven concentration.

[0021] In summary, the present invention has the following beneficial effects: (1) The present invention first adopts high-temperature hydrogen baking, and performs multiple cycles of baking and purging, which can effectively reduce the background doping concentration in the reaction chamber. Then, by increasing the growth rate, the forward reaction of silicon carbide is promoted, thereby effectively reducing the incorporation of impurities. In this environment, low temperature is used to grow epitaxial wafers. At this time, low temperature is conducive to adsorption, which will effectively inhibit the incorporation of background impurities in the reaction chamber, so that the epitaxial wafer has a lower intrinsic doping level and meets the strict requirements of high-voltage power devices.

[0022] (2) Through precise temperature, rate and atmosphere control, the epitaxial wafers finally produced by the present invention have extremely low intrinsic doping concentrations, meeting the strict requirements of 10 kV and above withstand voltage power devices for high purity and high uniformity of materials. Low-doped silicon carbide epitaxial wafers can support higher voltages and more reliable device performance. Combining the processes of high-temperature baking, high-rate growth and low-temperature epitaxial growth, the present invention can improve production efficiency while maintaining the quality of the epitaxial layer, and ensure that each production batch of epitaxial wafers can meet the expected quality standards. This stable process makes the production process more controllable and consistent, and is suitable for large-scale industrial production. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments described in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1This is a flow chart of the steps of a method for growing a low-doped silicon carbide homoepitaxial wafer according to an embodiment of the present invention; Figure 2 This is a graph showing relevant experimental data of multiple baking cycles in step S01 of an embodiment of the present invention; Figure 3 This is a graph of experimental data related to the improvement of the reaction rate in step S02 of an embodiment of the present invention; Figure 4 This is a graph of experimental data related to the reduction of the growth temperature in step S03 of an embodiment of the present invention; Figure 5 This is a graph showing experimental data related to the stability of intrinsic doping concentration in step S03 of an embodiment of the present invention; Figure 6 This is a graph showing experimental data related to doping uniformity and TCS inner circle ratio in step S04 of an embodiment of the present invention; Figure 7 This is a doping stability test diagram of multiple epitaxial wafers in an embodiment of the present invention; Figure 8 4 is a doping correlation diagram of the doping concentration and the N2 concentration in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, a method for growing a low-doped silicon carbide homoepitaxial wafer proposed in accordance with the present invention, its specific implementation method, characteristics and effects are described in detail as follows.

[0026] like Figure 1 As shown, a method for growing a low-doped silicon carbide homogeneous epitaxial wafer meets the requirements of 10 kV and above withstand voltage power devices for high-quality low-doped epitaxial wafers, including the following steps: S01: High temperature H2 baking is used to raise the temperature in the reaction chamber to 30~70℃ higher than the epitaxial growth temperature and maintain it for 2500~3000 seconds. Multiple cycles of baking and purging are performed to effectively remove residual impurities and pollutants in the reaction chamber. This treatment significantly reduces the background doping concentration in the reaction chamber to 3.0~4.0E14atoms / cm 3 , providing a pure environment for subsequent epitaxial growth and ensuring the high purity of the epitaxial layer.

[0027] Specifically, in step S01, the background doping concentration in the reaction chamber is measured in real time during the baking process, and based on the real-time monitoring data, 2 to 3 cycles of baking and purging are performed until the concentration reaches the target value. The epitaxial growth temperature is 1640°C.

[0028] The present invention is based on the principle that "high temperature is conducive to desorption, low temperature is conducive to adsorption". High temperature H2 baking is used to effectively reduce the impurities adsorbed in the reaction chamber, preventing them from being further doped into the epitaxial wafer during the subsequent epitaxial wafer growth, making it difficult to achieve the low doping requirements and causing doping instability. Figure 2 As shown in FIG. 1 , the method uses a high temperature baking temperature of about 10-20 °C higher than the original epitaxial growth temperature (1640 °C) for the reaction chamber, wherein the high temperature stage is maintained for 2500-3000 s. After 2-3 cycles of baking and purging the reaction chamber, the background doping (intrinsic doping) concentration in the chamber is reduced to 3.0-4.0E14atoms / cm 3 , if the baking is continued, the intrinsic doping concentration will no longer decrease but will slightly increase. The real-time monitoring and data-based feedback control of the present invention can optimize the baking time and frequency, so that each baking and purging is carried out under the most effective conditions. This can not only save time and energy, but also reduce the stress and wear in the reaction chamber and extend the service life of the equipment. At the same time, it avoids the uncertainty caused by human judgment and significantly improves the stability and reliability of the entire process.

[0029] S02: Gradually increase the epitaxial growth rate; effectively promote the forward reaction of silicon carbide and enhance the growth rate of the crystal. As the growth rate increases, the incorporation of impurities during the epitaxial process is significantly suppressed, thereby reducing the background doping concentration to 1.0E14 atoms / cm 3 ; This process not only improves production efficiency, but also ensures the high quality and low doping level of the epitaxial wafers.

[0030] Specifically, in step S02, the epitaxial growth rate is gradually increased from the standard of 50 μm / h by 10 μm / h each time until the background doping concentration is reduced to 1.0E14 atoms / cm 3 .

[0031] like Figure 3 As shown, the present invention is based on increasing the amount of reactants and improving the reaction rate, which is beneficial to the formation of intrinsic silicon carbide and thus effectively reduces the efficiency of impurity incorporation. This method gradually increases the reaction rate based on the original epitaxial growth rate (GR=50um / h). Experiments have found that when the reaction rate reaches 90 um / h, the intrinsic doping concentration is reduced to 1E14 atoms / cm 3 , if the reaction rate is continued to be increased, the intrinsic doping concentration will no longer decrease but will slightly increase. Therefore, in this application, the maximum epitaxial growth rate is 90 µm / h, which can significantly shorten the epitaxial growth time, thereby improving production efficiency and meeting the needs of large-scale industrial production, while ensuring the purity and crystal quality of the epitaxial wafer.

[0032] S03: Gradually reduce the reaction temperature to reduce the background doping concentration to <1.0E14 atoms / cm 3 , inhibiting the desorption and incorporation of impurities; in the process of gradually lowering the reaction temperature, the low temperature is conducive to the adsorption characteristics to be fully utilized, making it more difficult for impurities to desorb and enter the epitaxial layer. Through this low-temperature growth strategy, the background doping concentration is further reduced, and the desorption and incorporation of impurities into the epitaxial layer are effectively inhibited, thereby ensuring the extremely low intrinsic doping level of the epitaxial wafer.

[0033] Specifically, in step S03, the reaction temperature is gradually reduced in stages, and the temperature reduction range in each stage is 5-10°C. The reaction temperature after reduction is 30-50°C lower than the epitaxial growth temperature. The intrinsic doping concentration is reduced to <1E14atoms / cm 3 , and can be continuously stabilized at 5.0~6.0E13atoms / cm 3 .

[0034] In this step, based on the principle that “high temperature is conducive to desorption and low temperature is conducive to adsorption”, the intrinsic doping concentration is further reduced to <1E14 atoms / cm 3 , the reaction temperature is gradually reduced to effectively inhibit the desorption of background impurities in the reaction chamber and their incorporation into the epitaxial layer. The experiment found that when the original reaction temperature (1640℃) was reduced to 1600℃, the intrinsic doping concentration was reduced to <1E14 atoms / cm 3 , and can be continuously stabilized at 5.0~6.0E13 atoms / cm 3 , meeting the next step of debugging requirements. The low temperature environment can significantly reduce the migration and re-desorption of background impurities, thereby effectively reducing the background doping concentration of the epitaxial layer and ensuring that the epitaxial wafer has a higher purity. If the temperature continues to drop, the intrinsic doping concentration will no longer decrease but will increase slightly. Figure 4 and Figure 5 is the relevant experimental data. Preferably, the temperature is reduced by 10°C in each stage, and the reaction temperature after the reduction is 40°C lower than the epitaxial growth temperature.

[0035] S04: Adjust the flow rate of silicon source and doping source to achieve precise control of target low doping concentration and uniformity, ensuring high quality of epitaxial wafers. This step ensures the realization of target low doping concentration, while optimizing the uniformity within the wafer and ensuring the overall quality of the epitaxial wafer. This flow control not only helps to achieve low doping targets, but also improves product consistency and reliability, meeting the strict requirements of high-voltage power devices for epitaxial wafers.

[0036] Specifically, in step S04, when the TCS inner circle ratio is reduced from 18% to 16%, the uniformity within the chip is optimized to <2%. By adjusting the N2 flow rate from 0.41 to 1.82 sccm, the doping concentration can be increased from 2.36E14 to 1.06E15 atoms / cm 3 Linear controllable.

[0037] Uniform and stable doping concentration is a basic requirement for the key parameters of the epitaxial layer, and it also poses considerable challenges. Usually, key consumables of epitaxial furnaces, such as the purity of pure graphite parts, the quality of coated graphite parts, the structure of the carrier, etc., will seriously affect the stability of doping concentration; the debugging of process formulas, such as reaction temperature, pressure, various gas flows, carbon-silicon ratio, etc., also have a significant impact on the stability of doping concentration. This method adjusts the flow distribution of the silicon source (TCS) and the flow of the doping source (N2) in the wafer in order to adjust the doping uniformity and concentration target value (such as Figure 6 ) and tested its stability (such as Figure 7 ), and further conducted E14 atoms / cm 3 Magnitude of series doping (such as Figure 8 ), achieving the concentration specification requirements for low-doped epitaxial wafers for 10 kV withstand voltage devices.

[0038] like Figure 6 As shown in the figure, initially the doping uniformity within the chip was poor (>10%) and did not meet the product requirements. The doping distribution within the chip showed "high in the center and low at the edge". The TCS airflow distribution was changed in turn to reduce the inner circle proportion of TCS, that is, to increase the carbon-silicon ratio in the center and reduce the carbon-silicon ratio at the edge. When the TCS inner circle proportion was reduced from 18% to 16%, the uniformity within the chip was optimized to <2%, meeting the requirements of high-quality products.

[0039] The stability of doping concentration is still the focus and hot topic of epitaxial process. Figure 7 The experiment used this method to continuously test the doping stability of 5 pieces, and the concentration target value was continuously and stably controlled at 6.30~6.40E14atoms / cm 3 , the concentration uniformity is stable at 1.60%~2.10%.

[0040] like Figure 8 The doping concentration VS N2 flow rate is significantly positively correlated. By adjusting the N2 flow rate from 0.41 to 1.82 sccm, the doping concentration can be adjusted from 2.36E14 to 1.06E15 atoms / cm 3 Linear controllable.

[0041] The present invention first adopts high-temperature hydrogen baking, and performs multiple cycles of baking and purging, which can effectively reduce the background doping concentration in the reaction chamber. Then, by increasing the growth rate, the forward reaction of silicon carbide is promoted, thereby effectively reducing the incorporation of impurities. In this environment, low temperature is used to grow epitaxial wafers. At this time, low temperature is conducive to adsorption, which will effectively inhibit the incorporation of background impurities in the reaction chamber, so that the epitaxial wafer has a lower intrinsic doping level and meets the strict requirements of high-voltage power devices.

[0042] Through precise temperature, rate and atmosphere control, the epitaxial wafers finally obtained by the present invention have extremely low intrinsic doping concentrations, meeting the strict requirements of 10kV and above withstand voltage power devices for high purity and high uniformity of materials. Low-doped silicon carbide epitaxial wafers can support higher voltages and more reliable device performance. Combining the processes of high-temperature baking, high-rate growth and low-temperature epitaxial growth, the present invention can improve production efficiency while maintaining the quality of the epitaxial layer, and ensure that each production batch of epitaxial wafers can meet the expected quality standards. This stable process makes the production process more controllable and consistent, and is suitable for large-scale industrial production.

[0043] Those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for growing low-doped silicon carbide homoepitaxial wafers, which meets the requirements of 10 kV and above withstand voltage power devices for high-quality low-doped epitaxial wafers, characterized in that: The steps are as follows: S01: Use high-temperature H2 baking to raise the temperature in the reaction chamber to 30~70℃ higher than the epitaxial growth temperature and maintain it for 2500~3000 seconds. Perform multiple cycles of baking and purging to reduce the background doping concentration in the reaction chamber to 3.0~4.0E14atoms / cm 3 ; S02: Gradually increase the epitaxial growth rate; reduce the background doping concentration to 1.0E14 atoms / cm 3 ; S03: Gradually reduce the reaction deposition growth temperature to reduce the background doping concentration to <1.0E14 atoms / cm 3 , inhibiting the desorption and incorporation of background impurities; S04: Adjust the flow rate of silicon source and doping source to achieve precise control of target low doping concentration and uniformity to ensure high quality of epitaxial wafers.

2. The method for growing a low-doped silicon carbide homoepitaxial wafer according to claim 1, characterized in that: In step S01, the background doping concentration in the reaction chamber is measured in real time during the baking process, and based on the real-time monitoring data, 2 to 3 cycles of baking and purging are performed until the concentration reaches the target value.

3. The method for growing a low-doped silicon carbide homoepitaxial wafer according to claim 1, characterized in that: In step S01, the temperature of the epitaxial growth H2 baking is 30-70° C. higher than the deposition growth temperature.

4. The method for growing a low-doped silicon carbide homoepitaxial wafer according to claim 1, characterized in that: In step S02, the epitaxial growth rate is gradually increased from the standard 50 µm / h by 10 µm / h each time until the background doping concentration is reduced to 1.0E14 atoms / cm 3 .

5. The method for growing a low-doped silicon carbide homoepitaxial wafer according to claim 4, characterized in that: In step S02, the epitaxial growth rate is up to 90 µm / h.

6. The method for growing a low-doped silicon carbide homoepitaxial wafer according to claim 1, characterized in that: In step S03, the deposition growth reaction temperature is gradually reduced by stages, and the temperature reduction range in each stage is 5-10°C. The reaction temperature after reduction is 30-70°C lower than the epitaxial growth temperature.

7. The method for growing a low-doped silicon carbide homoepitaxial wafer according to claim 1, characterized in that: In step S03, the intrinsic doping concentration is reduced to <1E14 atoms / cm 3 , and can be continuously stabilized at 5.0~6.0E13 atoms / cm 3 .

8. The method for growing a low-doped silicon carbide homoepitaxial wafer according to claim 1, characterized in that: In step S04, when the TCS inner circle ratio is reduced from 18% to 16%, the intra-chip uniformity is optimized to <2%.

9. The method for growing a low-doped silicon carbide homoepitaxial wafer according to claim 1, characterized in that: In step S04, by adjusting the N2 flow rate from 0.41 to 1.82 sccm, the doping concentration can be increased from 2.36E14 to 1.06E15 atoms / cm 3 Linear controllable.

10. The method for growing a low-doped silicon carbide homoepitaxial wafer according to claim 1, characterized in that: The concentration target value of the epitaxial wafer produced is continuously and stably controlled at 6.30~6.40E14 atoms / cm 3 , the concentration uniformity is stable at 1.60%~2.10%.

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