Display device

Abstract

The invention provides a display device. The display device comprises a pixel array, a multiplexer circuit and a plurality of light-emitting driving circuits. The multiplexer circuit receives a plurality of data voltages and a plurality of multiplexing control signals so as to provide the data voltages to the self-luminous pixel circuits of the pixel array based on the multiplexing control signals. The light-emitting driving circuit provides a plurality of light-emitting signals to the self-light-emitting pixel circuits. In the horizontal scanning period, a first edge and a second edge of the light emitting pulse wave are formed on a corresponding one of the light emitting signals, and the first edge and the second edge are at least one charge discharge time away from a second multiplexing edge of the pre-charge pulse wave and the multiplexer pulse wave.

Description

Technical Field

[0001] The present invention relates to a display device, and in particular to a display device with a self-luminous pixel circuit. Background Art

[0002] With the advancement of semiconductor manufacturing technology, the size of various electronic products is gradually developing towards being lighter and thinner. Generally speaking, the display panel of a display device is composed of a pixel array, and the source driver transmits the data voltage required by the pixel array through multiple data lines. In addition, as the resolution of the display panel increases, the number of data lines also increases, resulting in an increase in the number of pins of the source driver. Therefore, a multiplexer circuit is configured between the pixel array and the source driver, thereby reducing the number of pins of the source driver. However, when the pixel array is composed of a self-luminous pixel circuit, the light signal that illuminates the self-luminous pixel circuit will affect the data voltage transmitted by the multiplexer circuit, affecting the display of the picture. Summary of the invention

[0003] The object of the present invention is to provide a display device which can stagger the pulse edge of a multiplex control signal and the pulse edge of a light emitting signal to reduce the influence of the pulse edge of the light emitting signal on a data voltage.

[0004] The display device of the present invention includes a pixel array, a multiplexer circuit, and a plurality of light-emitting driving circuits. The pixel array has a plurality of self-luminous pixel circuits arranged in an array. The multiplexer circuit is coupled to the pixel array and receives a plurality of data voltages and a plurality of multiplexed control signals to provide the data voltages to the self-luminous pixel circuits based on the multiplexed control signals. The light-emitting driving circuit is coupled to the pixel array to provide a plurality of light-emitting signals to the self-luminous pixel circuits. During a horizontal scanning period, the multiplexed control signal simultaneously forms a pre-charge pulse and sequentially forms a plurality of multiplexer pulses that do not overlap in time, wherein the pre-charge pulse and the multiplexer pulses have a first multiplexed edge in front and a second multiplexed edge in the back. A first edge and a second edge of the light-emitting pulse are formed on a corresponding one of the light-emitting signals, wherein the first edge and the second edge are at least one charge discharge time away from the second multiplexed edge of the pre-charge pulse and the multiplexer pulse.

[0005] Based on the above, in the display device of the embodiment of the present invention, during the horizontal scanning period, the first edge and the second edge of the corresponding one of the light-emitting signal are at least one charge discharge time away from the pre-charge pulse and the second multiplexed edge of the multiplexer pulse, so as to reduce the influence of the first edge and the second edge of the light-emitting pulse of the light-emitting signal on the data voltage.

[0006] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a system diagram of a display device according to an embodiment of the present invention.

[0008] Figure 2A FIG. 1 is a timing diagram of a multiplex control signal and a light emitting signal according to a first embodiment of the present invention.

[0009] Figure 2B and Figure 2C for Figure 2A An enlarged schematic diagram of a portion of the timing of the multiplexed control signal and the light emitting signal.

[0010] Figure 3 FIG. 4 is a timing diagram of a multiplex control signal and a light emitting signal according to a second embodiment of the present invention.

[0011] Figure 4 FIG. 4 is a timing diagram of multiplex control signals and light emitting signals according to the third embodiment of the present invention.

[0012] Figure 5 FIG. 4 is a timing diagram of multiplex control signals and light emitting signals according to a fourth embodiment of the present invention.

[0013] Figure 6 FIG. 4 is a timing diagram of multiplex control signals and light emitting signals according to a fifth embodiment of the present invention.

[0014] The reference numerals are as follows:

[0015] 100: Display device

[0016] 110: Timing controller

[0017] 120: Source driver

[0018] 130: Multiplexer circuit

[0019] 140_1~140_X:Scanning circuit

[0020] 150: Pixel Array

[0021] 160_1~160_X: Light-emitting drive circuit

[0022] A1~A6、A6a:Time interval

[0023] B1~B6, B1a, B6a: Multiplexer pulse

[0024] CS1, CS2, CS3: control signals

[0025] EM: Luminescent signal

[0026] Em1: First edge

[0027] Em2: Second edge

[0028] Ep11, Ep21 first multiplex edge

[0029] Ep12, Ep22: Second multiplexing edge

[0030] H-line: Horizontal scanning period

[0031] H-sync: horizontal synchronization signal

[0032] M11~MPN: Transistor

[0033] Mux1~MuxN: multiplex control signal

[0034] Pch: Pre-charge pulse

[0035] PX: Self-luminous pixel circuit

[0036] S1 and S2: Scanning signal

[0037] Ta, Tb: Charge discharge time

[0038] Vdata1~VdataP: data voltage

[0039] Vst, EMst: start signal DETAILED DESCRIPTION

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0041] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

[0042] The terms used herein are only for the purpose of describing specific embodiments and are not restrictive. As used herein, unless the content clearly indicates, the singular forms "one", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that when used in this specification, the terms "include" and / or "include" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or their combinations.

[0043] Figure 1 is a system diagram of a display device according to an embodiment of the present invention. Figure 1 In this embodiment, the display device 100 includes a timing controller 110, a source driver 120, a multiplexer circuit 130, a plurality of scanning circuits 140_1 to 140_X, a pixel array 150, and a plurality of light-emitting driving circuits 160_1 to 160_X, wherein the pixel array 150 has a plurality of self-luminous pixel circuits PX arranged in an array, and X is a positive integer.

[0044] The pixel array 150 is coupled between the multiplexer circuit 130, multiple scan circuits 140_1 to 140_X, the pixel array 150, and multiple light-emitting driving circuits 160_1 to 160_X to receive scan signals S1 and S2 from the scan circuits 140_1 to 140_X, receive data voltages Vdata1 to VdataP from the multiplexer circuit 130, and receive light-emitting signals EM from the multiple light-emitting driving circuits 160_1 to 160_X, where P is a positive integer.

[0045] The timing controller 110 is coupled to the source driver 120, the multiplexer circuit 130, the scan circuits 140_1-140_X, and the plurality of light-emitting driving circuits 160_1-160_X to provide a control signal CS3 to the source driver 120, a control signal CS1 and a start signal Vst to the scan circuits 140_1-140_X, and a control signal CS2 and a start signal EMst to the light-emitting driving circuits 160_1-160_X. In addition, the source driver 120 is coupled to the multiplexer circuit 130 to provide data voltages Vdata1-VdataP to the multiplexer circuit 130.

[0046] The multiplexer circuit 130 receives the data voltages Vdata1-VdataP from the source driver 120 and the multiplex control signals Mux1-MuxN from the timing controller 110, and provides the data voltages Vdata1-VdataP to the self-luminous pixel circuits PX based on the multiplex control signals Mux1-MuxN. In addition, the light-emitting driving circuits 160_1-160_X receive the control signal CS2 and the start signal EMst from the timing controller 110 to provide a plurality of light-emitting signals EM to the self-luminous pixel circuits PX.

[0047] During the horizontal scanning period, the multiplex control signals Mux1-MuxN simultaneously form pre-charge pulses and sequentially form multiplexer pulses that do not overlap in time (eg Figures 2A to 6 ), wherein the pre-charge pulse and the multiplexer pulses have a first multiplex edge in front and a second multiplex edge in the back. The first edge and the second edge of the luminous pulse are formed on a corresponding one of the luminous signals EM, wherein the first edge and the second edge are at least one charge discharge time away from the second multiplex edge of the pre-charge pulse and the multiplexer pulse.

[0048] Furthermore, the second multiplex edge of the multiplex control signals Mux1-MuxN is used to turn off the transmission of the data voltages Vdata1-VdataP. If the first edge and the second edge of the light pulse of the light emitting signal EM are too close to the second multiplex edge of the multiplex control signals Mux1-MuxN (i.e., the distance is less than the charge discharge time), the coupled charges cannot be released, affecting the data voltages Vdata1-VdataP transmitted by the multiplexer circuit 130. Therefore, if the first edge and the second edge of the light pulse of the light emitting signal EM are far away from the second multiplex edge of the multiplex control signals Mux1-MuxN by the charge discharge time, the coupled charges can be completely released, reducing the influence of the first edge and the second edge of the light pulse of the light emitting signal EM on the data voltages Vdata1-VdataP.

[0049] In this embodiment, the start signal Vst is used to start the scan circuits 140_1 ˜ 140_X, and the start signal EMst is used to start the light emitting driving circuits 160_1 ˜ 160_X.

[0050] In this embodiment, the multiplexer circuit 130 includes a plurality of transistors M11-MPN, which are controlled by multiplexing control signals Mux1-MuxN to transmit data voltages Vdata1-VdataP to corresponding rows of self-luminous pixel circuits PX, wherein the transistors M11-MPN are P-type transistors as an example, but the embodiment of the present invention is not limited thereto.

[0051] In this embodiment, the charge discharge time is, for example, a time constant of 5RC.

[0052] Figure 2A FIG. 1 is a timing diagram of a multiplex control signal and a light emitting signal according to a first embodiment of the present invention. Figure 2B and Figure 2C for Figure 2A This is an enlarged diagram of the timing of multiplexed control signals and light-emitting signals. Figure 1 , FIG. 2A to FIG. 2C In this embodiment, six multiplexing control signals Mux1 to Mux6 are taken as an example, but the embodiment of the present invention is not limited thereto. In the horizontal scanning period H-line defined between two pulses of the horizontal synchronization signal H-sync, the multiplexing control signals Mux1 to Mux6 will first simultaneously form a pre-charge pulse Pch to release the charge on the line. Then, the multiplexing control signals Mux1 to Mux6 sequentially form a plurality of multiplexer pulses B1 to B6 that do not overlap in time. The time intervals A1 to A6 between the multiplexer pulses B1 to B6 and the pre-charge pulses Pch are, for example, the same as each other, and the pulse widths of the multiplexer pulses B1 to B6 are also the same as each other. Among them, the horizontal synchronization signal H-sync can be one of the control signals CS3 provided to the source driver 120, but the embodiment of the present invention is not limited thereto.

[0053] In this embodiment, the pre-charge pulse Pch and the multiplexer pulses B1-B6 have a first multiplexing edge in front (such as the falling edge shown by Ep11 and Ep2, but the embodiment of the present invention is not limited thereto) and a second multiplexing edge in the back (such as the rising edge shown by Ep12 and Ep22, but the embodiment of the present invention is not limited thereto). In addition, a first edge Em1 (herein, the falling edge is taken as an example, but the embodiment of the present invention is not limited thereto) and a second edge Em2 (herein, the rising edge is taken as an example, but the embodiment of the present invention is not limited thereto) of the light emitting pulse are formed on the light emitting signal EM. In the horizontal scanning period H-line, the first edge Em1 of the light emitting pulse can be located in the pre-charge pulse Pch and is far away from the charge discharge time Ta and Tb range of the second multiplexing edge Ep12 of the pre-charge pulse Pch. Furthermore, the second edge Em2 of the light pulse may be located between the two later multiplexer pulses B5-B6 among the multiplexer pulses B1-B6, ie, away from the charge discharge time Ta and Tb of the second multiplexer edge (such as Ep22) of the multiplexer pulses B5-B6.

[0054] In the embodiment of the present invention, the charge discharge time Ta is related to the time constant of the data voltage (Vdata1~VdataP) (that is, the time constant related to the data line), and the charge discharge time Tb is related to the time constant of the circuit of the multiplexer circuit 130, which is determined according to the circuit design requirements, but the embodiment of the present invention is not limited thereto.

[0055] Figure 3 FIG. 1 is a timing diagram of multiplex control signals and light emitting signals according to the second embodiment of the present invention. Figure 1 , Figure 2A to Figure 2C and to Figure 3 , wherein the same or similar elements are numbered the same or similarly. In this embodiment, in the horizontal scanning period H-line, the first edge Em1 of the light pulse is located in the first multiplexer pulse B1a, and the second edge Em2 of the light pulse is located between the later two multiplexer pulses B5-B6 among the multiplexer pulses B1-B6.

[0056] In this embodiment, the pulse width of the first multiplexer pulse B1a is greater than the multiple pulse widths of the other multiplexer pulses B5-B6, that is, the pulse width of the first multiplexer pulse B1a is adjusted to be wider. In addition, the time interval A6a between the two later multiplexer pulses B5-B6 among the multiplexer pulses B1-B6 is greater than the multiple time intervals A1-A5 between the other multiplexer pulses B1-B6 among the multiplexer pulses B1-B6, that is, the time interval A6a is adjusted to be larger.

[0057] Figure 4 FIG. 1 is a timing diagram of multiplex control signals and light emitting signals according to the third embodiment of the present invention. Figure 1 , Figure 2A to Figure 2C and to Figure 4 , wherein the same or similar elements are numbered the same or similarly. In this embodiment, in the horizontal scanning period H-line, the first edge Em1 of the light emitting pulse is located in the last multiplexer pulse B6 among the multiplexer pulses B1 to B6, and the second edge Em2 of the light emitting pulse is located after the last multiplexer pulse B6 and close to the end of the horizontal scanning period H-line.

[0058] Figure 5 FIG. 1 is a timing diagram of multiplex control signals and light emitting signals according to the fourth embodiment of the present invention. Figure 1 , Figure 2A to Figure 2C and to Figure 5 , wherein the same or similar elements are numbered the same or similarly. In this embodiment, in the horizontal scanning period H-line, the first edge Em1 of the light emitting pulse is located in the last multiplexer pulse B6a among the multiplexer pulses B1 to B6, and the second edge Em2 of the light emitting pulse is located after the last multiplexer pulse B6a and close to the end of the horizontal scanning period H-line, wherein the pulse width of the last multiplexer pulse B6a is greater than the multiple pulse widths of the other multiplexer pulses B1 to B5, that is, the pulse width of the last multiplexer pulse B6a is adjusted to be wider.

[0059] Figure 6 FIG. 1 is a timing diagram of multiplex control signals and light emitting signals according to the fifth embodiment of the present invention. Figure 1 , Figure 2A to Figure 2C and to Figure 6 , wherein the same or similar elements are numbered the same or similarly. In this embodiment, during the horizontal scanning period H-line, the first edge Em1 of the light emitting pulse is located within the pre-charge pulse Pch, and the second edge Em2 of the light emitting pulse is located between the second to last multiplexer pulse B5 among the multiplexer pulses B1 to B6.

[0060] In summary of the above embodiments, the first edge Em1 and the second edge Em2 of the luminous signal EM are at least one charge discharge time (such as Ta, Tb) away from the pre-charge pulse Pch and the second multiplexed edges Ep12 of the multiplexer pulses B1-B6, so as to reduce the influence of the first edge and the second edge of the luminous pulse of the luminous signal EM on the data voltages Vdata1-VdataP. In addition, according to the lighting brightness requirement, the first edge Em1 of the luminous signal EM can be located at any one of the pre-charge pulse Pch and the multiplexer pulses B1-B6 or any one of the time intervals A1-A6 between the multiplexer pulses B1-B6 and the pre-charge pulse Pch, and the pre-charge pulse Pch, the multiplexer pulses B1-B6 and the time intervals A1-A6 can be adjusted according to the driving requirements. Relatively speaking, the first edge Em2 of the light emitting signal EM can be located at any one of the multiplexer pulses B1-B6 or any one of the time intervals A1-A6 between the multiplexer pulses B1-B6 and the pre-charge pulse Pch, and the multiplexer pulses B1-B6 and the time intervals A1-A6 can be adjusted according to the driving requirements. The above driving method can be determined according to the circuit design requirements or environmental changes, and the embodiment of the present invention is not limited thereto.

[0061] In summary, in the display device of the embodiment of the present invention, during the horizontal scanning period, the first edge and the second edge of the corresponding one of the light-emitting signal are at least one charge discharge time away from the pre-charge pulse and the second multiplexed edge of the multiplexer pulse, so as to reduce the influence of the first edge and the second edge of the light-emitting pulse of the light-emitting signal on the data voltage.

[0062] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended claims.

Claims

1. A display device, comprising: A pixel array having a plurality of self-luminous pixel circuits arranged in an array; a multiplexer circuit coupled to the pixel array and receiving a plurality of data voltages and a plurality of multiplex control signals, so as to provide the plurality of data voltages to the plurality of self-luminous pixel circuits based on the plurality of multiplex control signals; A plurality of light-emitting driving circuits are coupled to the pixel array to provide a plurality of light-emitting signals to the plurality of self-luminous pixel circuits. wherein during a horizontal scanning period, a plurality of the multiplex control signals simultaneously form a precharge pulse and sequentially form a plurality of multiplexer pulses that do not overlap in time, wherein the precharge pulse and the plurality of multiplexer pulses have a first multiplex edge in front and a second multiplex edge in the back, and A first edge and a second edge of a light pulse are formed on a corresponding one of the plurality of light signals, wherein the first edge and the second edge are at least one charge discharge time away from the pre-charge pulse and the plurality of the second multiplexed edges of the plurality of multiplexer pulses.

2. The display device as claimed in claim 1, wherein during the horizontal scanning period, the first edge of the light emitting pulse is located within the pre-charge pulse, and the second edge of the light emitting pulse is located between two later multiplexer pulses among the multiplexer pulses.

3. The display device as claimed in claim 1, wherein during the horizontal scanning period, the first edge of the light-emitting pulse is located in a first multiplexer pulse among the multiplexer pulses, and the second edge of the light-emitting pulse is located between two later multiplexer pulses among the multiplexer pulses.

4. The display device as claimed in claim 3, wherein a pulse width of the first multiplexer pulse is greater than a plurality of pulse widths of the remaining multiplexer pulses among the plurality of multiplexer pulses.

5. The display device as claimed in claim 3, wherein a time interval between the two later multiplexer pulses among the multiplexer pulses is greater than time intervals between the remaining multiplexer pulses among the multiplexer pulses.

6. The display device as claimed in claim 1, wherein during the horizontal scanning period, the first edge of the light emitting pulse is located in a last multiplexer pulse among the multiplexer pulses, and the second edge of the light emitting pulse is located after the last multiplexer pulse.

7. The display device as claimed in claim 6, wherein a pulse width of the last multiplexer pulse is greater than a plurality of pulse widths of the remaining multiplexer pulses among the plurality of multiplexer pulses.

8. The display device as claimed in claim 1, wherein during the horizontal scanning period, the first edge of the light emitting pulse is located within the pre-charge pulse, and the second edge of the light emitting pulse is located between the second to last multiplexer pulses among the multiplexer pulses.

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