Photoelectric driving circuit and electronic equipment

Abstract

A photoelectric driving circuit and an electronic device belong to the technical field of electronic circuits and comprise a detection circuit, a calibration circuit and a driving circuit. The detection circuit detects the power supply direct current flowing through the light-emitting component so as to output a detection signal; the calibration circuit outputs each enable signal based on the detection signal, reduces the number of the output enable signals in response to the detection signal being greater than a first preset voltage, and increases the number of the output enable signals in response to the detection signal being less than a second preset voltage; the driving circuit comprises a plurality of driving assemblies connected in parallel; the driving assembly transmits power supply direct current based on the enable signal; wherein the enabling signals are connected to the driving assemblies in a one-to-one correspondence mode; the current of the power supply direct current is dynamically adjusted, the LED aging possibility in the light-emitting assembly is reduced, and the stability and reliability of the photoelectric driving circuit are improved.

Description

Technical Field

[0001] The present application belongs to the field of drive technology, and in particular relates to a photoelectric drive circuit and an electronic device. Background Art

[0002] The light-emitting component usually includes at least one LED. The forward current of the LED changes with the temperature. Once the ambient temperature exceeds 50°C, the forward current of the LED will increase significantly. In this case, if a large current is still applied, it is easy to cause the LED to age.

[0003] Therefore, the stability and reliability of the related photoelectric drive circuit are poor. Summary of the invention

[0004] The purpose of the present application is to provide a photoelectric drive circuit and an image sensor, aiming to solve the problem of poor stability and reliability of related photoelectric drive circuits.

[0005] The embodiment of the present application provides a photoelectric drive circuit, which is connected to a light-emitting component and includes a detection circuit, a calibration circuit and a drive circuit;

[0006] The detection circuit is connected to the light-emitting component and is used to detect the power supply direct current flowing through the light-emitting component to output a detection signal;

[0007] The calibration circuit is connected to the detection circuit, and is used to output various enable signals based on the detection signal, and in response to the detection signal being greater than a first preset voltage, reduce the number of the output enable signals, and in response to the detection signal being less than a second preset voltage, increase the number of the output enable signals;

[0008] The driving circuit includes a plurality of driving components connected in parallel;

[0009] The driving component is connected to the light emitting component and the calibration circuit, and is used to transmit the power supply DC based on the enable signal;

[0010] Among them, each of the enable signals is connected to each driving component in a one-to-one correspondence.

[0011] In one embodiment, the calibration circuit comprises:

[0012] A first comparison circuit, connected to the detection circuit, for outputting a first decision signal in response to the detection signal being greater than a first preset voltage;

[0013] A second comparison circuit is connected to the detection circuit and is used to output a second decision signal in response to the detection signal being less than a second preset voltage;

[0014] The output circuit, together with the first comparison circuit, the second comparison circuit and the plurality of driving components, is used to output the enable signal, reduce the number of the output enable signals according to the first judgment signal, and increase the number of the output enable signals according to the second judgment signal.

[0015] In one embodiment, the number of the driving components is n, where n is an even number; and the output circuit includes:

[0016] The first output module is connected to the first comparison circuit and n / 2 of the driving components, and is used to output n / 2 enable signals according to a first configuration signal, and reduce the number of the output enable signals according to the first decision signal.

[0017] The second output module is connected to the second comparison circuit and n / 2 of the driving components, and is used to stop the output of the enable signal according to the second configuration signal, and increase the number of the output enable signals according to the second judgment signal.

[0018] In one embodiment, the first decision signal includes a first positive decision signal and a first negative decision signal; the first configuration signal includes a first reset signal and a first set signal;

[0019] The first output module includes a first D flip-flop, a first transmission gate and n / 2 second D flip-flops;

[0020] The data input terminal of the first D flip-flop and the positive control terminal of the first transmission gate are used together as the first negative pole decision signal input terminal of the first output module, and are connected to the first comparison circuit to receive the first negative pole decision signal;

[0021] The negative control terminal of the first transmission gate is used as the first positive decision signal input terminal of the first output module, and is connected to the first comparison circuit to receive the first positive decision signal;

[0022] The data output terminal of the first D flip-flop is connected to the input terminal of the first transmission gate, and the output terminal of the first transmission gate is connected to the data input terminal of the first second D flip-flop;

[0023] The data input terminal of the i-th second D flip-flop and the data output terminal of the (i+1)-th second D flip-flop serve together as the i-th enable signal output terminal of the first output module, and are connected to the i-th driving component to output the i-th enable signal;

[0024] The data output terminal of the n / 2th second D flip-flop is used as the n / 2th enable signal output terminal of the first output module, and is connected to the n / 2th driving component to output the n / 2th enable signal;

[0025] The clock end of the first D flip-flop and the clock ends of n / 2 of the second D flip-flops are used together as a clock signal input end of the first output module to receive a clock signal;

[0026] The reset terminals of n / 2 of the second D flip-flops (DFF1 to DFF(n / 2)) are used together as the first reset signal input terminal of the first output module to receive the first reset signal;

[0027] The set terminals of n / 2 of the second D flip-flops are used together as the first set signal input terminal of the first output module to receive the first set signal;

[0028] Here, i is a positive integer less than n / 2.

[0029] In one embodiment, the second decision signal includes a second positive decision signal and a second negative decision signal; the second configuration signal includes a second reset signal and a second set signal;

[0030] The second output module includes a third D flip-flop, a second transmission gate and n / 2 fourth D flip-flops;

[0031] The data input terminal of the third D flip-flop and the negative control terminal of the second transmission gate are used together as the second positive pole decision signal input terminal of the second output module, and are connected to the second comparison circuit to receive the second positive pole decision signal;

[0032] The positive control terminal of the second transmission gate is used as the second negative pole decision signal input terminal of the second output module, and is connected to the second comparison circuit to receive the second negative pole decision signal;

[0033] The data output terminal of the third D flip-flop is connected to the input terminal of the second transmission gate, and the output terminal of the second transmission gate is connected to the data input terminal of the first fourth D flip-flop;

[0034] The data input terminal of the jth fourth D flip-flop and the data output terminal of the i+1th second D flip-flop serve together as the jth enable signal output terminal of the second output module, and are connected to the n / 2+jth driving component to output the n / 2+jth enable signal;

[0035] The data output terminal of the n / 2th fourth D flip-flop is used as the n / 2th enable signal output terminal of the second output module, and is connected to the nth driving component to output the nth enable signal;

[0036] The clock end of the third D flip-flop and the clock ends of the n / 2 fourth D flip-flops are used together as the clock signal input end of the second output module to receive the clock signal;

[0037] The reset terminals of the n / 2 fourth D flip-flops are used together as the second reset signal input terminal of the second output module to receive the second reset signal;

[0038] The set terminals of the n / 2 fourth D flip-flops are used together as the second set signal input terminal of the second output module to receive the second set signal;

[0039] Here, j is an integer less than n and greater than or equal to n / 2+1.

[0040] In one embodiment, the first decision signal includes a first positive decision signal and a first negative decision signal;

[0041] The first comparison circuit includes a first comparator and a first inverter;

[0042] The non-inverting input terminal of the first comparator serves as the first reference voltage input terminal of the first comparison circuit to access the first reference voltage;

[0043] The inverting input terminal of the first comparator is used as a detection signal input terminal of the first comparison circuit and is connected to the detection circuit to receive the detection signal;

[0044] The output end of the first comparator and the input end of the first inverter are used together as the first positive pole decision signal output end of the first comparison circuit, and are connected to the output circuit to output the first positive pole decision signal;

[0045] The output end of the first inverter serves as the first negative pole decision signal output end of the first comparison circuit and is connected to the output circuit to output the first negative pole decision signal.

[0046] In one embodiment, the second decision signal includes a second positive decision signal and a second negative decision signal;

[0047] The second comparison circuit includes a second comparator and a second inverter;

[0048] The inverting input terminal of the second comparator serves as the second reference voltage input terminal of the second comparison circuit to access the second reference voltage;

[0049] The non-inverting input terminal of the second comparator is used as the detection signal input terminal of the second comparison circuit and is connected to the detection circuit to receive the detection signal;

[0050] The output terminal of the second comparator and the input terminal of the second inverter are used together as the second positive pole decision signal output terminal of the second comparison circuit, and are connected to the output circuit to output the second positive pole decision signal;

[0051] The output end of the second inverter serves as the second negative pole decision signal output end of the second comparison circuit and is connected to the output circuit to output the second negative pole decision signal.

[0052] In one embodiment, the detection circuit comprises:

[0053] A sampling circuit, connected to the light-emitting component, for sampling the DC power supply flowing through the light-emitting component to output a two-terminal sampling signal;

[0054] The conversion circuit is connected to the sampling circuit and the calibration circuit, and is used for converting the double-ended sampling signal into a single-ended detection signal.

[0055] In one embodiment, the sampling circuit includes a first field effect transistor, a second field effect transistor and a first resistor;

[0056] The source of the first field effect transistor and the source of the second field effect transistor are used together as a power supply DC input terminal of the sampling circuit to access the power supply DC;

[0057] The drain of the second field effect transistor, the drain of the first field effect transistor, the first end of the first resistor and the second end of the first resistor together serve as a sampling signal output end of the sampling circuit and are connected to the conversion circuit to output the sampling signal.

[0058] An embodiment of the present invention further provides an electronic device, wherein the electronic device includes the above-mentioned photoelectric driving circuit.

[0059] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: since the detection circuit detects the power supply DC flowing through the light-emitting component to output a detection signal; the calibration circuit outputs various enable signals based on the detection signal; when the detection signal is greater than a first preset voltage, the calibration circuit reduces the number of output enable signals, thereby reducing the number of drive components that transmit the power supply DC and reducing the current of the power supply DC; when the detection signal is less than a second preset voltage, the number of output enable signals is increased, thereby increasing the number of drive components that transmit the power supply DC and increasing the current of the power supply DC; therefore, the current of the power supply DC is dynamically adjusted, the possibility of aging of the LED in the light-emitting component is reduced, and the stability and reliability of the photoelectric drive circuit are improved; at the same time, when the current of the power supply DC is dynamically adjusted, there is no need to configure a microprocessor, which simplifies the circuit and reduces the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0061] Figure 1 A schematic diagram of a structure of a photoelectric drive circuit provided in an embodiment of the present application;

[0062] Figure 2 A schematic diagram of a structure of a calibration circuit in a photoelectric drive circuit provided in an embodiment of the present application;

[0063] Figure 3 A schematic diagram of a structure of a detection circuit in a photoelectric drive circuit provided in an embodiment of the present application;

[0064] Figure 4 A partial exemplary circuit schematic diagram of a calibration circuit in a photoelectric drive circuit provided in an embodiment of the present application;

[0065] Figure 5 A partial exemplary circuit schematic diagram of a photoelectric drive circuit provided in an embodiment of the present application;

[0066] Figure 6 Another partial exemplary circuit schematic diagram of a photoelectric drive circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0068] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0069] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0070] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0071] Figure 1 The schematic diagram of the structure of the photoelectric drive circuit provided by the preferred embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0072] The above-mentioned photoelectric driving circuit is connected to the light-emitting component 80 , and includes a detection circuit 01 , a calibration circuit 02 and a driving circuit 03 .

[0073] The detection circuit 01 is connected to the light-emitting component 80 and is used to detect the power supply DC current flowing through the light-emitting component 80 to output a detection signal.

[0074] The calibration circuit 02 is connected to the detection circuit 01, and is used to output various enable signals based on the detection signal, and in response to the detection signal being greater than the first preset voltage, reduce the number of output enable signals, and in response to the detection signal being less than the second preset voltage, increase the number of output enable signals.

[0075] The driving circuit 03 includes a plurality of driving components 31 connected in parallel.

[0076] The driving component 31 is connected to the light emitting component 80 and the calibration circuit 02, and is used to transmit the power supply DC based on the enable signal.

[0077] Among them, each enable signal is connected to each driving component 31 in a one-to-one correspondence.

[0078] The light emitting assembly 80 is used to emit light according to the supplied direct current.

[0079] like Figure 2 As shown, the calibration circuit 02 includes a first comparison circuit 21 , a second comparison circuit 22 and an output circuit 23 .

[0080] The first comparison circuit 21 is connected to the detection circuit 01, and is used to output a first decision signal in response to the detection signal being greater than a first preset voltage.

[0081] The second comparison circuit 22 is connected to the detection circuit 01, and is used to output a second decision signal in response to the detection signal being smaller than the second preset voltage.

[0082] The output circuit 23, the first comparison circuit 21, the second comparison circuit 22 and the plurality of driving components 31 are used to output enable signals, and reduce the number of output enable signals according to the first judgment signal, and increase the number of output enable signals according to the second judgment signal.

[0083] The calibration circuit 02 includes a first comparison circuit 21, a second comparison circuit 22 and an output circuit 23. Only a comparator and a logic circuit are required to implement the calibration circuit 02. No microprocessor is required. While dynamically adjusting the current of the DC power supply, the circuit is simplified and the cost is reduced.

[0084] There are n driving components 31, where n is an even number; the output circuit 23 includes a first output module and a second output module.

[0085] The first output module is connected to the first comparison circuit 21 and n / 2 driving components 31, and is used to output n / 2 enable signals according to the first configuration signal, and reduce the number of output enable signals according to the first decision signal.

[0086] The second output module is connected to the second comparison circuit 22 and n / 2 driving components 31, and is used to stop the output of the enable signal according to the second configuration signal, and increase the number of output enable signals according to the second decision signal.

[0087] It can be understood that when the photoelectric driving circuit is started, the first output module outputs n / 2 enable signals according to the first reset signal, and the second output module stops outputting the enable signal according to the second reset signal. Thereafter, when the detection signal is greater than the first preset voltage, the first output circuit 23 reduces the number of output enable signals, thereby reducing the number of drive components 31 that transmit power supply DC, thereby reducing the current of the power supply DC; when the detection signal is less than the second preset voltage, the second output module increases the number of output enable signals, thereby increasing the number of drive components 31 that transmit power supply DC, thereby increasing the current of the power supply DC.

[0088] In one embodiment, the current formed by the DC power transmitted by the n / 2 driving components 31 is the current required by the light-emitting component 80 at room temperature.

[0089] The output circuit 23 is realized by two output modules, so that the circuit is symmetrical and the adjustment accuracy is improved.

[0090] like Figure 3 As shown, the detection circuit 01 includes a sampling circuit 11 and a conversion circuit 12 .

[0091] The sampling circuit 11 is connected to the light emitting component 80 and is used to sample the DC power supply flowing through the light emitting component 80 to output a two-terminal sampling signal.

[0092] The conversion circuit 12 is connected to the sampling circuit 11 and the calibration circuit 02, and is used to convert the double-ended sampling signal into a single-ended detection signal.

[0093] The detection circuit 01 has a simple structure and low cost.

[0094] Figure 4 FIG. 1 shows a partial exemplary circuit structure of a calibration circuit of a photoelectric drive circuit provided by an embodiment of the present invention. Figure 5 FIG. 1 shows a partial exemplary circuit structure of a photoelectric drive circuit provided by an embodiment of the present invention. Figure 6 Another partial exemplary circuit structure of the photoelectric drive circuit provided by the embodiment of the present invention is shown. For the convenience of description, only the part related to the embodiment of the present invention is shown, which is described in detail as follows:

[0095] like Figure 4 As shown, the first judgment signal includes a first positive judgment signal and a first negative judgment signal; the first configuration signal includes a first reset signal and a first set signal; the first output module 231 includes a first D flip-flop U1, a first transmission gate U2 and n / 2 second D flip-flops (DFF1 to DFF(n / 2)).

[0096] The data input terminal D of the first D flip-flop U1 and the positive control terminal of the first transmission gate U2 serve together as the first negative decision signal input terminal of the first output module 231 and are connected to the first comparison circuit 21 to receive the first negative decision signal.

[0097] The negative control terminal of the first transmission gate U2 is commonly used as the first positive decision signal input terminal of the first output module 231, and is connected to the first comparison circuit 21 to receive the first positive decision signal.

[0098] The data output terminal Q of the first D flip-flop U1 is connected to the input terminal of the first transmission gate U2 , and the output terminal of the first transmission gate U2 is connected to the data input terminal D of the first second D flip-flop DFF1 .

[0099] The data input terminal D of the i-th second D flip-flop DFFi and the data output terminal Q of the i+1-th second D flip-flop DFF1 serve together as the i-th enable signal output terminal of the first output module 231, and are connected to the i-th driving component 31 to output the i-th enable signal.

[0100] The data output terminal Q of the n / 2th second D flip-flop DFF(n / 2) serves as the n / 2th enable signal output terminal of the first output module 231 and is connected to the n / 2th driving component 31 to output the n / 2th enable signal.

[0101] The clock terminal of the first D flip-flop U1 and the clock terminals of the n / 2 second D flip-flops (DFF1 to DFF(n / 2)) serve together as the clock signal input terminal of the first output module 231 to receive the clock signal CLK.

[0102] The reset terminals R of the n / 2 second D flip-flops (DFF1 to DFF(n / 2)) are commonly used as the first reset signal input terminal of the first output module 231 to receive the first reset signal R1.

[0103] The set terminals S of the n / 2 second D flip-flops (DFF1 to DFF(n / 2)) serve together as the first set signal input terminal of the first output module 231 to receive the first set signal S1.

[0104] Here, i is a positive integer less than n / 2.

[0105] like Figure 4 As shown, the second judgment signal includes a second positive judgment signal and a second negative judgment signal; the second configuration signal includes a second reset signal and a second set signal; the second output module 232 includes a third D flip-flop U3, a second transmission gate U4 and n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn).

[0106] The data input terminal D of the third D flip-flop U3 and the negative control terminal of the second transmission gate U2 serve together as the second positive decision signal input terminal of the second output module 232, and are connected to the second comparison circuit 22 to receive the second positive decision signal.

[0107] The positive control terminal of the second transmission gate U4 is used as the second negative decision signal input terminal of the second output module 232 and is connected to the second comparison circuit 22 to receive the second negative decision signal.

[0108] The data output terminal Q of the third D flip-flop U3 is connected to the input terminal of the second transmission gate U4, and the output terminal of the second transmission gate U4 is connected to the data input terminal D of the first fourth D flip-flop DFF(n / 2+1).

[0109] The data input terminal D of the jth fourth D flip-flop DFF(n / 2+j) and the data output terminal Q of the i+1th second D flip-flop DFF(n / 2+j+1) jointly serve as the jth enable signal output terminal of the second output module 232, and are connected to the n / 2+jth driving component 31 to output the n / 2+jth enable signal.

[0110] The data output terminal Q of the n / 2 th fourth D flip-flop DFFn serves as the n / 2 th enable signal output terminal of the second output module 232 and is connected to the n th driving component 31 to output the n th enable signal.

[0111] The clock end of the third D flip-flop U3 and the clock ends of n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn) serve together as the clock signal input end of the second output module 232 to receive the clock signal CLK.

[0112] The reset terminals R of the n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn) are commonly used as the second reset signal input terminal of the second output module 232 to receive the second reset signal R2.

[0113] The set terminals S of the n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn) serve together as the second set signal input terminal of the second output module 232 to receive the second set signal S2.

[0114] Here, j is an integer less than n and greater than or equal to n / 2+1.

[0115] like Figure 4 As shown, the first decision signal includes a first positive decision signal and a first negative decision signal; the first comparison circuit 21 includes a first comparator U5 and a first inverter U6;

[0116] The positive input terminal of the first comparator U5 serves as the first reference voltage input terminal of the first comparison circuit 21 to access the first reference voltage VH; the inverting input terminal of the first comparator U5 serves as the detection signal input terminal of the first comparison circuit 21 to be connected to the detection circuit 01 to access the detection signal VRO; the output terminal of the first comparator U5 and the input terminal of the first inverter U6 serve together as the first positive pole decision signal output terminal of the first comparison circuit 21 to be connected to the output circuit 23 to output the first positive pole decision signal; the output terminal of the first inverter U6 serves as the first negative pole decision signal output terminal of the first comparison circuit 21 to be connected to the output circuit 23 to output the first negative pole decision signal.

[0117] like Figure 4 As shown, the second decision signal includes a second positive decision signal and a second negative decision signal; the second comparison circuit 22 includes a second comparator U7 and a second inverter U8.

[0118] The inverting input terminal of the second comparator U7 serves as the second reference voltage input terminal of the second comparison circuit 22 to access the second reference voltage VL; the non-inverting input terminal of the second comparator U7 serves as the detection signal input terminal of the second comparison circuit 22, and is connected to the detection circuit 01 to access the detection signal VRO; the output terminal of the second comparator U7 and the input terminal of the second inverter U8 serve together as the second positive pole decision signal output terminal of the second comparison circuit 22, and are connected to the output circuit 23 to output the second positive pole decision signal; the output terminal of the second inverter U8 serves as the second negative pole decision signal output terminal of the second comparison circuit 22, and is connected to the output circuit 23 to output the second negative pole decision signal.

[0119] like Figure 5 and Figure 6 As shown, the sampling circuit 11 includes a first field effect transistor M1, a second field effect transistor M2 and a first resistor R1;

[0120] The source of the first field effect transistor M1 and the source of the second field effect transistor M2 serve together as the DC power supply input terminal of the sampling circuit 11 to access the DC power supply; the drain of the second field effect transistor M2, the drain of the first field effect transistor M1, the first end of the first resistor R1 and the second end of the first resistor R1 serve together as the sampling signal output terminal of the sampling circuit 11, which is connected to the conversion circuit 12 to output the sampling signal.

[0121] In a specific implementation, the first field effect tube M1 and the second field effect tube M2 are both PMOS tubes, and the width-to-length ratio of the first field effect tube M1 and the width-to-length ratio of the second field effect tube M2 are proportional, and the width-to-length ratio (W / L) of the first field effect tube M1 is K times the width-to-length ratio of the second field effect tube M2. According to the conduction characteristics of the PMOS switch tube, when the second field effect tube M2 is in a closed state, its conduction impedance of the first field effect tube is K times that of M1. The first resistor R1 is a current detection resistor, and the resistance is generally several mΩ. By detecting the voltage across the first resistor R1, a sampling signal of the current (current of the DC power supply) flowing through the light-emitting diode LED when the calibration circuit 02 is working can be accurately obtained.

[0122] It can be understood that the first field effect transistor M1 and the second field effect transistor M2 can be turned on based on the start signal; the gate of the first field effect transistor M1 and the gate of the second field effect transistor M2 are used together as the start signal input terminal of the sampling circuit 11 to access the start signal; or

[0123] The gate of the first field effect transistor M1 and the gate of the second field effect transistor M2 are both connected to the effective level, and the first field effect transistor M1 and the second field effect transistor M2 are both turned on based on the effective level.

[0124] like Figure 5 and Figure 6As shown, the conversion circuit 12 includes an operational amplifier U9, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5.

[0125] The second resistor R2 and the first end and the first end of the third resistor R3 are jointly used as the sampling signal input end of the conversion circuit 12, and are connected to the sampling circuit 11 to access the sampling signal; the inverting input end of the operational amplifier U9 is connected to the second end of the second resistor R2 and the first end of the fourth resistor R4, the non-inverting input end of the operational amplifier U9 is connected to the second end of the third resistor R3 and the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is connected to the power ground; the output end of the operational amplifier U9 and the second end of the fourth resistor R4 are jointly used as the detection signal output end of the conversion circuit 12, and are connected to the calibration circuit 02 to output the detection signal.

[0126] like Figure 5 and Figure 6 As shown, the light emitting assembly 80 includes a light emitting diode LED.

[0127] like Figure 5 As shown, the driving component 31 includes a third field effect transistor M3 and a fourth field effect transistor M4;

[0128] The drain of the fourth field effect transistor M4 serves as the DC power input terminal of the driving component 31, and is connected to the light-emitting component 80 to receive the DC power supply; the source of the fourth field effect transistor M4 is connected to the drain of the third field effect transistor M3, and the source of the third field effect transistor M3 is connected to the power ground; the gate of the fourth field effect transistor M4 serves as the enable signal input terminal of the driving component 31, and is connected to the calibration circuit 02 to receive the enable signal; the gate of the fourth field effect transistor M3 serves as the switch signal input terminal of the driving component 31 to receive the switch signal.

[0129] like Figure 6 As shown, the driving component 31 includes a fourth field effect transistor M4;

[0130] The drain of the fourth field effect transistor M4 serves as the DC power input terminal of the driving component 31, and is connected to the light-emitting component 80 to receive the DC power supply; the source of the fourth field effect transistor M4 is connected to the power ground, and the gate of the fourth field effect transistor M4 serves as the enable signal input terminal of the driving component 31, and is connected to the calibration circuit 02 to receive the enable signal.

[0131] The following is a combination of working principles Figures 4 to 6 As shown for further explanation:

[0132] like Figure 5 and Figure 6As shown, the first field effect transistor M1 and the second field effect transistor M2 can be turned on based on a start signal or an effective level; the first field effect transistor M1, the second field effect transistor M2 and the first resistor R1 sample the power supply DC flowing through the light emitting diode LED to output a double-ended sampling signal; the operational amplifier U9 and its peripheral circuit convert the double-ended detection signal into a single-ended detection signal VRO.

[0133] like Figure 4 As shown, the second comparator U7 outputs a first positive pole decision signal in response to the detection signal being greater than the first preset voltage VH, and the first positive pole decision signal is inverted by the second inverter U8 to obtain a first negative pole decision signal; the first comparator U5 outputs a second positive pole decision signal in response to the detection signal being less than the second preset voltage VL, and the second positive pole decision signal is inverted by the first inverter U6 to obtain a second negative pole decision signal.

[0134] In the initial state, the first configuration signal and the second configuration signal are connected, the first configuration signal includes a low-level first reset signal R1 and a high-level first set signal S1, and n / 2 second D flip-flops (DFF1 to DFF(n / 2)) output n / 2 enable signals according to the first configuration signal; the second configuration signal includes a high-level second reset signal R2 and a low-level second set signal S2, and n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn) stop outputting n / 2 enable signals according to the second configuration signal; thus, the n / 2 fourth field effect transistors M4 are turned on under the control of the n / 2 enable signals, that is, half of the drive components 31 are turned on.

[0135] Then, the input of the first configuration signal and the second configuration signal is stopped.

[0136] If the voltage of the detection signal VRO is greater than the first preset voltage VH, the first comparator U5 outputs the first positive decision signal SH (jumps from a high level to a low level), and the first inverter U6 outputs the first negative decision signal SHN (jumps from a low level to a high level); at this time, the second comparator U7 stops outputting the second positive decision signal SL (maintains a high level), and the second inverter U8 stops outputting the second negative decision signal SLN (maintains a low level); the first negative decision signal SHN passes through the first D flip-flop U1 and the first transmission gate U2 and reaches the input end of the first second D flip-flop DFF1. With the transmission of the clock signal, the n / 2 second D flip-flops (DFF1 to DFF(n / 2)) will gradually jump to a low level (i.e., reduce the number of enable signals), thereby gradually turning off the corresponding fourth field effect transistor M4 in the driving component 31, and reducing the driving current (current of the DC power supply) of the light-emitting diode LED.

[0137] If the voltage of the detection signal VRO is less than the second preset voltage VL, the first comparator U5 stops outputting the first positive pole decision signal SH (SH remains high), and the first inverter U6 stops outputting the first negative pole decision signal SHN (SHN remains low); the second comparator U7 outputs the second positive pole decision signal SL (SL changes from high to low), and the second inverter U8 outputs the second negative pole decision signal SLN (SLN changes from low to high). The second positive pole decision signal SL passes through the third D flip-flop U3 and the second transmission gate U4 and reaches the input end of the first fourth D flip-flop (DFF(n / 2+1)). With the transmission of the clock signal, the output signals (D(n / 2) to D(n)) of the n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn) will gradually jump to a high level, thereby gradually turning on the corresponding fourth field effect transistor M4 in the driving component 31, increasing the driving current (current of the DC power supply) of the light-emitting diode LED.

[0138] Figure 5 The photoelectric drive circuit shown is Figure 6 The difference of the photoelectric drive circuit shown is that the drive component 31 works when a switch signal is input.

[0139] An embodiment of the present invention further provides an electronic device, which includes the above-mentioned photoelectric driving circuit.

[0140] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0141] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A photoelectric drive circuit, characterized in that: connected to the light-emitting component, including a detection circuit, a calibration circuit and a driving circuit; The detection circuit is connected to the light-emitting component and is used to detect the power supply direct current flowing through the light-emitting component to output a detection signal; The calibration circuit is connected to the detection circuit, and is used to output various enable signals based on the detection signal, and in response to the detection signal being greater than a first preset voltage, reduce the number of the output enable signals, and in response to the detection signal being less than a second preset voltage, increase the number of the output enable signals; The driving circuit includes a plurality of driving components connected in parallel; The driving component is connected to the light emitting component and the calibration circuit, and is used to transmit the power supply DC based on the enable signal; Among them, each of the enable signals is connected to each driving component in a one-to-one correspondence.

2. The photoelectric drive circuit according to claim 1, characterized in that: The calibration circuit comprises: A first comparison circuit, connected to the detection circuit, for outputting a first decision signal in response to the detection signal being greater than a first preset voltage; A second comparison circuit, connected to the detection circuit, for outputting a second decision signal in response to the detection signal being less than a second preset voltage; The output circuit, together with the first comparison circuit, the second comparison circuit and the plurality of driving components, is used to output the enable signal, reduce the number of the output enable signals according to the first judgment signal, and increase the number of the output enable signals according to the second judgment signal.

3. The photoelectric drive circuit according to claim 2, characterized in that: The number of the driving components is n, where n is an even number; the output circuit includes: a first output module, connected to the first comparison circuit and n / 2 of the driving components, configured to output n / 2 enable signals according to a first configuration signal, and reduce the number of the output enable signals according to the first decision signal; The second output module is connected to the second comparison circuit and n / 2 of the driving components, and is used to stop the output of the enable signal according to the second configuration signal, and increase the number of the output enable signals according to the second judgment signal.

4. The photoelectric drive circuit according to claim 3, characterized in that: The first decision signal includes a first positive decision signal and a first negative decision signal; the first configuration signal includes a first reset signal and a first set signal; The first output module includes a first D flip-flop, a first transmission gate and n / 2 second D flip-flops; The data input terminal of the first D flip-flop and the positive control terminal of the first transmission gate are used together as the first negative pole decision signal input terminal of the first output module, and are connected to the first comparison circuit to receive the first negative pole decision signal; The negative control terminal of the first transmission gate is used as the first positive decision signal input terminal of the first output module, and is connected to the first comparison circuit to receive the first positive decision signal; The data output terminal of the first D flip-flop is connected to the input terminal of the first transmission gate, and the output terminal of the first transmission gate is connected to the data input terminal of the first second D flip-flop; The data input terminal of the i-th second D flip-flop and the data output terminal of the (i+1)-th second D flip-flop serve together as the i-th enable signal output terminal of the first output module, and are connected to the i-th driving component to output the i-th enable signal; The data output terminal of the n / 2th second D flip-flop is used as the n / 2th enable signal output terminal of the first output module, and is connected to the n / 2th driving component to output the n / 2th enable signal; The clock end of the first D flip-flop and the clock ends of n / 2 of the second D flip-flops are used together as a clock signal input end of the first output module to receive a clock signal; The reset terminals of n / 2 of the second D flip-flops (DFF1 to DFF(n / 2)) are used together as the first reset signal input terminal of the first output module to receive the first reset signal; The set terminals of n / 2 of the second D flip-flops are used together as the first set signal input terminal of the first output module to receive the first set signal; Here, i is a positive integer less than n / 2.

5. The photoelectric drive circuit according to claim 4, characterized in that: The second decision signal includes a second positive decision signal and a second negative decision signal; the second configuration signal includes a second reset signal and a second set signal; The second output module includes a third D flip-flop, a second transmission gate and n / 2 fourth D flip-flops; The data input terminal of the third D flip-flop and the negative control terminal of the second transmission gate are used together as the second positive pole decision signal input terminal of the second output module, and are connected to the second comparison circuit to receive the second positive pole decision signal; The positive control terminal of the second transmission gate is used as the second negative pole decision signal input terminal of the second output module, and is connected to the second comparison circuit to receive the second negative pole decision signal; The data output terminal of the third D flip-flop is connected to the input terminal of the second transmission gate, and the output terminal of the second transmission gate is connected to the data input terminal of the first fourth D flip-flop; The data input terminal of the jth fourth D flip-flop and the data output terminal of the i+1th second D flip-flop serve together as the jth enable signal output terminal of the second output module, and are connected to the n / 2+jth driving component to output the n / 2+jth enable signal; The data output terminal of the n / 2th fourth D flip-flop is used as the n / 2th enable signal output terminal of the second output module, and is connected to the nth driving component to output the nth enable signal; The clock end of the third D flip-flop and the clock ends of the n / 2 fourth D flip-flops are used together as the clock signal input end of the second output module to receive the clock signal; The reset terminals of the n / 2 fourth D flip-flops are used together as the second reset signal input terminal of the second output module to receive the second reset signal; The set terminals of the n / 2 fourth D flip-flops are used together as the second set signal input terminal of the second output module to receive the second set signal; Here, j is an integer less than n and greater than or equal to n / 2+1.

6. The photoelectric drive circuit according to claim 2, characterized in that: The first decision signal includes a first positive decision signal and a first negative decision signal; The first comparison circuit includes a first comparator and a first inverter; The non-inverting input terminal of the first comparator serves as the first reference voltage input terminal of the first comparison circuit to access the first reference voltage; The inverting input terminal of the first comparator is used as a detection signal input terminal of the first comparison circuit and is connected to the detection circuit to receive the detection signal; The output end of the first comparator and the input end of the first inverter are used together as the first positive pole decision signal output end of the first comparison circuit, and are connected to the output circuit to output the first positive pole decision signal; The output end of the first inverter serves as the first negative pole decision signal output end of the first comparison circuit and is connected to the output circuit to output the first negative pole decision signal.

7. The photoelectric drive circuit according to claim 2, characterized in that: The second decision signal includes a second positive decision signal and a second negative decision signal; The second comparison circuit includes a second comparator and a second inverter; The inverting input terminal of the second comparator serves as the second reference voltage input terminal of the second comparison circuit to access the second reference voltage; The non-inverting input terminal of the second comparator is used as the detection signal input terminal of the second comparison circuit and is connected to the detection circuit to receive the detection signal; The output terminal of the second comparator and the input terminal of the second inverter are used together as the second positive pole decision signal output terminal of the second comparison circuit, and are connected to the output circuit to output the second positive pole decision signal; The output end of the second inverter serves as the second negative pole decision signal output end of the second comparison circuit and is connected to the output circuit to output the second negative pole decision signal.

8. The photoelectric drive circuit according to claims 1 to 7, characterized in that: The detection circuit comprises: A sampling circuit, connected to the light-emitting component, for sampling the DC power supply flowing through the light-emitting component to output a two-terminal sampling signal; The conversion circuit is connected to the sampling circuit and the calibration circuit, and is used for converting the double-ended sampling signal into a single-ended detection signal.

9. The photoelectric drive circuit according to claim 8, characterized in that: The sampling circuit includes a first field effect transistor, a second field effect transistor and a first resistor; The source of the first field effect transistor and the source of the second field effect transistor are used together as a power supply DC input terminal of the sampling circuit to access the power supply DC; The drain of the second field effect transistor, the drain of the first field effect transistor, the first end of the first resistor and the second end of the first resistor together serve as a sampling signal output end of the sampling circuit and are connected to the conversion circuit to output the sampling signal.

10. An electronic device, characterized in that: The electronic device comprises the optoelectronic driving circuit as claimed in any one of claims 1 to 9.

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