Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device. The semiconductor device includes: a semiconductor substrate; a channel layer provided on the semiconductor substrate and comprising a first nitride semiconductor; a barrier layer provided on the channel layer and comprising a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; a metal film selectively formed over the barrier layer; a composite layer provided so as to be in contact with the metal film, the composite layer having at least a conductive material and an insulating material; and an insulating film formed on the barrier layer in a region where the metal film and the composite layer are not formed.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and in particular to a heterojunction field effect type semiconductor device composed of a semiconductor including a nitride. Background Art

[0002] As an example of a conventional heterojunction field effect semiconductor device composed of a semiconductor containing nitride (nitride semiconductor), there can be cited, for example, a heterojunction field effect transistor disclosed in Patent Document 1. The heterojunction field effect transistor has an AlGaN / GaN heterojunction having a channel layer of GaN (gallium nitride) and a barrier layer of AlGaN (aluminum gallium nitride).

[0003] An ohmic electrode composed of a metal film such as Ti (titanium), Al (aluminum), Mo (molybdenum), or a metal multilayer film or alloy film containing these is provided on the barrier layer to constitute the drain electrode and source electrode of the transistor.

[0004] The following structure is adopted: these ohmic electrodes are covered with an insulating film composed of SiN (silicon nitride) or SiO2 (silicon oxide), the insulating film is opened to form a contact hole so that a part of the upper surface is exposed, and connected to the wiring for connecting to the outside.

[0005] Generally, an ohmic electrode is formed by depositing a metal film (including a metal multilayer film or an alloy film) on a semiconductor layer, performing heat treatment, and then depositing a SiN film so as to cover the heat-treated metal film.

[0006] Prior art literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2014-179389 Summary of the invention

[0008] In ohmic electrodes such as source electrodes, drain electrodes, and cathode electrodes used in semiconductor devices such as transistors and diodes formed on a semiconductor layer including an AlGaN / GaN heterojunction, it is preferred that the resistance be as low as possible in order to improve the performance of the semiconductor device.

[0009] In order to reduce the resistance of the ohmic electrode, after depositing a metal film on the semiconductor layer, it is generally heat treated at a high temperature of more than 600°C to alloy with the semiconductor layer. After that, a surface protection film such as SiN is formed to protect the surface of the semiconductor layer, and the metal film is also covered. However, when the heat treatment is performed at a high temperature in the state where the metal film is exposed, sometimes part of the metal film evaporates and re-attaches to the area other than the area where the electrode is formed, and becomes a state of remaining between the semiconductor layer and the protection film, which has a negative impact on many characteristics of the semiconductor device.

[0010] On the other hand, in order to prevent the evaporation and re-adhesion of the metal, there is also a method of depositing a cap film (cap film) such as SiN that has low reactivity with the metal film in order to cover the metal film, performing high-temperature heat treatment, and then removing the cap film. However, since the cap film is deposited and a step for removing it is added afterwards, the manufacturing process sometimes becomes complicated and the manufacturing cost increases.

[0011] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device that does not deteriorate the characteristics of the semiconductor device and suppresses complication of the manufacturing process.

[0012] The semiconductor device involved in the present disclosure comprises: a semiconductor substrate; a channel layer, which is arranged on the semiconductor substrate and is composed of a first nitride semiconductor; a barrier layer, which is arranged on the channel layer and is composed of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; a metal film, which is selectively formed above the barrier layer; a composite layer, which is arranged in contact with the metal film and has at least a conductive material and an insulating material; and an insulating film, which is formed on the barrier layer in an area where the metal film and the composite layer are not formed.

[0013] According to the semiconductor device according to the present disclosure, it is possible to obtain a semiconductor device without reducing the characteristics of the semiconductor device and suppressing complication of the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present disclosure.

[0015] Figure 2 This is a diagram schematically showing the flow of current in the semiconductor device according to the first embodiment of the present disclosure.

[0016] Figure 3 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1 of the present disclosure.

[0017] Figure 4 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1 of the present disclosure.

[0018] Figure 5 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1 of the present disclosure.

[0019] Figure 6 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1 of the present disclosure.

[0020] Figure 7It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1 of the present disclosure.

[0021] Figure 8 It is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 2 of the present disclosure.

[0022] Fig. 9 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 2 of the present disclosure.

[0023] Fig.10 This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 3 of the present disclosure.

[0024] Fig.11 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 3 of the present disclosure.

[0025] Fig.12 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 3 of the present disclosure.

[0026] Fig.13 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 3 of the present disclosure.

[0027] Fig.14 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 3 of the present disclosure.

[0028] Fig.15 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 3 of the present disclosure.

[0029] Fig.16 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 3 of the present disclosure.

[0030] Fig.17 This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 4 of the present disclosure.

[0031] Fig.18 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 4 of the present disclosure.

[0032] Fig.19 This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 5 of the present disclosure.

[0033] Fig. 20 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 5 of the present disclosure.

[0034] Fig.21It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 5 of the present disclosure.

[0035] Fig. 22 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 5 of the present disclosure.

[0036] Fig.23 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 5 of the present disclosure.

[0037] Fig.24 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 5 of the present disclosure.

[0038] Fig.25 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 5 of the present disclosure.

[0039] Fig.26 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 5 of the present disclosure.

[0040] Fig. 27 This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 6 of the present disclosure.

[0041] Fig.28 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 6 of the present disclosure.

[0042] Fig.29 This is a cross-sectional view showing a semiconductor device according to Embodiment 7 of the present disclosure in a state where a metal film and an insulating film are not formed.

[0043] Fig.30 This is a cross-sectional view schematically showing 2DEG induced at the AlGaN / GaN interface of the semiconductor device according to the seventh embodiment of the present disclosure.

[0044] Fig.31 This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 9 of the present disclosure.

[0045] Fig.32 This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 10 of the present disclosure.

[0046] Fig.33 This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 11 of the present disclosure.

[0047] Fig.34 This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 12 of the present disclosure. DETAILED DESCRIPTION

[0048] <Implementation Method 1>

[0049] <Device Structure>

[0050] Figure 1 is a cross-sectional view showing the structure of a semiconductor device 100 according to Embodiment 1 of the present disclosure. Figure 1 In the figure, for convenience of explanation, for example, only the main electrode portion which is a part of the heterojunction field effect transistor is shown.

[0051] like Figure 1 As shown, in the semiconductor device 100, for example, a channel layer 3 composed of GaN (first nitride semiconductor) is stacked on a semiconductor substrate 1 composed of silicon carbide (SiC) via a buffer layer 2 composed of AlN (aluminum nitride), and a barrier layer 4 composed of AlGaN (second nitride semiconductor) forming a heterojunction with the channel layer 3 is formed on the channel layer 3. By using such a nitride semiconductor, a practical heterojunction field effect transistor can be obtained. In addition, the AlGaN constituting the barrier layer 4 is set to have a larger band gap than the GaN constituting the channel layer 3.

[0052] A metal film 5 constituting a drain electrode and a source electrode is selectively provided on the barrier layer 4, and a part of the side and upper surface of the metal film 5 is covered by a composite layer 8 of metal and an insulating material. An insulating film 6 of SiO2 or SiN is provided in a region on the barrier layer 4 other than the region where the composite layer 8 and the metal film 5 are formed.

[0053] In composite layer 8 on the upper surface of metal film 5 , contact hole CH is provided to expose a part of the upper surface of metal film 5 , and wiring layer 7 is provided to be in contact with metal film 5 through contact hole CH.

[0054] The composite layer 8 is, for example, a silicide layer formed by the reaction of the metal film 5 and SiO2, or a silicide layer formed by the reaction of the metal film 5 and SiN, and has a conductive portion with a lower resistance than the metal film 5. The composite layer 8 is not limited to a silicide layer, and any layer having conductivity can be used as long as it is a composite of a conductive material and an insulating material by heat treatment at 600°C or above.

[0055] Figure 2 Schematically shows the current flowing into the channel layer 3 via the wiring layer 7. Figure 2 As shown, the current flowing into the channel layer 3 via the wiring layer 7 passes through two paths: a current path C1 flowing from the wiring layer 7 via the metal film 5 into the channel layer 3 and a current path C2 flowing from the wiring layer 7 via the composite layer 8 into the channel layer 3, thereby achieving the effect of reducing the contact resistance.

[0056] Here, as an example of contact resistance, when the insulating film 6 is composed of SiO2 and the Al composition and thickness of the barrier layer 4 of AlGaN are set to 26% and 15nm, respectively, the contact resistance becomes 0.6Ωmm to 0.7Ωmm. In addition, when the Al composition of the barrier layer 4 is reduced from the above values ​​and the thickness is thinned, it is predicted that the contact resistance will become higher.

[0057] Such a structure in which the metal film 5 is covered by the composite layer 8 can be obtained by forming the metal film 5 on the barrier layer 4, depositing the insulating film 6 so as to cover the barrier layer 4 and the metal film 5, and then performing a heat treatment at a high temperature of, for example, 600° C. or higher, so that the metal film 5 and the barrier layer 4 are alloyed to form an ohmic electrode, and the metal film 5 and the insulating film 6 react to form a silicide layer. In this case, the insulating film 6 on the barrier layer 4 functions as a protective film for protecting the semiconductor layer below the barrier layer 4, and the evaporation of the metal during the high-temperature heat treatment and the re-adhesion to the barrier layer 4 can be prevented without adding a new process.

[0058] <Manufacturing method>

[0059] Next, the manufacturing process is shown in sequence. Figure 3 to Figure 7 , a method for manufacturing the semiconductor device 100 is described. Figure 3 to Figure 7 In Figure 1 The same components of the semiconductor device 100 are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0060] First, in Figure 3 In the process shown, a buffer layer 2 composed of AlN, a channel layer 3 composed of GaN, and a barrier layer 4 composed of AlGaN are sequentially grown on a SiC semiconductor substrate 1 using an epitaxial growth method such as MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy). Next, a metal film 5 is formed in a desired region using evaporation and lift-off methods. In addition, the metal film 5 may be a single layer film of Ti, Al, Ni (nickel), Au (gold), Mo, etc., or a multilayer film thereof.

[0061] Next, in Figure 4 In the process shown, the insulating film 6 is deposited on the barrier layer 4 by, for example, a plasma CVD method so as to cover the metal film 5. As the insulating film 6, for example, SiO2 or SiN can be formed. In addition, the method for forming the insulating film 6 is not limited to the plasma CVD method, and a thermal CVD method or a sputtering method can be used.

[0062] Next, in Figure 5 In the process shown, heat treatment is performed at a temperature of 500°C to 900°C, more preferably 800°C to 850°C, using the RTA (Rapid Thermal Annealing) method, etc., so that the portion where the metal film 5 and the insulating film 6 are in contact reacts to form a silicide layer as a composite layer 8, the metal film 5 is covered with the composite layer 8, and the metal film 5 is alloyed with the barrier layer 4 to form an ohmic electrode.

[0063] Next, in Figure 6 In the process shown, for example, a resist material is used as a mask and dry etching is used to remove the composite layer 8 in the region where the wiring layer 7 is to be formed, thereby forming a contact hole CH that exposes the upper surface of the metal film 5 at the bottom surface.

[0064] Next, in Figure 7 In the process shown in FIG. 1 , a resist mask RM is formed on the composite layer 8 and the insulating film 6 so that the portion where the wiring layer 7 is to be formed becomes an opening OP. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof is formed on the resist mask RM and in the opening OP by vapor deposition, and the resist mask RM is removed by a lift-off method, thereby forming the wiring layer 7 and obtaining Figure 1 A semiconductor device 100 is shown.

[0065] <Implementation Method 2>

[0066] <Device Structure>

[0067] Figure 8 2 is a cross-sectional view showing the structure of a semiconductor device 200 according to Embodiment 2 of the present disclosure. Figure 8 For use with Figure 1 The same reference numerals are used to denote the same structures as those of the semiconductor device 100 described above, and redundant description will be omitted.

[0068] like Figure 8 As shown, in the semiconductor device 200 , the metal film 5 is covered with the composite layer 8 , and an insulating film 6 such as SiO 2 or SiN is provided in a region on the barrier layer 4 other than the region where the composite layer 8 and the metal film 5 are formed.

[0069] A wiring layer 7 is selectively provided on the upper surface of the composite layer 8. The composite layer 8 is, for example, a silicide layer formed by the reaction of the metal film 5 and SiO2, or a silicide layer formed by the reaction of the metal film 5 and SiN, and has a conductive portion with a lower resistance than the metal film 5. Therefore, the current flowing into the channel layer 3 via the wiring layer 7 will pass through two paths, namely, a current path flowing from the wiring layer 7 via the composite layer 8 and the metal film 5 into the channel layer 3 and a current path flowing from the wiring layer 7 via the composite layer 8 into the channel layer 3, thereby achieving the effect of reducing the contact resistance.

[0070] The insulating film 6 on the barrier layer 4 provided to obtain a structure in which the metal film 5 is covered by the composite layer 8 functions as a protective film for protecting the semiconductor layer below the barrier layer 4 during heat treatment, thereby preventing the evaporation of the metal during high-temperature heat treatment and its re-adhesion to the barrier layer 4 without adding a new process.

[0071] Furthermore, since the wiring layer 7 is provided in contact with the upper surface of the composite layer 8, it is not necessary to provide a contact hole in the composite layer 8, so that the manufacturing process can be simplified.

[0072] <Manufacturing method>

[0073] Next, using the manufacturing process Fig. 9 , a method for manufacturing the semiconductor device 200 is described. Fig. 9 The steps shown in the figure are the same as those used in the description of the method for manufacturing the semiconductor device 100 in the first embodiment. Figure 3 to Figure 5 The same process is used, using RTA method or the like to react the contacting portion of the metal film 5 and the insulating film 6 to form a silicide layer as a composite layer 8, covering the metal film 5 with the composite layer 8, and alloying the metal film 5 with the barrier layer 4 to form an ohmic electrode.

[0074] Afterwards, in Fig. 9 In the process shown in FIG. 1 , a resist mask RM is formed on the composite layer 8 and the insulating film 6 so that the portion where the wiring layer 7 is to be formed becomes an opening OP. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof is formed on the resist mask RM and in the opening OP by vapor deposition, and the resist mask RM is removed by a lift-off method, thereby forming the wiring layer 7 and obtaining Figure 8 A semiconductor device 200 is shown.

[0075] <Implementation Method 3>

[0076] <Device Structure>

[0077] Fig.10 is a cross-sectional view showing the structure of a semiconductor device 300 according to Embodiment 3 of the present disclosure. Fig.10 For use with Figure 1 The same reference numerals are used to denote the same structures as those of the semiconductor device 100 described above, and redundant description will be omitted.

[0078] like Fig.10 As shown, in the semiconductor device 300, the upper surface and side surfaces of the metal film 5 are covered by a composite layer 8, and a composite layer 8 is also provided between the lower surface of the metal film 5 and the barrier layer 4, and an insulating film 6 such as SiO2 or SiN is provided in an area on the barrier layer 4 outside the area where the composite layer 8 and the metal film 5 are formed.

[0079] In composite layer 8 on the upper surface of metal film 5 , contact hole CH is provided to expose a part of the upper surface of metal film 5 , and wiring layer 7 is provided to be in contact with metal film 5 through contact hole CH.

[0080] The composite layer 8 is, for example, a silicide layer formed by the reaction of the metal film 5 and SiO2, or a silicide layer formed by the reaction of the metal film 5 and SiN, and has a conductive portion with a lower resistance than the metal film 5. Therefore, the current flowing into the channel layer 3 via the wiring layer 7 will flow through two paths, namely, a current path flowing from the wiring layer 7 via the metal film 5 and the composite layer 8 on the lower side into the channel layer 3 and a current path flowing from the wiring layer 7 via the composite layer 8 into the channel layer 3, thereby achieving the effect of reducing the contact resistance. In addition, the structure in which the composite layer 8 on the lower side is in contact with the barrier layer 4 can further reduce the contact resistance compared with the semiconductor device 100 of the first embodiment.

[0081] In addition, the insulating film 6 on the barrier layer 4 provided to obtain a structure in which the metal film 5 is covered by the composite layer 8 functions as a protective film for protecting the semiconductor layer below the barrier layer 4 during heat treatment, thereby preventing the evaporation of the metal during high-temperature heat treatment and its re-adhesion to the barrier layer 4 without adding a new process.

[0082] <Manufacturing method>

[0083] Next, the manufacturing process is shown in sequence. Figures 11 to 16 , a method for manufacturing the semiconductor device 300 is described.

[0084] First, in Fig.11 In the process shown, a buffer layer 2 composed of AlN, a channel layer 3 composed of GaN, and a barrier layer 4 composed of AlGaN are sequentially grown on a SiC semiconductor substrate 1 using an epitaxial growth method such as MOCVD or MBE. Next, an insulating film 61 (first insulating film) is deposited on the barrier layer 4, for example, by a plasma CVD method. As the insulating film 61, for example, SiO2 or SiN can be formed.

[0085] Next, in Fig.12 In the process shown, the metal film 5 is formed in a desired region on the insulating film 61 by using vapor deposition and lift-off methods. The metal film 5 may be a single layer film of Ti, Al, Ni, Au, Mo, or the like, or a multilayer film thereof.

[0086] Next, in Fig.13In the process shown, the insulating film 62 (second insulating film) is deposited by, for example, plasma CVD method so as to cover the metal film 5 and the insulating film 61. As the insulating film 62, SiO2 or SiN similar to the insulating film 61 can be formed. In addition, the method for forming the insulating films 61 and 62 is not limited to the plasma CVD method, and the thermal CVD method or the sputtering method can be used.

[0087] Next, in Fig.14 In the process shown, heat treatment is performed at a temperature of 500°C to 900°C using the RTA method or the like, so that the portion where the metal film 5 and the insulating film 6 are in contact reacts to form a silicide layer as a composite layer 8, the entire metal film 5 is covered with the composite layer 8, and the metal film 5, the composite layer 8, and the barrier layer 4 are alloyed with each other to form an ohmic electrode. Fig.14 In FIG. 6 , the insulating films 61 and 62 are integrated and represented as the insulating film 6 .

[0088] Next, in Fig.15 In the process shown, for example, a resist material is used as a mask and dry etching is used to remove the composite layer 8 in the region where the wiring layer 7 is to be formed, thereby forming a contact hole CH that exposes the upper surface of the metal film 5 at the bottom surface.

[0089] Next, in Fig.16 In the process shown in FIG. 1 , a resist mask RM is formed on the composite layer 8 and the insulating film 6 so that the portion where the wiring layer 7 is to be formed becomes an opening OP. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof is formed by vapor deposition on the resist mask RM and in the opening OP, and the resist mask RM is removed by a lift-off method to form the wiring layer 7, thereby obtaining Fig.10 A semiconductor device 300 is shown.

[0090] <Implementation Method 4>

[0091] <Device Structure>

[0092] Fig.17 is a cross-sectional view showing the structure of a semiconductor device 400 according to Embodiment 4 of the present disclosure. Fig.17 For use with Figure 1 The same reference numerals are used to denote the same structures as those of the semiconductor device 100 described above, and redundant description will be omitted.

[0093] like Fig.17 As shown, in the semiconductor device 400, the upper surface and side surfaces of the metal film 5 are covered by a composite layer 8, and a composite layer 8 is also provided between the lower surface of the metal film 5 and the barrier layer 4, and an insulating film 6 such as SiO2 or SiN is provided in an area on the barrier layer 4 outside the area where the composite layer 8 and the metal film 5 are formed.

[0094] A wiring layer 7 is selectively provided on the upper surface of the composite layer 8. The composite layer 8 is, for example, a silicide layer formed by the reaction of the metal film 5 and SiO2, or a silicide layer formed by the reaction of the metal film 5 and SiN, and has a conductive portion with a lower resistance than the metal film 5. Therefore, the current flowing into the channel layer 3 via the wiring layer 7 will flow through two paths, namely, a current path flowing from the wiring layer 7 through the composite layer 8 on the upper side, the metal film 5, and the composite layer 8 on the lower side into the channel layer 3, and a current path flowing from the wiring layer 7 through the composite layer 8 into the channel layer 3, thereby achieving the effect of reducing the contact resistance.

[0095] In addition, the insulating film 6 on the barrier layer 4 provided to obtain a structure in which the metal film 5 is covered by the composite layer 8 functions as a protective film for protecting the semiconductor layer below the barrier layer 4 during heat treatment, thereby preventing the evaporation of the metal during high-temperature heat treatment and its re-adhesion to the barrier layer 4 without adding a new process.

[0096] Furthermore, since the wiring layer 7 is provided in contact with the upper surface of the composite layer 8, it is not necessary to provide a contact hole in the composite layer 8, so that the manufacturing process can be simplified.

[0097] <Manufacturing method>

[0098] Next, using the manufacturing process Fig.18 , a method for manufacturing the semiconductor device 400 is described. Fig.18 The steps shown in the figure are similar to those used in the description of the method for manufacturing the semiconductor device 300 in the third embodiment. Figure 11 to Figure 14 The process is the same as that of the conventional method, using RTA method or the like to react the contacting parts of the metal film 5 and the insulating film 6 to form a silicide layer as a composite layer 8, covering the entire metal film 5 with the composite layer 8, and alloying the metal film 5, the composite layer 8 and the barrier layer 4 with each other to form an ohmic electrode.

[0099] Afterwards, in Fig.18 In the process shown in FIG. 1 , a resist mask RM is formed on the composite layer 8 and the insulating film 6 so that the portion where the wiring layer 7 is to be formed becomes an opening OP. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof is formed by vapor deposition on the resist mask RM and in the opening OP, and the resist mask RM is removed by a lift-off method to form the wiring layer 7, thereby obtaining Fig.17 A semiconductor device 400 is shown.

[0100] <Implementation method 5>

[0101] <Device Structure>

[0102] Fig.19is a cross-sectional view showing the structure of a semiconductor device 500 according to Embodiment 5 of the present disclosure. Fig.19 For use with Figure 1 The same reference numerals are used to denote the same structures as those of the semiconductor device 100 described above, and redundant description will be omitted.

[0103] like Fig.19 As shown, in the semiconductor device 500, the upper surface and side surfaces of the metal film 5 are covered by a composite layer 8, and a composite layer 8 is also provided between a portion of the lower surface of the metal film 5 and the barrier layer 4, and an insulating film 6 such as SiO2 or SiN is provided in an area on the barrier layer 4 outside the area where the composite layer 8 and the metal film 5 are formed.

[0104] In composite layer 8 on the upper surface of metal film 5 , contact hole CH is provided to expose a part of the upper surface of metal film 5 , and wiring layer 7 is provided to be in contact with metal film 5 through contact hole CH.

[0105] The composite layer 8 is, for example, a silicide layer formed by the reaction of the metal film 5 and SiO2, or a silicide layer formed by the reaction of the metal film 5 and SiN, and has a conductive portion with a lower resistance than the metal film 5. Therefore, the current flowing into the channel layer 3 via the wiring layer 7 will flow through two paths, namely, a current path flowing from the wiring layer 7 via the metal film 5 into the channel layer 3 and a current path flowing from the wiring layer 7 via the composite layer 8 into the channel layer 3, thereby achieving the effect of reducing the contact resistance. In addition, in order to form the composite layer 8, the metal film 5 and the barrier layer 4 are connected to each other, and heat treatment is performed at a high temperature of, for example, 600°C or more, so that the metal film 5 and the barrier layer 4 are alloyed to form an ohmic electrode, so that the contact resistance can be further reduced.

[0106] In this case, the insulating film 6 on the barrier layer 4 functions as a protective film for protecting the semiconductor layer below the barrier layer 4, and can prevent evaporation of the metal during high-temperature heat treatment and re-adhesion to the barrier layer 4 without adding a new process.

[0107] <Manufacturing method>

[0108] Next, the manufacturing process is shown in sequence. Figure 20 to Figure 26 , a method for manufacturing the semiconductor device 500 is described.

[0109] First, in Fig. 20In the process shown, a buffer layer 2 composed of AlN, a channel layer 3 composed of GaN, and a barrier layer 4 composed of AlGaN are sequentially grown on a SiC semiconductor substrate 1 using an epitaxial growth method such as MOCVD or MBE. Next, an insulating film 61 is deposited on the barrier layer 4, for example, by a plasma CVD method. As the insulating film 61, for example, SiO2 or SiN can be formed.

[0110] Next, in Fig.21 In the illustrated process, for example, a resist material is used as a mask and dry etching is used to remove the insulating film 61 in the region where the metal film 5 is to be formed, thereby forming a contact hole CH1 whose bottom surface exposes the upper surface of the barrier layer 4 .

[0111] Next, in Fig. 22 In the process shown, the metal film 5 is formed in a desired region on the insulating film 61 including on the contact hole CH1 by evaporation and lift-off. The metal film 5 may be a single layer film of Ti, Al, Ni, Au, Mo, etc., or a multilayer film thereof.

[0112] Next, in Fig.23 In the process shown, the insulating film 62 is deposited by, for example, a plasma CVD method so as to cover the metal film 5 and the insulating film 61. As the insulating film 62, SiO2 or SiN similar to the insulating film 61 can be formed. In addition, the method for forming the insulating films 61 and 62 is not limited to the plasma CVD method, and a thermal CVD method or a sputtering method can be used.

[0113] Next, in Fig.24 In the process shown, heat treatment is performed at a temperature of 500°C to 900°C using the RTA method or the like, so that the portion where the metal film 5 and the insulating film 6 are in contact reacts to form a silicide layer as a composite layer 8, the metal film 5 is covered with the composite layer 8, and the metal film 5, the composite layer 8 and the barrier layer 4 are alloyed with each other to form an ohmic electrode. At this time, the composite layer 8 is also formed between a portion of the lower surface of the metal film 5 and the barrier layer 4. In addition, Fig.24 In FIG. 5 , the insulating films 61 and 62 are integrated and represented as the insulating film 6 .

[0114] Next, in Fig.25 In the process shown, for example, a resist material is used as a mask and dry etching is used to remove the composite layer 8 in the region where the wiring layer 7 is to be formed, thereby forming a contact hole CH that exposes the upper surface of the metal film 5 at the bottom surface.

[0115] Next, in Fig.26In the process shown in FIG. 1 , a resist mask RM is formed on the composite layer 8 and the insulating film 6 so that the portion where the wiring layer 7 is to be formed becomes an opening OP. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof is formed by vapor deposition on the resist mask RM and in the opening OP, and the resist mask RM is removed by a lift-off method to form the wiring layer 7, thereby obtaining Fig.19 A semiconductor device 500 is shown.

[0116] <Implementation Method 6>

[0117] <Device Structure>

[0118] Fig. 27 is a cross-sectional view showing the structure of a semiconductor device 600 according to Embodiment 6 of the present disclosure. Fig. 27 For use with Figure 1 The same reference numerals are used to denote the same structures as those of the semiconductor device 100 described above, and redundant description will be omitted.

[0119] like Fig. 27 As shown, in the semiconductor device 600, the upper surface and side surfaces of the metal film 5 are covered by a composite layer 8, and a composite layer 8 is also provided between a portion of the lower surface of the metal film 5 and the barrier layer 4, and an insulating film 6 such as SiO2 or SiN is provided in an area on the barrier layer 4 outside the area where the composite layer 8 and the metal film 5 are formed.

[0120] A wiring layer 7 is selectively provided on the upper surface of the composite layer 8. The composite layer 8 is, for example, a silicide layer formed by the reaction of the metal film 5 and SiO2, or a silicide layer formed by the reaction of the metal film 5 and SiN, and has a conductive portion with a lower resistance than the metal film 5. Therefore, the current flowing into the channel layer 3 via the wiring layer 7 will pass through two paths, namely, a current path flowing from the wiring layer 7 through the composite layer 8 on the upper side and the metal film 5 into the channel layer 3 and a current path flowing from the wiring layer 7 through the composite layer 8 into the channel layer 3, thereby achieving the effect of reducing the contact resistance.

[0121] Furthermore, since the wiring layer 7 is provided in contact with the upper surface of the composite layer 8, it is not necessary to provide a contact hole in the composite layer 8, so that the manufacturing process can be simplified.

[0122] <Manufacturing method>

[0123] Next, using the manufacturing process Fig.28 , a method for manufacturing the semiconductor device 600 is described. Fig.28 The steps shown in the figure are the same as those used in the description of the method for manufacturing the semiconductor device 500 of the fifth embodiment. Figure 20 to Figure 24The same process as in the above is used, using the RTA method or the like to react the portion where the metal film 5 and the insulating film 6 are in contact to form a silicide layer as a composite layer 8, the metal film 5 is covered with the composite layer 8, and the metal film 5, the composite layer 8 and the barrier layer 4 are alloyed with each other to form an ohmic electrode. At this time, the composite layer 8 is also formed between a portion of the lower surface of the metal film 5 and the barrier layer 4.

[0124] Afterwards, in Fig.28 In the process shown in FIG. 1 , a resist mask RM is formed on the composite layer 8 and the insulating film 6 so that the portion where the wiring layer 7 is to be formed becomes an opening OP. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof is formed by vapor deposition on the resist mask RM and in the opening OP, and the resist mask RM is removed by a lift-off method to form the wiring layer 7, thereby obtaining Fig. 27 A semiconductor device 600 is shown.

[0125] <Implementation Method 7>

[0126] <Device Structure>

[0127] In the structure of the semiconductor device 700 according to the seventh embodiment of the present disclosure, in addition to controlling the sheet resistance caused by the two-dimensional electron gas generated at the interface between the barrier layer 4 and the channel layer 3, Figure 1 The structure of the semiconductor device 100 of the first embodiment shown in FIG. Figure 1 At the same time, use Fig.29 as well as Fig.30 The semiconductor device 700 will be described.

[0128] like Figure 1 As shown, the semiconductor device 700 has a structure in which a barrier layer 4 made of AlGaN is formed on a channel layer 3 made of GaN to form a heterojunction with the channel layer 3 , thereby having an AlGaN / GaN heterojunction.

[0129] In the ohmic electrode formed on the semiconductor layer having the AlGaN / GaN heterojunction, the Al composition and thickness of the AlGaN layer are designed as follows: in a state where the metal film 5 and the insulating film 6 are not formed, that is, Fig.29 In the state shown, the sheet resistance due to the two-dimensional electron gas (2DEG) generated at the interface (AlGaN / GaN interface) between the barrier layer 4 and the channel layer 3 is set to a sufficiently high value, that is, at least 10 kΩ / sq or more.

[0130] For example, when the Al composition and thickness of the AlGaN barrier layer 4 are set to 15% and 7 nm, 20% and 5 nm, or 100% and 1 nm, the sheet resistance is 10 kΩ / sq or more.

[0131] In addition, the sheet resistance in a state where the barrier layer 4 is formed only on the channel layer 3 is defined as the sheet resistance specific to the barrier layer 4 .

[0132] By depositing an insulating film 6 of SiO2 on the barrier layer 4 composed of the AlGaN layer designed in this way and performing a heat treatment at a temperature of 500°C to 900°C, a 1×10 12 cm -2 The above concentrations of 2DEG. Fig.30 This state is shown schematically.

[0133] exist Fig.30 , a case where 2DEG 9 is induced at the interface between the channel layer 3 and the barrier layer 4 is shown. Due to 2DEG, the sheet resistance is reduced to, for example, 1 kΩ / sq or less.

[0134] In semiconductor devices such as transistors and diodes composed of nitride semiconductors that use the 2DEG induced in this way as carriers, high-temperature heat treatment is required to achieve the purpose of initiating 2DEG and forming a low-resistance ohmic electrode described in embodiments 1 to 6, but there is no need to perform them separately. By performing them simultaneously, the process can be simplified.

[0135] That is, the process can be simplified by simultaneously performing the formation of the composite layer 8 for forming the low-resistance ohmic electrode described in the first to sixth embodiments and the high-temperature heat treatment for inducing 2DEG.

[0136] The structure of the ohmic electrode in the present disclosure becomes more effective when it is designed so that the sheet resistance due to 2DEG generated at the AlGaN / GaN interface becomes sufficiently high, that is, at least 10 kΩ / sq or more, in a state where the metal film 5 and the insulating film 6 are not formed.

[0137] <Implementation Method 8>

[0138] <Device Structure>

[0139] In the structure of the semiconductor device of the eighth embodiment of the present disclosure, in addition to the fact that the composite layer 8 contains the element constituting the insulating film 6 and the barrier layer 4 and the metal film 5 contain one or more metal elements, Figure 1 The structure of the semiconductor device 100 of the first embodiment shown in FIG. Figure 1 The semiconductor device of this embodiment is described.

[0140] As the metal element contained in the composite layer 8, one or more of Ga, Al and Au can be listed. By adopting such a structure, the composite layer 8 contains materials constituting a semiconductor device, especially a nitride semiconductor device, and unnecessary impurities are not mixed into the composite layer 8, so that a semiconductor device with stable electrical characteristics can be obtained.

[0141] Here, the barrier layer 4 is composed of AlGaN, and the metal film 5 is composed of Al or Au. It can be set to a structure in which at least one of Al and Ga as metal elements contained in the barrier layer 4 is introduced into the composite layer 8, and it can also be set to a structure in which at least one of Al and Au as metal elements contained in the metal film 5 is introduced into the composite layer 8.

[0142] In other words, by setting a structure in which one or more of Al, Ga, and Au, which are metal elements included in the barrier layer 4 and the metal film 5, are included in the composite layer 8, it is possible to suppress mixing of unnecessary impurities into the composite layer 8.

[0143] The following structure can be adopted: when gallium is included in the composite layer 8, it contains 2 atomic percent (at%) or more, when aluminum is included in the composite layer 8, it contains 10 atomic percent (at%) or more, and when gold is included in the composite layer 8, it contains 5 atomic percent (at%) or more. By adopting such a structure, the composite layer 8 can be formed with a material constituting a semiconductor device, especially a nitride semiconductor device, and the complication of the manufacturing process can be suppressed.

[0144] In addition, in Embodiment 8, Figure 1 Although the composite layer 8 in the structure of the semiconductor device 100 of the first embodiment is described, the composite layer 8 of the semiconductor devices 200 to 700 of the second to seventh embodiments may also be configured to include one or more metal elements included in the barrier layer 4 and the metal film 5 .

[0145] <Implementation Method 9>

[0146] <Device Structure>

[0147] Fig.31 is a cross-sectional view showing the structure of a semiconductor device 800 according to Embodiment 9 of the present disclosure. Fig.31 For use with Figure 1 The same reference numerals are used to denote the same structures as those of the semiconductor device 100 described above, and redundant description will be omitted.

[0148] like Fig.31 As shown, in the semiconductor device 800, in addition to Figure 1In addition to the structure of the semiconductor device 100 shown in the figure, it also has an insulating film 10 that partially covers the insulating film 6, the composite layer 8, and the wiring layer 7. When the semiconductor device 800 is a transistor, the insulating film 10 functions as a gate insulating film of a gate electrode provided in a portion not shown. In addition, when a gate insulating film is provided separately, it functions as a protective film of the gate electrode. The insulating film 10 can be made of Al2O3, SiO2, or SiN, similarly to the insulating film 6.

[0149] In this way, even in a structure in which an insulating film 10 is provided on the ohmic electrode formed on the semiconductor layer having an AlGaN / GaN heterojunction, the contact resistance can be reduced due to the presence of the composite layer 8, and by using the insulating film 10 as a protective film for the gate insulating film or the gate electrode, abnormalities such as degradation, deterioration or peeling of the gate insulating film or the gate electrode can be suppressed, thereby realizing various semiconductor devices.

[0150] In addition, Fig.31 2 shows a structure in which the insulating film 10 is provided in the semiconductor device 100 , but the insulating film 10 may also be provided in the structure of any of the semiconductor devices 200 to 700 of the second to seventh embodiments.

[0151] <Implementation Method 10>

[0152] <Device Structure>

[0153] Fig.32 is a cross-sectional view showing the structure of a semiconductor device 900 according to Embodiment 10 of the present disclosure. Fig.32 For use with Figure 1 The same reference numerals are used to denote the same structures as those of the semiconductor device 100 described above, and redundant description will be omitted.

[0154] like Fig.32 As shown, the semiconductor device 900 is configured as follows: the wiring layer 7 is bonded not only to the inside of the contact hole CH provided in the composite layer 8, but also to a part of the upper portion of the composite layer 8. By setting such a structure, the contact hole CH is completely covered by the wiring layer 7, and a gap can be prevented from being generated between the contact hole CH and the wiring layer 7. In addition, abnormalities such as peeling of the composite layer 8 or degradation of the metal film 5 inside the contact hole CH can be suppressed.

[0155] <Implementation Method 11>

[0156] <Device Structure>

[0157] Fig.33 is a cross-sectional view showing the structure of a semiconductor device 1000 according to Embodiment 11 of the present disclosure. Fig.33 For use with Figure 1 The same reference numerals are used to denote the same structures as those of the semiconductor device 100 described above, and redundant description will be omitted.

[0158] like Fig.33 As shown, the semiconductor device 1000 has a structure in which the buffer layer 2 is formed into multiple layers by alternately repeating the AlN layer 21 and the AlGaN layer 22. This structure has the effect of suppressing the deterioration of crystal quality caused by the difference in lattice constant between the semiconductor substrate 1 and the channel layer 3 composed of GaN.

[0159] <Implementation Method 12>

[0160] <Device Structure>

[0161] Fig.34 1 is a cross-sectional view showing the structure of a semiconductor device 1100 according to Embodiment 12 of the present disclosure. Fig.34 For use with Figure 1 The same reference numerals are used to denote the same structures as those of the semiconductor device 100 described above, and redundant description will be omitted.

[0162] like Fig.34 As shown, the semiconductor device 1100 has a structure in which a back barrier layer 11 made of AlGaN is formed on the buffer layer 2. By providing the back barrier layer 11 made of AlGaN having a larger band gap than GaN of the channel layer 3, drain leakage current can be suppressed.

[0163] <Modification>

[0164] In the semiconductor devices 100 to 1100 of the first to twelfth embodiments described above, the semiconductor substrate 1 is made of SiC, the buffer layer 2 is made of AlN, the channel layer 3 is made of GaN, and the barrier layer 4 is made of AlGaN, but the present invention is not limited to these.

[0165] That is, the semiconductor substrate 1 can be made of Si, sapphire, AlN, and GaN. When SiC or Si different from the channel layer 3 is used as the semiconductor substrate 1, the buffer layer 2 is required, but when GaN, AlGaN, or InAlGaN, which is the same material as the channel layer 3, is used as the semiconductor substrate 1, the buffer layer 2 is not necessarily required.

[0166] Therefore, if the channel layer 3 and the barrier layer 4 are formed as the semiconductor layer formed on the semiconductor substrate 1, the effects of each embodiment according to the present disclosure can be obtained.

[0167] The buffer layer may be made of GaN and AlGaN, the channel layer 3 may be made of AlGaN and InAlGaN, and the barrier layer 4 may be made of GaN, AlN, InAlGaN, and InAlN.

[0168] In addition, the insulating film 6 and the insulating film 10 are not limited to SiO 2 or SiN, and can be made of aluminum oxide (Al 2 O 3 ), HfO x , SiON, AlON, and HfON.

[0169] In addition, the nitride semiconductor layer can be set to be non-doped without impurities, but can also contain impurities such as Si, Mg (magnesium), Fe (iron), C (carbon) and Ge (germanium) as long as the amount does not affect the operation of the transistor.

[0170] Although the present disclosure has been described in detail, the above description is in all aspects illustrative and the present disclosure is not limited thereto. It should be understood that numerous modifications not shown in the examples can be conceived without departing from the scope of the present disclosure.

[0171] In addition, the present disclosure can freely combine the various embodiments within the scope of the disclosure, or appropriately modify or omit the various embodiments.

Claims

1. A semiconductor device comprising: Semiconductor substrates; A channel layer, disposed on the semiconductor substrate, and composed of a first nitride semiconductor; a barrier layer, disposed on the channel layer, and composed of a second nitride semiconductor having a band gap larger than a band gap of the first nitride semiconductor; a metal film selectively formed on the barrier layer; a composite layer, provided in contact with the metal film, and comprising at least a conductive material and an insulating material; and An insulating film is formed on the barrier layer in a region where the metal film and the composite layer are not formed.

2. The semiconductor device according to claim 1, wherein The composite layer is provided to cover a portion of the upper surface of the metal film on the side opposite to the barrier layer and a side surface of the metal film, A wiring layer is provided so as to be in contact with a region of the upper surface of the metal film where the composite layer is not provided.

3. The semiconductor device according to claim 1, wherein The composite layer is arranged to cover the upper surface of the metal film on the side opposite to the barrier layer and the side surface of the metal film, A wiring layer is provided so as to be in contact with the composite layer on the upper surface of the metal film.

4. The semiconductor device according to claim 1, wherein The composite layer is arranged to cover a portion of the upper surface of the metal film on the side opposite to the barrier layer, a side surface of the metal film, and a lower surface of the metal film on the side opposite to the upper surface. A wiring layer is provided so as to be in contact with a region of the upper surface of the metal film where the composite layer is not provided.

5. The semiconductor device according to claim 1, wherein The composite layer is arranged to cover the upper surface of the metal film on the side opposite to the barrier layer, the side surface of the metal film, and the lower surface of the metal film on the side opposite to the upper surface. A wiring layer is provided so as to be in contact with the composite layer on the upper surface of the metal film.

6. The semiconductor device according to claim 1, wherein The composite layer is provided to cover a portion of the upper surface of the metal film on the side opposite to the barrier layer, a side surface of the metal film, and a portion of the lower surface of the metal film on the side opposite to the upper surface. A wiring layer is provided so as to be in contact with a region of the upper surface of the metal film where the composite layer is not provided.

7. The semiconductor device according to claim 1, wherein The composite layer is provided to cover the upper surface of the metal film on the side opposite to the barrier layer, the side surface of the metal film, and a portion of the lower surface of the metal film on the side opposite to the upper surface. A wiring layer is provided so as to be in contact with the composite layer on the upper surface of the metal film.

8. The semiconductor device according to claim 1, wherein The sheet resistance caused by the two-dimensional electron gas generated at the interface between the channel layer and the barrier layer in a region of the barrier layer in contact with the insulating film is 10 kΩ / sq or more.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The composite layer is a silicide layer of the metal film.

10. The semiconductor device according to any one of claims 1 to 8, wherein: The channel layer is composed of gallium nitride, The barrier layer is composed of aluminum gallium nitride.

11. The semiconductor device according to any one of claims 1 to 10, wherein: The composite layer includes an element constituting the insulating film, and includes one or more metal elements included in the barrier layer and the metal film.

12. The semiconductor device according to claim 11, wherein The metal element includes one or more of gallium, aluminum and gold.

13. The semiconductor device according to claim 12, wherein: When the metal element is gallium, the metal element contains more than 2 atomic percent of gallium. When the metal element is aluminum, the metal element contains 10 atomic percent or more of aluminum. When the metal element is gold, 5 atomic % or more of gold is contained.

14. A method for manufacturing a semiconductor device, manufacturing the semiconductor device according to claim 1, wherein: The manufacturing method comprises: forming the channel layer on the semiconductor substrate; forming the barrier layer on the channel layer; A step of selectively forming the metal film on the barrier layer; forming the insulating film so as to cover the metal film; as well as After forming the insulating film, a heat treatment is performed at a temperature of 500° C. to 900° C. to react a portion where the metal film and the insulating film are in contact with each other to form the composite layer.

15. A method for manufacturing a semiconductor device, manufacturing the semiconductor device according to claim 1, wherein: The manufacturing method comprises: forming the channel layer on the semiconductor substrate; forming the barrier layer on the channel layer; forming a first insulating film on the barrier layer; A step of selectively forming the metal film on the first insulating film; forming a second insulating film so as to cover the metal film; as well as After forming the second insulating film, heat treatment is performed at a temperature of 500° C. to 900° C. to react the contacting portions of the metal film, the first insulating film, and the second insulating film to form the composite layer.

16. A method for manufacturing a semiconductor device, manufacturing the semiconductor device according to claim 1, wherein: The manufacturing method comprises: forming the channel layer on the semiconductor substrate; forming the barrier layer on the channel layer; forming a first insulating film on the barrier layer; and forming a contact hole reaching the barrier layer by partially removing the first insulating film. A step of selectively forming the metal film on the first insulating film including the contact hole; a step of forming a second insulating film so as to cover the metal film; and After forming the second insulating film, heat treatment is performed at a temperature of 500° C. to 900° C. to react the contacting portions of the metal film, the first insulating film, and the second insulating film to form the composite layer.

Images