Method for reducing instantaneous effect of internal current of chip

Abstract

The invention relates to the technical field of integrated circuits, and discloses a method for reducing the instantaneous effect of internal current of a chip, and the method comprises the steps: gradually starting clocks and resets of all functional systems in a starting stage of a target chip; in the turn-off stage of the target chip, gradually turning off clocks and resets of the functional systems; in a dynamic operation stage of the target chip, monitoring a first current of the first logic circuit; if the first current is reduced and the reduced current value meets a first condition, a second logic circuit is started to perform equivalent occupation on the first current; and if the first current is increased and the increased current value meets a second condition, closing the second logic circuit. According to the invention, for two stages of the working process of the chip, the current change rate of the corresponding stage is reduced so as to reduce the influence of a current abrupt change instantaneous effect, and the function stability of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for reducing the transient effect of current inside a chip. Background Art

[0002] As the scale, frequency, and performance of integrated circuits increase, power consumption also increases, making the design of power systems and signal integrity more difficult. Especially in high-power load scenarios, the voltage spike or drop caused by the rapid current change rate (di / dt) is particularly prominent, which can easily lead to chip failure, such as power supply noise, crosstalk, electromagnetic interference (EMI), and other problems, and may even affect the service life of the chip, such as causing local overheating or overvoltage damage.

[0003] Traditional chip-level power solutions, such as simple linear regulators and basic switching power supplies, often have difficulty effectively dealing with voltage spikes or drops caused by rapid current change rates, which can lead to chip failure (power noise, crosstalk, EMI, etc.) or even affect the service life (local overheating, overvoltage damage, etc.). Similarly, in the chip design process, the current change rate (di / dt) also poses challenges to the back-end power network-related design (PI, SI) and packaging design.

[0004] In view of this, a method is needed to reduce the transient effect of the current inside the chip, which can reduce di / dt from the chip design itself, that is, reduce the current mutation, thereby reducing the impact of the transient effect of the current mutation. Summary of the invention

[0005] In view of this, the present invention provides a method for reducing the transient effect of current inside a chip, which can reduce the current change rate to reduce the impact of the transient effect of current mutation and improve the functional stability of the chip.

[0006] In a first aspect, the present invention provides a method for reducing the transient effect of internal current of a chip, the method comprising: in the startup phase of the target chip, gradually turning on the clock and reset of each functional system; in the shutdown phase of the target chip, gradually turning off the clock and reset of each functional system; in the dynamic operation phase of the target chip, monitoring the first current of the first logic circuit; if the first current decreases and the decreased current value meets the first condition, turning on the second logic circuit to perform equivalent occupation of the first current; if the first current increases and the increased current value meets the second condition, turning off the second logic circuit.

[0007] In a possible implementation, the first condition is that the decreased current value is greater than a first threshold; the second condition is that the increased current value is greater than a second threshold.

[0008] In a possible implementation, the first condition is that a decreasing gradient of the first current is greater than a third threshold; and the second condition is that a rising gradient of the first current is greater than a fourth threshold.

[0009] In the second aspect, the present invention provides an integrated circuit chip, in which a soft start control system is deployed to execute a method of reducing the transient effect of internal current of the chip; the soft start control system includes a reset management module and a clock management module; the reset management module is used to control the sequence and time interval of the reset of each functional system; the clock management module is used to control the sequence and time interval of the clock of each functional system.

[0010] In a possible implementation manner, the first logic circuit is a functional system circuit preset in the chip.

[0011] In a possible implementation, the integrated circuit chip also includes a power consumption backup system; the power consumption backup system includes a second logic circuit, and the second logic circuit includes a multiplexing logic circuit; the second logic circuit is a circuit of a functional system other than a preset functional system in the chip.

[0012] In a possible implementation, the multiplexing logic circuit is also used to multiplex existing logic; the existing logic includes DFX logic and non-working circuits.

[0013] In a possible implementation, the second logic circuit includes at least one additional backup circuit; the additional backup circuit includes a D flip-flop logic circuit.

[0014] In a possible implementation, the power consumption backup system is further configured to control the working states of a corresponding number of second logic circuits according to a change gradient of the first current.

[0015] In a third aspect, the present invention provides an electronic device comprising: a memory and an integrated circuit chip, the memory and the integrated circuit chip being communicatively connected to each other, the memory storing instructions, and the integrated circuit chip executing the instructions to thereby execute a method for reducing the transient effect of internal current of a chip according to the first aspect or any corresponding embodiment thereof.

[0016] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute a method of reducing the transient effect of internal current of a chip according to the first aspect or any corresponding embodiment thereof.

[0017] The technical solution provided by this application may have the following beneficial effects:

[0018] The method of reducing the transient effect of the internal current of the chip of the present application is to gradually turn on the clock and reset of each functional system during the startup and shutdown stages of the chip, and by staggering the time points, the current is allowed to undergo multiple small-amplitude slow changes over a long period of time, thereby reducing the transient load pressure faced by the power supply system; in the dynamic operation stage of the chip, the current change of the first logic circuit is monitored in real time, and when the current of the first logic circuit is monitored to be reduced to less than the first threshold, the second logic circuit is turned on for equivalent current occupation, which can compensate for the decrease in total power consumption caused by the reduction in the current of the first logic circuit, and when the current of the first logic circuit is monitored to increase to more than the second threshold, the second logic circuit is turned off to avoid the second logic circuit from occupying too much power; by turning on and off the second logic circuit, the overall current is relatively stable at a certain value. The above scheme, respectively for the two stages of the chip working process, reduces the current change rate of the corresponding stage to reduce the impact of the transient effect of the current mutation, and improves the functional stability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 is a schematic diagram of the structure of a soft start control system according to an embodiment of the present invention;

[0021] Figure 2 is a flow chart of a method for reducing the transient effect of internal current of a chip according to an embodiment of the present invention;

[0022] Figure 3 is a schematic diagram of the structure of a power consumption backup system according to an embodiment of the present invention;

[0023] Figure 4 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0025] The embodiment of the present invention provides a method for reducing the transient effect of the internal current of a chip, by controlling the chip current change rate during the startup, shutdown and dynamic operation stages to reduce the impact of the transient effect of the current mutation and improve the functional stability of the chip.

[0026] According to an embodiment of the present invention, a method embodiment for reducing the transient effect of internal current of a chip is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0027] In this embodiment, an integrated circuit chip is also provided, in which a soft start control system is deployed to execute a method for reducing the transient effect of the internal current of the chip; the soft start control system is as follows Figure 1 As shown, including:

[0028] The reset management module 101 is used to control the sequence and time interval of the reset of each functional system;

[0029] The clock management module 102 is used to control the sequence and time interval of the clocks of each functional system.

[0030] Among them, the main purpose of the soft start control system is to control the reset and clock of each functional system so that the current changes more slowly during the startup and shutdown process of the chip, thereby reducing the transient effect of the current.

[0031] The reset management module receives the reset request and controls the sequence and time interval of the reset of each functional system, including the reset assert (reset pull low) and de-assert (reset cancel pull low). By designing the reset sequence and time interval, the sudden change of current during the startup and shutdown stages can be reduced.

[0032] The clock management module controls the sequence and time interval of the clocks of each functional system through ICG (clock gating). By controlling the opening and closing of the clock, it ensures that each functional system can increase or decrease power consumption in an orderly and slow manner when starting and shutting down, thereby reducing di / dt.

[0033] For example Figure 1 As shown, the reset management module receives reset requests from reset source O and reset source N, and the reset management module and the clock management module jointly control the sequence and time interval of the reset and clock of functional system O and functional system N through path (0), path (1), and path (2).

[0034] Figure 21 is a flow chart of a method for reducing the transient effect of internal current of a chip according to an embodiment of the present invention, the flow chart includes the following steps:

[0035] Step S201, during the startup phase of the target chip, gradually start the clock and reset of each functional system.

[0036] When the chip is started, since the simultaneous startup of each functional system may cause a huge instantaneous current change (di / dt), the present invention proposes to use a soft start control system in the startup phase, and gradually turn on the clock and reset of each functional system through the reset management module and the clock management module. Specifically, in the phase of gradual startup of the functional system, the reset management module and the clock management module cooperate to turn on the clock of the functional system in turn and release the reset. At this stage, there are three controllable variables: the order between different functional systems, the time interval between different functional systems, and the clock and reset interval within a functional system. Specifically, the gradual startup can be to turn on the clock and reset of each functional system at a certain time interval.

[0037] Optionally, in an embodiment of the present application, during the startup phase of the target chip, the time intervals between the functional systems correspond to the functional systems, that is, different functional systems correspond to different time intervals. This control of the sequence and time interval allows the current to undergo multiple small-amplitude slow changes over a longer period of time, thereby significantly reducing di / dt.

[0038] Step S202: during the shutdown phase of the target chip, the clocks and resets of the functional systems are gradually shut down.

[0039] Similar to the startup phase, if the clocks and resets of all functional systems are directly cut off during the shutdown phase, a large di / dt will also be generated. A soft-start control system is used to gradually shut down the clocks and resets of each functional system. Specifically, the gradual shutdown can be to shut down the clocks and resets of each functional system at a certain time interval.

[0040] Optionally, in an embodiment of the present application, during the shutdown phase of the target chip, the time intervals between the various functional systems correspond to the functional systems, that is, different functional systems correspond to different time intervals; for example, for a functional system that requires a longer time to complete data transmission, the time interval is set to be longer; for a functional system that requires a shorter time to complete data transmission, the time interval is set to be shorter. In the gradual shutdown process, the time interval can be adjusted according to the current changes of the functional system. For example, in the stage where the current drops significantly, a longer time interval may be required; in the stage where the current drops less, a shorter time interval may be required. According to the characteristics and current conditions of each functional system, the soft start control system can flexibly adjust the time interval to more accurately control di / dt.

[0041] Step S203, in the dynamic operation stage of the target chip, monitor the first current of the first logic circuit; if the first current decreases and the reduced current value meets the first condition, turn on the second logic circuit to perform equivalent occupation of the first current; if the first current increases and the increased current value meets the second condition, turn off the second logic circuit.

[0042] In the dynamic operation stage of the chip, the current change of the first logic circuit is monitored, and the second logic circuit is turned on or off according to preset conditions to perform equivalent occupation of power consumption.

[0043] Optionally, the first condition is that the decreased current value is greater than a first threshold; the second condition is that the increased current value is greater than a second threshold.

[0044] Alternatively, the first condition is that the falling gradient of the first current is greater than a third threshold; and the second condition is that the rising gradient of the first current is greater than a fourth threshold.

[0045] In order to more accurately control the opening and closing of the power consumption backup circuit system, a variety of optional conditions are set to determine whether the current change of the first logic circuit needs to be equivalently occupied by the second logic circuit.

[0046] Specifically, there are two ways to set the first condition and the second condition.

[0047] In the first setting method, the first condition is that when the current of the first logic circuit decreases and the reduced current value is greater than the preset first threshold, the second logic circuit is turned on to perform equivalent occupation of power consumption. The second condition is that when the current of the first logic circuit increases and the increased current value is greater than the preset second threshold, it is considered that the power consumption of the first logic circuit has recovered at this time, and the second logic circuit is turned off. This setting method is based on the absolute value of the current change and is used to determine whether the power consumption of the first logic circuit is sufficient or excessive.

[0048] In the second setting method, the first condition is that when the current drop gradient of the first logic circuit is greater than the preset third threshold value, that is, the current drops rapidly in a short time, it is considered that this rapid current change may cause a large impact on the power supply system, so it is necessary to immediately turn on the second logic circuit for equivalent power consumption. The second condition is that when the current rise gradient of the first logic circuit is greater than the preset fourth threshold value, that is, the current rises rapidly in a short time, it is considered that the power consumption of the original circuit is sufficient at this time, so the second logic circuit is turned off. This setting method is based on the rate of current change and can respond to current fluctuations more promptly.

[0049] The threshold in the present invention refers to the critical value of the current or the critical value of the current gradient. For example, the first threshold may be 0.5A. When the current value reduced by the first logic circuit is greater than 0.5A, the second logic circuit is turned on; the second threshold may be 1A. When the current value increased by the first logic circuit is greater than 1A, the second logic circuit is turned off; the third threshold may be 1A / us. When the current decreasing gradient of the first logic circuit is greater than 1A / us, the second logic circuit is turned on; the fourth threshold may be 2A / us. When the current increasing gradient of the first logic circuit is greater than 2A / us, the second logic circuit is turned off. The first threshold, the second threshold, the third threshold and the fourth threshold are configured according to the actual situation, so that the opening and closing of the second logic circuit can be controlled more flexibly.

[0050] In some optional implementations, the first logic circuit is a functional system circuit preset in the chip. In an embodiment of the present invention, the first logic circuit is a functional system circuit preset in the chip. During the operation of the chip, the current change of the first logic circuit directly reflects the fluctuation of its power consumption.

[0051] In some optional implementations, the above-mentioned integrated circuit chip also includes a power consumption backup system; the power consumption backup system includes a second logic circuit; the second logic circuit is a circuit of a functional system in the chip other than a preset functional system.

[0052] The second logic circuit includes a multiplexing logic circuit; the multiplexing logic circuit is also used to multiplex existing logic; the existing logic includes DFX logic and non-working circuits.

[0053] Optionally, the second logic circuit includes at least one additional backup circuit; the additional backup circuit includes a D flip-flop logic circuit.

[0054] Specifically, the power consumption backup system is composed of a second logic circuit. The second logic circuit refers to other functional system circuits in the chip except for the preset main functional system circuits. Under certain conditions, it can be turned on or off to adjust the transient effect of the internal current of the chip. The second logic circuit includes two implementation methods:

[0055] In the first implementation, the multiplexing logic circuit is the main component of the power backup system. The multiplexing logic circuit uses the existing logic in the chip that is not currently in operation (such as DFX logic, non-operating circuits, etc.) to perform equivalent power consumption. This method does not require the addition of too many additional logic circuits, and only requires the addition of some monitoring and control logic on the basis of the existing logic.

[0056] The second implementation method is to use additional backup circuits as an alternative to the power backup system. The additional backup circuits include additional logic components such as D-type flip-flop logic circuits. These circuits have no actual functional role and are only used as power backup. Although this method may have certain redundancy in functional logic, it provides higher flexibility and allows the size and scope of power backup to be adjusted according to actual needs.

[0057] Among them, the power consumption backup system structure is as follows Figure 3 As shown, the multiplexed logic circuit mainly includes DFX logic B, control unit C and monitoring unit D. DFX logic B is the main component that carries power consumption, and participates in or exits the main operation logic according to demand. Control unit C is the core of the entire multiplexed logic. It processes the signal from logic circuit A as the original functional signal to guide the behavior of DFX logic B. When the system starts, control unit C is responsible for initializing all DFX logic B to the default state, and can drive DFX logic B to run at full speed when necessary, and switch to the functional mode of cooperating with logic circuit A. Monitoring unit D is responsible for detecting the operating status of logic circuit A, directly receiving upstream interface signals or parsing local protocol layer status information.

[0058] The additional backup circuit includes control unit E and power backup circuit F. Control unit E is similar to control unit C, but provides more diverse control methods, such as clock enable (clken*), reset operation (reset, rst*), frequency adjustment (Div*), etc., to meet the needs of the system in different scenarios. Power backup circuit F is an important component of system power management and is composed of storage elements such as DFFs or MEMs. Power backup circuit F supports group management of circuits, enabling the separate opening and closing of different components and the adjustment of operating frequency.

[0059] like Figure 3 The power backup system structure shown has the following execution logic:

[0060] 1. Monitoring unit D receives upstream interface signals;

[0061] 2. The monitoring unit D monitors or processes the signal by parsing the local protocol layer status information;

[0062] 3. Control unit C processes the signal from monitoring unit D;

[0063] 4. Control unit C processes the signal from logic circuit A;

[0064] 5. DFX logic B is guided by control unit C;

[0065] 6. Control unit E processes the signal from monitoring unit D;

[0066] 7. The control unit E provides clock enable, reset operation, frequency adjustment and other signals to the power consumption backup circuit.

[0067] In summary, the multiplexing logic circuit of the first implementation of the second logic circuit is the main solution for the power backup system. The additional power backup circuit of the second implementation of the second logic circuit is an optional solution, which is only used as an alternative solution in scenarios where the number of logics and DIE size are not sensitive, and the power consumption of the logic multiplexing part is too small to meet the power balancing requirements.

[0068] In some optional implementations, the power consumption backup system is further used to control the working states of a corresponding number of second logic circuits according to a change gradient of the first current.

[0069] The current change gradient is a physical quantity that describes how fast the current changes over time, and reflects the degree of current change. In an embodiment of the present invention, by monitoring the current change gradient of the first logic circuit, the power consumption backup system can determine the trend and intensity of the current chip power consumption change, and respond accordingly. When the current change gradient of the first logic circuit is large, it means that the power consumption change intensity is large. At this time, the power consumption backup system will control the opening of more second logic circuits to provide more power consumption equivalent occupancy, thereby more effectively balancing the overall current change and reducing the current transient effect. On the contrary, when the current change gradient of the first logic circuit is small, the power consumption backup system will reduce the number of opened second logic circuits accordingly to avoid wasting resources.

[0070] To summarize, the embodiments of the present invention introduce a soft start control system and a power consumption backup system to respectively reduce the current change rate in the startup and shutdown stages and the dynamic operation stage of the chip working process, thereby reducing the impact of the transient effect of current mutation and improving the functional stability of the chip.

[0071] An embodiment of the present invention further provides an electronic device, wherein the electronic device is provided with a Figure 1 The soft start control system shown in Figure 3 The integrated circuit chip of the power backup system shown in FIG. Figure 2 The method shown.

[0072] See also Figure 4 , Figure 4 is a schematic diagram of the structure of an electronic device provided by an optional embodiment of the present invention, such as Figure 4As shown, the electronic device includes: one or more integrated circuit chips 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The integrated circuit chip can process instructions executed in the electronic device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple integrated circuit chips and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers). Figure 4 An integrated circuit chip 10 is taken as an example.

[0073] The integrated circuit chip 10 may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0074] The memory 20 stores instructions executable by at least one integrated circuit chip 10 , so that at least one integrated circuit chip 10 executes the method shown in the above embodiment.

[0075] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and applications required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the integrated circuit chip 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0076] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0077] The computer device also includes an input device 30 and an output device 40. The integrated circuit chip 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 4 The example of connecting through bus is taken in the following.

[0078] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0079] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0080] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0081] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for reducing the transient effect of internal current of a chip, characterized in that: The method comprises: During the startup phase of the target chip, the clock and reset of each functional system are gradually turned on; In the shutdown phase of the target chip, gradually shutting down the clocks and resets of the functional systems; During the dynamic operation phase of the target chip, the first current of the first logic circuit is monitored; if the first current decreases and the decreased current value satisfies a first condition, the second logic circuit is turned on to perform equivalent occupation of the first current; if the first current increases and the increased current value satisfies a second condition, the second logic circuit is turned off.

2. The method according to claim 1, characterized in that The first condition is that the decreased current value is greater than a first threshold; the second condition is that the increased current value is greater than a second threshold.

3. The method according to claim 1, characterized in that The first condition is that the descending gradient of the first current is greater than a third threshold; the second condition is that the ascending gradient of the first current is greater than a fourth threshold.

4. An integrated circuit chip, characterized in that: A soft start control system is deployed in the integrated circuit chip to execute the method according to any one of claims 1 to 3; the soft start control system includes a reset management module and a clock management module; The reset management module is used to control the sequence and time interval of resetting each functional system; The clock management module is used to control the sequence and time interval of the clocks of each functional system.

5. The chip according to claim 4, characterized in that: The first logic circuit is a functional system circuit preset in the chip.

6. The chip according to claim 5, characterized in that: The integrated circuit chip also includes a power consumption backup system; the power consumption backup system includes the second logic circuit, and the second logic circuit includes a multiplexing logic circuit; The second logic circuit is a circuit of a functional system in the chip except the preset functional system.

7. The chip according to claim 6, characterized in that: The multiplexing logic circuit is also used to multiplex existing logic; the existing logic includes DFX logic and non-working circuits.

8. The chip according to claim 5, characterized in that: The second logic circuit includes at least one additional backup circuit; the additional backup circuit includes a D flip-flop logic circuit.

9. The chip according to claim 6, characterized in that: The power consumption backup system is further used to control the working states of a corresponding number of second logic circuits according to the change gradient of the first current.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 3.

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