Pixel circuit, driving method, display panel and electronic equipment

Abstract

The invention relates to a pixel circuit, a driving method, a display panel and electronic equipment. The pixel circuit comprises a light-emitting element; the first transistor is provided with a back gate structure, the first transistor is coupled with the light-emitting element, and the first transistor is used for driving the light-emitting element to emit light; the second transistor is provided with a back gate structure, the first end of the second transistor is used for being coupled with a first signal line, the second end of the second transistor is coupled with the gate of the first transistor to form a first node, and the second transistor is used for initializing the gate of the first transistor; the third transistor is provided with a back gate structure, the first end of the third transistor is coupled with the first node, and the second end of the third transistor is coupled between the first transistor and the light-emitting element; wherein back gates formed by the back gate structures of the first transistor, the second transistor and the third transistor are all used for being coupled with a second signal line, and a second signal of the second signal line is used for resetting the first transistor, the second transistor and the third transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of display, and in particular to a pixel circuit, a driving method, a display panel and an electronic device. Background Art

[0002] At present, when the pixel circuit is displaying an image, the transistor used to drive the light-emitting element to emit light has a hysteresis effect. The hysteresis effect of the transistor will cause the display panel to have problems such as afterimage and flicker, resulting in poor image display effect. Summary of the invention

[0003] In order to overcome the problems existing in the related art, the present disclosure provides a pixel circuit, a driving method, a display panel and an electronic device.

[0004] According to a first aspect of the present disclosure, a pixel circuit is provided, the pixel circuit comprising:

[0005] Light emitting element;

[0006] A first transistor, the first transistor having a back gate structure, the first transistor being coupled to the light emitting element, and the first transistor being used to drive the light emitting element to emit light;

[0007] a second transistor, the second transistor having a back-gate structure, a first end of the second transistor being used to couple with a first signal line, a second end of the second transistor being coupled with a gate of the first transistor to form a first node, and the second transistor being used to initialize the gate of the first transistor;

[0008] a third transistor, the third transistor having a back-gate structure, a first end of the third transistor coupled to the first node, and a second end of the third transistor coupled between the first transistor and the light-emitting element;

[0009] The back gates formed by the back gate structures of the first transistor, the second transistor and the third transistor are all used to couple with a second signal line, and the second signal of the second signal line is used to reset the first transistor, the second transistor and the third transistor.

[0010] In some embodiments of the present disclosure, the first transistor, the second transistor and the third transistor share a back gate structure.

[0011] In some embodiments of the present disclosure, the first transistor, the second transistor and the third transistor are all P-type transistors, and in the process of resetting the first transistor, the second transistor and the third transistor, the voltage of the second signal is a negative voltage; or,

[0012] The first transistor, the second transistor and the third transistor are all N-type transistors. During the process of resetting the first transistor, the second transistor and the third transistor, the voltage of the second signal is a positive voltage.

[0013] In some embodiments of the present disclosure, the gate of the second transistor is used to couple to the first scan signal line, and the gate of the third transistor is used to couple to the second scan signal line.

[0014] In some embodiments of the present disclosure, the pixel circuit further includes:

[0015] A fourth transistor, wherein the first end of the fourth transistor is used to couple with the third signal line, the second end of the fourth transistor is coupled with the first end of the first transistor, the gate of the fourth transistor is used to couple with the second scanning signal line, and the fourth transistor is used to write the data of the third signal line into the gate of the first transistor.

[0016] In some embodiments of the present disclosure, the pixel circuit further includes:

[0017] A fifth transistor, wherein the first end of the fifth transistor is used to couple with the fourth signal line, the second end of the fifth transistor is coupled with the anode of the light-emitting element, the gate of the fifth transistor is used to couple with the second scanning signal line, and the fifth transistor is used to initialize the light-emitting element.

[0018] In some embodiments of the present disclosure, the pixel circuit further includes:

[0019] a sixth transistor, wherein a first terminal of the sixth transistor is used to be coupled to a first power source, and a second terminal of the sixth transistor is coupled to a first terminal of the first transistor;

[0020] a seventh transistor, wherein a first terminal of the seventh transistor is coupled to the second terminal of the first transistor, and a second terminal of the seventh transistor is coupled to the anode of the light emitting element;

[0021] The sixth transistor and the seventh transistor are used to control the first power source and the light-emitting element to be turned on and off.

[0022] In some embodiments of the present disclosure, the pixel circuit further includes:

[0023] A storage capacitor, wherein a first end of the storage capacitor is used to couple to a first power source, a second end of the storage capacitor is coupled to the gate of the first transistor, and the storage capacitor is used to adjust the voltage of the gate of the first transistor.

[0024] In some embodiments of the present disclosure, during the process of resetting the first transistor, the second transistor and the third transistor, the second signal is a constant voltage signal; or, the second signal is a pulse signal; or, the second signal is an AC signal.

[0025] According to a second aspect of the present disclosure, a method for driving a pixel circuit is provided, the method for driving a pixel circuit comprising at least one writing frame, the execution process of the writing frame comprising a data writing phase, in which data of a third signal line is written into a gate of a first transistor;

[0026] Before the data writing stage and / or after the data writing stage, the execution process of the writing frame also includes a reset stage. In the reset stage, a second signal is input to the back gates of the first transistor, the second transistor and the third transistor through a second signal line to reset the first transistor, the second transistor and the third transistor.

[0027] In some embodiments of the present disclosure, the execution process of writing the frame further includes an initialization phase executed before the data writing phase and a light emitting phase executed after the data writing phase, in the reset phase, the voltage of the second signal is a first preset voltage, and in the data writing phase, the initialization phase and the light emitting phase, the voltage of the second signal is a second preset voltage;

[0028] When the first transistor, the second transistor and the third transistor are all P-type transistors, the first preset voltage is a negative voltage, and the second preset voltage is a positive voltage;

[0029] When the first transistor, the second transistor, and the third transistor are all N-type transistors, the first preset voltage is a positive voltage, and the second preset voltage is a negative voltage.

[0030] In some embodiments of the present disclosure, when the second transistor, the third transistor, the fourth transistor and the fifth transistor are all P-type transistors,

[0031] In the initialization phase, the first scanning signal line is controlled to input a first level to the second transistor, and in the reset phase, the data writing phase and the light emitting phase, the first scanning signal line is controlled to input a second level to the second transistor;

[0032] In the data writing stage, the second scanning signal line is controlled to input the first level to the third transistor, the fourth transistor and the fifth transistor, and in the initialization stage, the reset stage and the light emitting stage, the second scanning signal line is controlled to input the second level to the third transistor, the fourth transistor and the fifth transistor; or

[0033] When the second transistor, the third transistor, the fourth transistor and the fifth transistor are all N-type transistors,

[0034] In the initialization phase, the first scanning signal line is controlled to input the second level to the second transistor, and in the reset phase, the data writing phase and the light emitting phase, the first scanning signal line is controlled to input the first level to the second transistor;

[0035] In the data writing stage, the second scanning signal line is controlled to input the second level to the third transistor, the fourth transistor and the fifth transistor. In the initialization stage, the reset stage and the light-emitting stage, the second scanning signal line is controlled to input the first level to the third transistor, the fourth transistor and the fifth transistor.

[0036] In some embodiments of the present disclosure, the driving method of the pixel circuit further includes at least one holding frame located after at least one of the writing frames.

[0037] In some embodiments of the present disclosure, when the second transistor, the third transistor, the fourth transistor and the fifth transistor are all P-type transistors, during the execution of the hold frame, the first scan signal line is controlled to continuously input the second level to the second transistor, and the second scan signal line is controlled to continuously input the second level to the third transistor, the fourth transistor and the fifth transistor;

[0038] When the second transistor, the third transistor, the fourth transistor and the fifth transistor are all N-type transistors, during the execution of the hold frame, the first scan signal line is controlled to continuously input the first level to the second transistor, and the second scan signal line is controlled to continuously input the first level to the third transistor, the fourth transistor and the fifth transistor.

[0039] According to a third aspect of the present disclosure, a display panel is provided, which includes the pixel circuit as described above and a first array substrate gate driving circuit, the first array substrate gate driving circuit includes the second signal line, and the first array substrate gate driving circuit is coupled to the back gates of the first transistor, the second transistor and the third transistor through the second signal line.

[0040] In some embodiments of the present disclosure, the display panel includes a plurality of pixel circuits arranged in an array, each row of the pixel circuits corresponds to one second signal line, and the second signal of the second signal line is used to reset the first transistor, the second transistor, and the third transistor of the pixel circuit in the corresponding row;

[0041] Among them, in the pixel circuits in the same row, the back gate structures of each of the first transistors, each of the second transistors and each of the third transistors are connected to form a back gate structure group; the back gate structure groups corresponding to the pixel circuits in different rows are separated from each other.

[0042] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising the display panel as described above.

[0043] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0044] The pixel circuit includes a light-emitting element, a first transistor, a second transistor and a third transistor. The first transistor is coupled to the light-emitting element and is used to drive the light-emitting element to emit light. The second transistor is coupled to the gate of the first transistor and is used to initialize the gate of the first transistor to eliminate the residual voltage of the gate of the first transistor. The third transistor is coupled between the first transistor and the light-emitting element and is used to change the gate voltage of the first transistor to eliminate the influence of the threshold voltage of the first transistor on the driving current of the light-emitting element. The first transistor, the second transistor and the third transistor have a back-gate structure, and the first transistor, the second transistor and the third transistor are reset by inputting the second signal of the second signal line into the back gate of the first transistor, the second transistor and the third transistor. When the first transistor, the second transistor and the third transistor are reset through the back gate by the second signal, the charge trapped in the trap state in the channel of the first transistor, the second transistor and the third transistor can be quickly released. The rapid release of the charge reduces the hysteresis of the first transistor, the second transistor and the third transistor, improves the problem of afterimage and flicker of the display panel, and thus improves the effect of picture display.

[0045] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0047] Figure 1-1 It is a schematic diagram of a pixel circuit display screen;

[0048] Figure 1-2It is a schematic diagram of another pixel circuit display screen;

[0049] Figure 1-3 It is a schematic diagram of a transistor characteristic curve;

[0050] Figure 2 It is a schematic diagram of the time-brightness of a light-emitting element;

[0051] Figure 3 is a schematic diagram of the structure of a pixel circuit;

[0052] Figure 4 is a schematic diagram of a pixel circuit driving structure;

[0053] Figure 5 It is a signal timing diagram of a pixel circuit;

[0054] Figure 6 is a schematic structural diagram of a pixel circuit provided by an exemplary embodiment of the present disclosure;

[0055] Figure 7 is a schematic structural diagram of a first transistor provided by an exemplary embodiment of the present disclosure;

[0056] Figure 8 is a schematic structural diagram of a first transistor provided by another exemplary embodiment of the present disclosure;

[0057] Fig. 9 is a structural schematic diagram of a pixel circuit provided by another exemplary embodiment of the present disclosure;

[0058] Figure 10-1 is a signal timing diagram of a pixel circuit provided by an exemplary embodiment of the present disclosure;

[0059] Figure 10-2 is a signal timing diagram of a pixel circuit provided by another exemplary embodiment of the present disclosure;

[0060] Fig.11 is a signal timing diagram of a pixel circuit provided by another exemplary embodiment of the present disclosure;

[0061] Figure 12-1 is a schematic diagram of a back-gate structure of a first transistor, a second transistor, and a third transistor in each pixel circuit provided by an exemplary embodiment of the present disclosure;

[0062] Figure 12-2 is a schematic diagram of a back gate structure of a first transistor, a second transistor and a third transistor in each pixel circuit provided by another exemplary embodiment of the present disclosure;

[0063] Figure 13-1 is a schematic diagram of a pixel circuit driving structure provided by an exemplary embodiment of the present disclosure;

[0064] Figure 13-2 is a schematic diagram of a pixel circuit driving structure provided by another exemplary embodiment of the present disclosure;

[0065] Fig.14 is a system block diagram of an electronic device provided by an exemplary embodiment of the present disclosure.

[0066] In the figure:

[0067] T1-first transistor; T2-second transistor; T3-third transistor; T4-fourth transistor; T5-fifth transistor; T6-sixth transistor; T7-seventh transistor; T8-eighth transistor; OLED-light-emitting element; Cst-storage capacitor; Vdd-first power supply; Vss-second power supply; Vdata-data signal line; VI1-initialization signal line; VI2-reset signal line; EM-enable signal line; Scan(n-1)-first scan signal line; Scan(n)-second scan signal line; ScanR-third scan signal line; VI G-first signal line; VBSM-second signal line; Vd-third signal line; VIA-fourth signal line; VIR-fifth signal line; N1-first node; N2-second node; N3-third node; N4-fourth node; 10-back gate structure; 11-gate structure; 12-channel layer; 13-substrate; 400-electronic device; 402-processing component; 404-memory; 406-power supply component; 408-multimedia component; 410-audio component; 412-input and output interface; 414-sensor component; 416-communication component; 420-processor. DETAILED DESCRIPTION

[0068] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items. In addition, the term "coupled" should be understood in a broad sense and can be a direct or physical connection, or an indirect or electrical connection.

[0069] At present, Low Temperature Poly-Silicon (LTPS) technology is a new generation of technology in the display field. It uses polysilicon liquid crystal materials to make the display panel have the advantages of high refresh rate, high response speed, low power consumption, etc. However, when the pixel circuit displays the picture, the hysteresis effect of the transistor used to drive the light-emitting element to emit light causes the display panel to have problems such as afterimage, flicker, mura, etc., resulting in poor picture display effect.

[0070] like Figure 1-1 , Figure 1-2 and Figure 1-3 As shown, different display areas display black and white in the previous frame, and switch to the same grayscale in the next frame. Since the stress of the transistor driving the light-emitting element to display black and white is different, the hysteresis effect of the transistor will cause the current driving different light-emitting elements to change, resulting in the afterimage problem. Figure 1-3 The current difference △I in is the driving current difference of the light-emitting element caused by the hysteresis effect. ds is the drain current of the transistor, V gs is the gate-source voltage of the transistor.

[0071] like Figure 2 As shown in FIG. 1 , due to the hysteresis effect of the transistor, the brightness of the light-emitting element decreases during the switching of the refresh rate of the display panel, resulting in the occurrence of flickering problems. Where b is the brightness and t is the time. The refresh rate of the display panel in stage T1 is 120 Hz, and the refresh rate of the display panel in stages T2 and T3 is 10 Hz.

[0072] In the related art, a pixel circuit, such as Figure 3As shown, it includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a light-emitting element OLED and a storage capacitor Cst. The first end of the first transistor T1 is coupled to the first power supply Vdd through the sixth transistor T6, and the second end is coupled to the anode of the light-emitting element OLED through the seventh transistor T7. The second transistor T2 is coupled between the initialization signal line VI1 and the gate of the first transistor T1. The third transistor T3 is coupled between the gate and the second end of the first transistor T1. The fourth transistor T4 is coupled between the data signal line Vdata and the first end of the first transistor T1. The fifth transistor T5 is coupled between the reset signal line VI2 and the anode of the light-emitting element OLED. The cathode of the light-emitting element OLED is coupled to the second power supply Vss. Among them, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-type transistors. And, the gate of the second transistor T2 is coupled to the first scan signal line Scan(n-1). The gates of the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are coupled to the second scan signal line Scan(n). The gates of the sixth transistor T6 and the seventh transistor T7 are coupled to the enable signal line EM. The enable signal line EM, the first scan signal line Scan(n-1) and the second scan signal line Scan(n) are provided by the array substrate gate drive circuit (Gate Driven on Array, GOA) in the display panel including the pixel circuit. The driving structure of the pixel circuit is as shown in FIG. Figure 4 As shown. The rectangle represents a pixel circuit. A plurality of array substrate gate drive circuits are arranged on one side or two opposite sides of the pixel circuit, and the plurality of array substrate gate drive circuits include an enable signal line EM drive circuit, a first scan signal line Scan(n-1) drive circuit and a second scan signal line Scan(n) drive circuit. When the first scan signal of the first scan signal line Scan(n-1) is delayed to obtain the second scan signal of the second scan signal line Scan(n), the plurality of array substrate gate drive circuits may not include the second scan signal line Scan(n) drive circuit. The enable signal line EM adopts a double-end drive, that is, the enable signal line EM drive circuit in the array substrate gate drive circuit is arranged on both sides of the pixel circuit. The first scan signal line Scan(n-1) adopts a double-end drive, that is, the first scan signal line Scan(n-1) drive circuit in the array substrate gate drive circuit is arranged on both sides of the pixel circuit.

[0073] like Figure 5 As shown, T1 to T3 are the three stages of the pixel circuit operation process. EM is the voltage of the enable signal line EM. Scan(n-1)is the voltage of the first scanning signal line Scan(n-1). Scan(n) is the voltage of the second scanning signal line Scan(n). Data is data. When the light-emitting element OLED is driven to emit light, it needs to go through the initialization stage T1, the data writing stage T2 and the light-emitting stage T3. However, due to the hysteresis effect of the first transistor T1, the second transistor T2 and the third transistor T3, the driving current for driving the light-emitting element OLED to emit light will be affected, resulting in afterimages and flickering on the display panel, resulting in poor display effect.

[0074] Based on this, the present disclosure provides a pixel circuit, wherein a first transistor for driving a light-emitting element to emit light, a second transistor for initializing the gate voltage of the first transistor, and a third transistor for eliminating the influence of the threshold voltage on the driving current have a back-gate structure, and by inputting a second signal into the back gates of the first transistor, the second transistor, and the third transistor in the reset phase, the charges trapped in the channels of the first transistor, the second transistor, and the third transistor can be quickly released to reset the first transistor, the second transistor, and the third transistor. Due to the rapid release of the charges, the hysteresis of the first transistor, the second transistor, and the third transistor is reduced, the problems of afterimage and flicker of the display panel are improved, and the effect of picture display is improved.

[0075] like Figure 6 and Figure 7 As shown, an exemplary embodiment of the present disclosure provides a pixel circuit, including a light-emitting element OLED, a first transistor T1, a second transistor T2 and a third transistor T3. The first transistor T1 has a back gate structure 10, and the first transistor T1 is coupled to the light-emitting element OLED, and is used to drive the light-emitting element OLED to emit light. The second transistor T2 has a back gate structure 10, a first end is used to couple with the first signal line VIG, and a second end is coupled with the gate of the first transistor T1 to form a first node N1, which is used to initialize the gate of the first transistor T1. The third transistor T3 has a back gate structure 10, a first end is coupled with the first node N1, and a second end is coupled between the first transistor T1 and the light-emitting element OLED to form a second node N2. Among them, the back gates formed by the back gate structures 10 of the first transistor T1, the second transistor T2 and the third transistor T3 are all used to couple with the second signal line VBSM, and the second signal of the second signal line VBSM is used to reset the first transistor T1, the second transistor T2 and the third transistor T3. The first transistor T1, the second transistor T2 and the third transistor T3 also have a gate structure 11 and a channel layer 12.

[0076] In this embodiment, the pixel circuit includes a light-emitting element, a first transistor, a second transistor and a third transistor, wherein the first transistor is coupled to the light-emitting element and is used to drive the light-emitting element to emit light. The second transistor is coupled to the gate of the first transistor and is used to initialize the gate of the first transistor to eliminate the residual voltage of the gate of the first transistor. The third transistor is coupled between the first transistor and the light-emitting element and is used to change the gate voltage of the first transistor to eliminate the influence of the threshold voltage of the first transistor on the driving current of the light-emitting element. The first transistor, the second transistor and the third transistor have a back-gate structure, and the first transistor, the second transistor and the third transistor are reset by inputting the second signal of the second signal line into the back gate of the first transistor, the second transistor and the third transistor. When the first transistor, the second transistor and the third transistor are reset through the back gate by the second signal, the charge captured by the trap state in the channel of the first transistor, the second transistor and the third transistor can be quickly released. The rapid release of the charge reduces the hysteresis of the first transistor, the second transistor and the third transistor, improves the problem of afterimage and flicker of the display panel, and thus improves the effect of picture display.

[0077] For example, Figure 8 As shown. In the first transistor T1, the second transistor T2 and the third transistor T3, the back gate structure 10 is located above the substrate 13 and below the channel layer 12, and the back gate structure 10 is patterned by a mask. In the process of patterning the back gate structure 10, the patterned back gate structure 10 can only block the first transistor T1, or can block the first transistor T1, the second transistor T2 and the third transistor T3 at the same time. The mask can be a photomask. In one embodiment, as Figure 6 As shown, the first transistor T1 , the second transistor T2 and the third transistor T3 share a back gate structure.

[0078] In this embodiment, since the back gates of the first transistor, the second transistor and the third transistor receive the same signal, the first transistor, the second transistor and the third transistor share a back gate structure, which can reduce the size of the transistor and thus reduce the complexity of the pixel circuit structure.

[0079] In one embodiment, the first transistor T1, the second transistor T2 and the third transistor T3 are all P-type transistors, and in the process of resetting the first transistor T1, the second transistor T2 and the third transistor T3, the voltage of the second signal is a negative voltage. For example, the voltage of the second signal can be -4V, -4.6V, -5V, etc.

[0080] In this embodiment, since the first transistor, the second transistor and the third transistor are all P-type transistors, when the first transistor, the second transistor and the third transistor need to be reset, the voltage of the second signal is set to a negative voltage. By releasing the charges trapped in the channels of the P-type first transistor, the second transistor and the third transistor with a negative voltage, the problems of afterimage and flicker of the display panel are improved, thereby improving the effect of picture display. At the same time, by setting the type of the first transistor to be the same as the type of the second transistor and the third transistor, low-temperature polysilicon backplane technology is realized, thereby improving the effect of picture display.

[0081] In one embodiment, the first transistor T1, the second transistor T2 and the third transistor T3 are all N-type transistors, and during the process of resetting the first transistor T1, the second transistor T2 and the third transistor T3, the voltage of the second signal is a positive voltage. Exemplarily, the voltage of the second signal can be 4V, 4.6V, 5V, etc.

[0082] In this embodiment, since the first transistor, the second transistor and the third transistor are all N-type transistors, when the first transistor, the second transistor and the third transistor need to be reset, the voltage of the second signal is set to a positive voltage. By releasing the charges trapped in the channels of the N-type first transistor, the second transistor and the third transistor with a positive voltage, the problems of afterimage and flicker of the display panel are improved, thereby improving the effect of picture display. At the same time, by setting the type of the first transistor to be the same as the type of the second transistor and the third transistor, low-temperature polysilicon backplane technology is realized, thereby improving the effect of picture display.

[0083] In one embodiment, the gate of the second transistor T2 is used to couple with the first scan signal line Scan(n-1), and the gate of the third transistor T3 is used to couple with the second scan signal line Scan(n), and the first scan signal of the first scan signal line Scan(n-1) is delayed to obtain the second scan signal of the second scan signal line Scan(n). Exemplarily, the first scan signal of the first scan signal line Scan(n-1) is extended by a preset time to obtain the second scan signal of the second scan signal line Scan(n).

[0084] In this embodiment, since the data writing phase of the pixel circuit is after the initialization phase, and the second transistor and the third transistor are of the same type, the first scanning signal can drive the third transistor to operate after the delay. Since the first scanning signal is used as the second scanning signal after the delay, it is convenient to generate the second scanning signal, thereby reducing the complexity of the display panel structure.

[0085] Exemplarily, the first scan signal line Scan(n-1) may be the second scan signal line Scan(n) of the previous row of pixel circuits of the current row, which facilitates the generation of the first scan signal, thereby reducing the complexity of the display panel structure.

[0086] In one embodiment, the pixel circuit further includes a fourth transistor T4. A first end of the fourth transistor T4 is used to couple with the third signal line Vd, a second end is coupled with the first end of the first transistor T1 to form a third node N3, and a gate is used to couple with the second scan signal line Scan(n) to write data of the third signal line Vd into the gate of the first transistor T1.

[0087] In this embodiment, the data is written into the gate of the first transistor through the fourth transistor, so that the display panel displays the expected picture when the first transistor drives the light-emitting element to emit light, thereby improving the reliability of the picture display. At the same time, because the fourth transistor reuses the second scanning signal line, one array substrate gate driving circuit is reduced, thereby reducing the complexity of the display panel structure.

[0088] In one embodiment, the pixel circuit further includes a fifth transistor T5. The first end of the fifth transistor T5 is used to couple with the fourth signal line VIA, the second end is coupled with the anode of the light emitting element OLED to form a fourth node N4, and the gate is used to couple with the second scan signal line Scan(n) to initialize the light emitting element OLED.

[0089] In this embodiment, the light emitting element is initialized by the fifth transistor with the fourth signal of the fourth signal line, thereby eliminating the residual image of the light emitting element in the previous frame, thereby improving the effect of picture display. At the same time, since the fifth transistor reuses the second scanning signal line, one array substrate gate driving circuit is reduced, thereby reducing the complexity of the display panel structure.

[0090] It is understandable that the gate of the fifth transistor T5 may also be coupled to a separate scanning signal line to initialize the light emitting element OLED in a reset phase or an initialization phase.

[0091] In one embodiment, the pixel circuit further includes a sixth transistor T6 and a seventh transistor T7. The first end of the sixth transistor T6 is used to couple with the first power supply Vdd, the second end is coupled with the first end of the first transistor T1, and the gate is used to couple with the enable signal line EM. The first end of the seventh transistor T7 is coupled with the second end of the first transistor T1, the second end is coupled with the anode of the light emitting element OLED, and the gate is used to couple with the enable signal line EM. The cathode of the light emitting element OLED is used to couple with the second power supply Vss. The sixth transistor T6 and the seventh transistor T7 are used to control the first power supply Vdd and the light emitting element OLED to be turned on and off.

[0092] In this embodiment, the sixth transistor and the seventh transistor can control the on and off of the first power supply and the light-emitting element, so that the first transistor, the second transistor and the third transistor are reset to reduce the hysteresis effect, and the driving current is used to drive the light-emitting element to emit light after the influence of the threshold voltage on the driving current is eliminated, thereby improving the picture display effect.

[0093] In one embodiment, if Fig. 9 As shown, the pixel circuit further includes an eighth transistor T8. The first end of the eighth transistor T8 is coupled to the fifth signal line VIR, the second end is coupled to the first end of the first transistor T1, and the gate is coupled to the third scan signal line ScanR, for resetting the first transistor T1.

[0094] In this embodiment, on the basis of resetting the first transistor by the second signal, resetting the first transistor by the eighth transistor can further reduce the hysteresis of the first transistor, thereby improving the effect of picture display.

[0095] In one embodiment, the pixel circuit further includes a storage capacitor Cst. A first end of the storage capacitor Cst is coupled to the first power source Vdd, and a second end of the storage capacitor Cst is coupled to the gate of the first transistor T1 to adjust the voltage of the gate of the first transistor T1.

[0096] In this embodiment, since the storage capacitor has the characteristics of storing and releasing energy, the third transistor and the fourth transistor are used to adjust the gate voltage of the first transistor, which can eliminate the influence of the threshold voltage of the first transistor on the driving current of the light-emitting element to improve the picture display effect.

[0097] Exemplarily, the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 and the eighth transistor T8 are of the same type, and may all be P-type transistors or N-type transistors.

[0098] It can be understood that the types of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may not be completely the same, some are N-type transistors and some are P-type transistors.

[0099] In one embodiment, during the process of resetting the first transistor T1 , the second transistor T2 , and the third transistor T3 , the second signal is a constant voltage signal, that is, the second signal is a direct current signal.

[0100] In this embodiment, the first transistor, the second transistor and the third transistor are reset by a constant voltage signal, which reduces the complexity of generating the second signal, thereby reducing the complexity of the display panel structure.

[0101] In one embodiment, during the process of resetting the first transistor T1 , the second transistor T2 , and the third transistor T3 , the second signal is a pulse signal.

[0102] In this embodiment, the first transistor, the second transistor and the third transistor are reset by a pulse signal, and the change of the pulse can speed up the release of charge in the channels of the first transistor, the second transistor and the third transistor to reduce the hysteresis of the first transistor, the second transistor and the third transistor, thereby improving the picture display effect.

[0103] In one embodiment, during the process of resetting the first transistor T1 , the second signal is an AC signal.

[0104] In this embodiment, the first transistor is reset by an AC signal, and the change of the AC voltage can accelerate the speed of charge release in the channel of the first transistor to reduce the hysteresis of the first transistor, thereby improving the effect of picture display.

[0105] Exemplarily, when the transistor is a P-type transistor, the first end of the transistor is a source, the second end is a drain, and the gate is turned on when a first level is input, and is turned off when a second level is input. When the transistor is an N-type transistor, the first end of the transistor is a drain, the second end is a source, and the gate is turned off when a first level is input, and is turned on when a second level is input. The first level is less than the second level.

[0106] For example, Figure 6As shown, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an energy storage capacitor Cst and a light emitting element OLED. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-type transistors. The back gate of the first transistor T1 is used to couple with the second signal line VBSM. The first end of the second transistor T2 is used to couple with the first signal line VIG, the second end is coupled with the gate of the first transistor T1 to form a first node N1, the gate is used to couple with the first scan signal line Scan (n-1), and the back gate is used to couple with the second signal line VBSM. The first end of the third transistor T3 is coupled with the first node N1, the second end is coupled between the first transistor T1 and the light emitting element OLED to form a second node N2, the gate is used to couple with the second scan signal line Scan (n), and the back gate is used to couple with the second signal line VBSM. The first end of the fourth transistor T4 is used to couple with the third signal line Vd, the second end is coupled with the first end of the first transistor T1 to form a third node N3, and the gate is used to couple with the second scan signal line Scan(n). The first end of the fifth transistor T5 is used to couple with the fourth signal line VIA, the second end is coupled with the anode of the light emitting element OLED to form a fourth node N4, and the gate is used to couple with the second scan signal line Scan(n). The first end of the sixth transistor T6 is used to couple with the first power supply Vdd, the second end is coupled with the third node N3, and the gate is used to couple with the enable signal line EM. The first end of the seventh transistor T7 is coupled with the second node N2, the second end is coupled with the fourth node N4, and the gate is used to couple with the enable signal line EM. The first end of the storage capacitor Cst is used to couple with the first power supply Vdd, and the second end is coupled with the first node N1. The cathode of the light emitting element OLED is used to couple with the second power supply Vss.

[0107] An exemplary embodiment of the present disclosure further provides a driving method for a pixel circuit, which can be applied to the above-mentioned pixel circuit, for example, and the driving method for the pixel circuit includes at least one writing frame, and the execution process of the writing frame includes a data writing stage, in which the data of the third signal line is written into the gate of the first transistor. Exemplarily, in the data writing stage, the third transistor and the fourth transistor are turned on by the second scanning signal of the second scanning signal line to write the data of the third signal line into the gate of the first transistor.

[0108] Before the data writing stage, the execution process of the writing frame also includes a reset stage. In the reset stage, a second signal is input to the back gates of the first transistor, the second transistor and the third transistor through the second signal line to reset the first transistor, the second transistor and the third transistor.

[0109] In this embodiment, before writing data to the gate of the first transistor, the first transistor, the second transistor and the third transistor are reset by inputting the second signal of the back gate to quickly release the charges captured by the trap state in the channels of the first transistor, the second transistor and the third transistor. Since the first transistor, the second transistor and the third transistor are reset before the data writing stage, the first transistor, the second transistor and the third transistor have enough time to release the charges to reduce the hysteresis, thereby improving the effect of the picture display.

[0110] An exemplary embodiment of the present disclosure further provides a driving method for a pixel circuit, which can be applied to the above-mentioned pixel circuit, for example, and the driving method for the pixel circuit includes at least one writing frame, and the execution process of the writing frame includes a data writing stage, in which the data of the third signal line is written into the gate of the first transistor. Exemplarily, in the data writing stage, the third transistor and the fourth transistor are turned on by the second scanning signal of the second scanning signal line to write the data of the third signal line into the gate of the first transistor.

[0111] After the data writing stage, the execution process of the writing frame also includes a reset stage. In the reset stage, a second signal is input to the back gates of the first transistor, the second transistor and the third transistor through the second signal line to reset the first transistor, the second transistor and the third transistor.

[0112] In this embodiment, after writing data to the gate of the first transistor, the first transistor, the second transistor and the third transistor are reset by inputting the second signal of the back gate to quickly release the charges captured by the trap state in the channels of the first transistor, the second transistor and the third transistor. Since the first transistor, the second transistor and the third transistor are reset after the data writing stage, the influence of data writing on the hysteresis of the transistor is reduced, thereby improving the effect of picture display.

[0113] An exemplary embodiment of the present disclosure further provides a driving method for a pixel circuit, which can be applied to the above-mentioned pixel circuit, for example, and the driving method for the pixel circuit includes at least one writing frame, and the execution process of the writing frame includes a data writing stage, in which the data of the third signal line is written into the gate of the first transistor. Exemplarily, in the data writing stage, the third transistor and the fourth transistor are turned on by the second scanning signal of the second scanning signal line to write the data of the third signal line into the gate of the first transistor.

[0114] Before and after the data writing stage, the execution process of the write frame also includes a reset stage. In the reset stage, a second signal is input to the back gates of the first transistor, the second transistor and the third transistor through the second signal line to reset the first transistor, the second transistor and the third transistor.

[0115] In this embodiment, before and after writing data to the gate of the first transistor, the first transistor, the second transistor and the third transistor are reset by inputting the second signal of the back gate respectively, so as to quickly release the charges captured by the trap state in the channels of the first transistor, the second transistor and the third transistor. Since the first transistor is reset before and after the data writing stage respectively, the charges in the first transistor are further released to reduce the hysteresis, thereby improving the effect of the picture display.

[0116] In one embodiment, the execution process of writing a frame further includes an initialization phase executed before the data writing phase, in which the gate of the first transistor is initialized with the first signal of the first signal line. Exemplarily, in the initialization phase, the second transistor is turned on with the first scan signal of the first scan signal line, so as to initialize the gate of the first transistor with the first signal of the first signal line.

[0117] In this embodiment, the gate of the first transistor is initialized by the first signal to eliminate the residual voltage of the gate of the first transistor, thereby improving the effect of picture display. At the same time, by initializing the gate of the first transistor, the written data is prevented from being affected by the residual data of the previous frame during the data writing stage, thereby improving the reliability of picture display.

[0118] In one embodiment, the execution process of writing a frame further includes a light emitting phase executed after the data writing phase, in which the first transistor is controlled to drive the light emitting element to emit light. Exemplarily, in the light emitting phase, the sixth transistor and the seventh transistor are turned on by an enable signal of the enable signal line to control the first transistor to drive the light emitting element to emit light.

[0119] In this embodiment, by controlling the first transistor to drive the light-emitting element to emit light in the light-emitting stage after the data writing stage, the hysteresis of the first transistor, the second transistor and the third transistor is reduced, and the influence of the threshold voltage of the first transistor on the driving current of the light-emitting element is eliminated, thereby improving the picture display effect.

[0120] In one embodiment, during the data writing phase, the light emitting element is initialized by the fourth signal of the fourth signal line. Exemplarily, during the data writing phase, the fifth transistor is turned on by the second scanning signal of the second scanning signal line, and the light emitting element is initialized by the fourth signal of the fourth signal line.

[0121] In this embodiment, by initializing the light emitting element with the fourth signal during the data writing phase, the residual image of the light emitting element in the previous frame is eliminated, thereby improving the picture display effect.

[0122] In one embodiment, in the reset phase, the voltage of the second signal is the first preset voltage. In the data writing phase, the initialization phase and the light emitting phase, the voltage of the second signal is the second preset voltage.

[0123] When the first transistor, the second transistor and the third transistor are all P-type transistors, the first preset voltage is a negative voltage, and the second preset voltage is a positive voltage.

[0124] When the first transistor, the second transistor and the third transistor are all N-type transistors, the first preset voltage is a positive voltage, and the second preset voltage is a negative voltage.

[0125] In this embodiment, when the first transistor, the second transistor and the third transistor are all P-type transistors, the first transistor, the second transistor and the third transistor are reset with a negative voltage in the reset stage to release the charge in the channel of the first transistor, the second transistor and the third transistor. In the data writing stage, the initialization stage and the light emitting stage, the first transistor, the second transistor and the third transistor are stopped with a positive voltage to prevent the reset from affecting the writing of data, the gate initialization and the driving light emitting element to emit light. When the first transistor, the second transistor and the third transistor are N-type transistors, the first transistor, the second transistor and the third transistor are reset with a positive voltage in the reset stage to release the charge in the channel of the first transistor, the second transistor and the third transistor. In the data writing stage, the initialization stage and the light emitting stage, the first transistor, the second transistor and the third transistor are stopped with a negative voltage to prevent the reset from affecting the writing of data, the gate initialization and the driving light emitting element to emit light. By inputting different voltages into the back gates of the first transistor, the second transistor and the third transistor at different stages of the pixel circuit, the first transistor, the second transistor and the third transistor are reset while preventing the reset from affecting each stage, thereby improving the reliability of the screen display.

[0126] In one embodiment, when the second transistor, the third transistor, the fourth transistor and the fifth transistor are all P-type transistors,

[0127] In the initialization phase, the first scanning signal line is controlled to input the first level to the second transistor. In the reset phase, the data writing phase and the light emitting phase, the first scanning signal line is controlled to input the second level to the second transistor.

[0128] In the data writing stage, the second scanning signal line is controlled to input the first level to the third transistor, the fourth transistor and the fifth transistor. In the initialization stage, the reset stage and the light emitting stage, the second scanning signal line is controlled to input the second level to the third transistor, the fourth transistor and the fifth transistor.

[0129] In this embodiment, in the initialization stage, the first level is input to the second transistor to turn on the second transistor, and the gate of the first transistor is initialized. In the reset stage, the data writing stage and the light emitting stage, the second level is input to the second transistor to turn off the second transistor, and the gate of the first transistor is stopped to be initialized. The second transistor is controlled by the first scanning signal line in different situations, and the gate of the first transistor is initialized before the data writing stage, thereby improving the effect of the screen display. In the data writing stage, the first level is input to the third transistor, the fourth transistor and the fifth transistor to turn on the third transistor, the fourth transistor and the fifth transistor, write data to the gate of the first transistor and initialize the light emitting element. In the initialization stage, the reset stage and the light emitting stage, the second level is input to the third transistor, the fourth transistor and the fifth transistor to turn off the third transistor, the fourth transistor and the fifth transistor, stop writing data and initializing the light emitting element. The third transistor, the fourth transistor and the fifth transistor are controlled by the second scanning signal line in different situations, and data is written and the light emitting element is initialized in the data writing stage, thereby improving the effect of the screen display.

[0130] In one embodiment, when the second transistor, the third transistor, the fourth transistor and the fifth transistor are all N-type transistors,

[0131] In the initialization phase, the first scanning signal line is controlled to input the second level to the second transistor. In the reset phase, the data writing phase and the light emitting phase, the first scanning signal line is controlled to input the first level to the second transistor.

[0132] In the data writing stage, the second scanning signal line is controlled to input the second level to the third transistor, the fourth transistor and the fifth transistor. In the initialization stage, the reset stage and the light-emitting stage, the second scanning signal line is controlled to input the first level to the third transistor, the fourth transistor and the fifth transistor.

[0133] In this embodiment, in the initialization stage, the second transistor is turned on by inputting the second level to the second transistor, and the gate of the first transistor is initialized. In the reset stage, the data writing stage and the light emitting stage, the first level is input to the second transistor to disconnect the second transistor, and the gate of the first transistor is stopped to be initialized. The second transistor is controlled by the first scanning signal line in different situations, and the gate of the first transistor is initialized before the data writing stage, thereby improving the effect of the screen display. In the data writing stage, the third transistor, the fourth transistor and the fifth transistor are turned on by inputting the second level to the third transistor, the fourth transistor and the fifth transistor, data is written to the gate of the first transistor and the light emitting element is initialized. In the initialization stage, the reset stage and the light emitting stage, the third transistor, the fourth transistor and the fifth transistor are disconnected by inputting the first level to the third transistor, the fourth transistor and the fifth transistor, and the data writing and the initialization of the light emitting element are stopped. The third transistor, the fourth transistor and the fifth transistor are controlled by the second scanning signal line in different situations, and the data writing and the initialization of the light emitting element are performed in the data writing stage, thereby improving the effect of the screen display.

[0134] Exemplarily, the sixth transistor and the seventh transistor are P-type transistors. In the reset phase, the initialization phase, and the data writing phase, the control enable signal line inputs the second level to the sixth transistor and the seventh transistor. In the light emitting phase, the control enable signal line inputs the first level to the sixth transistor and the seventh transistor.

[0135] Exemplarily, the sixth transistor and the seventh transistor are N-type transistors. In the reset phase, the initialization phase, and the data writing phase, the control enable signal line inputs a first level to the sixth transistor and the seventh transistor. In the light emitting phase, the control enable signal line inputs a second level to the sixth transistor and the seventh transistor.

[0136] In one embodiment, the driving method of the pixel circuit further includes at least one holding frame after the at least one writing frame. Exemplarily, the number of the holding frames may be 3, 4, 5, etc.

[0137] In this embodiment, a hold frame is added after the write frame to hold the displayed image, eliminating the need to refresh the image again, thereby reducing the power consumption of the pixel circuit.

[0138] In one embodiment, when the second transistor, the third transistor, the fourth transistor and the fifth transistor are all P-type transistors, during the execution of the hold frame, the first scanning signal line is controlled to continuously input the second level to the second transistor, and the second scanning signal line is controlled to continuously input the second level to the third transistor, the fourth transistor and the fifth transistor.

[0139] In this embodiment, during the execution of the hold frame, the second transistor, the third transistor, the fourth transistor and the fifth transistor are maintained in the off state, thereby reducing the power consumption of the pixel circuit.

[0140] In one embodiment, when the second transistor, the third transistor, the fourth transistor and the fifth transistor are all N-type transistors, during the execution of the hold frame, the first scanning signal line is controlled to continuously input the first level to the second transistor, and the second scanning signal line is controlled to continuously input the first level to the third transistor, the fourth transistor and the fifth transistor.

[0141] In this embodiment, during the execution of the hold frame, the second transistor, the third transistor, the fourth transistor and the fifth transistor are maintained in the off state, thereby reducing the power consumption of the pixel circuit.

[0142] Exemplarily, during the execution of the hold frame, when the first transistor is a P-type transistor, the second signal of the second signal line is a negative voltage corresponding to the reset phase of the write frame. The second signal of the second signal line is a positive voltage corresponding to the initialization phase, data writing phase, and light-emitting phase of the write frame. When the first transistor is an N-type transistor, the second signal of the second signal line is a positive voltage corresponding to the reset phase of the write frame. The second signal of the second signal line is a negative voltage corresponding to the initialization phase, data writing phase, and light-emitting phase of the write frame.

[0143] Exemplarily, during the execution of the hold frame, when the sixth transistor and the seventh transistor are P-type transistors, the enable signal of the enable signal line is at a first level corresponding to the light-emitting phase of the write frame. The enable signal of the enable signal line is at a second level corresponding to the reset phase, the initialization phase, and the data writing phase of the write frame. When the sixth transistor and the seventh transistor are N-type transistors, the enable signal of the enable signal line is at a second level corresponding to the light-emitting phase of the write frame. The enable signal of the enable signal line is at a first level corresponding to the reset phase, the initialization phase, and the data writing phase of the write frame.

[0144] Exemplarily, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are P-type transistors. Figure 10-1 and Figure 10-2As shown, the driving method of the pixel circuit includes writing a frame, and the execution process of writing a frame includes a reset phase, an initialization phase, a data writing phase, a reset phase, and a light-emitting phase. In the reset phase, the second signal of the second signal line is a negative voltage, and the first scanning signal of the first scanning signal line, the second scanning signal of the second scanning signal line, and the enable signal of the enable signal line are at the second level. In the initialization phase, the second signal of the second signal line is a positive voltage, the first scanning signal of the first scanning signal line is at the first level, and the second scanning signal of the second scanning signal line and the enable signal of the enable signal line are at the second level. In the data writing phase, the second signal of the second signal line is a positive voltage, the first scanning signal of the first scanning signal line and the enable signal of the enable signal line are at the second level, and the second scanning signal of the second scanning signal line is at the first level. In the light-emitting phase, the second signal of the second signal line is a positive voltage, the first scanning signal of the first scanning signal line and the second scanning signal of the second scanning signal line are at the second level, and the enable signal of the enable signal line is at the first level. Wherein, V EM is the voltage of the enable signal line EM. Scan(n-1) is the voltage of the first scanning signal line. Scan(n) is the voltage of the second scanning signal line. BSM is the voltage of the second signal line. Data is data. Phases T1 and T4 are reset phases, phase T2 is the initialization phase, phase T3 is the data writing phase, and phase T5 is the light emitting phase. In the reset phase, the first signal can be a constant voltage signal, a pulse signal, or an AC signal.

[0145] Exemplarily, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are all P-type transistors. Fig.11 As shown, the driving method of the pixel circuit also includes maintaining a frame. During the execution of maintaining the frame, corresponding to the reset phase of the write frame, the second signal of the second signal line is a negative voltage. Corresponding to the initialization phase, the data writing phase and the light-emitting phase of the write frame, the second signal of the second signal line is a positive voltage. Corresponding to the light-emitting phase of the write frame, the enable signal of the enable signal line is a first level. Corresponding to the reset phase, the initialization phase and the data writing phase of the write frame, the enable signal of the enable signal line is a second level. Corresponding to the reset phase, the initialization phase, the data writing phase and the light-emitting phase of the write frame, the first scanning signal of the first scanning signal line and the second scanning signal of the second scanning signal line are both at a second level. Wherein, A1 is the execution process of the write frame, and A2 is the execution process of the maintain frame.

[0146] An exemplary embodiment of the present disclosure also provides a display panel, which includes the pixel circuit as described above and a first array substrate gate driving circuit, the first array substrate gate driving circuit includes a second signal line, and the first array substrate gate driving circuit is coupled to the back gates of the first transistor, the second transistor and the third transistor through the second signal line.

[0147] Exemplarily, the display panel further includes a second array substrate gate driving circuit, a third array substrate gate driving circuit, a fourth array substrate gate driving circuit, a fifth array substrate gate driving circuit, a sixth array substrate gate driving circuit, a seventh array substrate gate driving circuit and an eighth array substrate gate driving circuit. The second array substrate gate driving circuit includes a first signal line. The third array substrate gate driving circuit includes a third signal line. The fourth array substrate gate driving circuit includes a fourth signal line. The fifth array substrate gate driving circuit includes a first scan signal line. The sixth array substrate gate driving circuit includes a second scan signal line. The seventh array substrate gate driving circuit includes an enable signal line.

[0148] Exemplarily, the display panel further includes an eighth array substrate gate driving circuit. The eighth array substrate gate driving circuit includes a fifth signal line.

[0149] In one embodiment, the display panel includes a plurality of pixel circuits arranged in an array. When the second signal is a constant voltage signal, each pixel circuit corresponds to a second signal line. The second signal of the second signal line is used to reset the first transistor, the second transistor and the third transistor of each pixel circuit.

[0150] In each pixel circuit, the back gate structures 10 of each first transistor, each second transistor, and each third transistor are connected. Exemplarily, the back gate structure 10 of the first transistor, the back gate structure 10 of the second transistor, and the back gate structure 10 of the third transistor are located in the same layer of the display panel. Figure 12-1The structure of the layer where the back gate structure 10 of the first transistor, the back gate structure 10 of the second transistor and the back gate structure 10 of the third transistor are located is shown, and the back gate structures 10 of each first transistor are connected to form a mesh structure, and the back gate structures 10 of each second transistor and the back gate structures 10 of each third transistor can be connected to form a mesh structure. It can be understood that the back gate structure 10 of the first transistor, the back gate structure 10 of the second transistor and the back gate structure 10 of the third transistor can also be located in different layers of the display panel. The back gate structures 10 of the second transistor and the third transistor are similar to the back gate structure 10 of the first transistor. The mesh structure formed by the back gate structures 10 of each first transistor, the mesh structure formed by the back gate structures 10 of each second transistor and the mesh structure formed by the back gate structures 10 of each third transistor are all connected by conductive columns. The second signal line is connected to the mesh structure, so that the second signal of the second signal line resets each first transistor, the second transistor and the third transistor through the mesh structure.

[0151] In one embodiment, the display panel includes a plurality of pixel circuits arranged in an array. When the second signal is an AC signal, in order to ensure that the first transistor, the second transistor, and the third transistor in the pixel circuit can be reset row by row, each row of pixel circuits corresponds to a second signal line, and the second signal of the second signal line is used to reset the first transistor, the second transistor, and the third transistor of the corresponding row of pixel circuits.

[0152] In the pixel circuits of the same row, the back gate structures 10 of each first transistor, each second transistor, and each third transistor are connected to form a back gate structure group. The back gate structure groups corresponding to pixel circuits of different rows are separated from each other. Exemplarily, the back gate structure 10 of the first transistor, the back gate structure 10 of the second transistor, and the back gate structure 10 of the third transistor are located in the same layer of the display panel. Figure 12-2 The structure of the layer where the back gate structure 10 of the first transistor, the back gate structure 10 of the second transistor and the back gate structure 10 of the third transistor are located is shown, and the back gate structure 10 of each first transistor, the back gate structure 10 of each second transistor and the back gate structure 10 of each third transistor are connected. It can be understood that the back gate structure 10 of the first transistor, the back gate structure 10 of the second transistor and the back gate structure 10 of the third transistor can also be located in different layers of the display panel. The back gate structure 10 of the second transistor and the third transistor is similar to the back gate structure 10 of the first transistor. In the same row of pixel circuits, the structure formed by the back gate structure 10 of each first transistor, the structure formed by the back gate structure 10 of each second transistor, and the structure formed by the back gate structure 10 of each third transistor are all connected by conductive columns.

[0153] Exemplarily, the second signal is provided by a separately provided first array substrate gate driving circuit.

[0154] In one embodiment, if Figure 13-1 As shown, the first array substrate gate driving circuit corresponding to the second signal line VBSM is set to one, and is coupled to one end of the second signal line VBSM. That is, the second signal of the second signal line VBSM is provided in a single-ended driving mode, and the second signal line VBSM driving circuit in the first array substrate gate driving circuit is arranged on one side of the pixel circuit. The first scanning signal of the first scanning signal line Scan(n-1), the second scanning signal of the second scanning signal line and the enable signal of the enable signal line EM can be provided in a single-ended driving mode or in a double-ended driving mode. When the first scanning signal of the first scanning signal line Scan(n-1) is delayed to obtain the second scanning signal of the second scanning signal line Scan(n), the display panel may not include the sixth array substrate gate driving circuit. When the first scanning signal line Scan(n-1) adopts single-ended driving, the first scanning signal line Scan(n-1) driving circuit in the fifth array substrate gate driving circuit is arranged on one side of the pixel circuit. When the enable signal line EM adopts double-ended driving, the enable signal line EM driving circuit in the seventh array substrate gate driving circuit is arranged on both sides of the pixel circuit.

[0155] In this embodiment, by providing the second signal in a single-ended driving manner, the number of gate driving circuits of the array substrate is small, thereby reducing the complexity of the display panel structure.

[0156] In one embodiment, if Figure 13-2 As shown, two first array substrate gate driving circuits corresponding to the second signal line VBSM are provided, and are respectively coupled to the two ends of the corresponding second signal line VBSM. That is, the second signal of the second signal line is provided in a double-ended driving mode, and the second signal line VBSM driving circuit in the first array substrate gate driving circuit is arranged on both sides of the pixel circuit. The first scanning signal of the first scanning signal line Scan(n-1), the second scanning signal of the second scanning signal line and the enable signal of the enable signal line EM can be provided in a single-ended driving mode or in a double-ended driving mode. When the first scanning signal of the first scanning signal line Scan(n-1) is delayed to obtain the second scanning signal of the second scanning signal line Scan(n), the display panel may not include the sixth array substrate gate driving circuit. When the first scanning signal line Scan(n-1) adopts double-ended driving, the first scanning signal line Scan(n-1) driving circuit in the fifth array substrate gate driving circuit is arranged on both sides of the pixel circuit. When the enable signal line EM adopts double-ended driving, the enable signal line EM driving circuit in the seventh array substrate gate driving circuit is arranged on both sides of the pixel circuit.

[0157] In this embodiment, by providing the second signal in a double-end driving manner, the voltage of the second signal is stable, thereby improving the reliability of the image display of the display panel.

[0158] In an exemplary embodiment, an electronic device is provided, and the electronic device is, for example, a mobile phone, a laptop computer, a tablet computer, a wearable device, etc.

[0159] refer to Fig.14 As shown, electronic device 400 may include one or more of the following components: a processing component 402 , a memory 404 , a power component 406 , a multimedia component 408 , an audio component 410 , an input / output (I / O) interface 412 , a sensor component 414 , and a communication component 416 .

[0160] The processing component 402 generally controls the overall operation of the electronic device 400, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 402 may include one or more modules to facilitate the interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate the interaction between the multimedia component 408 and the processing component 402.

[0161] The memory 404 is configured to store various types of data to support operations on the electronic device 400. Examples of such data include instructions for any application or method operating on the electronic device 400, contact data, phone book data, messages, pictures, videos, etc. The memory 404 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0162] The power supply component 406 provides power to the various components of the electronic device 400. The power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 400.

[0163] The multimedia component 408 includes a display panel that provides an output interface between the electronic device 400 and the user. In some embodiments, the display panel may include a liquid crystal display (LCD) and a touch panel (TP). If the display panel includes a touch panel, the display panel may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 408 includes a front camera module and / or a rear camera module. When the electronic device 400 is in an operating mode, such as a shooting mode or a video mode, the front camera module and / or the rear camera module may receive external multimedia data. Each front camera module and the rear camera module may be a fixed optical lens system or have a focal length and optical zoom capability. Among them, the screen includes a display panel as described above. When the first transistor, the second transistor, and the third transistor are reset through the back gate with a second signal through the pixel circuit in the display panel, the charge trapped in the first transistor, the second transistor, and the third transistor channel can be quickly released. The rapid release of the charge reduces the hysteresis of the first transistor, the second transistor and the third transistor, improves the problems of afterimage and flicker of the display panel, and thus improves the effect of picture display.

[0164] The audio component 410 is configured to output and / or input audio signals. For example, the audio component 410 includes a microphone (MIC), and when the electronic device 400 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 404 or sent via the communication component 416. In some embodiments, the audio component 410 also includes a speaker for outputting audio signals.

[0165] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0166] The sensor assembly 414 includes one or more sensors for providing various aspects of status assessment for the electronic device 400. For example, the sensor assembly 414 can detect the open / closed state of the electronic device 400, the relative positioning of components, such as the display and keypad of the electronic device 400, and the sensor assembly 414 can also detect the position change of the electronic device 400 or a component of the electronic device 400, the presence or absence of user contact with the electronic device 400, the orientation or acceleration / deceleration of the electronic device 400, and the temperature change of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 414 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0167] The communication component 416 is configured to facilitate wired or wireless communication between the electronic device 400 and other terminals. The electronic device 400 can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G, 5G, or a combination thereof. In an exemplary embodiment, the communication component 416 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 416 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0168] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing terminals (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to perform the above-described methods.

[0169] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, and the above instructions can be executed by the processor 420 of the electronic device 400 to complete the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a tape, a floppy disk, and an optical data storage terminal. When the instructions in the storage medium are executed by the processor of the terminal, the terminal is enabled to perform the method shown in the above embodiment.

[0170] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0171] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0172] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A pixel circuit, characterized in that: The pixel circuit comprises: Light emitting element; A first transistor, the first transistor having a back gate structure, the first transistor being coupled to the light emitting element, and the first transistor being used to drive the light emitting element to emit light; a second transistor, the second transistor having a back-gate structure, a first end of the second transistor being used to couple with a first signal line, a second end of the second transistor being coupled with a gate of the first transistor to form a first node, and the second transistor being used to initialize the gate of the first transistor; a third transistor, the third transistor having a back-gate structure, a first end of the third transistor coupled to the first node, and a second end of the third transistor coupled between the first transistor and the light-emitting element; The back gates formed by the back gate structures of the first transistor, the second transistor and the third transistor are all used to couple with a second signal line, and the second signal of the second signal line is used to reset the first transistor, the second transistor and the third transistor.

2. The pixel circuit according to claim 1, characterized in that: The first transistor, the second transistor and the third transistor share a back gate structure.

3. The pixel circuit according to claim 1, characterized in that: The first transistor, the second transistor and the third transistor are all P-type transistors, and in the process of resetting the first transistor, the second transistor and the third transistor, the voltage of the second signal is a negative voltage; or, The first transistor, the second transistor and the third transistor are all N-type transistors. During the process of resetting the first transistor, the second transistor and the third transistor, the voltage of the second signal is a positive voltage.

4. The pixel circuit according to claim 1, characterized in that: The gate of the second transistor is used to couple to the first scan signal line, and the gate of the third transistor is used to couple to the second scan signal line.

5. The pixel circuit according to claim 4, characterized in that: The pixel circuit further includes: A fourth transistor, wherein the first end of the fourth transistor is used to couple with the third signal line, the second end of the fourth transistor is coupled with the first end of the first transistor, the gate of the fourth transistor is used to couple with the second scanning signal line, and the fourth transistor is used to write the data of the third signal line into the gate of the first transistor.

6. The pixel circuit according to claim 4, characterized in that: The pixel circuit further includes: A fifth transistor, wherein the first end of the fifth transistor is used to couple with the fourth signal line, the second end of the fifth transistor is coupled with the anode of the light-emitting element, the gate of the fifth transistor is used to couple with the second scanning signal line, and the fifth transistor is used to initialize the light-emitting element.

7. The pixel circuit according to any one of claims 1 to 6, characterized in that: The pixel circuit further includes: a sixth transistor, wherein a first terminal of the sixth transistor is used to be coupled to a first power source, and a second terminal of the sixth transistor is coupled to a first terminal of the first transistor; a seventh transistor, wherein a first terminal of the seventh transistor is coupled to the second terminal of the first transistor, and a second terminal of the seventh transistor is coupled to the anode of the light emitting element; The sixth transistor and the seventh transistor are used to control the first power source and the light-emitting element to be turned on and off.

8. The pixel circuit according to any one of claims 1 to 6, characterized in that: The pixel circuit further includes: A storage capacitor, wherein a first end of the storage capacitor is used to couple to a first power source, a second end of the storage capacitor is coupled to the gate of the first transistor, and the storage capacitor is used to adjust the voltage of the gate of the first transistor.

9. The pixel circuit according to any one of claims 1 to 6, characterized in that: In the process of resetting the first transistor, the second transistor and the third transistor, the second signal is a constant voltage signal; or, the second signal is a pulse signal; or, the second signal is an alternating current signal.

10. A method for driving a pixel circuit, characterized in that: The driving method of the pixel circuit includes at least one writing frame, and the execution process of the writing frame includes a data writing stage, in which the data of the third signal line is written into the gate of the first transistor; Before the data writing stage and / or after the data writing stage, the execution process of the writing frame also includes a reset stage. In the reset stage, a second signal is input to the back gates of the first transistor, the second transistor and the third transistor through a second signal line to reset the first transistor, the second transistor and the third transistor.

11. The driving method of the pixel circuit according to claim 10, characterized in that: The execution process of the write frame also includes an initialization phase executed before the data write phase and a light emitting phase executed after the data write phase, in which the voltage of the second signal is a first preset voltage during the reset phase, and in which the voltage of the second signal is a second preset voltage during the data write phase, the initialization phase and the light emitting phase; When the first transistor, the second transistor and the third transistor are all P-type transistors, the first preset voltage is a negative voltage, and the second preset voltage is a positive voltage; When the first transistor, the second transistor, and the third transistor are all N-type transistors, the first preset voltage is a positive voltage, and the second preset voltage is a negative voltage.

12. The driving method of the pixel circuit according to claim 10, characterized in that: When the second transistor, the third transistor, the fourth transistor and the fifth transistor are all P-type transistors, In the initialization phase, the first scanning signal line is controlled to input a first level to the second transistor, and in the reset phase, the data writing phase and the light emitting phase, the first scanning signal line is controlled to input a second level to the second transistor; In the data writing stage, the second scanning signal line is controlled to input the first level to the third transistor, the fourth transistor and the fifth transistor, and in the initialization stage, the reset stage and the light emitting stage, the second scanning signal line is controlled to input the second level to the third transistor, the fourth transistor and the fifth transistor; or When the second transistor, the third transistor, the fourth transistor and the fifth transistor are all N-type transistors, In the initialization phase, the first scanning signal line is controlled to input the second level to the second transistor, and in the reset phase, the data writing phase and the light emitting phase, the first scanning signal line is controlled to input the first level to the second transistor; In the data writing stage, the second scanning signal line is controlled to input the second level to the third transistor, the fourth transistor and the fifth transistor. In the initialization stage, the reset stage and the light-emitting stage, the second scanning signal line is controlled to input the first level to the third transistor, the fourth transistor and the fifth transistor.

13. The driving method of a pixel circuit according to any one of claims 10 to 12, characterized in that: The driving method of the pixel circuit further includes at least one holding frame located after at least one of the writing frames.

14. The driving method of the pixel circuit according to claim 13, characterized in that: When the second transistor, the third transistor, the fourth transistor and the fifth transistor are all P-type transistors, during the execution of the hold frame, the first scanning signal line is controlled to continuously input the second level to the second transistor, and the second scanning signal line is controlled to continuously input the second level to the third transistor, the fourth transistor and the fifth transistor; When the second transistor, the third transistor, the fourth transistor and the fifth transistor are all N-type transistors, during the execution of the hold frame, the first scan signal line is controlled to continuously input the first level to the second transistor, and the second scan signal line is controlled to continuously input the first level to the third transistor, the fourth transistor and the fifth transistor.

15. A display panel, characterized in that: The display panel includes a pixel circuit as described in any one of claims 1 to 9 and a first array substrate gate driving circuit, the first array substrate gate driving circuit includes the second signal line, and the first array substrate gate driving circuit is coupled to the back gates of the first transistor, the second transistor and the third transistor through the second signal line.

16. The display panel according to claim 15, characterized in that: The display panel comprises a plurality of pixel circuits arranged in an array, each row of the pixel circuits corresponds to one second signal line, and the second signal of the second signal line is used to reset the first transistor, the second transistor and the third transistor of the pixel circuit in the corresponding row; Among them, in the pixel circuits in the same row, the back gate structures of each of the first transistors, each of the second transistors and each of the third transistors are connected to form a back gate structure group; the back gate structure groups corresponding to the pixel circuits in different rows are separated from each other.

17. An electronic device, characterized in that: The electronic device comprises the display panel according to claim 15 or 16.

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