A PCIe switch

Abstract

The present application discloses a PCIe switch, including a port controller, which processes the message input or output of the switch according to a preset first data processing flow and then transmits it; a switching core, which is connected to the port controller and processes the message transmitted by the port controller according to a preset second data processing flow, so that the switching core performs routing services and switching services based on the processing results of the second data processing flow; a data transmission optimization module is connected between the port controller and the switching core, so that when the port controller executes the first data processing flow, the processing flow of the first data processing flow is transferred to the data transmission optimization module for execution, and when the switching core executes the second data processing flow, the processing flow of the second data processing flow is transferred to the data transmission optimization module for execution. The solution of the present application can share the service intensity of the port controller and the switching core based on the data transmission optimization module, which is conducive to accelerating the convergence rate of the project.

Description

Technical Field

[0001] The present application relates to the technical field of communication circuit design, and in particular to a PCIe switch. Background Art

[0002] With the development of PCIe (Peripheral Component Interconnect Express) technology, it is a general trend to interconnect multiple devices between boards through the PCIe protocol for data forwarding, and this technology requires the use of PCIe switches.

[0003] Figure 1 The overall structure diagram of a data interaction system of a PCIe switch is shown as an example of the prior art. Figure 1 As shown, in the PCIe switch design of the prior art, the switch's services are mainly divided into a port controller (including upstream ports and downstream ports) and a switching core. In order to meet the needs of its own services, some functional adaptation modifications will be made to the port controller. At the same time, some services related to application layer functions, such as multicast, message filtering, error packet processing, error information registration, message routing, message arbitration, sorting rules, etc., will be implemented in the switching core.

[0004] However, in actual application, the process of adapting and modifying the function of the port controller in the PCIe switch of the prior art easily leads to a long verification convergence time of the port controller IP. At the same time, since the business volume of the switching core is too bloated, the logic volume of the entire business unit is also large, which makes it difficult to converge the entire business and affects the convergence rate of the project. Summary of the invention

[0005] To solve the above technical problems, an embodiment of the present application provides a PCIe switch.

[0006] The present application provides a PCIe switch, comprising: a port controller, which processes messages input to or output from the switch according to a preset first data processing flow and then transmits them; a switching core, which is connected to the port controller and processes the messages transmitted by the port controller according to a preset second data processing flow, so that the switching core performs routing services and switching services based on the processing results of the second data processing flow; a data transmission optimization module is connected between the port controller and the switching core, so that when the port controller executes the first data processing flow, the processing flow of the first data processing flow is transferred to the data transmission optimization module for execution, and when the switching core executes the second data processing flow, the processing flow of the second data processing flow is transferred to the data transmission optimization module for execution.

[0007] In some embodiments of the present application, based on the above technical solution, the data transmission optimization module includes a receiving module and a sending module, the receiving module and the sending module are used to execute the first data processing flow, and the receiving module and the sending module are used to execute the second data processing flow, and the receiving module and the sending module are used to perform message filtering processing, error processing, cross-clock domain processing and bandwidth switching processing on the message input into the data transmission optimization module according to the receiving module; and the message filtering processing, error processing, cross-clock domain processing and bandwidth switching processing are performed on the message output from the data transmission optimization module according to the sending module; wherein, the message filtering processing is used to filter the messages that are not related to the business requirements according to the acquired business requirements; the error processing is used to process the message errors corresponding to the business requirements; the cross-clock domain processing is used to coordinate the transmission rates between different transmission ports; and the bandwidth switching processing is used to coordinate the bandwidths between different transmission ports.

[0008] In some embodiments of the present application, based on the above technical solution, the data transmission optimization module also includes a cache unit and a clock domain asynchronous processing unit, and the coordination of transmission rates between different transmission ports includes: when the switching core or the port controller reads the message through the data transmission optimization module, delay processing of the message reading is performed based on the clock domain asynchronous processing unit, and cache processing of the message is performed based on the cache unit to coordinate the transmission rates between different transmission ports.

[0009] In some embodiments of the present application, based on the above technical solution, the cache processing of the message performed based on the cache unit includes: obtaining the first clock frequency of the port controller and the second clock frequency of the switching core; calculating the difference between the first clock frequency and the second clock frequency, and calculating the ratio of the difference to the second clock frequency to obtain the cache length of the message according to the ratio; controlling the cache unit to perform cache processing of the message according to the cache length.

[0010] In some embodiments of the present application, based on the above technical solution, filtering messages that are not related to the business needs according to the acquired business needs includes: obtaining the current mode of the switch port; if the current mode is a non-transparent bridge port, performing message filtering to retain target messages, and the target messages include at least one of a storage type message without lock, an atomic operation packet, and a completion packet without lock; if the current mode is a transparent bridge port, performing corresponding message filtering according to the business needs.

[0011] In some embodiments of the present application, based on the above technical solution, the processing of the message error corresponding to the business demand includes: obtaining the current mode of the switch port; if the current mode is a transparent bridge port and the end flag signal in the message is not detected, a new end flag signal is generated, and the new end flag signal is output with the message, and the error indicating that the message has a missing end flag is registered in a preset error record.

[0012] In some embodiments of the present application, based on the above technical solution, the processing of the message error corresponding to the business demand includes: obtaining the current state of the switch port; if the current state of the switch port is about to be reset or the clock is about to be shut down or about to enter a low power consumption state, and the message of the port has not been received or sent when the preset timeout mechanism is triggered, an end flag signal is generated, and the reception or sending of the message is stopped, and a message invalid flag signal is generated and sent to the switching core; the switching core performs a silent packet loss operation on the message that has a reception timeout or a sending timeout, and registers the error indicating that the message has a reception timeout or a sending timeout in a preset error record.

[0013] In some embodiments of the present application, based on the above technical solution, the processing of the message error corresponding to the business demand includes: obtaining the message type received by the receiving module; if the message type cannot be received by default at the current port, performing a silent discard operation on the message that cannot be received by default, and registering an error indicating that the message cannot be received by default in a preset error record.

[0014] In some embodiments of the present application, based on the above technical solution, the receiving module coordinates the bandwidth between different transmission ports for the message input into the data transmission optimization module, including: when the switching core reads the message based on the receiving module, judging the current number of port links, and screening one by one according to the number of port links to obtain the target port link with the maximum supported configuration among multiple port links; obtaining the number of clock cycles of the current message; if the number of clock cycles is multiple, obtaining the number of bytes of valid data in each clock cycle, and splicing the bytes of valid data in multiple clock cycles according to the maximum supported configuration of the target port link, and transmitting the spliced ​​message; if the current message has only 1 clock cycle, transmitting the message directly.

[0015] In some embodiments of the present application, based on the above technical solution, the sending module coordinates the bandwidth between different transmission ports for the message output from the data transmission optimization module, including: when the switching core reads back the message based on the sending module, the data output by the switching core is cached according to a preset maximum packet length, the cached message is read, and the message is output according to the maximum packet length.

[0016] In the technical solution of the embodiment of the present application, the above invention content can at least bring the following beneficial effects:

[0017] In the process of executing data exchange business processing according to the PCIe switch, the present application transfers the first data processing flow that needs to be executed by the port controller and the second data processing flow that needs to be executed by the switching core to the data transmission optimization module for processing, thereby reducing the business processing burden of the port controller and the switching core, and thus helping the PCIe switch to accelerate the overall convergence rate of the project during business processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0019] Figure 1 The present invention is a schematic diagram showing the overall structure of a data interaction system of a PCIe switch exemplarily shown in the prior art.

[0020] Figure 2 The present invention is a schematic diagram of the overall structure of a data interaction system of a PCIe switch shown in an exemplary embodiment of the present application.

[0021] Figure 3 This is a flowchart of the internal business processing of the data transmission optimization module shown in the exemplary embodiment of the present application.

[0022] Figure 4 A business process flow chart of cross-clock domain processing shown in an exemplary embodiment of the present application.

[0023] Figure 5 This is a schematic diagram of a port data buffering process at different clock frequencies according to an exemplary embodiment of the present application.

[0024] Figure 6 This is a business process flow chart of message filtering processing shown in an exemplary embodiment of the present application.

[0025] Figure 7This is a business process flow chart of error handling shown in an exemplary embodiment of the present application.

[0026] Figure 8 This is a business process flow chart of error handling shown in another exemplary embodiment of the present application.

[0027] Fig. 9 This is a business process flow chart of error handling shown as another exemplary embodiment of the present application.

[0028] Fig.10 This is a business process flow chart of bandwidth switching according to an exemplary embodiment of the present application.

[0029] Fig.11 A business processing framework diagram of bandwidth switching processing shown in an exemplary embodiment of the present application.

[0030] The following explanations are given for the multiple symbols in the accompanying drawings: inf represents a data transmission optimization module; arb represents an arbitrator; and cpl represents a completion packet without data. DETAILED DESCRIPTION

[0031] In order to make the purpose and implementation method of the present application clearer, the exemplary implementation method of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0032] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0033] The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances.

[0034] The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0035] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0036] Since the existing port controller and switching core in the PCIe switch have relatively complex logic design and poor timing convergence, resulting in a large delay in overall data transmission, in order to solve this problem, Figure 2 The overall structure diagram of a data interaction system of a PCIe switch shown in the exemplary embodiment of the present application. Figure 2 As shown, the present application provides a PCIe switch, which mainly includes business units such as a port controller, a data transmission optimization module, and a switching core; so as to share part of the business of the port controller and the switching core through the data transmission optimization module.

[0037] The PCIe switch disclosed in the present application may include a port controller.

[0038] When in use, the port controller processes the message input or output from the switch according to a preset first data processing flow and then transmits it.

[0039] The PCIe switch disclosed in the present application may also include a switching core, which is connected to the port controller.

[0040] When in use, the switching core processes the message transmitted by the port controller according to the preset second data processing flow, so that the switching core performs routing services and switching services based on the processing result of the second data processing flow.

[0041] The PCIe switch disclosed in the present application may also include a data transmission optimization module. The data transmission optimization module is connected between the port controller and the switch core.

[0042] When in use, when the port controller executes the first data processing flow, the processing flow of the first data processing flow is transferred to the data transmission optimization module for execution; and when the switching core executes the second data processing flow, the processing flow of the second data processing flow is transferred to the data transmission optimization module for execution.

[0043] It should be noted that if Figure 2 As shown in the figure, inf represents a data transmission optimization module, and different data transmission optimization modules are connected between the upstream port of the port controller and the switching core, and between the downstream port of the port controller and the switching core.

[0044] Specifically, the port controller mainly includes an upstream port and a downstream port, wherein the upstream port refers to the upward port of the topological structure, for example, the port connected to the Switch upward, and there can only be one upstream port in the device corresponding to the PCIe switch. Contrary to the upstream port in the topological sense, there can be several downstream ports in the device corresponding to the PCIe switch. The embodiment of the present application uses one upstream port and two downstream ports as an exemplary illustration. Since the port controller has at least one upstream port and one downstream port, in the PCIe switch of the present application, the number of data transmission optimization modules is at least two.

[0045] It should be noted that the PCIe switch port controller is a key component in the PCIe switch, responsible for managing and controlling the data transmission between the switch and the PCIe device. The controller communicates with the device through the PCIe bus to achieve fast and reliable data transmission.

[0046] Specifically, the PCIe switch port controller of the present application is responsible for controlling the data transmission process, including the sending, receiving and forwarding of data. It ensures that data is transmitted in the correct order and format on the PCIe bus, thereby achieving effective communication between devices. When a PCIe device is connected to the switch, the port controller identifies the type and configuration of the device and allocates corresponding resources to it. In addition, it monitors the status of the device to ensure the normal operation of the device. During the data transmission process, the port controller detects possible errors, such as data loss, corruption or transmission timeout. Once an error is detected, it immediately takes measures to recover to ensure the integrity and reliability of data transmission.

[0047] The switching core of the PCIe switch for this application is the core processing unit inside the switch, which is responsible for managing and coordinating data transmission between all PCIe ports. Through the switching core, the PCIe switch can convert the PCIe channels provided by the CPU and motherboard chipset into more PCIe expansion interfaces, thereby supporting the connection of more PCIe devices.

[0048] Specifically, the switching core can forward data from one PCIe port to another PCIe port according to the destination address of the data packet to achieve data transmission between multiple devices. When multiple devices need to transmit data at the same time, the switching core will perform flow control to ensure that each device can obtain appropriate bandwidth to avoid data congestion and transmission delays. In some cases, the switching core also supports protocol conversion between different PCIe versions and rates, such as conversion between PCIe 4.0 and PCIe 5.0, to meet the connection requirements of different devices.

[0049] Based on this, when the port controller of the present application processes the message of the input or output switch according to the first data processing flow, for example, the first data processing flow may include adding certain message filtering rules, adding error processing, etc. The first data processing flow of the present application is exemplarily described by message filtering processing, error processing, cross-clock domain processing and bandwidth switching processing, and the order of the various service processing flows is not specifically limited.

[0050] Similarly, the switching core of the present application adapts the internal business requirements of the switching core for the second data processing flow, which is similar to the first data processing flow and will not be repeated here.

[0051] In actual use, in order to meet the business needs of the switch itself, many functional adaptation modifications will be made to the port controller; some services related to application layer functions will be placed in the switching core; this will easily lead to a long verification convergence time for the port controller IP, and will also cause the switching core to have too much business volume, making the entire business unit logic huge, making the entire business convergence very difficult.

[0052] Based on this, the present application sets up an intermediate processing module, namely, a data transmission optimization module, between the port controller and the switching core, so that when the port controller executes the first data processing process, the processing flow of the first data processing process is transferred to the data transmission optimization module for execution, and when the switching core executes the second data processing process, the processing flow of the second data processing process is transferred to the data transmission optimization module for execution.

[0053] Through the above implementation, in the business processing process of data exchange according to the PCIe switch, the first data processing process that needs to be executed by the port controller and the second data processing process that needs to be executed by the switching core are respectively transferred to the data transmission optimization module for processing, thereby reducing the business processing burden of the port controller and the switching core, which is beneficial for the PCIe switch to accelerate the overall convergence rate of the project during business processing.

[0054] In some embodiments of the present application, based on the above technical solution, Figure 3 This is a flowchart of the internal business processing of the data transmission optimization module shown in the exemplary embodiment of this application. Figure 3 As shown, the data transmission optimization module of the present application may include a receiving module and a sending module, wherein the receiving module and the sending module may be used to execute a first data processing flow, and the receiving module and the sending module may also be used to execute a second data processing flow.

[0055] When executing the first data processing flow and executing the second data processing flow, performing message filtering processing, error processing, cross-clock domain processing and bandwidth switching processing on the message input to the data transmission optimization module according to the receiving module;

[0056] And according to the sending module, the message of the output data transmission optimization module is subjected to message filtering processing, error processing, cross-clock domain processing and bandwidth switching processing;

[0057] Among them, message filtering processing is used to filter messages that are not related to business needs based on the obtained business needs; error processing is used to handle message errors corresponding to business needs; cross-clock domain processing is used to coordinate the transmission rate between different transmission ports; bandwidth switching processing is used to coordinate the bandwidth between different transmission ports.

[0058] Specifically, for the message filtering and processing service, the receiving module mainly receives data from the external controller, and first performs message filtering to filter out packets that are not needed in the corresponding service. For example, if the port currently supports the sending and receiving of atomic operation packets, but the actual service does not use atomic operation at all, then it is necessary to filter out the atomic operation packets on the receiving side of the port; for another example, if the current port is a downstream port, and the configuration packet is a message for the upstream port, the receiving end needs to shield the reception of the configuration packet in order to filter out the configuration packet.

[0059] For error handling services, for example, messages of transparent bridge ports can be error handled and error information registered based on the technical solution of the present application.

[0060] Among them, it should be noted that a transparent bridge means that all devices on its secondary side are transparent to the main system on the primary side, that is, the main system can directly configure and control the devices on the secondary side without going through an additional intermediate layer or translation mechanism. The transparent bridge allows data to flow freely between the primary and secondary sides while maintaining the pass-through mode of the address without address translation. Transparent bridges are often used for expansion of the PCIe bus, especially when it is necessary to increase the number of loads or match PCIe bus segments with different operating frequencies, bus widths or voltages. Through a transparent bridge, multiple PCIe bus segments can be connected together to form a larger PCIe network while maintaining consistency in data communication and configuration control between the bus segments.

[0061] Compared with non-transparent bridges, the main difference of transparent bridges is the way addresses are passed and the configuration control of devices. Non-transparent bridges are usually used for embedded intelligent I / O boards. They connect two independent processor domains and allow the local processor on the secondary side to independently configure and control its subsystems. Transparent bridges require the host system on the primary side to have full control over the devices on the secondary side, and the addresses are directly passed between the primary and secondary sides.

[0062] For example, if the message at the receiving end does not have an end flag signal, the receiving module will generate a new end flag signal along with the message output and register it in the message end flag missing error.

[0063] For another example, if the current port is about to be reset, or the clock is about to be shut down, or it is about to enter a low-power state, but the message of the current port has not been received until the timeout mechanism is triggered; the receiving module will generate an end flag signal, and a message invalid flag signal to the switching core, and the switching core will perform a silent packet loss operation, and the receiving module will register a timeout error.

[0064] For another example, for some message packets, such as ltr (Latency Tolerance Reporting) or obff (Optimized Buffer Flush and Fill), the current port cannot receive them but receives them. The receiving module needs to perform a silent discard operation and register error status information.

[0065] For cross-clock domain processing services, since the ports of the PCIe controller may operate in different rate modes, cross-clock domain processing is required in the data receiving module to synchronize the data of the current port to the clock domain where the switching core is located.

[0066] For bandwidth switching processing services, since the link widths of various controller ports are different, and in order to ensure that the switching core continues to flow during data routing and switching, wide switching operations are required.

[0067] In some embodiments of the present application, based on the above technical solution, the sending module may include three channels (channel 0 receives non-forwarding type packets output by the switching core, channel 1 receives forwarding type packets output by the switching core, and channel 2 receives completion packets output by the switching core). Cross-clock domain processing requires transparent port message filtering, error handling operations are completed, and then bandwidth switching is performed to give the message to the controller.

[0068] In some embodiments of the present application, based on the above technical solution, the data transmission optimization module may further include a cache unit and a clock domain asynchronous processing unit.

[0069] When coordinating the transmission rates between different transmission ports, the technical solution of the present application may at least include the following execution steps:

[0070] When the switching core or port controller reads the message through the data transmission optimization module, the clock domain asynchronous processing unit performs delay processing of the message reading, and the cache unit performs cache processing of the message to coordinate the transmission rate between different transmission ports.

[0071] Specifically, the embodiment is described. When the switching core or port controller reads the message through the data transmission optimization module, if the transmission rates of different ports are different, the data transmission rate can be reduced by delay processing, or the data transmission rate can be increased by advance caching to adapt the transmission rate of the corresponding port.

[0072] It should be noted that the cache unit is a key component for achieving efficient data transmission and flow control in PCIe switches. In PCIe switches, the transaction layer cache is mainly used to store and forward TLPs. These TLPs may include memory read and write requests, IO requests, configuration requests, and messages. The transaction layer cache needs to ensure that the Headerbuffer and Data buffer at the receiving end have enough space to receive data before sending TLPs. The data link layer cache is mainly used to store DLLPs (DataLink Layer Packets) and perform error detection and correction. When an error occurs in the data packet during transmission, the data link layer will use the data in the cache to resend or perform other error handling operations.

[0073] At the same time, PCIe uses an embedded clock, and there are two clock domains at the receiving end. Through elastic buffering, data conversion between these two clock domains can be achieved. Due to the error of crystal oscillators or other frequency generators, the PCIe specification allows a certain frequency error range. With the help of elastic buffering, the influence of link frequency error can be eliminated by deleting or inserting SKP Ordered Set (a special control character sequence).

[0074] In addition, the clock domain asynchronous processing unit can be a FIFO (First In First Out), a first-in-first-out data structure that can be used to process data transmission between different clock domains. The asynchronous FIFO has independent read and write clocks, which can realize cross-clock domain transmission of data. When data is transmitted from one clock domain to another, the data may not be directly transmitted due to the difference in clock frequency and phase. At this time, the asynchronous FIFO can also be directly used as a data buffer to store data from one clock domain and transmit it to another clock domain at an appropriate time. The data transmission between different clock domains is processed by the asynchronous FIFO, thereby ensuring the correctness and integrity of the data. At the same time, in the PCIe switch, the asynchronous FIFO can also be directly used for flow control. By adjusting the read and write rate of the FIFO, the data transmission flow can be balanced to prevent data congestion or loss.

[0075] Based on the above technical solution, when receiving data, the receiving end can perform cache processing, cross-clock domain processing, and bandwidth switching processing in advance, thereby reducing the business complexity of the switching core, allowing the switching core receiving module to focus more on processing routing and data exchange, reducing the pressure of back-end layout and routing and the risk of timing convergence, and also reducing the difficulty of version release during FPGA prototype verification.

[0076] After completing the cross-clock domain processing, the sending end filters the message rules and handles errors, which can effectively share the business intensity of the switching core output port and allow the switching core output port to focus more on forwarding messages from different ports; and the message caching and bandwidth switching processing at the sending end can effectively avoid controller jams caused by bubble problems.

[0077] In some embodiments of the present application, based on the above technical solution, Figure 4 FIG. 1 is a flow chart of a cross-clock domain service process for an exemplary embodiment of the present application. Figure 4 As shown, when the cache processing of the message is performed based on the cache unit, the technical solution of the present application may at least include the following execution steps:

[0078] Acquire a first clock frequency of the port controller and a second clock frequency of the switch core;

[0079] Calculating a difference between the first clock frequency and the second clock frequency, and calculating a ratio of the difference to the second clock frequency, so as to obtain a buffer length of the message according to the ratio;

[0080] The control cache unit performs cache processing of the message according to the cache length.

[0081] Figure 5 FIG. 1 is a schematic diagram of a port data buffering process at different clock frequencies shown in an exemplary embodiment of the present application. Figure 5 As shown, it is explained by way of example, assuming that the current port is working at the maximum bandwidth, if the clock frequency of the switching core is 1000MHz, the clock frequency of the PCIe controller 0 is 500MHz, and the clock frequency of the PCIe controller 1 is 250MHz; then the inf0 receiving module must store 50% of the message length before allowing the switching core to read the message, so as to avoid the situation where the switching core reads empty due to the too fast rate; when inf0 reads back data from the switching core, since it is an operation from the fast clock domain to the slow clock domain, it only needs to wait until the inf0 sending module cache is full and then back pressure the switching core; similarly, the inf1 receiving module must store 75% of the message length before avoiding the situation where the switching core reads empty due to the too fast rate; the inf1 sending module cache is full and then back pressure the switching core. It should be noted that, in this embodiment, inf0 and inf1 represent different data transmission optimization modules.

[0082] In some embodiments of the present application, based on the above technical solution, Figure 6 This is a business process flow chart of message filtering processing shown in an exemplary embodiment of the present application. Figure 6 As shown, when filtering messages irrelevant to the business requirements according to the acquired business requirements, the technical solution of the present application may at least include the following execution steps:

[0083] Get the current mode of the switch port;

[0084] If the current mode is a non-transparent bridge port, performing message filtering to retain target messages, the target messages including at least one of a storage type message without a lock, an atomic operation packet, and a completion packet without a lock;

[0085] If the current mode is a transparent bridge port, corresponding message filtering is performed according to business requirements.

[0086] Specifically, in the message filtering process of the present application, the changes to the PCIe controller IP module can be minimized as much as possible, reducing the functional risks introduced by the changes to the PCIe controller; the messages to be filtered can also be flexibly selected according to current business needs; according to the current mode selection, if it is NTB mode, that is, non-transparent bridge port mode, the messages that need to be filtered are memory type messages without lock, atomic operation packets, and completion packets without lock; for non-NTB mode, that is, transparent port mode, messages can be filtered according to actual business needs.

[0087] In order to clearly explain the message filtering process in the technical solution of the present application, an exemplary description is given, and the filtering processing rules of multiple configuration parameters in the message are respectively illustrated here. Among them, the exemplary parameters and the corresponding functions of each parameter are described as follows:

[0088] mwr32 / 64 indicates a write operation with a 32 / 64-bit address; mrd32 / 64 indicates a read operation with a 32 / 64-bit address; mrdlk indicates a read operation with a lock; iowr indicates an io write operation; iord indicates an io read operation; cfgwr0 indicates configuration type0 write; cfgwr1 indicates configuration type1 write; cfgrd0 indicates configuration type0 read; cfgrd1 indicates configuration type1 read; FetchAdd (Fetchand Add) indicates an atomic operation packet "pre-fetch", reads data from the target device (original), then updates the target device data (original+FetchAdd), and then returns the target device original data; Swap (Unconditional Swap) indicates an atomic operation packet "swap", reads data from the target device (original), then writes the "Swap" data to the target device address, and then returns the target device original data; CAS (Compare and Swap) indicates the atomic operation packet "compare and exchange", first reads the target device data (original), then compares the original with the CAS data to see if they are equal, if they are equal, then writes the "Swap" data to the target device address, and then returns the target device original data; cpl indicates a completion packet without data; cpld indicates a completion packet with data; cpldlk indicates a completion packet with data and lock; INTx (INTA / INTB / INTC / INTD) indicates an INTx virtual line interrupt, which can support Legacy EP and PCIe / PCI-X; PM_Active_State_Nak indicates the message packet sent when the upstream component refuses to enter the L1 state; PM_PME indicates that the power management software wants the system to enter a low-power state, and sends a PM_PME message from the EP to the RC; PME_Turn_Off indicates that before the system reference clock is turned off, the RC will broadcast PME_Turn_Off to the EP; PME_To_Ack indicates that after the RC sends PME_Turn_Off, the EP returns PME_To_Ack when there is no message transmission; ERR_COR indicates reporting a correctable error (Bad TLP / DLLP); ERR_NONFATAL indicates an uncorrectable non-fatal error (receiving a poisoned TLP / ECRC check failure); ERR_FATAL indicates an uncorrectable fatal error (malformed packet); Unlocklock indicates that the transaction is over, and the RC sends an Unlock message to release the path from the RC to the target Legacy EP;Slot Power LimitSupport means that after the data link layer reports the DL_Up state and the Slot Capabilities register is configured, or the link changes from non-DL_Up to DL_Up, the RC automatically sends Slot Power Limit Support to the EP; LTR means that the minimum value Lmin is obtained by aggregating the delay information of each EP, and then the internal delay of the switch is subtracted from Lmin to get Cmin, and finally Cmin is reported to the RC for system power optimization; OBFF means that obff provides a mechanism for PCIe devices to obtain the system power status, and PCIe devices can choose the optimal time to interact with the system; obff only provides a recommended time, and PCIe devices can choose to ignore it; PTM means fine time management message; Vendor Defined Type 0 means vendor-defined message 0; Vendor Defined Type 1 means vendor-defined message 1. ;

[0089] Based on the above parameters, the message filtering rules for the receiving module are as follows:

[0090] mwr32 / 64 does not need filtering; mrd32 / 64 does not need filtering; mrdlk needs filtering; iowr does not need filtering; iord does not need filtering; cfgwr0 upstream port does not need filtering, downstream port needs filtering; cfgwr1 upstream port does not need filtering, downstream port needs filtering; cfgrd0 upstream port does not need filtering, downstream port needs filtering; cfgrd1 upstream port does not need filtering, downstream port needs filtering; FetchAdd (Fetch and Add) needs filtering; Swap (Unconditional Swap) needs filtering; CAS (Compare and Swap) needs filtering; cpl does not need filtering; cpld does not need filtering; cpldlk needs filtering; INTx (INTA / INTB / INTC / INTD) The upstream port needs to be filtered, but the downstream port does not need to be filtered; PM_Active_State_Nak The upstream port does not need to be filtered, but the downstream port needs to be filtered; PM_PME The upstream port needs to be filtered, but the downstream port does not need to be filtered; PME_Turn_Off The upstream port does not need to be filtered, but the downstream port needs to be filtered; PME_To_Ack The upstream port needs to be filtered, but the downstream port does not need to be filtered; ERR_COR The upstream port needs to be filtered, but the downstream port does not need to be filtered; ERR_NONFATAL The upstream port needs to be filtered, but the downstream port does not need to be filtered; ERR_FATAL The upstream port needs to be filtered, but the downstream port does not need to be filtered; Unlocklock needs to be filtered; Slot Power LimitSupport needs to be filtered; LTR needs to be filtered; OBFF needs to be filtered; PTM needs to be filtered; Vendor Defined Type 0 needs to be filtered; Vendor Defined Type 1 needs to be filtered.

[0091] Based on the above parameters, the message filtering rules for the sending module are as follows:

[0092] mwr32 / 64 does not need filtering; mrd32 / 64 does not need filtering; mrdlk needs filtering; iowr does not need filtering; iord does not need filtering; cfgwr0 upstream port needs filtering, downstream port does not need filtering; cfgwr1 upstream port needs filtering, downstream port needs filtering; cfgrd0 upstream port needs filtering, downstream port does not need filtering; cfgrd1 upstream port needs filtering, downstream port needs filtering; FetchAdd (Fetch and Add) needs filtering; Swap (UnconditionalSwap) needs filtering; CAS (Compare and Swap) needs filtering; cpl does not need filtering; cpld does not need filtering; cpldlk needs filtering; INTx (INTA / INTB / INTC / INTD) The upstream port does not need to be filtered, but the downstream port needs to be filtered; PM_Active_State_Nak The upstream port needs to be filtered, but the downstream port does not need to be filtered; PM_PME The upstream port does not need to be filtered, but the downstream port needs to be filtered; PME_Turn_Off The upstream port needs to be filtered, but the downstream port does not need to be filtered; PME_To_Ack The upstream port does not need to be filtered, but the downstream port needs to be filtered; ERR_COR The upstream port does not need to be filtered, but the downstream port needs to be filtered; ERR_NONFATAL The upstream port does not need to be filtered, but the downstream port needs to be filtered; ERR_FATAL The upstream port does not need to be filtered, but the downstream port needs to be filtered; Unlocklock needs to be filtered; Slot Power Limit Support needs to be filtered; LTR needs to be filtered; OBFF needs to be filtered; PTM needs to be filtered; Vendor Defined Type 0 needs to be filtered; Vendor Defined Type 1 needs to be filtered.

[0093] Through the above implementation, based on the message filtering process designed in the data transmission optimization module, some messages that are not required by the current business can be filtered, thereby reducing the data processing burden of the data transmission optimization module and improving the data transmission efficiency of the PCIe switch.

[0094] In some embodiments of the present application, based on the above technical solution, the receiving module mainly receives data from the controller, and the main operation is to filter the message.

[0095] For example, the current port supports the sending and receiving of atomic operation packets, but the actual business does not use atomic operation at all. In this case, it is necessary to filter out the atomic operation packets on the receiving side of the port; the configuration packet can only be received by the upstream port and then given to the downstream port; if the current port is a downstream port, the receiving module must block the reception of the configuration packet.

[0096] In some embodiments of the present application, based on the above technical solution, Figure 7 This is a business process flow chart of error handling shown in an exemplary embodiment of the present application. Figure 7 As shown, when processing a message error corresponding to a business requirement, the technical solution of the present application may at least include the following execution steps:

[0097] Get the current mode of the switch port;

[0098] If the current mode is a transparent bridge port and the end flag signal in the message is not detected, a new end flag signal is generated and output with the message, and an error indicating that the message has a missing end flag is registered in a preset error record.

[0099] Specifically, for example, error processing and error information registration can be performed for the message of the transparent bridge port; if the message at the receiving end does not have an end mark signal, the receiving module will generate a new end mark signal along with the message output and register it in the message end mark missing error. Similarly, if the sending end module does not have an end mark signal, the sending module will generate an end mark signal and indicate that the current message is an invalid packet.

[0100] Through the above implementation, the normal transmission of the message can be guaranteed and the smoothness of data transmission can be improved. At the same time, by registering the error of missing message end mark in the corresponding error record, it is convenient for troubleshooting in the subsequent maintenance process.

[0101] In some embodiments of the present application, based on the above technical solution, on the one hand, if the receiving module detects an error in a non-forwarding type message (memory read packet, atomic operation packet, configuration packet), it is necessary to report the status and generate an unsupported completion packet to return to the sending module.

[0102] If the receiving module needs to perform filtering operations on unsupported message packets, the message is directly discarded silently and an error of silent packet loss type is registered.

[0103] To illustrate by way of example, the upstream port needs to perform a packet drop operation for INTX type messages; the downstream port needs to receive and perform an upward forwarding operation for INTX type messages; for ltr messages, if the current switching chip does not support such services, the receiving module of the downstream port performs a silent discard operation, and the upstream port does not forward such messages.

[0104] On the other hand, if the sending module detects an error for non-forwarding type messages (memory read packets, atomic operation packets, configuration packets), it needs to report the status and generate an unsupported completion packet back to the receiving module; the receiving module routes the completion packet to the original port through the switching core.

[0105] To illustrate by way of example, if the sending module receives a packet of type cfg1, it needs to discard such message and generate an unsupported completion packet to the receiving module; if the sending module does not support atomic operation packets but receives this type of packet, it needs to perform a packet loss operation and generate an unsupported completion packet to the receiving module; if the message from the switching core carries a packet loss indication signal, it also needs to perform a packet loss operation.

[0106] In some embodiments of the present application, based on the above technical solution, Figure 8 FIG. 1 is a business process flow chart of error handling shown in another exemplary embodiment of the present application. Figure 8 As shown, when processing a message error corresponding to a business requirement, the technical solution of the present application may further include at least the following execution steps:

[0107] Get the current status of the switch port;

[0108] If the current state of the switch port is about to be reset, or the clock is about to be shut down, or about to enter a low power consumption state, and the message of the port has not been received or sent completely when the preset timeout mechanism is triggered, an end flag signal is generated, and the reception or sending of the message is stopped, and a message invalid flag signal is generated and sent to the switching core;

[0109] The switching core performs silent packet discarding on the messages with reception timeout or transmission timeout, and registers the errors indicating the reception timeout or transmission timeout of the messages in the preset error record.

[0110] Specifically, similar to the above-mentioned missing end flag signal, if the port corresponds to the sending module when the timeout mechanism is triggered, an end flag signal is generated based on the sending module, and the sending module is controlled to stop the sending of the message, and a message invalid flag signal is generated and sent to the switching core. If the port corresponds to the receiving module when the timeout mechanism is triggered, an end flag signal is generated based on the receiving module, and the receiving module is controlled to stop the receiving of the message, and a message invalid flag signal is generated and sent to the switching core.

[0111] After receiving the message invalid flag signal, the switching core performs a silent packet drop operation on the message, and registers the error indicating the reception timeout or transmission timeout of the message in a preset error record.

[0112] Through the above implementation, the normal transmission of messages can be guaranteed and the smoothness of data transmission can be improved. At the same time, by registering the errors of reception timeout or transmission timeout in the corresponding error records, it is convenient for troubleshooting in the subsequent maintenance process.

[0113] In some embodiments of the present application, based on the above technical solution, Fig. 9 FIG. 1 is a business process flow chart of error handling shown in another exemplary embodiment of the present application. Fig. 9 As shown, when processing a message error corresponding to a business requirement, the technical solution of the present application may further include at least the following execution steps:

[0114] Get the message type received by the receiving module;

[0115] If the message type cannot be received by the current port by default, a silent discard operation is performed on the message that cannot be received by default, and an error indicating that the message cannot be received by default is registered in a preset error record.

[0116] Specifically, for some message packets, such as ltr or obff, the current port should not be able to receive them, but they are received; then the receiving module needs to perform a silent discard operation and register the error status information. To illustrate by way of example, when filtering messages, there may be an error in the flag signal of the message, causing the receiving module to receive the message according to the wrong flag signal when receiving the message, and there will be messages that the corresponding port should not be able to receive by default, but they are received. After the receiving module identifies such messages, it will discard such messages, thereby reducing the interference of non-demand business type messages on demand business type messages, thereby improving the accuracy and reliability of the PCIe switch when performing data exchange.

[0117] In some embodiments of the present application, based on the above technical solution, Fig.10 FIG. 1 is a flow chart of the business process of bandwidth switching shown in an exemplary embodiment of the present application. Fig.10 As shown, when the receiving module coordinates the bandwidth between different transmission ports for the message input to the data transmission optimization module, the technical solution of the present application may at least include the following execution steps:

[0118] When the switching core reads the message based on the receiving module, the current number of port links is determined, and the number of port links is screened one by one to obtain the target port link with the largest supported configuration among the multiple port links;

[0119] Get the number of clock cycles of the current message;

[0120] If the number of clock cycles is multiple, the number of bytes of valid data in each clock cycle is obtained, and the bytes of valid data in multiple clock cycles are spliced ​​according to the maximum supported configuration of the target port link, and the spliced ​​message is transmitted;

[0121] If the current message has only one clock cycle, the message is directly transmitted.

[0122] It should be noted that bandwidth switching processing can effectively solve the data transmission efficiency problem caused by different port rates and bandwidths of exchange core data.

[0123] In this embodiment, the data bandwidth switching processing of the receiving module needs to determine how many lanes the current port has, and also needs to obtain the lane with the maximum supported configuration of the current port; for packets of multiple clock cycles, according to the bytes of valid data in each current clock cycle, the data is re-spliced ​​according to the maximum supported bandwidth, and then placed in the asynchronous FIFO to achieve cross-clock domain processing; if the current message has only one clock cycle, the data is directly placed in the asynchronous FIFO to achieve cross-clock domain processing.

[0124] It should be noted that the byte valid flag signal corresponding to the re-spliced ​​data in this application needs to be refreshed to achieve effective recognition of the message based on the new valid flag signal.

[0125] In order to clearly disclose the bandwidth switching process of this application, Fig.11 FIG. 1 is a business processing framework diagram of bandwidth switching processing shown in an exemplary embodiment of the present application. Fig.11 As shown, an exemplary explanation is given for the receiving module of the data transmission optimization module: assuming that the maximum link of port 0 is x8 lane, then the data bit width of port 0 is 8*32=256bit, and the data width of each lane is 32bit. Now port 0 has negotiated x1 lane, and the length of the data packet to be transmitted is 1024bit; for port 0 with x1 lane, 32 clock cycles need to be transmitted; in the switching core, if it is processed according to 32 clock cycles, it is easy to cause other ports to be stuck. Assuming that the current link of port 2 is x16, the maximum link of port 2 is x16. If the packet length required to be transmitted from port 2 to the destination port is 1024bit, then when the rates of port 0 and port 1 are the same, port 2 only needs 2 clock cycles to give the data to the switching core for processing; the data of port 0 every 8 clock cycles can be combined into a 256bit data, so that the switching core only needs 4 clock cycles when receiving the data of port 0.

[0126] Similarly, for port 1, the maximum link is lane x4, and the current negotiation is lane x4. When transmitting 1024-bit data, there is no need to reorganize the data, and the data transmission from the asynchronous processing FIFO to the switching core only takes 8 clock cycles; for port 3, the maximum link is lane x8, and the current negotiation is lane x4. When transmitting 1024-bit data, there is a need to reorganize the data, and the asynchronous FIFO receiver needs 16 clock cycles to collect the data, and the data transmission from the asynchronous FIFO to the switching core only takes 8 clock cycles.

[0127] In some embodiments of the present application, based on the above technical solution, when the sending module coordinates the bandwidth between different transmission ports for the message output from the data transmission optimization module, the technical solution of the present application may at least include the following execution steps:

[0128] When the switching core reads back the message based on the sending module, the data output by the switching core is cached according to the preset maximum packet length, the cached message is read, and the message is output according to the maximum packet length.

[0129] For the sending module of the data transmission optimization module: the cross-clock domain processing of the sending module will cache the data output by the switching core according to the maximum packet length of the switching chip. After the message is cached, the sending module reads the data and performs other operations. This can isolate the bubbles in the switching core data, that is, the invalid data segments; the bandwidth is switched before the data is given to the controller. Taking port 3 as an example, assuming that the message length is 1024 bits, the data will be split from 256 bits to 2 128 bits after the bandwidth is switched, and divided into 2 clock cycles to be given to the controller.

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0131] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A PCIe switch, characterized in that: include: The port controller processes the message input or output from the switch according to a preset first data processing flow and then transmits it; a switching core connected to the port controller, processing the message transmitted by the port controller according to a preset second data processing flow, so that the switching core performs routing services and switching services based on the processing result of the second data processing flow; A data transmission optimization module is connected between the port controller and the switching core, so that when the port controller executes the first data processing flow, the processing flow of the first data processing flow is transferred to the data transmission optimization module for execution, and when the switching core executes the second data processing flow, the processing flow of the second data processing flow is transferred to the data transmission optimization module for execution; The data transmission optimization module includes a receiving module and a sending module, the receiving module and the sending module are used to execute the first data processing flow, and the receiving module and the sending module are used to execute the second data processing flow, and the execution content includes: According to the receiving module, the message input into the data transmission optimization module is subjected to message filtering processing, error processing, cross-clock domain processing and bandwidth switching processing; and performing message filtering, error processing, cross-clock domain processing and bandwidth switching processing on the message output from the data transmission optimization module according to the sending module; Among them, the message filtering processing is used to filter messages that are not related to the business needs according to the acquired business needs; the error processing is used to process message errors corresponding to the business needs; the cross-clock domain processing is used to coordinate the transmission rate between different transmission ports; and the bandwidth switching processing is used to coordinate the bandwidth between different transmission ports.

2. The PCIe switch according to claim 1, wherein the data transmission optimization module further comprises a cache unit and a clock domain asynchronous processing unit, wherein: The coordinating the transmission rates between different transmission ports includes: When the switching core or the port controller reads a message through the data transmission optimization module, delay processing of message reading is performed based on the clock domain asynchronous processing unit, and cache processing of the message is performed based on the cache unit to coordinate the transmission rates between different transmission ports.

3. The PCIe switch according to claim 2, wherein: The cache processing of the message based on the cache unit includes: Acquire a first clock frequency of the port controller and a second clock frequency of the switch core; Calculating a difference between the first clock frequency and the second clock frequency, and calculating a ratio of the difference to the second clock frequency, so as to obtain a cache length of the message according to the ratio; The cache unit is controlled to perform cache processing of the message according to the cache length.

4. The PCIe switch according to claim 1, wherein: The filtering of messages irrelevant to the business requirements according to the acquired business requirements includes: Obtaining the current mode of the switch port; If the current mode is a non-transparent bridge port, performing message filtering to retain a target message, wherein the target message includes at least one of a storage type message without a lock, an atomic operation packet, and a completion packet without a lock; If the current mode is a transparent bridge port, corresponding message filtering is performed according to the service requirements.

5. The PCIe switch according to claim 1, wherein: The processing of the message error corresponding to the service requirement includes: Get the current mode of the switch port; If the current mode is a transparent bridge port and the end flag signal in the message is not detected, a new end flag signal is generated and output with the message, and an error indicating that the message has a missing end flag is registered in a preset error record.

6. The PCIe switch according to claim 1, wherein: The processing of the message error corresponding to the service requirement includes: Get the current status of the switch port; If the current state of the switch port is about to be reset or the clock is about to be shut down or about to enter a low power consumption state, and the message of the port has not been received or sent completely when the preset timeout mechanism is triggered, an end flag signal is generated, and the reception or sending of the message is stopped, and a message invalid flag signal is generated and sent to the switching core; The switching core performs a silent packet drop operation on the message with reception timeout or transmission timeout, and registers an error indicating that the message has reception timeout or transmission timeout in a preset error record.

7. The PCIe switch according to claim 1, wherein: The processing of the message error corresponding to the service requirement includes: Obtaining the type of message received by the receiving module; If the message type cannot be received by default at the current port, a silent discard operation is performed on the message that cannot be received by default, and an error indicating that the message cannot be received by default is registered in a preset error record.

8. The PCIe switch according to any one of claims 1 to 7, characterized in that: The receiving module coordinates the bandwidth between different transmission ports for the message input into the data transmission optimization module, including: When the switching core reads the message based on the receiving module, the current number of port links is determined, and the number of port links is screened one by one to obtain the target port link with the maximum supported configuration among the multiple port links; Get the number of clock cycles of the current message; If the number of the clock cycles is multiple, the number of bytes of valid data in each clock cycle is obtained, so as to splice the bytes of valid data in multiple clock cycles according to the maximum supported configuration of the target port link, and then transmit the spliced ​​message; If the current message has only one clock cycle, the message is directly transmitted.

9. The PCIe switch according to any one of claims 1 to 7, characterized in that: The sending module coordinates the bandwidth between different transmission ports for the message output from the data transmission optimization module, including: When the switching core reads back the message based on the sending module, the data output by the switching core is cached according to a preset maximum packet length, the cached message is read, and the message is output according to the maximum packet length.

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