Address allocation method and device, computer-readable storage medium, and communication system

Abstract

An address allocation method and device, a computer-readable storage medium, and a communication system, wherein the communication system comprises: a master node and N slave nodes, wherein the master node is coupled to the N slave nodes via a serial data bus; the i-th slave node among the N slave nodes comprises an addressing module, wherein the addressing module comprises a current sampling unit, which is suitable for obtaining a bus current, wherein the bus current is the difference between a sampling current and an interference current; wherein the sampling current is the actual current flowing through the shunt resistor, and the interference current is the current generated by the interference noise on the serial data bus on the shunt resistor. The above scheme can improve the accuracy of address allocation for slave nodes.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an address allocation method and device, a computer-readable storage medium, and a communication system. Background Art

[0002] The Local Interconnect Network (LIN) communication system usually consists of a master node (Master) and several slave nodes (Slave) with the same structure. In order to distinguish several slave nodes, it is necessary to assign corresponding addresses to different slave nodes.

[0003] The Bus Shunt method (BSM) provides a solution for assigning addresses to different slave nodes. Different slave nodes are assigned corresponding addresses based on their positions in the LIN communication network.

[0004] The existing address allocation method is easily affected by interference and noise on the LIN bus during address allocation, and the accuracy of address allocation is poor. Summary of the invention

[0005] The purpose of the present invention is at least to provide a serial data bus communication system and an address allocation method, which can improve the accuracy of address allocation in the serial data bus communication system.

[0006] In a first aspect, the present invention provides a serial data bus communication system, comprising: a master node and N slave nodes; wherein the master node is coupled to the N slave nodes through the serial data bus; the i-th slave node among the N slave nodes comprises an addressing module; N is a positive integer and N≥2, i is a positive integer and 1≤i≤N; the addressing module comprises: a first switch unit, a pull-up resistor, a second switch unit, a current source, a shunt resistor and a current sampling unit, wherein: the first switch unit has a first end inputting a power supply voltage, and a second end thereof is coupled to the first end of the pull-up resistor; The pull-up resistor has a second end coupled to the serial data bus; the second switch unit has a first end inputting the power supply voltage and a second end coupled to the first end of the current source; the current source has a second end coupled to the serial data bus; the shunt resistor is coupled to the serial data bus; the current sampling unit is suitable for obtaining the bus current, and the bus current is the difference between the sampling current and the interference current; the sampling current is the actual current flowing through the shunt resistor, and the interference current is the current generated on the shunt resistor by the interference noise on the serial data bus.

[0007] The slave node includes a current sampling unit, through which the bus current is obtained. Since the obtained bus current is the difference between the actual current on the shunt resistor and the interference current, that is, the bus current is the current after noise removal, the influence of interference noise can be effectively avoided in the subsequent address allocation process, thereby improving the accuracy of address allocation.

[0008] Optionally, the current sampling unit includes: a sampling current acquisition module and an interference current acquisition module, wherein: the sampling current acquisition module is used to obtain the actual voltage drop across the shunt resistor and determine the sampling current based on the actual voltage drop; the interference current acquisition module is used to obtain the interference voltage drop across the shunt resistor and determine the interference current based on the interference voltage drop.

[0009] Optionally, the current sampling unit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a matching resistor, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, an operational amplifier and an analog-to-digital converter, wherein: the first resistor, a first end thereof is coupled to the first end of the shunt resistor, and a second end thereof is coupled to the first end of the third switch unit; the second resistor, a first end thereof is coupled to the first end of the shunt resistor, and a second end thereof is coupled to the first end of the fourth switch unit; the matching resistor, a first end thereof is coupled to the first end of the second resistor and the first end of the shunt resistor, and a second end thereof is coupled to the first end of the third resistor; the third resistor, a second end thereof is coupled to the first end of the fifth switch unit; the fourth resistor, a first end thereof is coupled to the second end of the shunt resistor, and a second end thereof is coupled to the first end of the The first end of the sixth switch unit is coupled; the second end of the third switch unit is coupled to the second input end of the operational amplifier, and the control end thereof inputs the first control signal; the second end of the fourth switch unit is coupled to the second input end of the operational amplifier, and the control end thereof inputs the second control signal; the first control signal is inverted with the second control signal; the second end of the fifth switch unit is coupled to the first input end of the operational amplifier, and the control end thereof inputs the second control signal; the second end of the sixth switch unit is coupled to the first input end of the operational amplifier, and the control end thereof inputs the first control signal; the first end of the fifth resistor is input with the reference voltage, and the second end thereof is coupled to the first input end of the operational amplifier; the first end of the sixth resistor is coupled to the second input end of the operational amplifier, and the second end thereof is coupled to the output end of the operational amplifier.

[0010] Optionally, the current sampling unit further includes: a first diode, a second diode, a third diode and a fourth diode, wherein: the first diode has a positive electrode connected to ground, and a negative electrode connected to the second end of the first resistor; the second diode has a positive electrode connected to ground, and a negative electrode connected to the second end of the second resistor; the third diode has a positive electrode connected to ground, and a negative electrode connected to the second end of the third resistor; the fourth diode has a positive electrode connected to ground, and a negative electrode connected to the second end of the fourth resistor.

[0011] In a second aspect, the present invention provides an address allocation method, which is suitable for allocating addresses to slave nodes in any of the above-mentioned serial data bus communication systems; the address allocation method comprises: receiving an address allocation command, the address allocation command comprising N addresses to be allocated; obtaining a first bus current on the serial data bus; controlling the first switch unit to be closed, and obtaining a second bus current on the serial data bus; if the first difference is less than a preset first threshold, controlling the second switch unit to be closed; the first difference is the difference between the first bus current and the second bus current; obtaining a third bus current on the serial data bus; if the second difference is less than a preset second threshold, obtaining a target address from the N addresses to be allocated; the second difference is the difference between the first bus current and the third bus current.

[0012] The slave node receives an address allocation command and obtains a first bus current on the serial data bus; then controls the first switch unit to close so as to connect the pull-up resistor to the serial data bus, and obtains a second bus current on the serial data bus after the pull-up resistor is connected to the serial data bus. When the first difference between the first bus current and the second bus current is less than a preset first threshold, the second switch is controlled to close so as to connect the current source to the serial data bus, and obtains a third bus current on the serial data bus after the current source is connected to the serial data bus. When the second difference between the first bus current and the third bus current is less than a preset second threshold, it can be determined that the slave node is the slave node farthest from the master node, and the corresponding address to be allocated is selected as the target address. Thus, based on the change in the bus current (the first difference, the second difference), accurate address allocation is achieved for different slave nodes.

[0013] Optionally, the first bus current is the difference between the first sampling current and the first interference current; the first sampling current is: the actual current flowing through the shunt resistor after the master node sends the address assignment command on the serial data bus; the first interference current is: the current generated on the shunt resistor by the interference noise on the serial data bus after the master node sends the address assignment command on the serial data bus; the second bus current is the difference between the second sampling current and the second interference current; the second sampling current is: the actual current flowing through the shunt resistor after the first switch unit is closed; the second interference current is: the current generated on the shunt resistor by the interference noise on the serial data bus after the first switch unit is closed; the third bus current is the difference between the third sampling current and the third interference current; the third sampling current is: the actual current flowing through the shunt resistor after the second switch unit is closed; the third interference current is: the current generated on the shunt resistor by the interference noise on the serial data bus after the second switch unit is closed.

[0014] Optionally, before receiving the address allocation command, the method further includes: determining that the target address does not exist.

[0015] Optionally, if the first difference is greater than the first threshold, the first switch unit is controlled to be disconnected.

[0016] Optionally, if the second difference is greater than the second threshold, the first switch unit is controlled to be disconnected, and the second switch unit is controlled to be disconnected.

[0017] Optionally, the first threshold is equal to the second threshold.

[0018] In a third aspect, the present invention further provides an address allocation device, suitable for allocating addresses to slave nodes in any of the above-mentioned serial data bus communication systems; the address allocation device comprises: a receiving unit, used to receive an address allocation command, the address allocation command comprising N addresses to be allocated; a first acquisition unit, used to acquire a first bus current on the serial data bus; a second acquisition unit, used to control the first switch unit to close, and acquire a second bus current on the serial data bus; a first control unit, used to detect that a first difference is less than a preset first threshold, and control the second switch unit to close; the first difference is the difference between the first bus current and the second bus current; a third acquisition unit, used to acquire a third bus current on the serial data bus; an address allocation unit, used to detect that a second difference is less than a preset second threshold, and acquire a target address from the N addresses to be allocated; the second difference is the difference between the first bus current and the third bus current.

[0019] In a fourth aspect, the present invention further provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above-mentioned address allocation methods are executed.

[0020] In a fifth aspect, the present invention also provides another address allocation device, comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor executes the steps of any one of the above-mentioned address allocation methods when running the computer program. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a structural schematic diagram of a serial data bus communication system in an embodiment of the present invention;

[0022] Figure 2 is a structural schematic diagram of a current sampling unit in an embodiment of the present invention;

[0023] Figure 3 is a flow chart of an address allocation method in an embodiment of the present invention;

[0024] Figure 4 It is a structural diagram of an address allocation device in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] As described in the above background technology, the existing address allocation method is easily affected by interference and noise on the LIN bus during address allocation, and the accuracy of address allocation is poor.

[0026] In the embodiment of the present invention, the slave node obtains the bus current after noise reduction through the current sampling unit in the addressing module, so that in the subsequent address allocation process, the influence of interference noise can be effectively avoided and the accuracy of address allocation can be improved.

[0027] The bus current is a current after noise reduction processing, so in the subsequent address allocation process, the influence of interference noise can be effectively avoided, thereby improving the accuracy of address allocation.

[0028] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] An embodiment of the present invention provides a serial data bus communication system. The serial data bus communication system may include a master node and N slave nodes.

[0030] In a specific implementation, the above-mentioned master node may also be referred to as a host, a master device, a Master device, etc. The above-mentioned slave node may also be referred to as a slave machine, a slave device, a Slave device, etc.

[0031] In the embodiment of the present invention, the master node may be coupled to N slave nodes via a serial data bus, where N is a positive integer and N≥2.

[0032] In a specific implementation, the serial data bus may be a LIN bus, a controller area network (CAN) bus, or other types of serial data buses.

[0033] In the embodiment of the present invention, the structure of each slave node may be the same or similar. Each slave node may include an addressing module. The structure of the addressing module in each slave node may be the same or similar.

[0034] In some embodiments, the structures of the N slave nodes are the same, and the structures of the addressing modules in the N slave nodes are also the same.

[0035] Reference Figure 1 , a schematic diagram of the structure of a serial data bus communication system in an embodiment of the present invention is given. Figure 1 Provide explanation. Figure 1 In the embodiment, the serial data bus communication system includes a master node and N slave nodes (Slave1~SlaveN). For the N slave nodes, their corresponding structures are the same.

[0036] In a specific implementation, for any slave node, the addressing module may include: a first switch unit S1, a pull-up resistor R slave , a second switch unit S2, a current source I, a shunt resistor Rshunt and a current sampling unit CSA, wherein:

[0037] The first terminal of the first switch unit S1 is input with a power supply voltage V BAT The second end of the first switch unit S1 is connected to the pull-up resistor R slave The first end of the first switch unit S1 is missing; when the control end of the first switch unit S1 inputs the first enable signal, the first switch unit S1 is turned on, otherwise, when the control end of the first switch unit S1 does not have the first enable signal input, the first switch unit S1 is turned off;

[0038] Pull-up resistor R slave The second end may be coupled to the serial data bus;

[0039] The first terminal of the second switch unit S2 is input with a power supply voltage V BAT, the second end of the second switch unit S2 is coupled to the first end of the current source I; when the control end of the second switch unit S2 inputs the second enable signal, the second switch unit S2 is turned on, otherwise, when the control end of the second switch unit S2 does not input the second enable signal, the second switch unit S2 is turned off;

[0040] The second end of the current source I may be coupled to the serial data bus;

[0041] The shunt resistor Rshunt may be coupled to the serial data bus;

[0042] The current sampling unit CSA can obtain the bus current; the bus current can be the difference between the sampling current and the interference current, the sampling current is the actual current flowing through the shunt resistor Rshunt, and the interference current can be the current generated on the shunt resistor Rshunt by the interference noise on the serial data bus.

[0043] In other words, the bus current finally acquired by the current sampling unit CSA is the current after the interference elimination process.

[0044] In a specific implementation, the current sampling unit CSA may first obtain the actual current and then obtain the interference current; or, the current sampling unit CSA may first obtain the interference current and then obtain the actual current.

[0045] In a specific implementation, the layout of the shunt resistor Rshunt is matched with that of the matching resistor Rf to ensure that the actual states of the shunt resistor Rshunt and the matching resistor Rf remain consistent.

[0046] In a specific implementation, the resistance of the shunt resistor Rshunt can be 1 ohm, and the pull-up resistor R slave The resistance value can be 30K ohms.

[0047] In a specific implementation, any slave node may also include a data sending module TXD and a data receiving module RXD.

[0048] Figure 1 For the master node, it can add an additional master node resistance to the slave node structure. Rmaster It should be noted that the specific structure of the master node is not limited to Figure 1 Examples in .

[0049] In a specific implementation, the current sampling unit may include a sampling current acquisition module and an interference current acquisition module, wherein:

[0050] The sampling current acquisition module can be used to obtain the actual voltage drop across the shunt resistor and determine the sampling current based on the actual voltage drop across the shunt resistor;

[0051] The interference current acquisition module is used to acquire the interference voltage drop across the shunt resistor and determine the interference current based on the interference voltage drop.

[0052] It can be understood that the sampling current is the quotient of the actual voltage drop across the shunt resistor and the resistance value of the shunt resistor. Correspondingly, the interference current is the quotient of the interference voltage drop across the shunt resistor and the resistance value of the shunt resistor.

[0053] Reference Figure 2 , a schematic structural diagram of a current sampling unit in an embodiment of the present invention is given.

[0054] In a specific implementation, the current sampling unit may include: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor, a matching resistor Rf, a third switch unit S3, a fourth switch unit S4, a fifth switch unit S5, a sixth switch unit S6, an operational amplifier AMP, and an analog-to-digital converter ADC, wherein:

[0055] A first end of the first resistor R1 may be coupled to a first end of the shunt resistor, and a second end of the first resistor R1 may be coupled to a first end of the third switch unit S3;

[0056] A first end of the second resistor R2 may be coupled to a first end of the shunt resistor, and a second end of the second resistor R2 may be coupled to a first end of the fourth switch unit S4;

[0057] The first end of the matching resistor Rf can be coupled to the first end of the second resistor R2 and the first end of the shunt resistor, and the second end of the matching resistor Rf can be coupled to the first end of the third resistor R3; the resistance value of the matching resistor Rf is equal to the resistance value of the pull-up resistor;

[0058] The second end of the third resistor R3 is coupled to the first end of the fifth switch unit S5;

[0059] A first end of the fourth resistor R4 is leak-connected to a second end of the shunt resistor, and a second end of the fourth resistor R4 is coupled to a first end of the sixth switch unit S6;

[0060] The second end of the third switch unit S3 is coupled to the second input end of the operational amplifier AMP, and the control end of the third switch unit S3 inputs the first control signal;

[0061] The second terminal of the fourth switch unit S4 is coupled to the second input terminal of the operational amplifier AMP, and the control terminal of the fourth switch unit S4 inputs the second control signal;

[0062] The second terminal of the fifth switch unit S5 is coupled to the first input terminal of the operational amplifier AMP, and the control terminal of the fifth switch unit S5 inputs the second control signal;

[0063] The second terminal of the sixth switch unit S6 is coupled to the second input terminal of the operational amplifier AMP, and the control terminal of the sixth switch unit S6 inputs the first control signal; the first control signal is inverted with the second control signal;

[0064] A reference voltage is input to a first terminal of the fifth resistor R5, and a second terminal of the fifth resistor R5 is coupled to a first input terminal of the operational amplifier AMP;

[0065] A first end of the sixth resistor R6 is coupled to the second input end of the operational amplifier AMP, and a second end of the sixth resistor R6 is coupled to the output end of the operational amplifier AMP;

[0066] The input terminal of the analog-to-digital converter ADC is coupled to the output terminal of the operational amplifier AMP, and is suitable for converting the output signal of the operational amplifier AMP into a corresponding digital voltage.

[0067] When the resistance of the pull-up resistor is a fixed value, the target current flowing through the pull-up resistor can be determined by knowing the voltage drop between the two ends of the pull-up resistor.

[0068] In a specific implementation, when the second control signal input to the control end of the fourth switch unit and the fifth switch unit is at a high level, the fourth switch unit and the fifth switch unit are turned on; the first control signal input to the control end of the third switch unit and the sixth switch unit is at a low level, and the third switch unit and the sixth switch unit are disconnected. In this scenario, the operational amplifier samples the noise interference on the matching resistor, and the ADC performs analog-to-digital conversion on the noise interference to obtain the interference voltage drop, and then the interference current.

[0069] When the second control signal input to the control end of the fourth switch unit and the fifth switch unit is at a low level, the fourth switch unit and the fifth switch unit are disconnected; the first control signal input to the control end of the third switch unit and the sixth switch unit is at a high level, and the third switch unit and the sixth switch unit are turned on. In this scenario, the operational amplifier samples the actual voltage drop across the shunt resistor, and the ADC performs analog-to-digital conversion on the actual voltage drop to obtain the sampled current.

[0070] Therefore, the interference current and the sampling current can be acquired respectively through the first control signal and the second control signal, and then the bus current can be obtained.

[0071] In an embodiment of the present invention, the above-mentioned first resistor, third switch unit, fourth resistor, sixth switch unit, fifth resistor, sixth resistor and operational amplifier AMP constitute a sampling current acquisition module, which is used to obtain the actual voltage drop across the shunt resistor to determine the sampling current; the above-mentioned matching resistor, second resistor, fourth switch unit, third resistor, fifth switch unit, fifth resistor, sixth resistor and operational amplifier AMP constitute an interference current acquisition module, which is used to obtain the interference voltage drop across the shunt resistor to determine the interference current.

[0072] In some embodiments, the third switch unit, the fourth switch unit, the fifth switch unit and the sixth switch unit can all be NMOS tubes. The first end of the NMOS tube is the drain of the NMOS tube, the second end of the NMOS tube is the source of the NMOS tube, and the control end of the NMOS tube is the gate of the NMOS tube.

[0073] In a specific implementation, the current sampling unit may further include a first diode, a second diode, a third diode and a fourth diode ( Figure 2 ), where:

[0074] An anode of the first diode is grounded, and a cathode of the first diode is coupled to a second end of the first resistor;

[0075] The anode of the second diode is grounded, and the cathode of the second diode is coupled to the second end of the second resistor;

[0076] An anode of the third diode is grounded, and a cathode of the third diode is coupled to a second end of the third resistor;

[0077] An anode of the fourth diode is grounded, and a cathode of the fourth diode is coupled to the second end of the fourth resistor.

[0078] The address allocation method of the serial data bus communication system provided in the above embodiment of the present invention is described below.

[0079] Reference Figure 3 , an address allocation method in an embodiment of the present invention is given, and the following is described in detail through specific steps.

[0080] In the embodiment of the present invention, the following address allocation method can be executed by a control chip (such as a microcontroller, a central processing unit, etc.) with data processing capabilities in the slave node, or by a chip module with data processing capabilities in the slave node, or by the slave node. The following is an example of the slave node executing the address allocation method.

[0081] Step 301: Receive an address allocation command.

[0082] In the embodiment of the present invention, the master node may send an address allocation instruction through a serial data bus. The address allocation instruction may include N addresses to be allocated. The N addresses to be allocated may correspond one-to-one to the N slave nodes.

[0083] In a specific implementation, after the master node sends an address assignment instruction through the serial data bus, the level on the serial data bus is reduced to a low level. The control ends of the first switch units of the N slave nodes do not have the first enable signal input, and the control ends of the second switch units of the N slave nodes do not have the second enable signal input.

[0084] In a specific implementation, after receiving the address allocation command, the slave node may first detect whether it has been allocated a target address. If the slave node detects that it has been allocated a target address, the slave node may not need to perform the subsequent address allocation steps (i.e., steps 302 to 306); if the slave node has not been allocated a target address, the slave node continues to perform the following steps 302 to 306.

[0085] That is, the slave node that executes the following steps 302 to 306 is a slave node that has not yet been assigned a target address (hereinafter, slave node j is taken as an example).

[0086] For example, the N slave nodes are slave node 1 to slave node 8, and slave node 8 has obtained the target address through steps 301 to 306. Therefore, slave node 8 detects that it has been assigned the target address, so slave node 1 to slave node 7 all execute the following steps 302 to 306.

[0087] Step 302: Acquire a first bus current on the serial data bus.

[0088] In the embodiment of the present invention, if the slave node j detects that there is no allocated target address, the slave node j can obtain the bus current on the serial data bus through its internal addressing module. For the convenience of distinction, in step 302, the bus current obtained by the slave node is called the first bus current.

[0089] For different slave nodes, the first bus currents obtained may be the same or different.

[0090] For example, the first bus currents on the serial data bus are respectively obtained from the slave nodes 1 to 7. The first bus currents obtained from the slave nodes 1 to 7 are different from each other.

[0091] In the embodiment of the present invention, the first bus current may be the difference between the first sampling current and the first interference current. Specifically, the first sampling current may be: the actual current flowing through the shunt resistor detected by the slave node j after the master node sends the address assignment command on the serial data bus; the first interference current may be: the interference current flowing through the shunt resistor detected by the slave node j after the master node sends the address assignment command on the serial data bus.

[0092] Specifically, the specific working principle and process of acquiring the first bus current from the addressing module of the node j can correspond to the description in the above embodiment, which will not be repeated here.

[0093] Step 303: Control the first switch unit to close, and obtain the second bus current on the serial data bus.

[0094] In the embodiment of the present invention, for the slave node j, after obtaining the first bus current, the first switch unit in the internal addressing module can be controlled to close. Specifically, the slave node j can input a first enable signal to the control end of the first switch unit in the internal addressing module. After the control end of the first switch unit receives the first enable signal, the first switch unit is turned on, thereby connecting the pull-up resistor to the serial data bus.

[0095] For example, no target address is assigned to slave node 1 to slave node 7. After obtaining the first bus current corresponding to each slave node 1 to slave node 7, the first switch unit in each addressing module can be controlled to close. The pull-up resistors in the addressing modules of slave node 1 to slave node 7 are all connected to the serial data bus.

[0096] When the pull-up resistor of the slave node is connected to the serial data bus, the bus current on the serial data bus will change. The slave node obtains the bus current on the serial data bus as the second bus current.

[0097] That is to say, for a certain slave node, the second bus current obtained by it is the bus current after the pull-up resistors of several slave nodes are connected to the serial data bus.

[0098] For example, the pull-up resistors in the addressing modules of slave nodes 1 to 7 are all connected to the serial data bus. The second bus currents corresponding to the respective slave nodes 1 to 7 are obtained. For slave node 1, the second bus current obtained by it is the current flowing through the shunt resistor of slave node 1 after the pull-up resistors of slave nodes 1 to 7 are all connected to the serial data bus.

[0099] In the embodiment of the present invention, the second bus current may be the difference between the second sampling current and the second interference current. Specifically, for the slave node j, the corresponding second sampling current may be: the actual current flowing through the shunt resistor detected after the first switch unit of the slave node j is closed; the second interference current may be: the interference current flowing through the shunt resistor detected after the first switch unit of the slave node j is closed.

[0100] Step 304: If the first difference is less than a preset first threshold, control the second switch unit to close.

[0101] In the embodiment of the present invention, for the slave node j, the difference between the first bus current obtained in step 302 and the second bus current obtained in step 303 is obtained, and the difference obtained is the first difference.

[0102] In a specific implementation, if the first difference detected from node j is less than a preset first threshold, the second switch unit can be controlled to close, thereby connecting the current source in the addressing module of node j to the serial data bus. If the first difference detected from node j is greater than the first threshold, the first switch unit in the internal addressing module can be controlled from node j to open (that is, stop inputting the first enable signal to the first switch unit), thereby disconnecting the path between the pull-up resistor in the addressing module and the serial data bus.

[0103] For example, slave node 7 obtains the first bus current I1 based on step 302, obtains the second bus current I2 based on step 303, and the first threshold is Δ1. Slave node 1 detects that I1-I2>Δ1, and then slave node 7 controls the first switch unit in the addressing module (that is, the addressing module of slave node 7) to disconnect.

[0104] If the first difference detected from node j is smaller than the first threshold, the second switch unit in the internal addressing module can be controlled to be turned on from node j, thereby connecting the current source in the internal addressing module to the serial data bus.

[0105] Specifically, it is detected from node j that the first difference is less than the first threshold, and a second enable signal is input to the control end of the second switch unit in the internal addressing module, so that the current source in the internal addressing module is connected to the serial data bus.

[0106] In this scenario, in the addressing module of the slave node j, the first switch unit and the second switch unit are both turned on, and the pull-up resistor and the current source are both connected to the serial data bus.

[0107] Step 305: Acquire a third bus current on the serial data bus.

[0108] In a specific implementation, after the current source of the slave node is connected to the serial data bus, the bus current on the serial data bus will change again. The bus current on the serial data bus is obtained from the slave node j as the third bus current.

[0109] For example, the current sources in the addressing modules of slave nodes 1 to 7 are all connected to the serial data bus. The third bus currents corresponding to the respective slave nodes 1 to 7 are obtained. For slave node 1, the third bus current obtained by it is the current flowing through the shunt resistor of slave node 1 after the current sources of slave nodes 1 to 7 are all connected to the serial data bus.

[0110] In the embodiment of the present invention, the third bus current may be the difference between the third sampling current and the third interference current. Specifically, for the slave node j, the corresponding third sampling current may be: the actual current flowing through the shunt resistor detected after the second switch unit of the slave node j is closed; the third interference current may be: the interference current flowing through the shunt resistor detected after the second switch unit of the slave node j is closed.

[0111] That is to say, the first bus current, the second bus current and the third bus current are all bus currents that have been processed for interference.

[0112] Step 306: If the second difference is less than a preset second threshold, obtain a target address from the N addresses to be allocated.

[0113] In a specific implementation, for slave node j, if it is detected that the second difference is less than a preset second threshold, one can be selected from N addresses to be allocated as its corresponding target address; conversely, if it is detected that the second difference is greater than the second threshold, the first switch unit and the second switch unit of the internal addressing module can be controlled to be disconnected, thereby controlling the pull-up resistor and the current source of the internal addressing module to disconnect from the serial data bus.

[0114] Specifically, for the slave node j, if it is detected that the second difference is greater than the second threshold, the first enable signal is stopped from being input to the control end of the internal first switch unit, thereby disconnecting the internal pull-up resistor from the serial data bus; and the second enable signal is stopped from being input to the control end of the internal second switch unit, thereby disconnecting the internal current source from the serial data bus.

[0115] If it is detected that the second difference is less than the second threshold, an address to be allocated is selected from the address allocation command as the target address corresponding to the slave node j.

[0116] In the embodiment of the present invention, after assigning the target address to the slave node j, the master node can determine whether there is a slave node that has not been assigned a target address. If the master node detects that there is a slave node that has not been assigned a target address, the master node can resend the address assignment instruction, and the slave node that has not been assigned a target address can re-execute steps 301 to 306; if the master node detects that all N slave nodes have been assigned a target address, the master node ends the address assignment operation.

[0117] In summary, by adopting the address allocation method provided in the above embodiment, accurate address allocation for N slave nodes can be achieved.

[0118] Reference Figure 4 , an address allocation device 40 in an embodiment of the present invention is provided, which is suitable for allocating addresses to slave nodes in the serial data bus communication system provided by any of the above embodiments; the address allocation device 40 comprises: a receiving unit 401, a first acquisition unit 402, a second acquisition unit 403, a first control unit 404, a third acquisition unit 405 and an address allocation unit 406, wherein:

[0119] The receiving unit 401 is used to receive an address allocation command, where the address allocation command includes N addresses to be allocated;

[0120] A first acquisition unit 402, configured to acquire a first bus current on the serial data bus;

[0121] A second acquisition unit 403, configured to control the first switch unit to close and acquire a second bus current on the serial data bus;

[0122] A first control unit 404 is configured to detect that the first difference is less than a preset first threshold value, and control the second switch unit to close; the first difference is the difference between the first bus current and the second bus current;

[0123] A third acquisition unit 405, configured to acquire a third bus current on the serial data bus;

[0124] The address allocation unit 406 is used to detect that the second difference is less than a preset second threshold, and obtain a target address from the N addresses to be allocated; the second difference is the difference between the first bus current and the third bus current.

[0125] In a specific implementation, the specific execution process of the above-mentioned receiving unit 401, the first acquisition unit 402, the second acquisition unit 403, the first control unit 404, the third acquisition unit 405 and the address allocation unit 406 can correspond to step 301 to step 306, which will not be repeated here.

[0126] In a specific implementation, each module / unit included in each device or product described in the above embodiments may be a software module / unit or a hardware module / unit, or may be partly a software module / unit and partly a hardware module / unit.

[0127] For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on the processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on the processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0128] An embodiment of the present invention further provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the address allocation method provided in any of the above embodiments are executed.

[0129] An embodiment of the present invention further provides another address allocation device, including a memory and a processor, wherein the memory stores a computer program that can be executed on the processor, and the processor executes the steps of the address allocation method provided in any of the above embodiments when running the computer program.

[0130] A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the relevant hardware through a program, and the program may be stored in a computer-readable storage medium, which may include: ROM, RAM, disk or CD, etc.

[0131] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A serial data bus communication system, characterized in that: include: A master node and N slave nodes, where: The master node is coupled to the N slave nodes via the serial data bus; The i-th slave node among the N slave nodes includes an addressing module; N is a positive integer and N≥2, i is a positive integer and 1≤i≤N; The addressing module includes: a first switch unit, a pull-up resistor, a second switch unit, a current source, a shunt resistor and a current sampling unit, wherein: The first switch unit has a first end input with a power supply voltage, and a second end coupled with a first end of the pull-up resistor; The pull-up resistor has a second end coupled to the serial data bus; The second switch unit has a first end input with the power supply voltage, and a second end coupled with the first end of the current source; The current source has a second end coupled to the serial data bus; The shunt resistor is coupled to the serial data bus; The current sampling unit is suitable for acquiring bus current, where the bus current is the difference between the sampling current and the interference current; the sampling current is the actual current flowing through the shunt resistor, and the interference current is the current generated by the interference noise on the serial data bus on the shunt resistor; the current sampling unit includes: a sampling current acquisition module and an interference current acquisition module, wherein: the sampling current acquisition module is used to acquire the actual voltage drop across the shunt resistor and determine the sampling current based on the actual voltage drop; the interference current acquisition module is used to acquire the interference voltage drop across the shunt resistor and determine the interference current based on the interference voltage drop; The current sampling unit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a matching resistor, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, and an operational amplifier, wherein: the first resistor, a first end thereof is coupled to the first end of the shunt resistor, and a second end thereof is coupled to the first end of the third switch unit; the second resistor, a first end thereof is coupled to the first end of the shunt resistor, and a second end thereof is coupled to the first end of the fourth switch unit; the matching resistor, a first end thereof is coupled to the first end of the second resistor and the first end of the shunt resistor, and a second end thereof is coupled to the first end of the third resistor; the third resistor, a second end thereof is coupled to the first end of the fifth switch unit; the fourth resistor, a first end thereof is coupled to the second end of the shunt resistor, and a second end thereof is coupled to the sixth switch unit. The first end of the unit is coupled; the second end of the third switch unit is coupled to the second input end of the operational amplifier, and the control end thereof inputs the first control signal; the second end of the fourth switch unit is coupled to the second input end of the operational amplifier, and the control end thereof inputs the second control signal; the first control signal is inverted with the second control signal; the second end of the fifth switch unit is coupled to the first input end of the operational amplifier, and the control end thereof inputs the second control signal; the second end of the sixth switch unit is coupled to the first input end of the operational amplifier, and the control end thereof inputs the first control signal; the first end of the fifth resistor is input with the reference voltage, and the second end thereof is coupled to the first input end of the operational amplifier; the first end of the sixth resistor is coupled to the second input end of the operational amplifier, and the second end thereof is coupled to the output end of the operational amplifier.

2. The serial data bus communication system according to claim 1, characterized in that: The current sampling unit further includes: a first diode, a second diode, a third diode and a fourth diode, wherein: The first diode has an anode connected to the ground and a cathode coupled to the second end of the first resistor; The second diode has an anode connected to the ground and a cathode coupled to the second end of the second resistor; The third diode has an anode connected to the ground and a cathode coupled to the second end of the third resistor; The fourth diode has an anode connected to the ground, and a cathode connected to the second end of the fourth resistor.

3. An address allocation method, characterized in that: Suitable for performing address allocation on slave nodes in the serial data bus communication system according to claim 1 or 2; the address allocation method comprises: Receiving an address allocation command, wherein the address allocation command includes N addresses to be allocated; Acquiring a first bus current on the serial data bus; Controlling the first switch unit to close, and obtaining a second bus current on the serial data bus; If the first difference is less than a preset first threshold, controlling the second switch unit to close; the first difference is the difference between the first bus current and the second bus current; Acquiring a third bus current on the serial data bus; If the second difference is less than a preset second threshold, a target address is obtained from the N addresses to be allocated; the second difference is a difference between the first bus current and the third bus current.

4. The address allocation method according to claim 3, characterized in that: The first bus current is the difference between the first sampling current and the first interference current; the first sampling current is: the actual current flowing through the shunt resistor after the master node sends the address assignment command on the serial data bus; the first interference current is: the current generated on the shunt resistor by the interference noise on the serial data bus after the master node sends the address assignment command on the serial data bus; The second bus current is the difference between the second sampling current and the second interference current; The second sampling current is: the actual current flowing through the shunt resistor after the first switch unit is closed; the second interference current is: the current generated on the shunt resistor by the interference noise on the serial data bus after the first switch unit is closed; The third bus current is the difference between the third sampling current and the third interference current; The third sampling current is: the actual current flowing through the shunt resistor after the second switch unit is closed; the third interference current is: the current generated on the shunt resistor by the interference noise on the serial data bus after the second switch unit is closed.

5. The address allocation method according to claim 4, characterized in that: Before receiving the address allocation command, it also includes: It is determined that the target address does not exist.

6. The address allocation method according to claim 4, characterized in that: If the first difference is greater than the first threshold, the first switch unit is controlled to be disconnected.

7. The address allocation method according to claim 4, characterized in that: If the second difference is greater than the second threshold, the first switch unit is controlled to be disconnected, and the second switch unit is controlled to be disconnected.

8. The address allocation method according to claim 4, characterized in that: The first threshold is equal to the second threshold.

9. An address allocation device, characterized in that: Suitable for performing address allocation to slave nodes in the serial data bus communication system according to claim 1 or 2, the address allocation device comprising: A receiving unit, configured to receive an address allocation command, wherein the address allocation command includes N addresses to be allocated; A first acquisition unit, used for acquiring a first bus current on the serial data bus; a second acquisition unit, configured to control the first switch unit to close, and acquire a second bus current on the serial data bus; A first control unit, configured to detect that a first difference is less than a preset first threshold value, and control the second switch unit to close; the first difference is a difference between the first bus current and the second bus current; A third acquisition unit, used for acquiring a third bus current on the serial data bus; The address allocation unit is used to detect that the second difference is less than a preset second threshold value and obtain a target address from the N addresses to be allocated; the second difference is the difference between the first bus current and the third bus current.

10. A computer-readable storage medium, wherein the computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium, and a computer program is stored thereon, wherein: When the computer program is executed by a processor, the steps of the address allocation method according to any one of claims 3 to 8 are executed.

11. An address allocation device, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor runs the computer program, the steps of the address allocation method according to any one of claims 3 to 8 are performed.

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