Circuit board and electronic device

Abstract

This invention relates to the field of electronic technology, and discloses a circuit board and an electronic device. The circuit board includes: a board body, the surface of which has a chip mounting area and a signal connector mounting area arranged along a first direction; the chip mounting area has a first signal pin area at one end away from the signal connector mounting area, and the first signal pin area is furthest from the signal connector mounting area in the chip mounting area; the pins of the first signal pin area are connected to the corresponding pins of the signal connector mounting area via a first signal trace, and the first signal trace passes through the portion of the board body located on the bottom side of the chip mounting area, which can avoid the first signal trace going around to the part of the board body outside the chip mounting area, and directly using the space on the bottom side of the chip mounting area as the channel for the first signal trace can significantly shorten the length of the first signal trace and reduce losses.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a circuit board and an electronic device. Background Technology

[0002] Currently, with the increasing capacity of switching chips, the speed of SERDES (serializer / deserializer) is also increasing, from the early 10Gbps to the current 112Gbps. The higher the signal speed, the greater the signal loss per unit length on the transmission line. Therefore, shortening the length of high-speed traces on the PCB (Printed Circuit Board) and reducing total loss is a core aspect of SI (Signal Integrity) design.

[0003] Taking the standard of direct drive system as an example, the trace loss on the PCB is limited to 7dB, which is equivalent to a trace length of about 9 inches. Moreover, the current M8 level (the highest level) PCB must be used to meet the standard requirements.

[0004] refer to Figure 1 Taking the PCB design of a switch as an example, using the current industry-leading switching chip 02, PCB 01 has 512 pairs of high-speed SERDEs distributed around the periphery of chip 02, with the power pins of chip 02 located in the central area. Chip 02 is placed in the middle of PCB 01, and the entire lower edge of PCB 01 is equipped with optical port devices 03. The high-speed traces 04 in the top area of ​​chip 02 (the area away from the optical port devices 03) are interconnected with the optical port devices 03 in front. To avoid the traces 04 crossing, the top area can only connect to the optical port devices 03 at both ends, resulting in a relatively long trace length of nearly 12 inches, which does not meet the standard requirements. Summary of the Invention

[0005] This invention discloses a circuit board and electronic device that can shorten the length of traces without increasing costs, thereby reducing signal loss.

[0006] In a first aspect, a circuit board is provided, comprising: a board body, the surface of which has a chip mounting area and a signal connector mounting area arranged along a first direction; the chip mounting area has a first signal pin area at one end away from the signal connector mounting area, wherein the first signal pin area is furthest from the signal connector mounting area in the chip mounting area; the pins of the first signal pin area are connected to the corresponding pins of the signal connector mounting area via a first signal trace, wherein the first signal trace passes through the portion of the board body located on the bottom side of the chip mounting area, thereby avoiding the first signal trace from detouring to the portion of the board body outside the chip mounting area, and directly using the space on the bottom side of the chip mounting area as the channel for the first signal trace can significantly shorten the length of the first signal trace and reduce losses.

[0007] Optionally, at least one end of the chip mounting area in the second direction has a second signal pin area, and a power pin area is provided on the side of the second signal pin area away from the corresponding side of the chip mounting area. The first signal trace passes through the portion of the board located on the bottom side of the second signal pin area, and the second direction is perpendicular to the first direction.

[0008] Optionally, the board body includes a first board layer and a second board layer stacked together, the chip mounting area and the signal connector mounting area are located on the surface of the first board layer opposite to the second board layer; each second signal pin area includes a first sub-area, the pins of the first sub-area are connected to the corresponding pins of the signal connector mounting area through a first sub-signal trace, the first sub-signal trace passes through the portion of the first board layer located on the bottom side of the first sub-area; the first signal trace passes through the portion of the second board layer located on the bottom side of the first sub-area.

[0009] Optionally, each second signal pin area further includes a second sub-region. In each second signal pin area, the second sub-region is located between the first sub-region and the corresponding side of the chip mounting area. The pins of each second sub-region are connected to the corresponding pins of the signal connector mounting area via second sub-signal traces. The second sub-signal traces fan out from the second sub-region in a direction away from the corresponding first sub-region. Along the direction close to the signal connector mounting area, the second sub-signal traces corresponding to the pins of the second sub-region are gradually arranged inward. The inward side refers to the side of the second sub-region pointing towards the corresponding first sub-region.

[0010] Optionally, both the first signal trace and the first sub-signal trace are located inside any one of the second sub-signal traces in the corresponding second sub-region.

[0011] Optionally, the second sub-signal trace passes through both the first and second board layers; or, the second sub-signal trace passes through the second board layer.

[0012] Optionally, the chip mounting area has a third signal pin area at one end near the signal connector mounting area; the pins of the third signal pin area are connected to the corresponding pins of the signal connector mounting area via a second signal trace, the second signal trace passing through the board and fanning out towards the signal connector mounting area along the first direction.

[0013] Optionally, the first board layer includes a first dielectric layer and a first metal layer arranged alternately in sequence. The first board layer has a first metal via that penetrates the first board layer along the thickness direction and is connected to the first metal layer. The first sub-signal trace is formed by the first metal layer and the first metal via. The second board layer includes a second dielectric layer and a second metal layer arranged alternately in sequence. The second board layer has a second metal via that penetrates the second board layer along the thickness direction and is connected to the second metal layer. The first signal trace is formed by the second metal layer and the second metal via.

[0014] Optionally, the first layer and the second layer are each independently formed single boards, which are pressed together to form the board body.

[0015] In a second aspect, an electronic device is provided, comprising: a chip, a signal connector, and a circuit board as described in any of the above technical solutions, wherein the chip is mounted in the chip mounting area and is connected to the pins of the chip mounting area, and the signal connector is mounted in the signal connector mounting area and is connected to the pins of the signal connector mounting area.

[0016] Compared with the prior art, the electronic device and the circuit board have the same advantages, which will not be repeated here. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the circuit board, chip, and optical port device in the relevant technical solution.

[0018] Figure 2 This is a schematic diagram of the structure of the circuit board and signal connector provided in the embodiments of this application;

[0019] Figure 3 express Figure 2 A schematic diagram of the chip mounting area in the diagram;

[0020] Figure 4 express Figure 3 A cross-sectional view of point AA on the circuit board shown.

[0021] Figure 5 express Figure 2 A partial longitudinal cross-sectional view of the circuit board shown;

[0022] Figure 6 express Figure 2 The diagram shows the structure of the first layer of the circuit board. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Combination Figure 2 and Figure 3 :

[0025] The circuit board provided in this application embodiment includes, but is not limited to, a PCB (Printed Circuit Board). The circuit board includes: a board body 1, the surface of which has chip mounting areas S and signal connector mounting areas P arranged along a first direction (referring to the direction of the y-axis); a first signal pin area S1 is located at one end of the chip mounting area S furthest from the signal connector mounting area P; the pins of the first signal pin area S1 are connected to the corresponding pins of the signal connector mounting area P via a first signal trace B1 (their positions can be referenced). Figure 6 The signal connection is located at the bottom metal via M. The first signal trace B1 passes through the bottom part of the board 1 located in the chip mounting area S. This avoids the first signal trace B1 detouring to the part of the board 1 outside the chip mounting area S. By directly using the space at the bottom of the chip mounting area S as the channel for the first signal trace B1, the length of the first signal trace B1 can be significantly shortened, reducing losses. The pins can be serdes (serializer / deserializer).

[0026] In one specific embodiment, at least one end of the chip mounting region S in the second direction (referring to the direction where the x-axis is located) has a second signal pin area S2. Figure 2 and Figure 3In the chip mounting area S, each end has a second signal pin area S2. The second signal pin area S2 extends along the corresponding side of the chip mounting area S to make full use of the space on each side of the chip mounting area S to increase the number of outgoing lines. A power pin area S4 is provided on the side of the second signal pin area S2 away from the corresponding side of the chip mounting area S. The first signal trace B1 passes through the part of the board 1 located on the bottom side of the second signal pin area S2 without interfering with or being interfered with by the capacitors or other devices in the power pin area S4, thereby improving signal transmission performance and avoiding increasing the thickness or number of layers of the board 1. The second direction (referring to the x-axis direction) is perpendicular to the first direction (referring to the y-axis direction).

[0027] In one specific embodiment, combined with Figures 4 to 6 The board body 1 includes a first board layer 11 and a second board layer 12 stacked together. The chip mounting area S and the signal connector mounting area P are located on the surface of the first board layer 11 facing away from the second board layer 12. Each second signal pin area S2 includes a first sub-area S21, and the pins of the first sub-area S21 are routed through a first sub-signal trace. Figure 2 (Not shown) The corresponding pin signal of the signal connector mounting area P is connected, and the first sub-signal trace passes through the portion of the first board layer 11 located on the bottom side of the first sub-region S21; the first signal trace B1 passes through the portion of the second board layer 12 located on the bottom side of the first sub-region S21. Thus, to form the first sub-signal trace for routing the pins of the first sub-region S21, a metal via needs to be opened along the thickness direction (referring to the z-axis direction). If the first sub-signal trace is placed on the second board layer 12, the metal via corresponding to the first sub-signal trace will pass through the portion of the first board layer 11 corresponding to the first sub-region S21, resulting in no trace being able to be routed within the corresponding portion of the first board layer 11, and therefore the first signal trace B1 cannot pass through there. Conversely, if... Figure 4 Therefore, by placing the first sub-signal trace on the first layer 11 corresponding to the first sub-region S1, the metal via corresponding to the first sub-signal trace will only pass through the first layer 11 and will not interfere with the portion of the second layer 12 corresponding to the first sub-region S21. The clearance space reserved in the portion of the second layer 12 corresponding to the first sub-region S21 can be used to form the trace channel K of the first signal trace B1. At the same time, Figure 6 The diagram shows the opening of the metal vias on the first substrate 11. It can be seen that at the position corresponding to the first sub-region S21, the first substrate 11 is not obstructed by any metal vias, and this area forms the aforementioned trace channel K. Metal layers and dielectric layers can be alternately placed in the trace channel K, and the first signal trace B1 can be formed using metal vias and metal layers.

[0028] refer to Figure 2The first signal trace B1 first fans out in a direction away from the signal connector mounting area P, and then extends in two directions along the second direction (referring to the x-axis direction) towards the first sub-area S21 on both sides. After reaching the top of the first sub-area S21, it extends along the first direction (referring to the y-axis direction) along the trace channel K towards the signal connector mounting area P. The first sub-signal trace extends directly along the first direction (referring to the y-axis direction) towards the signal connector mounting area P. Since the first signal trace B1 and the first sub-signal trace are distributed in different board layers, they will not interfere with each other or cross each other, and can be connected to different signal connectors 2 signals in the signal connector mounting area P respectively.

[0029] In one specific embodiment, each second signal pin area S2 further includes a second sub-area S22. In each second signal pin area S2, the second sub-area S22 is located between the corresponding side of the first sub-area S21 and the chip mounting area S, that is, the second sub-area S22 is located outside the corresponding first sub-area S21. The pins of each second sub-area S22 are connected to the corresponding pins of the signal connector mounting area P through second sub-signal traces B22. The second sub-signal traces B22 fan out from the second sub-area S22 in a direction away from the corresponding first sub-area S21. As the second sub-signal traces B22 fan outward, they gradually move closer to the signal connector mounting area P. Along the direction close to the signal connector mounting area P, the second sub-signal traces B22 corresponding to the pins of the second sub-area S22 are gradually arranged inward. The inward side refers to the side of the second sub-area S22 in the same second signal pin area S2 pointing towards the corresponding first sub-area S21, to prevent different signal traces from crossing and increasing the thickness or number of layers of the circuit board. Figure 2 The further a pin in the second sub-region S22 is from the signal connector mounting area P, the further the corresponding pin in the signal connector mounting area P is from the chip mounting area S in the second direction (referencing the x-axis direction). Different second sub-signal traces B22 are less likely to cross each other. Since the second sub-region S22 is located outside the corresponding first sub-region S21, the second sub-region S22 can fan out in a direction away from the corresponding first sub-region S22. Conversely, if the second sub-region S22 is located inside the corresponding first sub-region S21, the second sub-signal trace B22 will be blocked by the first signal trace B1 and the first sub-signal trace, and cannot fan out.

[0030] In one specific embodiment, the first signal trace B1 and the first sub-signal trace are both located inside any of the second sub-signal traces B22 in the corresponding second sub-region S22. The definition of "inside" is as described above, in order to prevent the second sub-signal trace B22 from intersecting with the first signal trace B1 and the first sub-signal trace.

[0031] In one specific embodiment, the second sub-signal trace B22 passes through both the first board layer 11 and the second board layer 12 to increase the number of fan-out traces B22 in the second sub-region S22, which is beneficial to increase the number of pins and improve performance; or, the second sub-signal trace B22 passes through the second board layer 12, which is beneficial to avoid the first sub-signal trace in the first board layer 11 and provide fan-out space for the first sub-signal trace.

[0032] In one specific embodiment, the chip mounting area S has a third signal pin area S3 at one end near the signal connector mounting area P; the pins of the third signal pin area S3 are connected to the corresponding pins of the signal connector mounting area P through a second signal trace B3. The second signal trace B3 runs through the board 1 and fans out towards the signal connector mounting area P along a first direction (referencing the direction of the y-axis). The second signal trace B3 has the shortest trace length and is less likely to interfere with other signal traces.

[0033] In one specific embodiment, reference Figure 5 The first plate layer 11 includes a first dielectric layer 112 and a first metal layer 111 arranged alternately in sequence. The first plate layer 11 has a first metal via T1 that penetrates the first plate layer 11 along the thickness direction (referring to the z-axis direction) and is connected to the first metal layer 111. The first metal layer 111 and the first metal via T1 are used to form a first sub-signal trace, which is convenient for processing and can stably transmit the pin signals of the first sub-region S21. The second plate layer 12 includes a second dielectric layer 122 and a second metal layer 121 arranged alternately in sequence. The second plate layer 12 has a second metal via T2 that penetrates the second plate layer 12 along the thickness direction (referring to the z-axis direction) and is connected to the second metal layer 121. The second metal layer 121 and the second metal via T2 are used to form a first signal trace B1, which is convenient for processing and can stably transmit the pin signals of the first signal pin region S1. The first metal via T1 and the second metal via T2 can respectively form a metal via penetrating the first plate 11 and a metal via penetrating the second plate 12. For example, the aforementioned sub-signal trace and the first signal trace B1 can be formed using this type of metal via. When it is necessary to form a second sub-signal trace B22 that simultaneously penetrates the first plate 11 and the second plate 12, a through hole T that penetrates the entire plate 1 can be formed as a metal via.

[0034] In one specific embodiment, the first plate layer 11 and the second plate layer 12 are each independently formed single boards, which are pressed together to form the plate body 1. The first plate layer 11 serves as the upper N-plate, and the second plate layer 12 serves as the lower N-plate. Due to technical limitations, when forming metal vias, they can only completely penetrate the plate. In some cases (such as forming the first sub-signal trace), only the first metal via T1 needs to be formed at the corresponding position of the first plate 11. Therefore, only the first through-hole T1 needs to be formed in the first plate layer 11, which is a single board, and there is no need to form the second metal via T2 at the corresponding position of the second plate layer 12, which helps to save the wiring space in the second plate layer 12; similarly, it also helps to save the wiring space in the first plate layer 11. In this case, after the first plate layer 11 and the second plate layer 12 are pressed together, a through hole T is drilled to form the through-hole T that penetrates the entire plate body 1.

[0035] Using upper and lower N-boards to achieve reuse of wiring space in densely via areas of the chip, and after testing in certain specific embodiments, the first signal trace B1 of the first signal pin area S1 is relative to... Figure 1 The corresponding technical solution can shorten the wiring by about 30%. It makes full use of the wiring space, allowing cables to exit from four sides simultaneously, thus solving the problem of cable crossing.

[0036] With the loss remaining constant, this solution can reduce the material grade by one level. In certain specific embodiments, testing has shown that the overall PCB cost can be reduced by approximately 20%. Furthermore, the solution provided in the above embodiments simplifies the architecture and provides a pure PCB solution that meets direct-drive requirements.

[0037] Based on the same inventive concept, this application also provides an electronic device, which can be a switch, router, or server. The electronic device includes: a chip, a signal connector 2, and the circuit board provided in the above embodiments. The chip is mounted in a chip mounting area S and connected to the pin signals of the chip mounting area S. The signal connector 2 is mounted in a signal connector mounting area P and connected to the pin signals of the signal connector mounting area P. Its effect is similar to that of the circuit board described above. The signal connector 2 can be an optical port device such as an optical module.

[0038] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A circuit board, characterized by, Includes: a board body, the surface of which has a chip mounting area and a signal connector mounting area arranged along a first direction; the chip mounting area is used to mount a chip and to connect to the chip via signals; The chip mounting area has a first signal pin area at one end away from the signal connector mounting area; The pins of the first signal pin area are connected to the corresponding pins of the signal connector mounting area through the first signal trace, and the first signal trace passes through the part of the board located on the bottom side of the chip mounting area.

2. The circuit board of claim 1, wherein At least one end of the chip mounting area in the second direction has a second signal pin area, and a power pin area is provided on the side of the second signal pin area away from the corresponding side of the chip mounting area. The first signal trace passes through the part of the board located on the bottom side of the second signal pin area, and the second direction is perpendicular to the first direction.

3. The circuit board of claim 2, wherein, The board body includes a first board layer and a second board layer stacked together, and the chip mounting area and the signal connector mounting area are located on the surface of the first board layer opposite to the second board layer. Each of the second signal pin areas includes a first sub-area, and the pins of the first sub-area are connected to the corresponding pin signals of the signal connector mounting area through a first sub-signal trace. The first sub-signal trace passes through the portion of the first board layer located on the bottom side of the first sub-area. The first signal trace passes through the portion of the second board layer located on the bottom side of the first sub-region.

4. The circuit board according to claim 3, characterized in that, Each second signal pin area further includes a second sub-region, wherein in each second signal pin area, the second sub-region is located between the first sub-region and the corresponding side of the chip mounting area; Each pin of the second sub-region is connected to the corresponding pin signal of the signal connector mounting area through a second sub-signal trace. The second sub-signal trace fans out from the second sub-region in a direction away from the corresponding first sub-region. Along the direction close to the mounting area of ​​the signal connector, the second sub-signal traces corresponding to the pins of the second sub-region are gradually arranged inwards, where the inwards refers to the side of the second sub-region pointing towards the corresponding first sub-region.

5. The circuit board according to claim 4, characterized in that, Both the first signal trace and the first sub-signal trace are located inside any one of the second sub-signal traces in the corresponding second sub-region.

6. The circuit board according to claim 4, characterized in that, The second sub-signal trace runs through both the first and second board layers; or, The second sub-signal trace runs through the second board layer.

7. The circuit board according to claim 1, characterized in that, The chip mounting area has a third signal pin area at one end near the signal connector mounting area; The pins of the third signal pin area are connected to the corresponding pins of the signal connector mounting area via a second signal trace. The second signal trace runs through the board and extends outwards towards the signal connector mounting area along the first direction.

8. The circuit board according to any one of claims 3 to 6, characterized in that, The first board layer includes a first dielectric layer and a first metal layer arranged alternately in sequence. The first board layer has a first metal via that penetrates the first board layer along the thickness direction and is connected to the first metal layer. The first sub-signal trace is formed by the first metal layer and the first metal via. The second plate layer includes a second dielectric layer and a second metal layer arranged alternately in sequence. The second plate layer has a second metal via that penetrates the second plate layer along the thickness direction and is connected to the second metal layer. The first signal trace is formed by the second metal layer and the second metal via.

9. The circuit board according to any one of claims 3 to 6, characterized in that, The first and second layers are each independently formed single boards, which are pressed together to form the board body.

10. An electronic device, characterized in that, include: The chip, the signal connector, and the circuit board according to any one of claims 1 to 9, wherein the chip is mounted in the chip mounting area and is connected to the pin signals of the chip mounting area, and the signal connector is mounted in the signal connector mounting area and is connected to the pin signals of the signal connector mounting area.

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