Display panel, driving method thereof, and display device

Abstract

The application discloses a display panel and a driving method thereof, and a display device, and belongs to the technical field of display. The sub-pixel of the display panel comprises a pixel circuit and a light emitting element. The pixel circuit comprises at least a driving transistor, a data writing module, a threshold compensation module and a bias adjustment module. The data writing module is used for providing a data signal to the driving transistor. The bias adjustment module is used for adjusting the bias state of the driving transistor through a bias adjustment signal. The threshold compensation module is used for detecting and compensating the deviation of the threshold voltage of the driving transistor. The first power signal connected to the first electrode of the driving transistor is a fixed value. The second power signal connected to the second electrode of the driving transistor is a variable value. The bias adjustment signal is a variable value. The driving method is applied to the display panel. The display device comprises the display panel. The application can improve the problem of poor display effect caused by the threshold drift of the driving transistor after long-term work, and can reduce the power consumption of the panel.

Description

[0001] This application is a divisional application of application number 202211456256.4 filed on November 21, 2022, entitled "Display Panel and Driving Method Thereof, Display Device". Technical Field

[0002] This invention relates to the field of display technology, and more specifically, to a display panel and its driving method and display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) possess characteristics such as self-illumination, fast response, wide color gamut, wide viewing angle, and high brightness. They can be used to fabricate thin and flexible display devices, and are thus gradually becoming a key research focus in the field of display technology. OLEDs require current to drive them. In display applications, driving transistors in the pixel circuit are controlled to provide driving current to the OLEDs, enabling them to emit light. Furthermore, a stable driving current is needed to ensure display performance during application.

[0004] In existing technologies, the driving transistors of pixel circuits suffer from threshold voltage drift after long-term operation, which affects the display effect. Furthermore, existing display panels consume a lot of power during display, which limits the further application of display panels.

[0005] Therefore, providing a display panel, its driving method, and display device that can both improve the poor display effect caused by threshold drift after long-term operation of the driving transistor and reduce panel power consumption is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a display panel and its driving method and display device to solve the problems of threshold voltage drift of driving transistors in the prior art display panel after long-term operation, which affects the display effect and high power consumption during display.

[0007] This invention discloses a display panel, comprising: a plurality of sub-pixels, each sub-pixel including an electrically connected pixel circuit and a light-emitting element; the pixel circuit includes at least a driving transistor, a data writing module, a threshold compensation module, and a bias adjustment module; the first terminal of the driving transistor is electrically connected to the data writing module and the bias adjustment module respectively, and the driving transistor is used to generate a driving current; the first terminal of the data writing module is electrically connected to a data signal, and the second terminal of the data writing module is electrically connected to the first terminal of the driving transistor, and the data writing module is used to provide a data signal to the driving transistor; the first terminal of the bias adjustment module is electrically connected to a bias adjustment signal, and the second terminal of the bias adjustment module is electrically connected to the first terminal of the driving transistor, and the bias adjustment module is used to provide a bias adjustment signal to the first terminal of the driving transistor to adjust the bias state of the driving transistor; the threshold compensation module is connected between the gate of the driving transistor and the second terminal of the driving transistor, and the threshold compensation module is used to detect and compensate for the deviation of the threshold voltage of the driving transistor; the first terminal of the driving transistor is connected to a first power supply signal, and the second terminal of the driving transistor is connected to a second power supply signal; the first power supply signal is a fixed value, the second power supply signal is a variable value, and the bias adjustment signal is a variable value.

[0008] Based on the same inventive concept, this invention also discloses a driving method for a display panel, which is applied to the aforementioned display panel. The driving method includes at least: a first bias voltage adjustment stage, a threshold compensation and data writing stage, and a light emission stage. The first bias voltage adjustment stage is performed before the threshold compensation and data writing stage. In the first bias voltage adjustment stage, a bias adjustment module is turned on, and a bias adjustment signal is provided to the first electrode of the driving transistor to adjust the bias state of the driving transistor. In the threshold compensation and data writing stage, a threshold compensation module detects and compensates for the deviation of the threshold voltage of the driving transistor, and a data writing module writes the compensated threshold voltage deviation and a data signal together into the driving transistor. In the light emission stage, the driving transistor generates a driving current to drive the light-emitting element to emit light. The driving method also includes a power supply adjustment stage. In the power supply adjustment stage, the value of a second power supply signal is adjusted according to the change in the display brightness of the display panel, and the value of a bias adjustment signal is adjusted according to the change in the value of the second power supply signal.

[0009] Based on the same inventive concept, the present invention also discloses a display device, which includes the above-described display panel.

[0010] Compared with the prior art, the display panel, driving method, and display device provided by the present invention achieve at least the following beneficial effects:

[0011] The sub-pixels of the display panel provided by this invention may include electrically connected pixel circuits and light-emitting elements. The pixel circuits are used to control the light-emitting elements to emit light. The pixel circuits include at least a driving transistor, a data writing module, a threshold compensation module, and a bias adjustment module. The data writing module provides data signals to the driving transistor. The threshold compensation module detects and compensates for the deviation of the threshold voltage of the driving transistor, and provides the compensated threshold voltage deviation and the data signal provided by the data line itself to the driving transistor to achieve threshold compensation. This can improve display unevenness caused by differences in the threshold voltage of the driving transistor due to manufacturing processes and threshold voltage drift caused by transistor aging. The bias adjustment module provides a bias adjustment signal to the driving transistor to adjust the bias state of the driving transistor, improve the threshold drift problem of the driving transistor, and enhance the display effect. The first terminal of the driving transistor is connected to a first power supply signal, and the second terminal is connected to a second power supply signal. When the pixel circuit drives the light-emitting element electrically connected to it to emit light, the driving transistor can generate a driving current to drive the light-emitting element to emit light through the conductive path between the first power supply signal, the driving transistor, the light-emitting element, and the second power supply signal, thereby achieving the light-emitting effect of the light-emitting element. In this invention, the first power signal connected to the first terminal of the driving transistor in the pixel circuit is set to a fixed value, while the second power signal connected to the second terminal of the driving transistor is set to a variable value. The voltage value of the second power signal can change according to the brightness required by the display panel, which helps to save the overall power consumption of the panel. When the display panel uses a dynamically changing second power signal to reduce panel power consumption according to the brightness requirements of the light emission display, the bias adjustment signal connected to the bias adjustment module also changes dynamically accordingly. This can prevent the brightness of the light-emitting element from deviating from the originally required brightness due to the change of the second power signal, thereby improving the display quality of the display panel.

[0012] Of course, any product implementing this invention need not necessarily achieve all of the technical effects described above at the same time.

[0013] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0015] Figure 1 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention;

[0016] Figure 2 yes Figure 1A schematic diagram of the circuit connection structure of a neutron pixel;

[0017] Figure 3 yes Figure 1 A schematic diagram of another circuit connection structure for neutron pixels;

[0018] Figure 4 yes Figure 3 Comparison chart of the changing trends of the effective level of the first scan signal;

[0019] Figure 5 yes Figure 1 A schematic diagram of another circuit connection structure for neutron pixels;

[0020] Figure 6 yes Figure 1 A schematic diagram of another circuit connection structure for neutron pixels;

[0021] Figure 7 yes Figure 6 Timing diagram of the middle pixel circuit;

[0022] Figure 8 yes Figure 1 A schematic diagram of another circuit connection structure for neutron pixels;

[0023] Figure 9 yes Figure 1 A schematic diagram of another circuit connection structure for neutron pixels;

[0024] Figure 10 yes Figure 9 Timing diagram of the middle pixel circuit;

[0025] Figure 11 This is a flowchart of the driving method provided in an embodiment of the present invention;

[0026] Figure 12 yes Figure 6 Another timing diagram of the middle pixel circuit;

[0027] Figure 13 yes Figure 6 Another timing diagram of the middle pixel circuit;

[0028] Figure 14 This is a schematic diagram of the planar structure of the display device provided in an embodiment of the present invention. Detailed Implementation

[0029] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0030] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0031] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0032] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0033] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0034] Please refer to the reference. Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention. Figure 2 yes Figure 1 A schematic diagram of the circuit connection structure of a sub-pixel. The display panel 000 provided in this embodiment includes: a plurality of sub-pixels 00, each sub-pixel 00 including a pixel circuit 10 and a light-emitting element 20 electrically connected.

[0035] The pixel circuit 10 includes at least a driving transistor DT, a data writing module 101, a threshold compensation module 102, and a bias adjustment module 103;

[0036] The first terminal of the driving transistor DT is electrically connected to the data writing module 101 and the bias adjustment module 103 respectively. The driving transistor DT is used to generate driving current.

[0037] The first terminal of the data writing module 101 is electrically connected to the data signal Vdata, and the second terminal of the data writing module 101 is electrically connected to the first terminal of the driving transistor DT. The data writing module 101 is used to provide the data signal Vdata to the driving transistor DT.

[0038] The first terminal of the bias adjustment module 103 is electrically connected to the bias adjustment signal Vbias, and the second terminal of the bias adjustment module 103 is electrically connected to the first terminal of the driving transistor DT. The bias adjustment module 103 is used to provide the bias adjustment signal Vbias to the first terminal of the driving transistor DT to adjust the bias state of the driving transistor DT.

[0039] The threshold compensation module 102 is connected between the gate of the driving transistor DT and the second terminal of the driving transistor DT. The threshold compensation module 102 is used to detect and compensate for the deviation of the threshold voltage of the driving transistor DT.

[0040] The first terminal of the driving transistor DT is connected to the first power supply signal Vpvdd, and the second terminal of the driving transistor DT is connected to the second power supply signal Vpvee; the first power supply signal Vpvdd is a fixed value, the second power supply signal Vpvee is a variable value, and the bias adjustment signal Vbias is a variable value.

[0041] Specifically, the display panel 000 provided in this embodiment can be an organic light-emitting display panel, or it can be any other display panel that uses the driving transistor DT in the pixel circuit 10 to provide driving current so that the light-emitting element 20 emits light. The light-emitting element 20 in this embodiment can be an organic light-emitting diode, or in some other optional embodiments, the light-emitting element 20 can also be a micro light-emitting diode or a sub-millimeter light-emitting diode. This embodiment does not limit this; this embodiment uses an organic light-emitting diode display panel as an example for illustration. The display panel 000 in this embodiment includes a plurality of sub-pixels 00. Optionally, the plurality of sub-pixels 00 in this embodiment can be arranged in an array, that is, the plurality of sub-pixels 00 are arranged along the first direction X to form a sub-pixel row, the plurality of sub-pixel rows are arranged along the second direction Y, the plurality of sub-pixels 00 are arranged along the second direction Y to form a sub-pixel column, and the plurality of sub-pixel columns are arranged along the first direction X to form an array arrangement of sub-pixel 00 structures; wherein the first direction X and the second direction Y can be understood as intersecting or perpendicular to each other in directions parallel to the plane where the display panel 000 is located. Alternatively, in some other optional embodiments, the multiple sub-pixels 00 can be arranged in other ways. This embodiment does not limit this to any particular arrangement. Figure 1This example illustrates the arrangement of multiple sub-pixels 00. Each sub-pixel 00 may include an electrically connected pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 controls the light-emitting element 20 to emit light. Since the light-emitting element 20 in an organic light-emitting diode (OLED) display panel is generally an OLED, and OLEDs are current-driven devices, a corresponding pixel circuit 10 is needed to provide a driving current to the light-emitting element 20 so that it can emit light. In this embodiment, the pixel circuit 10 includes at least a driving transistor DT, a data writing module 101, a threshold compensation module 102, and a bias adjustment module 103. The first terminal of the driving transistor DT is electrically connected to the data writing module 101 and the bias adjustment module 103, respectively. The driving transistor DT generates a driving current. The first terminal of the driving transistor DT can be understood as the source of the driving transistor DT, and the second terminal of the driving transistor DT can be understood as the drain of the driving transistor DT. Alternatively, the first terminal of the driving transistor DT can be understood as the drain of the driving transistor DT, and the second terminal of the driving transistor DT can be understood as the source of the driving transistor DT. This embodiment does not limit this interpretation. The first terminal of the data writing module 101 is electrically connected to the data signal Vdata. Optionally, the first terminal of the data writing module 101 can be connected to the data line S in the display panel 000, and the data signal Vdata is transmitted to the first terminal of the data writing module 101 through the data line S. The second terminal of the data writing module 101 is electrically connected to the first electrode of the driving transistor DT. The data writing module 101 is used to provide the data signal Vdata to the driving transistor DT. The threshold compensation module 102 is connected between the gate of the driving transistor DT and the second electrode of the driving transistor DT. The threshold compensation module 102 is used to detect and compensate for the deviation of the threshold voltage of the driving transistor DT, and provides the compensated threshold voltage deviation and the data signal provided by the data line itself to the driving transistor DT to achieve threshold compensation of the driving transistor DT. In this embodiment, the threshold compensation module 102 can improve the display unevenness caused by the threshold voltage difference of the driving transistor DT caused by the manufacturing process and the threshold voltage drift of the driving transistor DT caused by transistor aging.

[0042] In existing technologies, during the driving cycle of a pixel circuit driving a light-emitting element for display, when the pixel circuit operates in the light-emitting stage, the gate potential of the driving transistor is higher than its secondary electrode (such as the drain) potential. This forward bias causes a hysteresis effect in the driving transistor. Prolonged operation in this state leads to ion polarization within the driving transistor, resulting in a built-in electric field. This causes the threshold voltage of the driving transistor to continuously increase, and the threshold voltage drift results in unstable display brightness during image switching, which the human eye can perceive as flickering. Therefore, the hysteresis effect of the driving transistor is a significant factor affecting display quality. The threshold voltage shift caused by the hysteresis effect is on the nanosecond level, while the threshold compensation module in existing pixel circuits only compensates for thresholds on the microsecond or millisecond level. This indicates that the existing conventional threshold compensation module in pixel circuits is insufficient to adequately compensate for the threshold voltage shift caused by the hysteresis effect. Since the driving transistor in the pixel circuit operates in a forward bias state to provide driving current to the light-emitting element, prolonged operation in this bias state leads to threshold shift, thus affecting display quality.

[0043] Therefore, the pixel circuit 10 in this embodiment also includes a bias adjustment module 103. The first terminal of the bias adjustment module 103 is electrically connected to a bias adjustment signal Vbias, and the second terminal of the bias adjustment module 103 is electrically connected to the first electrode of the driving transistor DT. The bias adjustment module 103 is used to provide the bias adjustment signal Vbias to the first electrode of the driving transistor DT, adjusting the bias state of the driving transistor DT. By controlling the bias adjustment module 103 to write the bias adjustment signal Vbias to the first electrode of the driving transistor DT during the partial operation of the pixel circuit 10, the bias state of the driving transistor DT is adjusted, improving the threshold drift problem of the driving transistor DT and enhancing the display effect. It is understood that this embodiment does not limit the operating time of the bias adjustment module 103, only requiring it to operate before the light-emitting element 20 emits light. Optionally, in this embodiment, the bias adjustment signal Vbias can be provided by the bias signal line (not shown in the figure) in the display panel 000. Alternatively, in some other optional embodiments, the bias adjustment signal Vbias can also reuse the driving signal included in the pixel circuit 10 itself, such as reusing the data signal to achieve bias adjustment. Or, when performing bias adjustment on the current row, the data signal of the next row can be reused to perform bias adjustment on the driving transistor DT of the current row. This embodiment does not limit this, and you can refer to the bias adjustment structure in the related technology for a specific understanding.

[0044] It is understood that this embodiment is only an example illustrating the electrical connection structure of the pixel circuit 10 of each sub-pixel 00 in the display panel 000. In specific implementation, the pixel circuit 10 may also include other structures, such as a reset module for resetting, a light emission control module for controlling the light emission of the light-emitting element 20, etc. This embodiment will not elaborate on these details. For specific understanding, please refer to the circuit structure of the organic light-emitting diode display panel in the related art.

[0045] In this embodiment, the first terminal of the driving transistor DT is connected to the first power supply signal Vpvdd, and the second terminal of the driving transistor DT is connected to the second power supply signal Vpvee. Optionally, a light-emitting element 20 can be provided between the second terminal of the driving transistor DT and the second power supply signal Vpvee. It can be understood that the connection between the first terminal of the driving transistor DT and the first power supply signal Vpvdd in this embodiment can be understood as including multiple ways to achieve electrical connection between the two. For example, if there are no other structures between the first terminal of the driving transistor DT and the first power supply signal Vpvdd, then the first terminal of the driving transistor DT and the first power supply signal Vpvdd can be directly connected to achieve electrical connection. If there are other structures between the first terminal of the driving transistor DT and the first power supply signal Vpvdd, such as the pixel circuit 10 including a first light-emitting control transistor connected to the first terminal of the driving transistor DT, then when the first light-emitting control transistor is turned on, the first terminal of the driving transistor DT and the first power supply signal Vpvdd can also achieve electrical connection. This embodiment does not limit the specific structure of the electrical connection between the first terminal of the driving transistor DT and the first power supply signal Vpvdd. In specific implementation, it can be understood according to the actual design structure of the pixel circuit. In this embodiment, the second terminal of the driving transistor DT is connected to the second power supply signal Vpvee. This can also be understood as the pixel circuit 10 further including a second light-emitting control transistor connected to the second terminal of the driving transistor DT. In this case, when the second light-emitting control transistor is turned on, the second terminal of the driving transistor DT can also be electrically connected to the light-emitting element 20 and the second power supply signal Vpvee. In this embodiment, the first power supply signal Vpvdd can be provided by the first power signal line (not shown in the figure) in the display panel 000, and the second power supply signal Vpvee can be provided by the second power signal line (not shown in the figure) in the display panel 000. This will not be elaborated upon in this embodiment. When the pixel circuit 10 drives the light-emitting element 20, which is electrically connected to it, to emit light, the driving transistor DT generates a driving current to drive the light-emitting element 20 to emit light through the conductive path between the first power supply signal Vpvdd, the driving transistor DT, the light-emitting element 20, and the second power supply signal Vpvee, thereby achieving the light-emitting effect of the light-emitting element 20.

[0046] In this embodiment, the first power supply signal Vpvdd connected to the first terminal of the driving transistor DT in the pixel circuit 10 is set to a fixed value, and the second power supply signal Vpvee connected to the second terminal of the driving transistor DT is set to a variable value. Since the power consumption of the pixel circuit 10 is mainly determined by the voltage difference between the first power supply signal Vpvdd and the second power supply signal Vpvee multiplied by the driving current in the conductive path, and the driving current is affected by the brightness of the light-emitting display, if power consumption needs to be saved under a certain brightness of the light-emitting display, the voltage difference between the first power supply signal Vpvdd and the second power supply signal Vpvee can be reduced. Therefore, in this embodiment, the first power signal Vpvdd is set to a fixed value, and the second power signal Vpvee is set to a variable value. The voltage value of the second power signal Vpvee can change according to the brightness required by the display panel 000. If the required brightness of the display panel 000 decreases, that is, when a large voltage difference between the first power signal Vpvdd and the second power signal Vpvee is not required, the voltage value of the second power signal Vpvee can be increased to reduce the voltage difference between the first power signal Vpvdd and the second power signal Vpvee, thereby saving power consumption of the panel. Alternatively, when the required brightness of the entire display panel 000 is high, the voltage value of the second power signal Vpvee can be decreased to increase the voltage difference between the first power signal Vpvdd and the second power signal Vpvee, thus ensuring the overall brightness of the display panel 000. Alternatively, when the usage scenario changes to only displaying a very small area of ​​the 000 display panel that requires high brightness, while other areas have zero brightness or are very dark, the value of the second power signal Vpvee can be increased to reduce the voltage difference between the first power signal Vpvdd and the second power signal Vpvee. For example, the voltage value of the second power signal Vpvee can be increased from the original 0V to 0.3V, thereby reducing the voltage difference between the first power signal Vpvdd and the second power signal Vpvee, which helps to save the overall power consumption of the panel.

[0047] However, when dynamically adjusting the value of the second power supply signal Vpvee to reduce power consumption, during the operation of the pixel circuit 10, as the second power supply signal Vpvee dynamically changes, the second terminal of the driving transistor DT... Figure 2The potential of the third node N3 in the pixel circuit changes accordingly, and the bias characteristics of the driving transistor DT also change. If a fixed bias adjustment signal Vbias is used to adjust the bias state of the driving transistor DT, during the hold frame stage of the pixel circuit 10, the working potential of the driving transistor DT is the potential of the gate of the driving transistor DT, i.e., the first node N1, minus the voltage value of the first power supply signal Vpvdd minus the potential of the third node N3. The potential of the third node N3 is directly related to the second power supply signal Vpvee. When the display panel 000 dynamically adjusts the value of the second power supply signal Vpvee to reduce power consumption, the potential of the third node N3 will also change dynamically. Thus, the dynamic change of the potential of the third node N3 causes the working potential of the driving transistor DT, i.e., the potential of the first node N1, to change, which in turn causes the bias characteristics of the driving transistor DT to change. When the pixel circuit 10 is working in the hold frame stage, the state of the driving transistor DT will also change, resulting in a deviation in the light emission brightness, which is not conducive to improving the display quality of the display panel 000.

[0048] Therefore, in order to reduce panel power consumption while ensuring display quality, this embodiment sets the bias adjustment signal Vbias to a variable value. That is, the bias adjustment signal Vbias connected to the bias adjustment module 103 changes with the change of the second power supply signal Vpvee, so as to adjust the bias state of the driving transistor DT through the bias adjustment signal Vbias connected to the bias adjustment module 103. Specifically, when the bias adjustment module 103 is turned on, the bias adjustment signal Vbias is applied to the first terminal of the driving transistor DT, i.e., the second node N2. Since the driving transistor DT is turned on, the bias adjustment signal Vbias is also transmitted to the second terminal of the driving transistor DT, i.e., the third node N3. At this time, the threshold compensation module 102 is also turned on, so the bias adjustment signal Vbias is written to the gate of the driving transistor DT, i.e., the first node N1. Since the bias adjustment signal Vbias is a relatively high voltage value, regardless of the image displayed in the previous frame, the driving transistor DT needs to be written with the bias adjustment signal Vbias once when writing to the current image. This can reduce the bias effect of the image displayed in the previous frame, making the state of the driving transistor DT closer to the preset value when writing to the current image. This reduces the bias difference of the driving transistor DT when displaying the current frame and the previous frame, improves the threshold drift problem of the driving transistor DT, and enhances the display effect. Due to the changing second power supply signal... The bias adjustment signal Vpvee can reduce panel power consumption. Therefore, in this embodiment, by changing the bias adjustment signal Vbias, the bias adjustment signal Vbias connected to the bias adjustment module 103 also changes dynamically according to the brightness requirements of the display panel. For example, when the brightness required by the display panel 000 is low, and it is necessary to reduce the voltage difference between the first power signal Vpvdd and the second power signal Vpvee, the second power signal Vpvee is raised. When the second power signal Vpvee is raised, the potential of the third node N3 is also raised. Therefore, the operating potential of the driving transistor DT is the driving transistor's operating potential. The value of the potential of the DT gate (i.e., the first node N1) minus the voltage value of the first power supply signal Vpvdd minus the potential of the third node N3 will decrease. After the decrease, it is equivalent to the negative bias voltage (i.e., reverse bias) of the driving transistor DT will be enhanced when the pixel circuit 10 controls the light-emitting element 20 to emit light. Therefore, in order to ensure the adjustment effect of the bias state of the driving transistor DT, it is necessary to weaken the negative bias state of the driving transistor DT. That is, at this time, the voltage value of the bias adjustment signal Vbias can be reduced to avoid the light-emitting brightness of the light-emitting element 20 deviating from the original required brightness due to the change of the second power supply signal Vpvee, which is conducive to improving the display quality of the display panel 000.

[0049] Understandably, when the display panel 000 is an organic light-emitting diode (OLED) display panel, the signal line layout in the display panel 000 is relatively complex. The display panel 000 may include, in addition to... Figure 1 The data line S shown in the figure may also include other signal lines such as scan lines, reference voltage lines, and power signal lines (not shown in the figure). One sub-pixel row may correspond to multiple scan lines. In specific implementation, the layout structure of the signal traces in this embodiment can be understood according to the actual situation.

[0050] It is understood that the pixel circuit 10 in this embodiment is illustrated by taking the driving transistor DT as a P-type transistor. In specific implementation, the type of driving transistor DT includes but is not limited to this, and this embodiment does not limit it.

[0051] It should be noted that the display panel 000 provided in this embodiment can be an organic light-emitting diode display panel. The figure in this embodiment is only an example of the structure of the display panel. In specific implementation, the structure of the display panel 000 includes but is not limited to this. It may also include other structures that can realize the display function. For details, please refer to the structure of organic light-emitting diode display panels in related technologies. This embodiment will not elaborate on it here.

[0052] In some alternative embodiments, please continue to refer to the references. Figure 1 and Figure 2 In this embodiment, the brightness variation trend of the display panel 000 is inversely proportional to the variation trend of the second power signal Vpvee, and the bias adjustment signal Vbias is inversely proportional to the variation trend of the second power signal Vpvee. Optionally, when the value of the second power signal Vpvee increases, the value of the bias adjustment signal Vbias decreases.

[0053] This embodiment explains that the power consumption of the pixel circuit 10 is mainly determined by the voltage difference between the first power signal Vpvdd and the second power signal Vpvee multiplied by the driving current in the conductive path. Since the driving current is affected by the brightness of the light-emitting display, power saving can be achieved by reducing the voltage difference between the first power signal Vpvdd and the second power signal Vpvee at a certain brightness level. The power consumption of the light-emitting element 20 can be calculated using P = UI, where P represents the power consumption of the light-emitting element 20, U represents the voltage difference between the first power signal Vpvdd and the second power signal Vpvee, and I represents the driving current flowing through the conductive path formed by the driving transistor DT between the first power signal Vpvdd and the second power signal Vpvee and the light-emitting element 20. When the display brightness of the display panel 000 remains constant (i.e., I remains constant), the smaller the voltage difference U between the first power signal Vpvdd and the second power signal Vpvee, the smaller the power consumption P of the light-emitting element 20. Therefore, based on the change in display brightness of the display panel 000, the value of the second power signal Vpvee can be dynamically adjusted, effectively reducing the power consumption of the light-emitting element 20, and thus reducing the overall power consumption of the display panel 000. Therefore, in this embodiment, the first power signal Vpvdd is set to a fixed value, and the second power signal Vpvee is a variable value. The voltage value of the second power signal Vpvee can change with the brightness required by the display panel 000, and the trend of the display brightness change of the display panel 000 is inversely proportional to the trend of the second power signal Vpvee. When the required light-emitting display brightness of the display panel 000 decreases, i.e., when a large voltage difference between the first power signal Vpvdd and the second power signal Vpvee is not required, the voltage value of the second power signal Vpvee can be increased to reduce the voltage difference between the first power signal Vpvdd and the second power signal Vpvee. Conversely, when the required light-emitting display brightness of the entire display panel 000 is high, the voltage value of the second power signal Vpvee can be decreased. The voltage value of Vpvee increases the voltage difference between the first power signal Vpvdd and the second power signal Vpvee, ensuring the overall brightness of the display panel 000. Specifically, when the required display brightness of the display panel 000 is high, decreasing the voltage value of the second power signal Vpvee increases the voltage difference between the first power signal Vpvdd and the second power signal Vpvee. Conversely, when the required display brightness of the display panel 000 is low, increasing the voltage value of the second power signal Vpvee decreases the voltage difference between the first power signal Vpvdd and the second power signal Vpvee. The trend of the display brightness change of the display panel 000 is inversely proportional to the trend of the second power signal Vpvee. Dynamically adjusting the value of the second power signal Vpvee according to the display brightness helps save overall panel power consumption.When the bias adjustment signal Vbias dynamically changes in accordance with the second power supply signal Vpvee, the trend of Vbias is inversely proportional to the trend of Vpvee. Optionally, when the value of the second power supply signal Vpvee increases, the value of Vbias decreases. For example, if the brightness required by the display panel 000 is low, and it is necessary to reduce the voltage difference between the first power supply signal Vpvdd and the second power supply signal Vpvee, the second power supply signal Vpvee is raised. When the second power supply signal Vpvee is raised, the potential of the second terminal of the driving transistor DT, i.e., the third node N3, also rises. Therefore, the operating potential of the driving transistor DT is the potential of the gate of the driving transistor DT, i.e., the first node N1, minus the voltage value of the first power supply signal Vpvdd, minus the potential of the third node N3. This decrease is equivalent to controlling the light-emitting element 2 in the pixel circuit 10. During the light-emitting stage of 0, the negative bias voltage (i.e., reverse bias) of the driving transistor DT will be enhanced. Therefore, in order to ensure the adjustment effect of the bias state of the driving transistor DT, it is necessary to weaken the negative bias state of the driving transistor DT. That is, at this time, the voltage value of the bias adjustment signal Vbias can be reduced. That is, when the value of the second power supply signal Vpvee is raised, the value of the bias adjustment signal Vbias decreases accordingly, so that the change trend of the bias adjustment signal Vbias is inversely proportional to the change trend of the second power supply signal Vpvee. This can avoid the light-emitting brightness of the light-emitting element 20 from deviating from the original required brightness due to the change of the second power supply signal Vpvee, thereby improving the display quality of the display panel 000.

[0054] In some alternative embodiments, please continue to refer to the references. Figure 1 and Figure 2 In this embodiment, the increase in the value of the second power supply signal Vpvee is ΔA, and the decrease in the value of the bias adjustment signal Vbias is ΔB; wherein, ΔB≤0.5ΔA.

[0055] This embodiment explains that when the bias adjustment signal Vbias provided in the display panel 000 dynamically changes in accordance with the second power supply signal Vpvee, and the trend of the bias adjustment signal Vbias is inversely proportional to the trend of the second power supply signal Vpvee, the increase in the value of the second power supply signal Vpvee can be set to ΔA, and the decrease in the value of the bias adjustment signal Vbias can be set to ΔB, where ΔB ≤ 0.5ΔA. That is, the change in the bias adjustment signal Vbias is half the change in the second power supply signal Vpvee, or the change in the bias adjustment signal Vbias is less than the change in the second power supply signal Vpvee. Since when the scheme of dynamically adjusting the second power supply signal Vpvee is adopted, the change in the second power supply signal Vpvee only causes a change in the potential of the second terminal, i.e., the third node N3, of the driving transistor DT, while the potential of the first terminal, i.e., the second node N2, of the driving transistor DT does not change, and the bias adjustment signal Vbi is dynamically adjusted by the bias adjustment module 103. When the bias adjustment signal Vbias changes, it is simultaneously applied to the first terminal (second node N2) and the second terminal (third node N3) of the driving transistor DT. This means that when the applied bias adjustment signal Vbias changes, the potentials of both the second node N2 and the third node N3 will change. Therefore, the change in the bias adjustment signal Vbias can be set to be less than the change in the second power supply signal Vpvee. Specifically, the change in the bias adjustment signal Vbias should be half the change in the second power supply signal Vpvee, or the change in the bias adjustment signal Vbias should be less than the change in the second power supply signal Vpvee. This achieves a stronger effect in adjusting the bias voltage, which helps prevent the brightness of the light-emitting element 20 from deviating from the required brightness due to the change in the second power supply signal Vpvee. This improves the display quality of the display panel 000 while also reducing the amount of change in the bias adjustment signal Vbias, avoiding power waste caused by an excessively large range of Vbias variation.

[0056] In some alternative embodiments, please refer to the references. Figure 1 and Figure 3 , Figure 3 yes Figure 1 Another circuit connection structure diagram of the neutron pixel. In this embodiment, the control terminal of the bias adjustment module 103 is electrically connected to the first scan signal Scan1. The bias adjustment module 103 is used to provide the bias adjustment signal Vbias to the first pole of the driving transistor DT, i.e., the second node N2, under the effective level control of the first scan signal Scan1.

[0057] This embodiment explains that the display panel 000 may include at least multiple first scan signal lines (not shown in the figure). The first scan signal lines can be used to provide the first scan signal Scan1 to the control terminal of the bias adjustment module 103. Under the effective level control of the first scan signal Scan1, the bias adjustment module 103 is turned on, so that the bias adjustment signal Vbias can be transmitted to the first pole, i.e. the second node N2, of the driving transistor DT through the turned-on bias adjustment module 103, thereby adjusting the bias state of the driving transistor DT, improving the threshold drift problem of the driving transistor DT, and improving the display effect.

[0058] It is understood that the effective level of the first scan signal Scan1 provided by the first scan signal line in this embodiment can be understood as a voltage signal that enables the bias adjustment module 103 to conduct. The ineffective level of the first scan signal Scan1 can be understood as a voltage signal that enables the bias adjustment module 103 to be turned off. When the bias adjustment module 103 includes a P-type transistor, the control terminal of the bias adjustment module 103 can be understood as the gate of the P-type transistor. At this time, the effective level of the first scan signal Scan1 is a low-level voltage signal. If the bias adjustment module 103 includes an N-type transistor, the control terminal of the bias adjustment module 103 can be understood as the gate of the N-type transistor. At this time, the effective level of the first scan signal Scan1 is a high-level voltage signal. This embodiment does not make specific limitations on this. Specifically, the effective level of the first scan signal Scan1 can be selected according to the specific setting structure of the pixel circuit 10. It is only necessary to satisfy that the bias adjustment module 103 is turned on under the control of the effective level of the first scan signal Scan1.

[0059] Optional, please refer to the reference. Figure 1 , Figure 3 and Figure 4 , Figure 4 yes Figure 3 The comparison chart shows the trend of the effective level change of the first scan signal. In this embodiment, as the value of the second power supply signal Vpvee increases, the duration of the effective level of the first scan signal Scan1 decreases. It is understood that in this embodiment... Figure 4 The example below uses the first scan signal Scan1 as an example where the effective level is low.

[0060] This embodiment explains that when the bias adjustment signal Vbias provided in the display panel 000 dynamically changes in accordance with the second power supply signal Vpvee, and the trend of the change of the bias adjustment signal Vbias is inversely proportional to the trend of the change of the second power supply signal Vpvee, the bias adjustment effect of the bias adjustment signal Vbias on the driving transistor DT can be controlled by adjusting the duration of the effective level of the first scan signal Scan1. Figure 4As shown, the dashed line represents the effective level maintenance time t1' of the first scan signal Scan1 required to adjust the bias state of the driving transistor DT. The solid line represents the effective level maintenance time t1 of the first scan signal Scan1 required to adjust the bias state of the driving transistor DT when the value of the second power supply signal Vpvee is dynamically adjusted to increase and the bias adjustment signal Vbias decreases accordingly. t1 is less than t1'. When the value of the second power supply signal Vpvee is dynamically adjusted to increase its voltage value, the effective level maintenance time of the first scan signal Scan1 is reduced. For example, if the bias adjustment signal Vbias required to adjust the bias state of the driving transistor DT originally required the effective level maintenance time of the first scan signal Scan1 to be t1', but in this embodiment, after the value of the second power supply signal Vpvee increases, the value of the bias adjustment signal Vbias needs to be reduced, the effective level maintenance time of the first scan signal Scan1 can be shortened to t1, which is equivalent to shortening the bias adjustment module 10. The conduction time of 3 can reduce the value of the bias adjustment signal Vbias. Since the bias adjustment module 103 is turned on under the control of the effective level of the first scan signal Scan1, the bias effect is the strongest. When the bias adjustment module 103 is turned off, that is, the first scan signal Scan1 becomes an ineffective level, the bias adjustment process relies only on the parasitic capacitance on the second node N2 to maintain the bias effect. Since the parasitic capacitance will slowly leak current, the effect of the negative bias on the driving transistor DT will be weakened. That is, shortening the maintenance time of the effective level of the first scan signal Scan1 can weaken the effect of the negative bias on the driving transistor DT during the bias adjustment stage. When the value of the second power supply signal Vpvee is raised, the value of the bias adjustment signal Vbias decreases accordingly. It can still meet the adjustment effect of the bias state of the driving transistor DT, and avoid the light emission brightness of the light-emitting element 20 from deviating from the original required brightness due to the change of the second power supply signal Vpvee, which is conducive to improving the display quality of the display panel 000.

[0061] In some alternative embodiments, please refer to the references. Figure 1 and Figure 5 , Figure 5 yes Figure 1 Another circuit connection structure diagram of the neutron pixel. In this embodiment, the pixel circuit 10 further includes a first light emission control module 104, a second light emission control module 105, a first reset module 106, and a second reset module 107.

[0062] The first terminal of the first light-emitting control module 104 is electrically connected to the first power signal Vpvdd, and the second terminal of the first light-emitting control module 104 is electrically connected to the first electrode of the driving transistor DT.

[0063] The first terminal of the second light-emitting control module 105 is electrically connected to the first electrode of the driving transistor DT, and the second terminal of the second light-emitting control module 105 is electrically connected to the light-emitting element 20.

[0064] The first terminal of the first reset module 106 is electrically connected to the first reset signal Vref1, and the second terminal of the first reset module 106 is electrically connected to the gate of the driving transistor DT.

[0065] The first terminal of the second reset module 107 is electrically connected to the second reset signal Vref2, and the second terminal of the second reset module 107 is electrically connected to the light-emitting element 20.

[0066] This embodiment explains the module connection structure between the pixel circuit 10 and the light-emitting element 20 of each sub-pixel P. Optionally, the pixel circuit 10 includes a data writing module 101 and a bias adjustment module 103 connected to the first terminal of the driving transistor DT, a threshold compensation module 102 connected between the gate and the second terminal of the driving transistor DT, and also includes a first light-emitting control module 104, a second light-emitting control module 105, a first reset module 106, and a second reset module 107. When the pixel circuit 10 is operating in the light-emitting stage, the first light-emitting control module 104 and the second light-emitting control module 105 are turned on, and a conduction circuit is formed between the first power signal Vpvdd and the second power signal Vpvee, and the light-emitting element 20 emits light. The first light-emitting control module 104 and the second light-emitting control module 105 cooperate to provide driving current to the light-emitting element 20. Specifically, the first light-emitting control module 104 is turned on, and the positive voltage signal provided by the first power supply signal Vpvdd is supplied to the first terminal of the driving transistor DT. The driving transistor DT conducts under the control of its gate voltage, and the voltage signal from the first terminal of the driving transistor DT is supplied to the second terminal of the driving transistor DT. The second light-emitting control module 105 is turned on, and the voltage signal from the second terminal of the driving transistor DT is supplied to the light-emitting element 20, so that driving current flows through the light-emitting element 20, controlling the light-emitting element 20 to emit light. When the data writing module 101 is turned on, the data signal Vdata on the data line S can be transmitted to the driving transistor DT. When the bias adjustment module 103 is turned on, the bias adjustment signal Vbias provided on the bias voltage signal line can be transmitted to the driving transistor DT to adjust the bias state of the driving transistor DT. When the threshold compensation module 102 is turned on, threshold compensation can be performed on the driving transistor DT. When the first reset module 106 is turned on, the gate potential of the driving transistor DT is the first reset signal Vref1, which resets the gate of the driving transistor DT, thus facilitating the conduction of the driving transistor DT during threshold compensation. When the second reset module 107 is turned on, the anode potential of the light-emitting element 20 is the second reset signal Vref2. The second reset signal Vref2 initializes the anode of the light-emitting element 20, thereby improving the retention of the previous frame's data signal, reducing ghosting, and enhancing the display effect of the display panel 000. Optionally, in this embodiment, the first reset signal Vref1 and the second reset signal Vref2 can be the same or different, and can be set according to actual needs during specific implementation.

[0067] It is understood that the dynamic adjustment of the second power signal Vpvee and the bias adjustment signal Vbias in this embodiment can be directly adjusted by inputting the second power signal line of the second power signal Vpvee and the bias voltage signal line of the bias adjustment signal Vbias. For example, the second power signal line and the bias voltage signal line can be connected to the driver chip or flexible circuit board bonded to the display panel 000. The dynamic values ​​of the second power signal Vpvee and the bias adjustment signal Vbias can be directly changed by the potential signal input from the input pad of the driver chip or flexible circuit board. Alternatively, the dynamic adjustment of the bias adjustment signal Vbias can also be achieved by changing the conduction time of the bias adjustment module 103. For example, controlling the duration of the effective level of the first scan signal Scan1 can also change the value of the bias adjustment signal Vbias to follow the dynamic changes of the second power signal Vpvee and ensure the display quality of the display panel 000. This embodiment does not limit the method of dynamic adjustment.

[0068] Optional, such as Figure 1 and Figure 6 As shown, Figure 6 yes Figure 1 Another circuit connection structure diagram of the neutron pixel. In this embodiment, the data writing module 101 includes a first transistor M1. The gate of the first transistor M1 is electrically connected to the second scan signal Scan2, the source of the first transistor M1 is electrically connected to the data signal Vdata, and the drain of the first transistor M1 is electrically connected to the first terminal of the driving transistor DT.

[0069] The bias adjustment module 103 includes a second transistor M2, the gate of the second transistor M2 is electrically connected to the first scan signal Scan1, the source of the second transistor M2 is electrically connected to the bias adjustment signal Vbias, and the drain of the second transistor M2 is electrically connected to the first terminal of the driving transistor DT.

[0070] The threshold compensation module 102 includes a third transistor M3, the gate of the third transistor M3 is electrically connected to the third scan signal Scan3, the source of the third transistor M3 is electrically connected to the gate of the driving transistor DT, and the drain of the third transistor M3 is electrically connected to the second terminal of the driving transistor DT.

[0071] The first light-emitting control module 104 includes a fourth transistor M4, the gate of the fourth transistor M4 is electrically connected to the first light-emitting control signal EM1, the source of the fourth transistor M4 is electrically connected to the first power supply signal Vpvdd, and the drain of the fourth transistor M4 is electrically connected to the first terminal of the driving transistor DT.

[0072] The second light-emitting control module 105 includes a fifth transistor M5, the gate of the fifth transistor M5 is electrically connected to the second light-emitting control signal EM2, the source of the fifth transistor M5 is electrically connected to the second terminal of the driving transistor DT, and the drain of the fifth transistor M5 is electrically connected to the anode of the light-emitting element 20.

[0073] The first reset module 106 includes a sixth transistor M6, the gate of the sixth transistor M6 is electrically connected to the fourth scan signal Scan4, the source of the sixth transistor M6 is electrically connected to the first reset signal Vref1, and the drain of the sixth transistor M6 is electrically connected to the gate of the driving transistor DT.

[0074] The second reset module 107 includes a seventh transistor M7, the gate of the seventh transistor M7 is electrically connected to the first scan signal Scan1, the source of the seventh transistor M7 is electrically connected to the second reset signal Vref2, and the drain of the seventh transistor M7 is electrically connected to the anode of the light-emitting element 20.

[0075] Optionally, the pixel circuit 10 further includes a storage capacitor C, one end of which is connected to the first power supply signal Vpvdd, and the other end of which is connected to the gate of the driving transistor DT. The storage capacitor C is used to stabilize the potential of the gate of the driving transistor DT, which helps the driving transistor DT to remain on.

[0076] It is understood that in this embodiment, the third transistor M3 and the sixth transistor M6, which are connected to the gate of the driving transistor DT, are N-type metal-oxide transistors, while the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the driving transistor DT are all P-type low-temperature polysilicon transistors. The third transistor M3 and the sixth transistor M6 are N-type metal-oxide transistors. The third transistor M3 is electrically connected to the gate of the driving transistor DT, and the sixth transistor M6 is also electrically connected to the gate of the driving transistor DT. Metal-oxide transistors have low leakage current in the off-state, thereby reducing the impact of leakage current on the gate potential of the driving transistor DT, stabilizing the gate voltage of the driving transistor DT, improving the operating stability of the driving transistor DT, and ensuring the stability of the driving current. This is beneficial for the display panel 000 of this embodiment to ensure the uniformity of the light emission brightness of the light-emitting element 20. Especially when the display panel 000 implements low-frequency drive display, the display time of one frame is relatively long, so the potential of the driving transistor DT needs to be maintained for a longer time. If the transistor connected to the gate of the driving transistor DT is a low-temperature polysilicon transistor, the large leakage current of the low-temperature polysilicon transistor in the off-state can significantly affect the potential of the gate of the driving transistor DT, thus causing obvious flickering. Therefore, this embodiment sets the third transistor M3 and the sixth transistor M6 to N-type metal-oxide transistors, utilizing their characteristic of low off-state leakage current. This allows the potential of the gate of the driving transistor DT to be maintained for a longer time when the display panel 000 implements low-frequency drive display, improving the flickering phenomenon during low-frequency drive and enhancing the display effect.

[0077] like Figure 6 and Figure 7 As shown, Figure 7 yes Figure 6 The working timing diagram of the sub-pixel circuit in this embodiment shows that the working process of the pixel circuit 10 in the sub-pixel P includes at least the first bias voltage adjustment stage T1, the reset stage T2, the threshold compensation and data writing stage T3, and the light emission stage T4.

[0078] In the first bias adjustment stage T1, before the gate of the driving transistor DT is reset, the first scan signal Scan1 is input at a low level to control the second transistor M2 of the bias adjustment module 103 to turn on, and the third scan signal Scan3 at a high level to control the third transistor M3 of the threshold compensation module 102 to turn on. The bias adjustment signal Vbias is transmitted to the driving transistor DT through the second transistor M2 to adjust the bias state of the driving transistor DT, so that the driving transistor DT is reverse biased, the first and second terminals of the driving transistor DT are reversed, the degree of ion polarization inside the driving transistor DT is reduced, and the threshold voltage of the driving transistor DT is reduced. By biasing the driving transistor DT, the threshold voltage of the driving transistor DT is adjusted to compensate for the threshold voltage drift caused by the hysteresis effect of the driving transistor due to the forward bias state of the driving transistor DT. Optionally, the bias adjustment signal Vbias can be a DC positive voltage signal. Since the bias adjustment signal Vbias is a relatively high positive voltage value, regardless of the image displayed in the previous frame, the driving transistor DT needs to be written with the bias adjustment signal Vbias before resetting the gate of the driving transistor DT and before writing the current image. This ensures that the sub-pixel 00 undergoes the same bias adjustment signal Vbias writing before resetting the gate of the driving transistor DT. The written bias adjustment signal Vbias is a relatively high positive voltage value, allowing the driving transistor DT to flow with a large instantaneous current. This current can adjust the bias defects inside the driving transistor DT, improve the hysteresis characteristics of the driving transistor DT, thereby reducing the bias effect of the image displayed in the previous frame. This makes the state of the driving transistor DT closer to the preset when writing the current image, thereby reducing the bias difference of the driving transistor DT when displaying the current frame and the previous frame, improving the threshold drift problem of the driving transistor DT, and improving the display effect.

[0079] During the reset phase T2, if the sixth transistor M6 is an N-type metal-oxide transistor, the fourth scan signal Scan4 is at a high potential signal and controls the sixth transistor M6 of the first reset module 106 to turn on. The first reset signal Vref1 resets the gate of the driving transistor DT.

[0080] During the threshold compensation and data writing stage T3, the second scan signal line Scan2 inputs a low-potential signal to control the first transistor M1 of the data writing module 101 to turn on, and the third scan signal Scan3 inputs a high-potential signal to control the third transistor M3 of the threshold compensation module 102 to turn on. The threshold-compensated data voltage signal provided by the data line S is transmitted to the gate of the driving transistor DT through the first transistor M1, the driving transistor DT, and the third transistor M3 to perform threshold compensation on the driving transistor DT and self-compensate the deviation of the threshold voltage of the driving transistor DT.

[0081] During the light-emitting stage T4, the first light-emitting control signal EM1 is given a low-potential signal to control the fourth transistor M4 of the first light-emitting control module 104 to turn on, and the second light-emitting control signal EM2 is given a low-potential signal to control the fifth transistor M5 of the second light-emitting control module 105 to turn on. The driving transistor DT generates a driving current under the control of its gate voltage. The first light-emitting control signal EM1 and the second light-emitting control signal EM2 can be provided by the same light-emitting control signal line. A conductive path is formed between the first power supply signal Vpvdd, the fourth transistor M4, the driving transistor DT, the fifth transistor M5, the light-emitting element 20, and the second power supply signal Vpvee. The driving current is provided to the light-emitting element 20 so that the driving current flows through the light-emitting element 20 and controls the light-emitting element 20 to emit light.

[0082] It should be noted that, in specific implementation, the connection structure of the pixel circuit 10 in this embodiment includes, but is not limited to, the above-described structure and driving timing, and may also be other connection structures and driving methods. This embodiment does not limit these.

[0083] It is understood that the low potential signal of the first scan signal Scan1 in this embodiment can also control the seventh transistor M7 of the second reset module 107 to be turned on. The second reset signal Vref2 resets the anode of the light-emitting element 20 through the seventh transistor M7, thereby initializing the anode of the light-emitting element 20, which can improve the retention of the previous frame data signal, improve the afterimage phenomenon, and improve the display effect of the display panel 000.

[0084] The operation phase of the pixel circuit 10 provided in this embodiment may also include a power adjustment phase T5. The power adjustment phase T5 is used to dynamically adjust the value of the second power signal Vpvee according to the display brightness required by the display panel 000. When the brightness required by the display panel 000 is low and it is necessary to reduce the voltage difference between the first power signal Vpvdd and the second power signal Vpvee, the value of the second power signal Vpvee can be raised through the second power signal line in the power adjustment phase T5 to reduce the voltage difference between the first power signal Vpvdd and the second power signal Vpvee and reduce power consumption. Optionally, the operating time of the power supply adjustment stage T5 and the operating time of the first bias voltage adjustment stage T1 in this embodiment can be set to at least partially overlap. That is, when the power supply adjustment stage T5 dynamically adjusts the second power supply signal Vpvee, the bias adjustment signal Vbias can be adjusted synchronously and the first bias voltage adjustment stage T1 can be performed. Specifically, the synchronous adjustment of the bias adjustment signal Vbias means that when the second power supply signal Vpvee is raised, the potential of the third node N3 is also raised. Therefore, the operating potential of the driving transistor DT is the potential of the gate of the driving transistor DT, i.e., the first node N1, minus the voltage value of the first power supply signal Vpvdd, and then minus the voltage value of the third node N3. The value of the bit will decrease. After the decrease, it is equivalent to the negative bias voltage (i.e., reverse bias) of the driving transistor DT will be enhanced when the pixel circuit 10 controls the light-emitting element 20 to emit light. Therefore, in order to ensure the adjustment effect of the bias state of the driving transistor DT, it is necessary to weaken the negative bias state of the driving transistor DT. That is, at this time, the voltage value of the bias adjustment signal Vbias can be reduced, and the bias state of the driving transistor DT can be adjusted by using the reduced bias adjustment signal Vbias. This avoids the light-emitting brightness of the light-emitting element 20 from deviating from the original required brightness due to the change of the second power supply signal Vpvee, which is conducive to improving the display quality of the display panel 000.

[0085] Optionally, this embodiment is only an example illustrating the time period that can be set in the power adjustment stage T5 of the pixel circuit 10 during its operation. In specific implementation, the power adjustment stage T5 for dynamically adjusting the second power signal Vpvee is not limited to this time period, and can also be performed in the light-emitting stage T4 of the light-emitting element 20. This embodiment does not make specific limitations on this.

[0086] In some alternative embodiments, please refer to the references. Figure 1 and Figure 8 , Figure 8 yes Figure 1 A schematic diagram of another circuit connection structure for neutron pixels. In this embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the driving transistor DT are all P-type low-temperature polysilicon transistors.

[0087] This embodiment explains that the transistors included in the pixel circuit 10 can all be P-type transistors, such as P-type low-temperature polysilicon transistors. It is understood that when all transistors in the pixel circuit 10 are P-type transistors, this embodiment can utilize the high mobility and high driving speed characteristics of low-temperature polysilicon transistors, enabling the data writing module 101 to have a faster response speed for the driving transistor DT when writing data signals. This allows the data signal to be written quickly, avoiding insufficient charging due to a long on-time of the driving transistor DT. It should be noted that when all transistors in the pixel circuit 10 in this embodiment are P-type transistors, the polarity of the driving signals corresponding to the third scan signal Scan3 and the fourth scan signal Scan4 needs to be changed, only requiring reference to... Figure 7 The schematic driving timing is illustrated by reversing the polarity of the third scan signal Scan3 connected to the gate of the third transistor M3 and the fourth scan signal Scan4 connected to the gate of the sixth transistor M6, so as to apply the driving process when the third transistor M3 and the sixth transistor M6 are P-type transistors. This embodiment does not describe the driving timing for all transistors in the pixel circuit 10 as P-type transistors. For details, please refer to the driving principle of the pixel circuit in the relevant technology.

[0088] Optional, such as Figure 1 , Figure 9 and Figure 10 As shown, Figure 9 yes Figure 1 A schematic diagram of another circuit connection structure for neutron pixels. Figure 10 yes Figure 9 The timing diagram of the operation of the mid-pixel circuit is shown in this embodiment. The data writing module 101 is multiplexed as the bias adjustment module 103, and the data signal Vdata is multiplexed as the bias adjustment signal Vbias.

[0089] This embodiment explains that the data writing module 101 in the pixel circuit 10 can be multiplexed as a bias adjustment module 103. That is, in the first bias adjustment stage T1, the data signal Vdata can be multiplexed as a bias adjustment signal Vbias to adjust the bias of the driving transistor DT. Since the data writing module 101 is multiplexed as the bias adjustment module 103, it is beneficial to reduce the number of transistors in the pixel circuit 10, and it also makes... Figure 6 and Figure 7 The first and second scan signals can be reused, which helps to reduce the number of scan lines in the display panel 000, and thus helps to improve the aperture ratio of the sub-pixels 00 in the panel.

[0090] In some alternative embodiments, please refer to the references. Figures 1-7 , Figure 11 , Figure 11This is a flowchart of the driving method provided in the embodiment of the present invention. The driving method of the display panel provided in this embodiment can be applied to the display panel 000 in the above embodiment for driving operation. The driving method of this embodiment includes at least: a first bias voltage adjustment stage T1, a threshold compensation and data writing stage T3, and a light emission stage T4. The first bias voltage adjustment stage T1 is executed before the threshold compensation and data writing stage T3.

[0091] In the first bias adjustment stage T1, the bias adjustment module 103 is turned on, and the bias adjustment signal Vbias is provided to the first terminal of the driving transistor DT to adjust the bias state of the driving transistor DT.

[0092] During the threshold compensation and data writing stage T3, the threshold compensation module 102 detects and compensates for the deviation of the threshold voltage of the driving transistor DT, and the data writing module 101 writes the compensated threshold voltage deviation together with the data signal into the driving transistor DT.

[0093] During the light-emitting stage T4, the driving transistor DT generates a driving current, which drives the light-emitting element 20 to emit light.

[0094] The driving method also includes a power conditioning stage T5;

[0095] During the power adjustment phase T5, the value of the second power signal Vpvee is adjusted according to the change in the display brightness of the display panel 000, and the value of the bias adjustment signal Vbias is adjusted according to the change in the value of the second power signal Vpvee.

[0096] In the driving method provided in this embodiment, the working stage of the pixel circuit 10 includes at least a power adjustment stage T5. Since the power consumption of the pixel circuit 10 is mainly determined by the voltage difference between the first power signal Vpvdd and the second power signal Vpvee multiplied by the driving current in the conductive path, and the driving current is affected by the brightness of the light emission display, this embodiment sets a power adjustment stage T5 to adjust the value of the second power signal Vpvee according to the change in the brightness of the display panel 000. If the required light emission brightness of the display panel 000 decreases, that is, when a large voltage difference between the first power signal Vpvdd and the second power signal Vpvee is not required, the voltage value of the second power signal Vpvee can be increased to reduce the voltage difference between the first power signal Vpvdd and the second power signal Vpvee, thereby saving the power consumption of the panel. Alternatively, when the required light emission brightness of the entire display panel 000 is high, the voltage value of the second power signal Vpvee can be decreased to increase the voltage difference between the first power signal Vpvdd and the second power signal Vpvee, so as to ensure the overall brightness of the display panel 000 and save the overall power consumption of the panel. Optionally, in this embodiment, the operating time of the power adjustment stage T5 is set to at least partially overlap with the operating time of the first bias adjustment stage T1. That is, the driving method in this embodiment is further set to adjust the value of the bias adjustment signal Vbias according to the change in the value of the second power signal Vpvee in the power adjustment stage T5. That is, the bias adjustment signal Vbias connected to the bias adjustment module 103 changes with the change of the second power signal Vpvee. Specifically, when the bias adjustment module 103 is turned on, the bias adjustment signal Vbias is applied to the first terminal of the driving transistor DT, i.e., the second node N2. Since the driving transistor DT is turned on, the bias adjustment signal Vbias is also transmitted to the second terminal of the driving transistor DT, i.e., the third node N3. Since the threshold compensation module 102 is also turned on at this time, the bias adjustment signal Vbias is written into the gate of the driving transistor DT, i.e., the first node N1. Since the bias adjustment signal Vbias is a high voltage value, that is, regardless of the previous frame The display image is determined by the bias adjustment signal Vbias applied to the driving transistor DT during the writing of the current image. This reduces the bias effect of the previous frame, making the state of the driving transistor DT closer to the preset value. This reduces the bias difference between the current and previous frames, improves the threshold drift problem of the driving transistor DT, and enhances the display effect. When the second power signal Vpvee is dynamically changed to reduce panel power consumption according to the brightness requirements of the light-emitting display, the bias adjustment signal Vbias connected to the bias adjustment module 103 also changes dynamically. This prevents the brightness of the light-emitting element 20 from deviating from the required brightness due to the change of the second power signal Vpvee, thereby improving the display quality of the display panel 000.

[0097] Optional, please refer to the following: Figures 1-7 , Figure 11 The driving method in this embodiment further includes a reset phase T2, which is executed between the first bias adjustment phase T1 and the threshold compensation and data writing phase T3. Optionally, the reset phase T2 is used to reset the gate of the driving transistor DT.

[0098] The driving method configured in this embodiment is set before the reset phase T2, i.e. before resetting the gate of the driving transistor DT. This allows the first scan signal Scan1 to input a low-level signal to control the second transistor M2 of the bias adjustment module 103 to turn on, and the third scan signal Scan3 to input a high-level signal to control the third transistor M3 of the threshold compensation module 102 to turn on. The bias adjustment signal Vbias is then transmitted to the driving transistor DT through the second transistor M2 to adjust the bias state of the driving transistor DT, causing the driving transistor DT to be reverse biased. The first and second terminals of the driving transistor DT are reversed, reducing the degree of ion polarization inside the driving transistor DT and lowering the threshold voltage of the driving transistor DT. By biasing the driving transistor DT, the threshold voltage of the driving transistor DT is adjusted to compensate for the threshold voltage drift problem caused by the hysteresis effect of the driving transistor due to the forward bias state of the driving transistor DT. Because the hysteresis characteristic manifests when switching from a black and white frame to the next, the bias voltage of the driving transistor DT differs between the black and white frames. This results in different bias states of the driving transistor DT when writing the next frame, leading to different brightness levels. For example, when switching from a black frame to a white frame, the brightness of the first few frames of the white frame will be darker, resulting in ghosting. Therefore, in this embodiment, the reset phase T2 is executed between the first bias voltage adjustment phase T1 and the threshold compensation and data writing phase T3. The first bias voltage adjustment phase T1 is performed before the gate of the driving transistor DT is reset. Because the bias adjustment signal Vb... ias is a relatively high positive voltage value. This means that regardless of the image displayed in the previous frame, before resetting the gate of the driving transistor DT and writing the current image, the driving transistor DT must undergo a bias adjustment signal Vbias once. This can reduce the bias effect of the previous image, making the state of the driving transistor DT closer to the preset when writing the current image. This reduces the bias difference of the driving transistor DT when displaying the current and previous frames, improves the threshold drift problem of the driving transistor DT, and helps to improve the display problem of ghosting that is easily caused when switching between black and white images, thereby improving the display quality.

[0099] In some alternative embodiments, please refer to the references. Figure 1 , Figure 6 and Figure 12 , Figure 12 yes Figure 6 Another timing diagram of the middle pixel circuit. In the driving method of this embodiment, the working time of the power conditioning stage T5 and the working time of the light emission stage T4 are set to overlap at least partially.

[0100] This embodiment explains that the operating time of the power adjustment stage T5, which dynamically adjusts the second power signal Vpvee, can at least partially overlap with the operating time of the light emission stage T4. When the brightness required by the display panel 000 is low, and it is necessary to reduce the voltage difference between the first power signal Vpvdd and the second power signal Vpvee, the second power signal Vpvee is raised. When the second power signal Vpvee is raised, the potential of the third node N3 is also raised. Therefore, the operating potential of the driving transistor DT is the value of the potential of the gate of the driving transistor DT (i.e., the first node N1) minus the voltage value of the first power signal Vpvdd minus the potential of the third node N3, which will decrease. After the decrease... This is equivalent to enhancing the negative bias voltage (i.e., reverse bias) of the driving transistor DT during the light-emitting stage T4 when the pixel circuit 10 controls the light-emitting element 20. Therefore, the bias adjustment signal Vbias can be adjusted synchronously during the light-emitting stage T4. If the second power supply signal Vpvee is raised during the light-emitting stage T4, the bias adjustment signal Vbias will be reduced synchronously during the light-emitting stage T4 to weaken the negative bias voltage state of the driving transistor DT. That is, by reducing the voltage value of the bias adjustment signal Vbias, the brightness of the light-emitting element 20 is prevented from deviating from the original required brightness due to the change of the second power supply signal Vpvee, which is beneficial to improving the display quality of the display panel 000.

[0101] In some alternative embodiments, please refer to the references. Figure 1 , Figure 6 and Figure 13 , Figure 13 yes Figure 6 Another timing diagram of the middle pixel circuit. The driving method provided in this embodiment also includes a second bias adjustment stage T6 and a third bias adjustment stage T7. The second bias adjustment stage T6 is executed between the reset stage T2 and the threshold compensation and data writing stage T3, and the third bias adjustment stage T7 is executed between the threshold compensation and data writing stage T3 and the light emission stage T4.

[0102] This embodiment explains that the working process of the pixel circuit 10 includes at least a first bias voltage adjustment stage T1, a reset stage T2, a second bias voltage adjustment stage T6, a threshold compensation and data writing stage T3, a third bias voltage adjustment stage T7, and a light emission stage T4.

[0103] In the first bias adjustment stage T1, before the gate of the driving transistor DT is reset, the first scan signal Scan1 is input at a low level to control the second transistor M2 of the bias adjustment module 103 to turn on, and the third scan signal Scan3 at a high level to control the third transistor M3 of the threshold compensation module 102 to turn on. The bias adjustment signal Vbias is transmitted to the driving transistor DT through the second transistor M2 to adjust the bias state of the driving transistor DT, so that the driving transistor DT is reverse biased, the first and second terminals of the driving transistor DT are reversed, the degree of ion polarization inside the driving transistor DT is reduced, and the threshold voltage of the driving transistor DT is reduced. By biasing the driving transistor DT, the threshold voltage of the driving transistor DT is adjusted to compensate for the threshold voltage drift caused by the hysteresis effect of the driving transistor due to the forward bias state of the driving transistor DT. Optionally, the bias adjustment signal Vbias can be a DC positive voltage signal. Since the bias adjustment signal Vbias is a relatively high positive voltage value, regardless of the image displayed in the previous frame, the driving transistor DT needs to be written with the bias adjustment signal Vbias before resetting the gate of the driving transistor DT and before writing the current image. This can reduce the bias effect of the image displayed in the previous frame, making the state of the driving transistor DT closer to the preset when writing the current image. This reduces the bias difference of the driving transistor DT when displaying the current frame and the previous frame, improves the threshold drift problem of the driving transistor DT, and enhances the display effect.

[0104] During the reset phase T2, the fourth scan signal Scan4 is an active level signal. If the sixth transistor M6 is an N-type metal-oxide transistor, the fourth scan signal Scan4 controls the sixth transistor M6 of the first reset module 106 to turn on under the high potential signal, and the first reset signal Vref1 resets the gate of the driving transistor DT.

[0105] In the second bias adjustment stage T6, that is, before the threshold compensation and data writing stage T3, the fourth scan signal Scan4 can be made to be an effective level signal. If the sixth transistor M6 is an N-type metal-oxide transistor, the fourth scan signal Scan4 controls the sixth transistor M6 of the first reset module 106 to be turned on under the high potential signal. The high potential signal of the third scan signal Scan3 controls the third transistor M3 of the threshold compensation module 102 to be turned on. The first reset signal Vref1 is written to the second node N2 and the third node N3, which can eliminate the potential difference between the second node N2 (i.e., the first terminal of the driving transistor DT) and the third node N3 (the second terminal of the driving transistor DT) as much as possible. This avoids the difference in the bias state of the driving transistor DT caused by the different potentials of the second node N2 and the third node N3 due to different screens. In this way, the state of the gate, the first terminal and the second terminal of the driving transistor DT can be kept as close as possible during the subsequent data voltage signal writing.

[0106] Optionally, this embodiment may further set a second bias adjustment stage T6 to change the value of the bias adjustment signal Vbias so that the voltage values ​​of the gate, the first terminal, and the second terminal of the driving transistor DT are equal.

[0107] This embodiment adds a second bias voltage adjustment stage T6 before the threshold compensation and data writing stage T3. In this second bias voltage adjustment stage T6, by changing the value of the input bias adjustment signal Vbias, the potentials of the first node N1, the second node N2, and the third node N3 are set to the same potential. That is, by changing the value of the bias adjustment signal Vbias through the added second bias voltage adjustment stage T6, the voltage values ​​of the gate, the first terminal, and the second terminal of the driving transistor DT are made equal. This further reduces the bias voltage difference of the driving transistor DT before threshold compensation, which is beneficial to achieving a better bias voltage adjustment effect for the driving transistor DT.

[0108] During the threshold compensation and data writing stage T3, the second scan signal line Scan2 inputs a low-potential signal to control the first transistor M1 of the data writing module 101 to turn on, and the third scan signal Scan3 inputs a high-potential signal to control the third transistor M3 of the threshold compensation module 102 to turn on. The threshold-compensated data voltage signal provided by the data line S is transmitted to the gate of the driving transistor DT through the first transistor M1, the driving transistor DT, and the third transistor M3 to perform threshold compensation on the driving transistor DT and self-compensate the deviation of the threshold voltage of the driving transistor DT.

[0109] In the third bias adjustment stage T7, which is after the threshold compensation and data writing stage T3 and before the light emission stage T4, the pixel circuit 10 executes the third bias adjustment stage T7. In the third bias adjustment stage T7, a low-level signal is supplied to the first scan signal Scan1 to turn on the second transistor M2 of the bias adjustment module 103, thereby providing the bias adjustment signal Vbias to the second node N2 to adjust the bias state of the driving transistor DT. This embodiment sets three bias adjustment stages in the working cycle of the pixel circuit 10, intentionally increasing the time for adjusting the bias state of the driving transistor DT in the driving cycle, in order to improve the degree of improvement of the threshold voltage drift caused by the hysteresis effect of the driving transistor DT.

[0110] Optionally, the third bias adjustment stage T7 in this embodiment can be performed after the threshold compensation and data writing stage T3 in the data writing frame of the pixel circuit 10 and before the light emission stage T4. Alternatively, in some other optional embodiments, the operation of the pixel circuit 10 includes a data writing frame and a holding frame, so the operation of the third bias adjustment stage T7 can also be performed before the light emission stage of the holding frame. When the display panel 000 adopts a low-frequency driving mode, since there is no data writing stage in the holding frame of the low-frequency driving mode, the state of the first pole of the driving transistor DT, i.e., the second node N2, is different from the state of the second node N2 in the data writing frame. Therefore, in order to make the state of the second node N2 in the light-emitting stage of the holding frame and the light-emitting stage of the data writing frame as close as possible, a bias adjustment signal Vbias can be applied to the second node N2 in the light-emitting stage of the holding frame. That is, the first scan signal Scan1 is given a low-level signal to turn on the second transistor M2 of the bias adjustment module 103, so as to provide the bias adjustment signal Vbias to the second node N2, so as to adjust the bias voltage of the driving transistor DT to fit the state of the data writing frame. In this way, a third bias adjustment stage T7 is also performed before the light-emitting stage T4 of the data writing frame, and the bias adjustment signal Vbias is applied to the second node N2, so that the state of the second node N2 in the data writing frame and the holding frame is closer, which is beneficial to improve the light emission difference and improve the quality of the light emission display.

[0111] During the light-emitting stage T4, the first light-emitting control signal EM1 is given a low-potential signal to control the fourth transistor M4 of the first light-emitting control module 104 to turn on, and the second light-emitting control signal EM2 is given a low-potential signal to control the fifth transistor M5 of the second light-emitting control module 105 to turn on. The driving transistor DT generates a driving current under the control of its gate voltage. The first light-emitting control signal EM1 and the second light-emitting control signal EM2 can be provided by the same light-emitting control signal line. A conductive path is formed between the first power supply signal Vpvdd, the fourth transistor M4, the driving transistor DT, the fifth transistor M5, the light-emitting element 20, and the second power supply signal Vpvee. The driving current is provided to the light-emitting element 20 so that the driving current flows through the light-emitting element 20 and controls the light-emitting element 20 to emit light.

[0112] It should be noted that, in specific implementation, the connection structure of the pixel circuit 10 in this embodiment includes, but is not limited to, the above-described structure and driving timing, and may also be other connection structures and driving methods. This embodiment does not limit these.

[0113] In some alternative embodiments, please refer to Figure 14 , Figure 14 This is a schematic diagram of the planar structure of the display device provided in the embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Figure 14 This embodiment uses a mobile phone as an example to illustrate the display device 111. It is understood that the display device 111 provided in this embodiment can be any other display device 111 with display functions, such as a computer, television, or in-vehicle display device; this invention does not impose specific limitations on this. The display device 111 provided in this embodiment has the beneficial effects of the display panel 000 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 000 in the above embodiments; these will not be repeated here.

[0114] As can be seen from the above embodiments, the display panel, driving method, and display device provided by the present invention achieve at least the following beneficial effects:

[0115] The sub-pixels of the display panel provided by this invention may include electrically connected pixel circuits and light-emitting elements. The pixel circuits are used to control the light-emitting elements to emit light. The pixel circuits include at least a driving transistor, a data writing module, a threshold compensation module, and a bias adjustment module. The data writing module provides data signals to the driving transistor. The threshold compensation module detects and compensates for the deviation of the threshold voltage of the driving transistor, and provides the compensated threshold voltage deviation and the data signal provided by the data line itself to the driving transistor to achieve threshold compensation. This can improve display unevenness caused by differences in the threshold voltage of the driving transistor due to manufacturing processes and threshold voltage drift caused by transistor aging. The bias adjustment module provides a bias adjustment signal to the driving transistor to adjust the bias state of the driving transistor, improve the threshold drift problem of the driving transistor, and enhance the display effect. The first terminal of the driving transistor is connected to a first power supply signal, and the second terminal is connected to a second power supply signal. When the pixel circuit drives the light-emitting element electrically connected to it to emit light, the driving transistor can generate a driving current to drive the light-emitting element to emit light through the conductive path between the first power supply signal, the driving transistor, the light-emitting element, and the second power supply signal, thereby achieving the light-emitting effect of the light-emitting element. In this invention, the first power signal connected to the first terminal of the driving transistor in the pixel circuit is set to a fixed value, while the second power signal connected to the second terminal of the driving transistor is set to a variable value. The voltage value of the second power signal can change according to the brightness required by the display panel, which helps to save the overall power consumption of the panel. When the display panel uses a dynamically changing second power signal to reduce panel power consumption according to the brightness requirements of the light emission display, the bias adjustment signal connected to the bias adjustment module also changes dynamically accordingly. This can prevent the brightness of the light-emitting element from deviating from the originally required brightness due to the change of the second power signal, thereby improving the display quality of the display panel.

[0116] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, include: Multiple sub-pixels, each sub-pixel comprising an electrically connected pixel circuit and a light-emitting element; The pixel circuit includes at least a driving transistor, a data writing module, a threshold compensation module, and a bias adjustment module; The first terminal of the driving transistor is electrically connected to the data writing module and the bias adjustment module, respectively, and the driving transistor is used to generate driving current. The first end of the data writing module is electrically connected to the data signal, and the second end of the data writing module is electrically connected to the first electrode of the driving transistor. The data writing module is used to provide a data signal to the driving transistor. The first terminal of the bias adjustment module is electrically connected to the bias adjustment signal, and the second terminal of the bias adjustment module is electrically connected to the first electrode of the driving transistor. The bias adjustment module is used to provide the bias adjustment signal to the first electrode of the driving transistor to adjust the bias state of the driving transistor. The threshold compensation module is connected between the gate of the driving transistor and the second electrode of the driving transistor. The threshold compensation module is used to detect and compensate for the deviation of the threshold voltage of the driving transistor. The first terminal of the driving transistor is connected to a first power supply signal, and the second terminal of the driving transistor is connected to a second power supply signal; The second power supply signal is a changing value, and the bias adjustment signal is a changing value; The brightness variation trend of the display panel is inversely proportional to the variation trend of the second power signal, and the bias adjustment signal variation trend is inversely proportional to the variation trend of the second power signal.

2. The display panel according to claim 1, characterized in that, When the value of the second power supply signal increases, the value of the bias adjustment signal decreases.

3. The display panel according to claim 2, characterized in that, The increase in the value of the second power supply signal is ΔA, and the decrease in the value of the bias adjustment signal is ΔB; wherein, ΔB≤0.5ΔA.

4. The display panel according to claim 2, characterized in that, The control terminal of the bias adjustment module is electrically connected to the first scan signal. The bias adjustment module is used to provide the bias adjustment signal to the first pole of the driving transistor under the control of the effective level of the first scan signal.

5. The display panel according to claim 4, characterized in that, As the value of the second power signal increases, the duration of the effective level of the first scan signal decreases.

6. The display panel according to claim 1, characterized in that, The pixel circuit further includes a first light emission control module, a second light emission control module, a first reset module, and a second reset module; The first terminal of the first light-emitting control module is electrically connected to the first power signal, and the second terminal of the first light-emitting control module is electrically connected to the first electrode of the driving transistor. The first terminal of the second light-emitting control module is electrically connected to the first electrode of the driving transistor, and the second terminal of the second light-emitting control module is electrically connected to the light-emitting element; The first terminal of the first reset module is electrically connected to the first reset signal, and the second terminal of the first reset module is electrically connected to the gate of the driving transistor. The first end of the second reset module is electrically connected to the second reset signal, and the second end of the second reset module is electrically connected to the light-emitting element.

7. The display panel according to claim 6, characterized in that, The data writing module includes a first transistor, the gate of the first transistor is electrically connected to a second scan signal, the source of the first transistor is electrically connected to a data signal, and the drain of the first transistor is electrically connected to the first electrode of the driving transistor. The bias adjustment module includes a second transistor, the gate of which is electrically connected to a first scan signal, the source of which is electrically connected to the bias adjustment signal, and the drain of which is electrically connected to the first terminal of the driving transistor. The threshold compensation module includes a third transistor, the gate of which is electrically connected to a third scan signal, the source of which is electrically connected to the gate of the driving transistor, and the drain of which is electrically connected to the second terminal of the driving transistor. The first light-emitting control module includes a fourth transistor, the gate of which is electrically connected to a first light-emitting control signal, the source of which is electrically connected to a first power supply signal, and the drain of which is electrically connected to the first terminal of the driving transistor. The second light-emitting control module includes a fifth transistor, the gate of which is electrically connected to a second light-emitting control signal, the source of which is electrically connected to the second terminal of the driving transistor, and the drain of which is electrically connected to the anode of the light-emitting element. The first reset module includes a sixth transistor, the gate of which is electrically connected to a fourth scan signal, the source of which is electrically connected to the first reset signal, and the drain of which is electrically connected to the gate of the driving transistor. The second reset module includes a seventh transistor, the gate of which is electrically connected to the first scan signal, the source of which is electrically connected to the second reset signal, and the drain of which is electrically connected to the anode of the light-emitting element.

8. The display panel according to claim 7, characterized in that, The third transistor and the sixth transistor are N-type metal-oxide transistors, while the first transistor, the second transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the driving transistor are all P-type low-temperature polycrystalline silicon transistors.

9. The display panel according to claim 7, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the driving transistor are all P-type low-temperature polycrystalline silicon transistors.

10. The display panel according to claim 1, characterized in that, The data writing module is multiplexed as the bias adjustment module, and the data signal is multiplexed as the bias adjustment signal.

11. The display panel according to claim 1, characterized in that, The bias adjustment signal is a DC positive voltage signal.

12. A driving method for a display panel, characterized in that, The driving method is applied to the display panel according to any one of claims 1-11; The driving method includes at least: a first bias voltage adjustment stage, a threshold compensation and data writing stage, and a light emission stage, wherein the first bias voltage adjustment stage is performed before the threshold compensation and data writing stage; During the first bias voltage adjustment stage, the bias adjustment module is turned on, and the bias adjustment signal is provided to the first terminal of the driving transistor to adjust the bias state of the driving transistor. During the threshold compensation and data writing phase, the threshold compensation module detects and compensates for the deviation of the threshold voltage of the driving transistor, and the data writing module writes the compensated threshold voltage deviation together with the data signal into the driving transistor. During the light-emitting phase, the driving transistor generates a driving current to drive the light-emitting element to emit light; The driving method further includes a power regulation stage; During the power adjustment phase, the value of the second power signal is adjusted according to the change in the display brightness of the display panel, and the value of the bias adjustment signal is adjusted according to the change in the value of the second power signal.

13. The driving method according to claim 12, characterized in that, The brightness variation trend of the display panel is inversely proportional to the variation trend of the second power signal, and the bias adjustment signal variation trend is inversely proportional to the variation trend of the second power signal.

14. The driving method according to claim 12, characterized in that, During the power adjustment phase, the display brightness of the display panel decreases, the value of the second power signal increases, and the value of the bias adjustment signal decreases.

15. The driving method according to claim 12, characterized in that, The operating time of the power supply regulation phase overlaps at least partially with the operating time of the first bias voltage regulation phase.

16. The driving method according to claim 12, characterized in that, The operating time of the power conditioning phase overlaps at least partially with the operating time of the light emission phase.

17. The driving method according to claim 12, characterized in that, The driving method further includes a reset phase, which is performed between the first bias adjustment phase and the threshold compensation and data writing phase.

18. The driving method according to claim 17, characterized in that, The driving method further includes a second bias adjustment stage and a third bias adjustment stage; the second bias adjustment stage is performed between the reset stage and the threshold compensation and data writing stage, and the third bias adjustment stage is performed between the threshold compensation and data writing stage and the light emission stage.

19. The driving method according to claim 18, characterized in that, During the second bias adjustment phase, the value of the bias adjustment signal is changed so that the voltage values ​​of the gate, the first terminal, and the second terminal of the driving transistor are equal.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1-11.

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