Slave node address allocation method and device, readable storage medium, and communication system

Abstract

A method and device for assigning addresses to slave nodes, a readable storage medium, and a communication system, the communication system comprising: a master node and N slave nodes, the master node is coupled to the N slave nodes via a serial data bus; the i-th slave node among the N slave nodes comprises an addressing module, the addressing module comprises a current sampling unit, suitable for obtaining bus current, the bus current is the difference between the sampling current and the interference current; the sampling current is the actual current flowing through the sampling resistor, and the interference current is the current generated by the interference noise on the serial data bus on the sampling resistor. The above scheme can improve the accuracy of assigning addresses to slave nodes.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method and device for allocating slave node addresses, a readable storage medium, and a communication system. Background Art

[0002] The Local Interconnect Network (LIN) communication system usually consists of a master node (Master) and several slave nodes (Slave) with the same structure. In order to distinguish several slave nodes, it is necessary to assign corresponding addresses to different slave nodes.

[0003] The Bus Shunt method (BSM) provides a solution for assigning addresses to different slave nodes. Different slave nodes are assigned corresponding addresses based on their positions in the LIN communication network.

[0004] The existing address allocation method is easily affected by interference and noise on the LIN bus during address allocation, and the accuracy of address allocation is poor. Summary of the invention

[0005] The purpose of the present invention is at least to provide a serial data bus communication system and a slave node address allocation method, which can improve the accuracy of address allocation in the serial data bus communication system.

[0006] In a first aspect, the present invention provides a serial data bus communication system, comprising: a master node and N slave nodes; wherein the master node is coupled to the N slave nodes through the serial data bus; the i-th slave node among the N slave nodes comprises an addressing module; N is a positive integer and N≥2, i is a positive integer and 1≤i≤N; the addressing module comprises: a first switch unit, a pull-up resistor, a second switch unit, a current source, a sampling resistor and a current sampling unit, wherein: the first switch unit, a first end of which inputs a power supply voltage, and a second end of which is coupled to the first end of the pull-up resistor; the pull-up resistor, a second end of which is coupled to the serial data bus; the second switch unit, a first end of which inputs the power supply voltage, and a second end of which is coupled to the first end of the current source; the current source, a second end of which is coupled to the serial data bus; the sampling resistor, coupled to the serial data bus; the current sampling unit, adapted to obtain a bus current, the bus current being the difference between an actual current flowing through the sampling resistor and an interference current generated by interference noise on the sampling resistor.

[0007] The slave node includes a current sampling unit, through which the bus current is obtained. Since the obtained bus current is the difference between the actual current on the sampling resistor and the interference current, that is, the bus current is the current after noise removal, the influence of interference noise can be effectively avoided in the subsequent address allocation process, thereby improving the accuracy of address allocation.

[0008] Optionally, the current sampling unit includes: a sampling current acquisition module and an interference current acquisition module, wherein: the sampling current acquisition module is used to obtain the actual voltage drop across the sampling resistor and determine the sampling current based on the actual voltage drop; the interference current acquisition module is used to obtain the interference voltage drop across the sampling resistor and determine the interference current based on the interference voltage drop.

[0009] Optionally, the current sampling unit includes: a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein: the first resistor, a first end thereof is coupled to the first end of the sampling resistor, and a second end thereof is coupled to the first end of the third switch unit and the first end of the third resistor; the second resistor, a first end thereof is coupled to the second end of the sampling resistor, and a second end thereof is coupled to the second end of the fourth switch unit and the second input end of the first operational amplifier; the third switch unit, a second end thereof is coupled to the first input end of the first operational amplifier and the first end of the fourth switch unit; the fourth switch unit, a second end thereof is coupled to the second input end of the first operational amplifier and the first end of the fourth resistor; the fifth switch unit, a first end thereof is coupled to the The first end of the sixth switch unit is coupled to the output end of the first operational amplifier, and the second end is coupled to the compensation input end of the second operational amplifier; the fourth switch unit and the fifth switch unit are turned on or off at the same time, the third switch unit and the sixth switch unit are turned on or off at the same time, and the third switch unit and the fourth switch unit are not turned on at the same time; the second operational amplifier, the first input end of which is coupled to the first end of the third resistor, the second input end of which is coupled to the first end of the fourth resistor, and the output end of which is coupled to the analog-to-digital converter; the third resistor, the second end of which inputs the reference voltage; the fourth resistor, the first end of which is coupled to the second input end of the second operational amplifier, and the second end of which is coupled to the output end of the second operational amplifier.

[0010] Optionally, the current sampling unit further includes: a first capacitor, a second capacitor and a third capacitor, wherein: the first capacitor, a first end of which is coupled to the output end of the first operational amplifier, and a second end of which is grounded; the second capacitor, a first end of which is coupled to the first end of the fourth resistor, and a second end of which is coupled to the second end of the fourth resistor; the third capacitor, a first end of which is coupled to the output end of the second operational amplifier, and a second end of which is grounded.

[0011] Optionally, the current sampling unit also includes: a first switch tube and a second switch tube, wherein: the first switch tube has a drain coupled to the second end of the first resistor, a gate input enable signal, and a source coupled to the first end of the fourth switch unit and the first end of the third resistor; the second switch tube has a drain coupled to the second end of the second resistor, a gate coupled to the gate of the first switch tube, and a source coupled to the second end of the third switch unit.

[0012] Optionally, the current sampling unit further includes: a first diode and a second diode, wherein: the first diode has a cathode coupled to the second end of the first resistor, and an anode coupled to the anode of the second diode and the ground; the second diode has a cathode coupled to the second end of the second resistor.

[0013] Optionally, the current sampling unit further includes: a fourth capacitor, a first end of which is coupled to the input end of the first operational amplifier and the compensation input end of the second operational amplifier, and a second end of which is grounded.

[0014] In a second aspect, the present invention provides a method for allocating addresses from nodes, which is suitable for allocating addresses to slave nodes in any of the above-mentioned serial data bus communication systems; the method for allocating addresses from nodes comprises: receiving an address allocation command, the address allocation command comprising N addresses to be allocated; obtaining a first bus current on the serial data bus; controlling the first switch unit to close, and obtaining a second bus current on the serial data bus; if the first difference is less than a preset first threshold, controlling the second switch unit to close; the first difference is the difference between the first bus current and the second bus current; obtaining a third bus current on the serial data bus; if the second difference is less than a preset second threshold, obtaining a target address from the N addresses to be allocated; the second difference is the difference between the first bus current and the third bus current.

[0015] The slave node receives an address allocation command and obtains a first bus current on the serial data bus; then controls the first switch unit to close so as to connect the pull-up resistor to the serial data bus, and obtains a second bus current on the serial data bus after the pull-up resistor is connected to the serial data bus. When the first difference between the first bus current and the second bus current is less than a preset first threshold, the second switch is controlled to close so as to connect the current source to the serial data bus, and obtains a third bus current on the serial data bus after the current source is connected to the serial data bus. When the second difference between the first bus current and the third bus current is less than a preset second threshold, it can be determined that the slave node is the slave node farthest from the master node, and the corresponding address to be allocated is selected as the target address. Thus, based on the change in the bus current (the first difference, the second difference), accurate address allocation is achieved for different slave nodes.

[0016] Optionally, before receiving the address allocation command, the method further includes: determining that the target address does not exist.

[0017] Optionally, if the first difference is greater than the first threshold, the first switch unit is controlled to be disconnected.

[0018] Optionally, if the second difference is greater than the second threshold, the first switch unit is controlled to be disconnected, and the second switch unit is controlled to be disconnected.

[0019] Optionally, the first threshold is equal to the second threshold.

[0020] In a third aspect, the present invention further provides a slave node address allocation device, suitable for allocating addresses to slave nodes in any of the above-mentioned serial data bus communication systems; the slave node address allocation device comprises: a receiving unit, used to receive an address allocation command, the address allocation command comprising N addresses to be allocated; a first acquisition unit, used to acquire a first bus current on the serial data bus; a second acquisition unit, used to control the first switch unit to close, and acquire a second bus current on the serial data bus; a first control unit, used to detect that a first difference is less than a preset first threshold, and control the second switch unit to close; the first difference is the difference between the first bus current and the second bus current; a third acquisition unit, used to acquire a third bus current on the serial data bus; an address allocation unit, used to detect that a second difference is less than a preset second threshold, and acquire a target address from the N addresses to be allocated; the second difference is the difference between the first bus current and the third bus current.

[0021] In a fourth aspect, the present invention further provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above-mentioned slave node address allocation methods are executed.

[0022] In a fifth aspect, the present invention also provides another slave node address allocation device, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor executes the steps of any of the above-mentioned slave node address allocation methods when running the computer program. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a structural schematic diagram of a serial data bus communication system in an embodiment of the present invention;

[0024] Figure 2 is a structural schematic diagram of a current sampling unit in an embodiment of the present invention;

[0025] Figure 3 is a schematic diagram of the principle of a first operational amplifier OP1 in an embodiment of the present invention;

[0026] Figure 4 is a flow chart of a method for allocating slave node addresses in an embodiment of the present invention;

[0027] Figure 5 It is a structural schematic diagram of a slave node address allocation device in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As described in the above background technology, the existing address allocation method is easily affected by interference and noise on the LIN bus during address allocation, and the accuracy of address allocation is poor.

[0029] In the embodiment of the present invention, the slave node obtains the bus current after noise reduction through the current sampling unit in the addressing module, so that in the subsequent address allocation process, the influence of interference noise can be effectively avoided and the accuracy of address allocation can be improved.

[0030] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] An embodiment of the present invention provides a serial data bus communication system. The serial data bus communication system may include a master node and N slave nodes.

[0032] In a specific implementation, the above-mentioned master node may also be referred to as a host, a master device, a Master device, etc. The above-mentioned slave node may also be referred to as a slave machine, a slave device, a Slave device, etc.

[0033] In the embodiment of the present invention, the master node may be coupled to N slave nodes via a serial data bus, where N is a positive integer and N≥2.

[0034] In a specific implementation, the serial data bus may be a LIN bus, a controller area network (CAN) bus, or other types of serial data buses.

[0035] In the embodiment of the present invention, the structure of each slave node may be the same or similar. Each slave node may include an addressing module. The structure of the addressing module in each slave node may be the same or similar.

[0036] In some embodiments, the structures of the N slave nodes are the same, and the structures of the addressing modules in the N slave nodes are also the same.

[0037] Reference Figure 1 , a schematic diagram of the structure of a serial data bus communication system in an embodiment of the present invention is given. Figure 1 Provide explanation. Figure 1 In the embodiment, the serial data bus communication system includes a master node and N slave nodes (Slave1~SlaveN). For the N slave nodes, their corresponding structures are the same.

[0038] In a specific implementation, for any slave node, the addressing module may include: a first switch unit S1, a pull-up resistor R slave , a second switch unit S2, a current source I, a shunt resistor Rshunt and a current sampling unit CSA, wherein:

[0039] The first terminal of the first switch unit S1 is input with a power supply voltage V BAT The second end of the first switch unit S1 is connected to the pull-up resistor R slave The first end of the first switch unit S1 is missing; when the control end of the first switch unit S1 inputs the first enable signal, the first switch unit S1 is turned on, otherwise, when the control end of the first switch unit S1 does not have the first enable signal input, the first switch unit S1 is turned off;

[0040] Pull-up resistor R slave The second end may be coupled to the serial data bus;

[0041] The first terminal of the second switch unit S2 is input with a power supply voltage V BAT, the second end of the second switch unit S2 is coupled to the first end of the current source I; when the control end of the second switch unit S2 inputs the second enable signal, the second switch unit S2 is turned on, otherwise, when the control end of the second switch unit S2 does not input the second enable signal, the second switch unit S2 is turned off;

[0042] The second end of the current source I may be coupled to the serial data bus;

[0043] The sampling resistor Rshunt can be coupled to the serial data bus;

[0044] The current sampling unit CSA can obtain the bus current; the bus current can be the difference between the sampling current and the interference current, the sampling current is the actual current flowing through the sampling resistor Rshunt, and the interference current can be the current generated by the interference noise on the serial data bus in the sampling resistor Rshunt.

[0045] In other words, the bus current finally acquired by the current sampling unit CSA is the current after the interference elimination process.

[0046] In a specific implementation, the resistance of the sampling resistor Rshunt may be 1 ohm, and the resistance of the pull-up resistor R may be 30K ohms.

[0047] Figure 1 For the master node, it can add an additional master node resistance to the slave node structure. Rmaster .

[0048] It should be noted that the specific structure of the master node is not limited to Figure 1 In a specific implementation, any slave node may also include a data sending module TXD and a data receiving module RXD.

[0049] Reference Figure 2 , a schematic structural diagram of a current sampling unit in an embodiment of the present invention is given.

[0050] In the embodiment of the present invention, the current sampling unit may include: a third switch unit SW3, a fourth switch unit SW4, a fifth switch unit SW5, a sixth switch unit SW6, a first operational amplifier OP1, a second operational amplifier OP2, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, wherein:

[0051] A first end of the first resistor R1 is coupled to a first end of the sampling resistor Rshunt, and a second end of the first resistor R1 is coupled to a first end of the third switch unit SW3;

[0052] A first end of the second resistor R2 is coupled to a second end of the sampling resistor, and a second end of the second resistor R2 is coupled to a second end of the fourth switch unit SW4 and a second input end of the first operational amplifier OP1;

[0053] The first end of the third switch unit SW3 is also coupled to the first end of the third resistor R3, and the second end of the third switch unit SW3 is coupled to the first end of the fourth switch unit SW4 and the first input end of the first operational amplifier OP1;

[0054] A first end of the fourth switch unit SW4 is coupled to the first input end of the first operational amplifier OP1, and a second end of the fourth switch unit SW4 is coupled to the first end of the fourth resistor R4 and the second input end of the first operational amplifier OP1;

[0055] A first terminal of the fifth switch unit SW5 is coupled to the compensation input terminal of the first operational amplifier OP1, and a second terminal of the fifth switch unit SW5 is coupled to the output terminal of the first operational amplifier OP1;

[0056] A first terminal of the sixth switch unit SW6 is coupled to the output terminal of the first operational amplifier OP1, and a second terminal of the sixth switch unit SW6 is coupled to the compensation input terminal of the second operational amplifier OP2;

[0057] A first input terminal of the second operational amplifier OP2 is coupled to a first terminal of the third resistor R3, a second input terminal of the second operational amplifier OP2 is coupled to a first terminal of the fourth resistor R4, and an output terminal of the second operational amplifier OP2 is coupled to the analog-to-digital converter;

[0058] The second end of the third resistor R3 is input with a reference voltage VCM;

[0059] A first terminal of the fourth resistor R4 is coupled to the second input terminal of the second operational amplifier OP2 , and a second terminal of the fourth resistor R4 is coupled to the output terminal of the second operational amplifier OP2 .

[0060] In a specific implementation, the fourth switch unit SW4 and the fifth switch unit SW5 are turned on or off at the same time, and the third switch unit SW3 and the sixth switch unit SW6 are turned on or off at the same time. Moreover, when the third switch unit SW3 is turned on, the fourth switch unit SW4 is turned off; when the third switch unit SW3 is turned off, the fourth switch unit SW4 is turned on.

[0061] In a specific implementation, the first input terminal of the first operational amplifier OP1 may be a positive input terminal, and the second input terminal of the first operational amplifier OP1 may be a negative input terminal. The first input terminal of the second operational amplifier OP2 may be a positive input terminal, and the second input terminal of the second operational amplifier OP2 may be a negative input terminal.

[0062] In a specific implementation, the current sampling unit may further include: a first capacitor C1, a second capacitor C2 and a third capacitor C3, wherein:

[0063] A first terminal of the first capacitor C1 is coupled to the output terminal of the first operational amplifier OP1, and a second terminal of the first capacitor C1 is grounded;

[0064] The first end of the second capacitor C2 is coupled to the first end of the fourth resistor R4, and the second end of the second capacitor C2 is coupled to the second end of the fourth resistor R4; that is, the second capacitor C2 is connected in parallel with the fourth resistor R4;

[0065] A first terminal of the third capacitor C3 is coupled to the second input terminal of the second operational amplifier OP2 , and a second terminal of the third capacitor C3 is grounded.

[0066] In a specific implementation, the current sampling unit may further include a first diode D1 and a second diode D2, wherein:

[0067] A cathode of the first diode D1 is coupled to the second end of the first resistor R1, and an anode of the first diode D1 is coupled to an anode of the second diode D2 and a ground terminal;

[0068] A cathode of the second diode D2 is coupled to the second end of the second resistor R2 .

[0069] By providing the first diode D1 and the second diode D2 , it is possible to prevent the negative voltage on the serial data bus from affecting the current sampling unit.

[0070] In a specific implementation, the current sampling unit may further include a first switch tube M1 and a second switch tube M2, wherein:

[0071] The drain of the first switch tube M1 is coupled to the second end of the first resistor R1, the gate of the first switch tube M1 inputs an enable signal, and the source of the first switch tube M1 is coupled to the first section of the third switch unit SW3 and the first end of the third resistor R3;

[0072] The drain of the second switch tube M2 is coupled to the first end of the second resistor R2 , the gate of the second switch tube M2 is input with an enable signal, and the source of the second switch tube M2 is coupled to the second end of the fourth switch unit SW4 .

[0073] By controlling the level of the enable signal, the first switch tube M1 and the second switch tube M2 can be controlled to be turned on or off.

[0074] In some embodiments, the first switch transistor M1 may be an NMOS transistor, and the second switch transistor M2 may also be an NMOS transistor.

[0075] In a specific implementation, the current sampling unit may further include a fourth capacitor C4. A first end of the fourth capacitor C4 is connected to the output end of the first operational amplifier OP1 and the compensation input end of the second operational amplifier OP2, and a second end of the fourth capacitor C4 is grounded.

[0076] In a specific implementation, the current sampling unit may further include a fifth capacitor C5. A first end of the fifth capacitor C5 is coupled to a first end of the third resistor R3, and a second end of the fifth capacitor C5 is grounded.

[0077] The specific working principle of the current sampling unit provided in the above embodiment is described below.

[0078] The first operational amplifier OP1 and the second operational amplifier OP2 may have the same structure. The internal structure and working principle of the first operational amplifier OP1 are described below. Figure 3 , a schematic diagram of the principle of a first operational amplifier OP1 is given.

[0079] The first operational amplifier OP1 may include a first PMOS transistor MP1, a second PMOS transistor MP2, and a first NMOS transistor MN1. The gate of the first PMOS transistor MP1 is the first input terminal (input voltage wieVIN+) of the first operational amplifier OP1, and the source of the first PMOS transistor MP1 is connected to the current source I M The drain of the first PMOS tube MP1 is coupled to the source of the first NMOS tube MN1; the gate of the second PMOS tube MP2 is the second input terminal of the first operational amplifier OP1 (the input voltage is VIN-), and the source of the second PMOS tube MP2 is coupled to the current source I M The first PMOS tube MP1 and the second PMOS tube MP2 are equivalent to common source amplifiers, the first NMOS tube MN1 is equivalent to a source follower, and VCIN is a negative feedback structure formed when the output voltage from the output end of the first operational amplifier OP1 is fed back.

[0080] When VCIN is 0, the first NMOS transistor MN1 is disconnected, and the drain voltage of the first PMOS transistor MP1 is equal to the drain voltage of the second PMOS transistor MP2.

[0081] When the output voltage of the first operational amplifier OP1 gradually rises, if VCIN> the threshold voltage of the first NMOS tube MN1, the first NMOS tube MN1 is turned on. At this time, the first NMOS tube MN1 generates a current, which is added to the current on the first PMOS tube MP1, which is equivalent to the input voltage of the first input terminal of the first operational amplifier OP1 being lower than the input voltage of the second input terminal. Therefore, the output voltage of the first operational amplifier OP1 will decrease with the increase of VCIN, and then VCIN will also be reduced.

[0082] In theory, when the first input terminal and the second input terminal of the first operational amplifier OP1 are both connected to the Vy point (see Figure 2 ), the input voltage of the first input terminal of the first operational amplifier OP1 is equal to the input voltage of the second input terminal.

[0083] However, due to factors such as process errors, there is an offset voltage at the input end of the first operational amplifier OP1. Specifically, when the first input end of the first operational amplifier OP1 and the second input end of the first operational amplifier OP1 are both connected to the Vy point, the input voltage of the first input end of the first operational amplifier OP1 and the input voltage of the second input end actually differ by Voffset1, and Voffset1 is the offset voltage corresponding to the first operational amplifier OP1. The overdrive voltage of the first NMOS tube MN1 can represent the size of Voffset1.

[0084] The working process of the above-mentioned current sampling unit may include two stages:

[0085] In stage 1, the fourth switch unit SW4 and the fifth switch unit SW5 are closed, and the third switch unit SW3 and the sixth switch unit SW6 are opened. In this scenario, the first input terminal and the second input terminal of the first operational amplifier OP1 are both connected to the Vy point, and the voltages of the first input terminal and the second input terminal of the first operational amplifier OP1 are equal. The output terminal of the first operational amplifier OP1 is fed back to the compensation input terminal of the first operational amplifier OP1 to form negative feedback.

[0086] Due to the existence of the feedback loop, the output voltage of the first operational amplifier OP1 is clamped to the threshold voltage of the first NMOS transistor MN1, and the output voltage is used to charge the first capacitor C1. Since the first operational amplifier OP1 and the second operational amplifier OP2 have the same structure, the Voffset1 generated by the first operational amplifier OP1 and the Voffset2 generated by the second operational amplifier OP2 are approximately the same.

[0087] In the first stage, the output voltage of the output terminal of the second operational amplifier OP2 includes Voffset2 generated by the second operational amplifier OP2 and the voltage drop generated by the noise at both ends of the sampling resistor.

[0088] In stage two, the third switch unit SW3 and the sixth switch unit SW6 are turned on, and the fourth switch unit SW4 and the fifth switch unit SW5 are turned off. The negative feedback loop of the first operational amplifier OP1 is disconnected. Since the input voltage LIN_S of the first input terminal of the first operational amplifier OP1 is greater than the input voltage LIN_M of the second input terminal, the output voltage of the first operational amplifier OP1 increases. The output voltage of the first operational amplifier OP1 includes Voffset1 and the voltage drop caused by noise at both ends of the sampling resistor. The output voltage of the first operational amplifier OP1 is output to the first NMOS tube MN1 in the second operational amplifier OP2, and the overdrive voltage of the first NMOS tube MN1 in the second operational amplifier OP2 is modulated, thereby reducing Voffset2 generated by the second operational amplifier OP2 and the voltage drop caused by noise at both ends of the sampling resistor. As a result, the second operational amplifier OP2 can output a precise voltage value.

[0089] Based on the output voltage of the second operational amplifier OP2 and the sampling resistor in the second stage, the bus current on the serial data bus can be determined, that is, the current after the interference is eliminated.

[0090] The address allocation method of the serial data bus communication system provided in the above embodiment of the present invention is described below.

[0091] Reference Figure 4 , a flowchart of a method for allocating slave node addresses in an embodiment of the present invention is given, and the following is described in detail through specific steps.

[0092] In the embodiment of the present invention, the following slave node address allocation method can be executed by a control chip (such as a microcontroller, a central processing unit, etc.) with data processing capabilities in the slave node, or by a chip module with data processing capabilities in the slave node, or by the slave node. The following is an example of a slave node executing the slave node address allocation method.

[0093] Step 401: Receive an address allocation command.

[0094] In the embodiment of the present invention, the master node may send an address allocation instruction through a serial data bus. The address allocation instruction may include N addresses to be allocated. The N addresses to be allocated may correspond one-to-one to the N slave nodes.

[0095] In a specific implementation, after the master node sends an address assignment instruction through the serial data bus, the level on the serial data bus is reduced to a low level. The control ends of the first switch units of the N slave nodes do not have the first enable signal input, and the control ends of the second switch units of the N slave nodes do not have the second enable signal input.

[0096] In a specific implementation, after receiving the address allocation command, the slave node may first detect whether it has been allocated a target address. If the slave node detects that it has been allocated a target address, the slave node may not need to perform the subsequent address allocation steps (i.e., steps 402 to 406); if the slave node has not been allocated a target address, the slave node continues to perform the following steps 402 to 406.

[0097] That is, the slave node that executes the following steps 402 to 406 is a slave node that has not yet been assigned a target address (hereinafter, slave node j is taken as an example).

[0098] For example, the N slave nodes are slave node 1 to slave node 8, and slave node 8 has obtained the target address through steps 401 to 406. Therefore, slave node 8 detects that it has been assigned the target address, so slave node 1 to slave node 7 all execute the following steps 402 to 406.

[0099] Step 402: Acquire a first bus current on the serial data bus.

[0100] In the embodiment of the present invention, if the slave node j detects that there is no allocated target address, the slave node j can obtain the bus current on the serial data bus through its internal addressing module. For the convenience of distinction, in step 402, the bus current obtained by the slave node is called the first bus current.

[0101] For the slave node j, when obtaining the first bus current, the fourth switch unit and the fifth switch unit are first controlled to be turned on, and the third switch unit and the sixth switch unit are controlled to be turned off (the above-mentioned phase 1). The bus current on the serial data bus during the acquisition phase 1 is the first bus current.

[0102] For different slave nodes, the first bus currents obtained may be the same or different.

[0103] For example, the first bus currents on the serial data bus are respectively obtained from the slave nodes 1 to 7. The first bus currents obtained from the slave nodes 1 to 7 are different from each other.

[0104] Specifically, the specific working principle and process of the addressing module acquiring the first bus current can correspond to the description in the above embodiment, which will not be repeated here.

[0105] Step 403: Control the first switch unit to close, and obtain the second bus current on the serial data bus.

[0106] In the embodiment of the present invention, for the slave node j, after obtaining the first bus current, the first switch unit in the internal addressing module can be controlled to close. Specifically, the slave node j can input a first enable signal to the control end of the first switch unit in the internal addressing module. After the control end of the first switch unit receives the first enable signal, the first switch unit is turned on, thereby connecting the pull-up resistor to the serial data bus.

[0107] For example, no target address is assigned to slave node 1 to slave node 7. After obtaining the first bus current corresponding to each slave node 1 to slave node 7, the first switch unit in each addressing module can be controlled to close. The pull-up resistors in the addressing modules of slave node 1 to slave node 7 are all connected to the serial data bus.

[0108] For slave node j, after controlling the first switch unit to be turned on, the third switch unit and the sixth switch unit are controlled to be turned on, and the fourth switch unit and the fifth switch unit are controlled to be turned off (the above-mentioned stage 2). After completing stage 2, the second bus current corresponding to slave node j can be obtained based on the output voltage of the second operational amplifier and the sampling resistor.

[0109] When the pull-up resistor of the slave node is connected to the serial data bus, the bus current on the serial data bus will change. The slave node obtains the bus current on the serial data bus as the second bus current.

[0110] That is to say, for a certain slave node, the second bus current obtained by it is the bus current after the pull-up resistors of several slave nodes are connected to the serial data bus.

[0111] For example, the pull-up resistors in the addressing modules of slave nodes 1 to 7 are all connected to the serial data bus. The second bus currents corresponding to the respective slave nodes 1 to 7 are obtained. For slave node 1, the second bus current obtained is the current flowing through the sampling resistor of slave node 1 after the pull-up resistors of slave nodes 1 to 7 are all connected to the serial data bus.

[0112] Step 404: If the first difference is less than a preset first threshold, control the second switch unit to close.

[0113] In the embodiment of the present invention, for the slave node j, the difference between the first bus current obtained in step 402 and the second bus current obtained in step 403 is obtained, and the difference obtained is the first difference.

[0114] In a specific implementation, if the first difference detected from node j is less than a preset first threshold, the second switch unit can be controlled to close, thereby connecting the current source in the addressing module of node j to the serial data bus. If the first difference detected from node j is greater than the first threshold, the first switch unit in the internal addressing module can be controlled from node j to open (that is, stop inputting the first enable signal to the first switch unit), thereby disconnecting the path between the pull-up resistor in the addressing module and the serial data bus.

[0115] For example, slave node 7 obtains the first bus current I1 based on step 402, obtains the second bus current I2 based on step 403, and the first threshold is Δ1. Slave node 1 detects that I1-I2>Δ1, and then slave node 7 controls the first switch unit in the addressing module (that is, the addressing module of slave node 7) to disconnect.

[0116] If the first difference detected from node j is smaller than the first threshold, the second switch unit in the internal addressing module can be controlled to be turned on from node j, thereby connecting the current source in the internal addressing module to the serial data bus.

[0117] Specifically, it is detected from node j that the first difference is less than the first threshold, and a second enable signal is input to the control end of the second switch unit in the internal addressing module, so that the current source in the internal addressing module is connected to the serial data bus.

[0118] In this scenario, in the addressing module of the slave node j, the first switch unit and the second switch unit are both turned on, and the pull-up resistor and the current source are both connected to the serial data bus.

[0119] Step 405: Acquire a third bus current on the serial data bus.

[0120] In a specific implementation, after the current source of the slave node is connected to the serial data bus, the bus current on the serial data bus will change again. The bus current on the serial data bus is obtained from node j as the third bus current. At this time, the third switch unit and the sixth switch unit remain turned on, and the fourth switch unit and the fifth switch unit remain turned off (the above-mentioned stage 2). After completing stage 2, the third bus current corresponding to the slave node j can be obtained based on the output voltage of the second operational amplifier and the sampling resistor.

[0121] For example, the current sources in the addressing modules of slave nodes 1 to 7 are all connected to the serial data bus. The third bus currents corresponding to the respective slave nodes 1 to 7 are obtained. For slave node 1, the third bus current obtained by it is the current flowing through the sampling resistor of slave node 1 after the current sources of slave nodes 1 to 7 are all connected to the serial data bus.

[0122] Step 406: If the second difference is less than the preset second threshold, obtain the target address from the N addresses to be allocated.

[0123] In the embodiment of the present invention, the second difference is the difference between the third bus current and the first bus current.

[0124] In a specific implementation, for slave node j, if it is detected that the second difference is less than a preset second threshold, one can be selected from N addresses to be allocated as its corresponding target address; conversely, if it is detected that the second difference is greater than the second threshold, the first switch unit and the second switch unit of the internal addressing module can be controlled to be disconnected, thereby controlling the pull-up resistor and the current source of the internal addressing module to disconnect from the serial data bus.

[0125] Specifically, for the slave node j, if it is detected that the second difference is greater than the second threshold, the first enable signal is stopped from being input to the control end of the internal first switch unit, thereby disconnecting the internal pull-up resistor from the serial data bus; and the second enable signal is stopped from being input to the control end of the internal second switch unit, thereby disconnecting the internal current source from the serial data bus.

[0126] If it is detected that the second difference is less than the second threshold, an address to be allocated is selected from the address allocation command as the target address corresponding to the slave node j.

[0127] In the embodiment of the present invention, after assigning the target address to the slave node j, the master node can determine whether there is a slave node that has not been assigned a target address. If the master node detects that there is a slave node that has not been assigned a target address, the master node can resend the address assignment instruction, and the slave node that has not been assigned a target address can re-execute steps 401 to 406; if the master node detects that all N slave nodes have been assigned a target address, the master node ends the address assignment operation.

[0128] In summary, by adopting the slave node address allocation method provided in the above embodiment, accurate address allocation for N slave nodes can be achieved.

[0129] Reference Figure 5 , a slave node address allocation device 50 in an embodiment of the present invention is provided, which is suitable for allocating addresses to slave nodes in a serial data bus communication system provided in any of the above embodiments; the address allocation device 50 comprises: a receiving unit 501, a first acquisition unit 502, a second acquisition unit 503, a first control unit 504, a third acquisition unit 505 and an address allocation unit 506, wherein:

[0130] The receiving unit 501 is configured to receive an address allocation command, wherein the address allocation command includes N addresses to be allocated;

[0131] A first acquisition unit 502, configured to acquire a first bus current on the serial data bus;

[0132] A second acquisition unit 503, used for controlling the first switch unit to close and acquiring a second bus current on the serial data bus;

[0133] A first control unit 504 is configured to detect that the first difference is less than a preset first threshold value, and control the second switch unit to close; the first difference is the difference between the first bus current and the second bus current;

[0134] A third acquisition unit 505, configured to acquire a third bus current on the serial data bus;

[0135] The address allocation unit 506 is used to detect that the second difference is less than a preset second threshold, and obtain a target address from the N addresses to be allocated; the second difference is the difference between the first bus current and the third bus current.

[0136] In a specific implementation, the specific execution process of the above-mentioned receiving unit 501, the first acquisition unit 502, the second acquisition unit 503, the first control unit 504, the third acquisition unit 505 and the address allocation unit 506 can correspond to steps 501 to 506, which will not be repeated here.

[0137] In a specific implementation, each module / unit included in each device or product described in the above embodiments may be a software module / unit or a hardware module / unit, or may be partly a software module / unit and partly a hardware module / unit.

[0138] For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on the processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on the processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0139] An embodiment of the present invention further provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the address allocation method provided in any of the above embodiments are executed.

[0140] An embodiment of the present invention further provides another address allocation device, including a memory and a processor, wherein the memory stores a computer program that can be executed on the processor, and the processor executes the steps of the address allocation method provided in any of the above embodiments when running the computer program.

[0141] A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the relevant hardware through a program, and the program may be stored in a computer-readable storage medium, which may include: ROM, RAM, disk or CD, etc.

[0142] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A serial data bus communication system, characterized in that: include: A master node and N slave nodes, where: The master node is coupled to the N slave nodes via the serial data bus; The i-th slave node among the N slave nodes includes an addressing module; N is a positive integer and N≥2, i is a positive integer and 1≤i≤N; The addressing module includes: a first switch unit, a pull-up resistor, a second switch unit, a current source, a sampling resistor and a current sampling unit, wherein: The first switch unit has a first end input with a power supply voltage, and a second end coupled with a first end of the pull-up resistor; The pull-up resistor has a second end coupled to the serial data bus; The second switch unit has a first end input with the power supply voltage, and a second end coupled with the first end of the current source; The current source has a second end coupled to the serial data bus; The sampling resistor is coupled to the serial data bus; The current sampling unit is adapted to obtain a bus current, wherein the bus current is a difference between an actual current flowing through the sampling resistor and an interference current generated by interference noise on the sampling resistor; the current sampling unit comprises: a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein: the first resistor has a first end coupled to a first end of the sampling resistor, and a second end coupled to a first end of the third switch unit and a first end of the third resistor; the second resistor has a first end coupled to a second end of the sampling resistor, and a second end coupled to a second end of the fourth switch unit and a second input end of the first operational amplifier; the third switch unit has a second end coupled to a first input end of the first operational amplifier and a first end of the fourth switch unit; the fourth switch unit has a second end coupled to a second input end of the first operational amplifier; the fifth switch unit, a first end of which is coupled to the compensation input terminal of the first operational amplifier, and a second end of which is coupled to the output terminal of the first operational amplifier; the sixth switch unit, a first end of which is coupled to the output terminal of the first operational amplifier, and a second end of which is coupled to the compensation input terminal of the second operational amplifier; the fourth switch unit and the fifth switch unit are turned on or off at the same time, the third switch unit and the sixth switch unit are turned on or off at the same time, and the third switch unit and the fourth switch unit are not turned on at the same time; the second operational amplifier, a first input end of which is coupled to the first end of the third resistor, a second input end of which is coupled to the first end of the fourth resistor, and an output end of which is coupled to the analog-to-digital converter; the third resistor, a second end of which inputs a reference voltage; the fourth resistor, a first end of which is coupled to the second input terminal of the second operational amplifier, and a second end of which is coupled to the output terminal of the second operational amplifier.

2. The serial data bus communication system according to claim 1, characterized in that: The current sampling unit further includes: a first capacitor, a second capacitor and a third capacitor, wherein: The first capacitor has a first end coupled to the output end of the first operational amplifier and a second end grounded; The second capacitor has a first end coupled to the first end of the fourth resistor, and a second end coupled to the second end of the fourth resistor; The third capacitor has a first terminal coupled to the output terminal of the second operational amplifier and a second terminal grounded.

3. The serial data bus communication system according to claim 1 or 2, characterized in that: The current sampling unit further includes: a first switch tube and a second switch tube, wherein: The first switch tube has a drain coupled to the second end of the first resistor, a gate inputting an enable signal, and a source coupled to the first end of the third switch unit and the first end of the third resistor; The second switch tube has a drain coupled to the second end of the second resistor, a gate coupled to the gate of the first switch tube, and a source coupled to the second end of the fourth switch unit.

4. The serial data bus communication system according to claim 3, characterized in that: The current sampling unit further includes: a first diode and a second diode, wherein: The first diode has a cathode coupled to the second end of the first resistor and an anode coupled to the anode of the second diode and a ground terminal; The cathode of the second diode is coupled to the second end of the second resistor.

5. The serial data bus communication system according to claim 3, characterized in that: The current sampling unit further includes: a fourth capacitor, a first end of which is coupled to the input end of the first operational amplifier and the compensation input end of the second operational amplifier, and a second end of which is grounded.

6. A method for allocating slave node addresses, characterized in that: Suitable for allocating addresses to slave nodes in the serial data bus communication system according to any one of claims 1 to 5; The slave node address allocation method comprises: Receiving an address allocation command, wherein the address allocation command includes N addresses to be allocated; Acquiring a first bus current on the serial data bus; Controlling the first switch unit to close, and obtaining a second bus current on the serial data bus; If the first difference is less than a preset first threshold, controlling the second switch unit to close; the first difference is the difference between the first bus current and the second bus current; Acquiring a third bus current on the serial data bus; If the second difference is less than a preset second threshold, a target address is obtained from the N addresses to be allocated; the second difference is a difference between the first bus current and the third bus current.

7. The slave node address allocation method according to claim 6, characterized in that: Before receiving the address allocation command, it also includes: It is determined that the target address does not exist.

8. The slave node address allocation method according to claim 6, characterized in that: If the first difference is greater than the first threshold, the first switch unit is controlled to be disconnected.

9. The slave node address allocation method according to claim 6, characterized in that: If the second difference is greater than the second threshold, the first switch unit is controlled to be disconnected, and the second switch unit is controlled to be disconnected.

10. The slave node address allocation method according to claim 6, characterized in that: The first threshold is equal to the second threshold.

11. A slave node address allocation device, characterized in that: Suitable for allocating addresses to slave nodes in the serial data bus communication system according to any one of claims 1 to 5, the slave node address allocation device comprising: A receiving unit, configured to receive an address allocation command, wherein the address allocation command includes N addresses to be allocated; A first acquisition unit, used for acquiring a first bus current on the serial data bus; a second acquisition unit, configured to control the first switch unit to close, and acquire a second bus current on the serial data bus; A first control unit, configured to detect that a first difference is less than a preset first threshold value, and control the second switch unit to close; the first difference is a difference between the first bus current and the second bus current; A third acquisition unit, used for acquiring a third bus current on the serial data bus; The address allocation unit is used to detect that the second difference is less than a preset second threshold value and obtain a target address from the N addresses to be allocated; the second difference is the difference between the first bus current and the third bus current.

12. A computer-readable storage medium, wherein the computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium, and a computer program is stored thereon, wherein: When the computer program is executed by a processor, the steps of the slave node address allocation method according to any one of claims 6 to 10 are executed.

13. A slave node address allocation device, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor runs the computer program, the processor executes the steps of the slave node address allocation method described in any one of claims 6 to 10.

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