Terminal structure of semiconductor power device and manufacturing method thereof

Abstract

The invention discloses a terminal structure of a semiconductor power device. The terminal structure comprises a plurality of field limiting rings. Each field limiting ring is of an annular structure formed by connecting a plurality of field limiting ring linear sections and a plurality of field limiting ring corner sections end to end, and each field limiting ring corner section comprises a field limiting ring outer side corner edge and a field limiting ring inner side corner edge. The curvature radius of the field limiting ring outer side corner edge and the curvature radius of the field limiting ring inner side corner edge are independently arranged. The curvature radius of the outer corner edge of the field limiting ring is larger than or equal to a first set value, and the larger the curvature radius of the outer corner edge of the field limiting ring is, the more relieved the electric field concentration at the edge of the field limiting ring is and the smaller the electric field intensity is. The curvature radius of the inner side corner edge of the field limiting ring is smaller than or equal to a second set value, the smaller the curvature radius of the inner side corner edge of the field limiting ring is, the larger the area surrounded by the inner side edge of the field limiting ring is, and the larger the area of the active area is. The invention further discloses a manufacturing method of the terminal structure of the semiconductor power device. The reverse voltage endurance capability of the device can be improved, and the area and the current density of the active region can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a terminal structure of a semiconductor power device; the present invention also relates to a method for manufacturing the terminal structure of a semiconductor power device. Background Art

[0002] With the development of science and technology, power fast recovery diode (FRD) devices have been widely used in many fields. Power FRD devices play a key role in energy conversion and power electronic equipment, and have become indispensable devices in life and industry.

[0003] In the design of semiconductor FRD devices, the active area often determines the main characteristics of the device, such as forward resistance, withstand voltage, and switching speed, etc., but the active area has always been limited by the design of the terminal area, such as the area. The design of the terminal area of ​​existing power devices is usually based on structures such as field limiting rings (FLR) and junction terminal extensions (JTE). Among them, the field limiting ring is more commonly used but occupies a larger area. However, the turning point of the field limiting ring, as shown by the mark 107 in Figure 1, is usually a weak point in withstand voltage, because this is the intersection of the electric field lines on both sides of the chip and the PN junction will change from a planar junction to a spherical junction. When the curvature radius of the spherical junction is set too small, it is easy for the electric field lines to concentrate and exceed the maximum electric field strength that the semiconductor material, such as Si body, can withstand, resulting in breakdown. If the curvature radius is too large, the terminal area will occupy too large an area, squeezing the conduction area of ​​the active area and thus deteriorating the device performance. Therefore, the radius of the corner area of ​​the field limiting ring of the existing power fast recovery diode is not easy to set. If it is too large, it will occupy a larger area, and if it is too small, it will reduce the breakdown voltage.

[0004] like Figure 1A As shown, it is a top view of the corner area of ​​the terminal structure of the existing fast recovery diode. Figure 1A The top view is a top view of the metal layer; Figure 1B As shown in FIG. 1 , it is a schematic diagram of the cross-sectional structure of an existing fast recovery diode; Figure 1C , which is a top view of the terminal structure of the existing fast recovery diode; Figure 1C The top view is a top view of the bottom of the metal layer. The terminal structure of the conventional fast recovery diode is formed in the terminal region 101b, and the terminal region 101b surrounds the peripheral side of the active region 101a.

[0005] The terminal structure includes:

[0006] A plurality of P-type doped field limiting rings 104 are formed in a selected region of the N-type lightly doped first epitaxial layer 102 .

[0007] like Figure 1CAs shown, each field limiting ring 104 is formed by connecting four straight line segments through arc-shaped corner segments.

[0008] A P-type doped main junction region 103 is formed in the active region 101 a , and the main junction region 103 and the first epitaxial layer 102 form a PN main junction.

[0009] The active region 101 a is defined by the field oxide layer at the bottom of the interlayer film 105 , and the formation region of each field limiting ring 104 is also defined by the field oxide layer.

[0010] A terminal field plate 106b composed of a front metal layer is disposed on the top of each field limiting ring 104, and each field limiting ring 104 and the terminal field plate 106b on the top are connected via a contact hole passing through the interlayer film 105. Figure 1A As shown, the terminal field plate 106b is also formed by connecting straight line segments and arc-shaped corner segments.

[0011] like Figure 1B As shown, the coverage area of ​​the terminal field plate 106 b ensures that the corresponding field limiting ring 104 at the bottom is completely covered and extends to the outside of the field limiting ring 104 .

[0012] An anode metal 106 a formed by a front metal layer is formed on the top of the active region 101 a , and the anode metal 106 a is connected to the main junction region 103 .

[0013] The anode metal 106a also extends into the termination region 101b outside the main junction region 103 and forms a second field plate.

[0014] An N-type heavily doped cathode region is formed on the back side of the first epitaxial layer 102 , and a cathode metal (not shown) composed of a back metal layer is formed on the back side of the cathode region. In the prior art, the cathode region is formed in the thinned semiconductor substrate 101 .

[0015] like Figure 1A As shown, the field limiting ring 104 of the existing fast recovery diode is prone to produce electric field concentration in the corner area, and the corner area of ​​the field limiting ring 104 also corresponds to Figure 1A In the corner area of ​​the middle terminal field plate 106 b , such as the area indicated by the mark 107 , the electric field is concentrated so that the electric field strength in the corner area of ​​the field limiting ring 104 is increased, which is easy to cause breakdown. Summary of the invention

[0016] The technical problem to be solved by the present invention is to provide a terminal structure of a semiconductor power device, which can improve the reverse withstand voltage capability of the field limiting ring and thus improve the reverse withstand voltage characteristics of the entire power device and optimize the reverse leakage current of the device, thereby improving the reliability of the device; and can also increase the active area and current density. To this end, the present invention also discloses a method for manufacturing the terminal structure of a semiconductor power device.

[0017] In order to solve the above technical problems, the terminal structure of the semiconductor power device provided by the present invention is formed in a terminal region, and the terminal region surrounds the peripheral side of the active region.

[0018] The terminal structure comprises:

[0019] A plurality of second conductivity type doped field limiting rings are each formed in a selected region of the first epitaxial layer lightly doped with the first conductivity type.

[0020] Each of the field limiting rings is an annular structure formed by connecting multiple field limiting ring straight segments and multiple field limiting ring corner segments end to end. Each adjacent field limiting ring straight segment is connected by a field limiting ring corner segment, and the number of the field limiting ring straight segments is the same as the number of the field limiting ring corner segments; the field limiting ring straight segments with the same serial number between different field limiting rings are parallel to each other, and the field limiting ring corner segments with the same serial number between different field limiting rings are aligned with each other.

[0021] Each of the field-limiting ring corner sections comprises an outer corner edge of the field-limiting ring and an inner corner edge of the field-limiting ring.

[0022] The curvature radii of the outer corner edge of the field limiting ring and the inner corner edge of the field limiting ring are independently set.

[0023] The radius of curvature of the outer corner edge of the field limiting ring is greater than or equal to a first set value. The larger the radius of curvature of the outer corner edge of the field limiting ring, the more the electric field concentration at the edge of the field limiting ring is alleviated and the smaller the electric field strength is. When the radius of curvature of the outer corner edge of the field limiting ring is the first set value, the electric field strength at the edge of the field limiting ring reaches a maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer.

[0024] The radius of curvature of the inner corner edge of the field limiting ring is less than or equal to a second set value. The smaller the radius of curvature of the inner corner edge of the field limiting ring is, the larger the area surrounded by the inner edge of the field limiting ring is, and the larger the area of ​​the active region is. When the radius of curvature of the inner corner edge of the field limiting ring is the second set value, the area of ​​the active region reaches the minimum required value.

[0025] A further improvement is that a main junction region doped with the second conductivity type is formed in the active region, and the main junction region and the first epitaxial layer form a PN main junction.

[0026] The outermost edge of the main junction region is formed by connecting multiple main junction region straight edges and multiple main junction region corner edges end to end; the number of the main junction region straight edges is the same as the number of the field limiting ring straight segments, each of the main junction region straight edges and the field limiting ring straight segments with the same serial number are parallel to each other, and each of the main junction region corner edges and the field limiting ring corner segments with the same serial number are aligned with each other.

[0027] The radius of curvature of each main junction region corner edge is greater than or equal to a third set value. The larger the radius of curvature of the main junction region corner edge, the more alleviated the electric field concentration at the main junction region corner edge and the smaller the electric field strength. When the radius of curvature of the main junction region corner edge is the third set value, the electric field strength at the main junction region corner edge reaches the maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer.

[0028] A further improvement is that it also includes a plurality of terminal field plates composed of front metal layers.

[0029] A terminal field plate composed of a front metal layer is arranged on the top of each field limiting ring, and each field limiting ring and the terminal field plate on the top are connected via a contact hole penetrating through the interlayer film.

[0030] Each of the terminal field plates is a ring structure formed by connecting multiple terminal field plate straight segments and multiple terminal field plate corner segments end to end, and the number of the terminal field plate straight segments is the same as the number of the field limiting ring straight segments.

[0031] The coverage area of ​​each terminal field plate straight segment is guaranteed to completely cover the corresponding field limiting ring straight segment at the bottom and extend to the outside of the field limiting ring straight segment.

[0032] The coverage area of ​​each terminal field plate corner segment ensures that the corresponding field limiting ring corner segment at the bottom is completely covered and extends to the outside of the field limiting ring corner segment.

[0033] A further improvement is that a first electrode formed by a front metal layer is formed on the top of the active area, and the first electrode is connected to the main junction area.

[0034] The first electrode also extends into the termination region outside the main junction region and forms a second field plate.

[0035] A further improvement is that it also includes: a plurality of dielectric layer field plates.

[0036] Each of the dielectric layer field plates is arranged in the interlayer film at the top of each of the field limiting ring corner segments and each of the main junction region corner edges, and the material of the dielectric layer field plate is different from that of the interlayer film.

[0037] The dielectric layer field plate at the top of each field limiting ring corner segment extends from the inner side of the outer edge of the terminal field plate corner segment to the outer side.

[0038] The dielectric layer field plate at the top of each corner edge of the main junction region extends from the inner side of the outer edge of the first electrode to the outer side.

[0039] A further improvement is that the material of the interlayer film includes an oxide layer; and the material of the dielectric layer field plate includes polysilicon doped with the second conductivity type.

[0040] A further improvement is that a second electrode region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer, and a second electrode composed of a back metal layer is formed on the back side of the second electrode region.

[0041] A further improvement is that the semiconductor power device includes a fast recovery diode.

[0042] A further improvement is that the number of the field-limiting ring straight line segments is four, and each two adjacent field-limiting ring straight line segments are perpendicular to each other.

[0043] In order to solve the above technical problems, the present invention provides a method for manufacturing a terminal structure of a semiconductor power device, comprising the following steps:

[0044] A first epitaxial layer lightly doped with a first conductivity type is formed by epitaxial growth on a semiconductor substrate.

[0045] Ions of the second conductivity type are implanted to form a plurality of field limiting rings in selected areas of the terminal region, the terminal region surrounding the peripheral side of the active region.

[0046] Each of the field limiting rings is an annular structure formed by connecting multiple field limiting ring straight segments and multiple field limiting ring corner segments end to end. Each adjacent field limiting ring straight segment is connected by a field limiting ring corner segment, and the number of the field limiting ring straight segments is the same as the number of the field limiting ring corner segments; the field limiting ring straight segments with the same serial number between different field limiting rings are parallel to each other, and the field limiting ring corner segments with the same serial number between different field limiting rings are aligned with each other.

[0047] Each of the field-limiting ring corner sections comprises an outer corner edge of the field-limiting ring and an inner corner edge of the field-limiting ring.

[0048] The curvature radii of the outer corner edge of the field limiting ring and the inner corner edge of the field limiting ring are independently set.

[0049] The radius of curvature of the outer corner edge of the field limiting ring is greater than or equal to a first set value. The larger the radius of curvature of the outer corner edge of the field limiting ring, the more the electric field concentration at the edge of the field limiting ring is alleviated and the smaller the electric field strength is. When the radius of curvature of the outer corner edge of the field limiting ring is the first set value, the electric field strength at the edge of the field limiting ring reaches a maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer.

[0050] The radius of curvature of the inner corner edge of the field limiting ring is less than or equal to a second set value. The smaller the radius of curvature of the inner corner edge of the field limiting ring is, the larger the area surrounded by the inner edge of the field limiting ring is, and the larger the area of ​​the active region is. When the radius of curvature of the inner corner edge of the field limiting ring is the second set value, the area of ​​the active region reaches the minimum required value.

[0051] Further improvements include:

[0052] Ions of the second conductivity type are implanted to form a main junction region in the active region, and the main junction region and the first epitaxial layer form a PN main junction.

[0053] The outermost edge of the main junction region is formed by connecting multiple main junction region straight edges and multiple main junction region corner edges end to end; the number of the main junction region straight edges is the same as the number of the field limiting ring straight segments, each of the main junction region straight edges and the field limiting ring straight segments with the same serial number are parallel to each other, and each of the main junction region corner edges and the field limiting ring corner segments with the same serial number are aligned with each other.

[0054] The radius of curvature of each main junction region corner edge is greater than or equal to a third set value. The larger the radius of curvature of the main junction region corner edge, the more alleviated the electric field concentration at the main junction region corner edge and the smaller the electric field strength. When the radius of curvature of the main junction region corner edge is the third set value, the electric field strength at the main junction region corner edge reaches the maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer.

[0055] Further improvements include:

[0056] An interlayer film, a contact hole passing through the interlayer film and a front metal layer are formed, and the front metal layer is patterned to form a plurality of terminal field plates and a first electrode.

[0057] A terminal field plate is disposed on the top of each field limiting ring, and each field limiting ring and the terminal field plate on the top are connected through corresponding contact holes.

[0058] Each of the terminal field plates is a ring structure formed by connecting multiple terminal field plate straight segments and multiple terminal field plate corner segments end to end, and the number of the terminal field plate straight segments is the same as the number of the field limiting ring straight segments.

[0059] The coverage area of ​​each terminal field plate straight segment is guaranteed to completely cover the corresponding field limiting ring straight segment at the bottom and extend to the outside of the field limiting ring straight segment.

[0060] The coverage area of ​​each terminal field plate corner segment ensures that the corresponding field limiting ring corner segment at the bottom is completely covered and extends to the outside of the field limiting ring corner segment.

[0061] The first electrode is connected to the main junction region.

[0062] The first electrode also extends into the termination region outside the main junction region and forms a second field plate.

[0063] A further improvement is that before the ion implantation of the field limiting ring is performed, the method further comprises:

[0064] A field oxide layer is formed on the surface of the first epitaxial layer.

[0065] A photolithography process is performed to open the formation area of ​​the field limiting ring, and then the field oxide layer in the opened area is removed.

[0066] Afterwards, ion implantation of the field limiting ring is performed using the field oxide layer as a mask.

[0067] After the ion implantation of the field limiting ring is completed, the method further comprises:

[0068] A first photoresist pattern is formed by a photolithography process to open the active area, and then the field oxide layer in the open area is removed.

[0069] Afterwards, ion implantation is performed in the main junction region using the first photoresist pattern as a mask.

[0070] Afterwards, the field limiting ring and the main junction region are simultaneously annealed.

[0071] A further improvement is that after the field limiting ring and the main junction region are formed, the method further comprises:

[0072] A material layer for forming a dielectric layer field plate.

[0073] The material layer of the dielectric layer field plate is patterned and etched to form a plurality of dielectric layer field plates.

[0074] Each of the dielectric layer field plates is arranged in the interlayer film at the top of each of the field limiting ring corner segments and each of the main junction region corner edges, and the material of the dielectric layer field plate is different from that of the interlayer film.

[0075] The dielectric layer field plate at the top of each field limiting ring corner segment extends from the inner side of the outer edge of the terminal field plate corner segment to the outer side.

[0076] The dielectric layer field plate at the top of each corner edge of the main junction region extends from the inner side of the outer edge of the first electrode to the outer side.

[0077] The interlayer film is formed after the dielectric layer field plate is formed, and in the terminal region, the field oxide layer serves as a part of the interlayer film.

[0078] A further improvement is that the material of the interlayer film includes an oxide layer; and the material of the dielectric layer field plate includes polysilicon doped with the second conductivity type.

[0079] A further improvement is that after the front process is completed, the following back process is also included:

[0080] The semiconductor substrate is thinned and a second electrode region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer. The second electrode region is directly composed of the thinned semiconductor substrate heavily doped with the first conductivity type or the second electrode region is formed by back-side implantation of the heavily doped first conductivity type into the thinned semiconductor substrate.

[0081] A back metal layer is formed on the back side of the second electrode region, and the back metal layer constitutes a second electrode.

[0082] A further improvement is that the number of the field-limiting ring straight line segments is four, and each two adjacent field-limiting ring straight line segments are perpendicular to each other.

[0083] The present invention makes special arrangements for the corner section of the field limiting ring, i.e., the structure of the field limiting ring corner section, mainly by independently setting the curvature radii of the outer corner edge of the field limiting ring and the inner corner edge of the field limiting ring as required, and by increasing the curvature radius of the outer corner edge of the field limiting ring to improve the reverse voltage withstand capability of the field limiting ring. This is because, after the curvature radius of the outer corner edge of the field limiting ring is increased, the injection area of ​​the field limiting ring can be expanded, and the spherical junction part at the corner of the field limiting ring can be fully converted into a parallel junction, thereby improving the reverse bias performance, including increasing the reverse breakdown voltage and reducing the reverse leakage current.

[0084] At the same time, the present invention can increase the active area and the current density by reducing the curvature radius of the inner corner edge of the field limiting ring.

[0085] The present invention can also improve the structure of the corner area of ​​the terminal field plate at the top of the field limiting ring synchronously with the structure of the corner area of ​​the field limiting ring, which can further alleviate the concentration of electric field lines in the corner area of ​​the field limiting ring and thereby further increase the reverse voltage withstand capability.

[0086] The present invention can also make a similar arrangement to the outer corner edge of the field limiting ring for the corner edge of the main junction region, which can further increase the reverse voltage withstand capability of the device.

[0087] The present invention can also improve the corner area structure of the second field plate formed by extending the first electrode at the top of the active area to the outside of the main junction area in synchronization with the corner edge area of ​​the main junction area, which can further concentrate the electric field lines in the corner edge area of ​​the main junction area and thereby further increase the reverse voltage withstand capability.

[0088] The present invention can further provide dielectric layer field plates such as polysilicon field plates at the top of the field limiting ring corner segment and the top of the main junction region corner edge, which can further alleviate the electric field line concentration in the field limiting ring and the main junction region corner region and thereby further increase the reverse withstand voltage capability.

[0089] Therefore, the present invention can expand the injection area of ​​the corner zone, thereby improving the P / N junction morphology at the turning point of the field limiting ring. Combined with the improvement of the field plate synchronization structure in the corner zone, the edge curvature of the P / N junction can be increased, thereby improving the reverse withstand voltage capability of the field limiting ring. The present invention can adjust the distribution of the electric field, realize a more uniform longitudinal electric field in the drift zone, improve the reverse withstand voltage characteristics of power devices such as fast recovery diodes, and optimize the reverse leakage current, thereby improving the reliability of the device.

[0090] The present invention can be implemented under existing process capability conditions, and the reverse withstand voltage characteristics of power devices such as fast recovery diodes can be improved by only modifying the morphology and structure of the device, thereby increasing the application scenarios of the device and enhancing the reliability of the device.

[0091] The present invention further improves the reverse bias performance, such as increasing the reverse breakdown voltage and reducing the reverse leakage current, by enlarging the curvature radius of the field limiting ring, and converting the terminal spherical junction part of the body region, i.e., the main junction region, into a parallel junction, thereby increasing the active area and current density.

[0092] The manufacturing process of the present invention is fully compatible with the existing general power device FRD process, and the solution is relatively easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0093] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0094] Figure 1A is a top view of a corner region of a terminal structure of an existing fast recovery diode;

[0095] Figure 1B It is a schematic diagram of the cross-sectional structure of an existing fast recovery diode;

[0096] Figure 1C It is a top view of the terminal structure of the existing fast recovery diode;

[0097] Figure 2A is a top view of a corner region of a terminal structure of a semiconductor power device according to a first embodiment of the present invention;

[0098] Figure 2B is a schematic cross-sectional structure diagram of a semiconductor power device according to a first embodiment of the present invention;

[0099] Figure 3A is a top view of a corner region of a terminal structure of a semiconductor power device according to a second embodiment of the present invention;

[0100] Figure 3B is a schematic cross-sectional structural diagram of a semiconductor power device according to a second embodiment of the present invention;

[0101] Figure 4A-4H It is a schematic diagram of the device structure in each step of the method for manufacturing the terminal structure of the semiconductor power device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0102] like Figure 2A FIG. 1 is a top view of a corner region of a terminal structure of a semiconductor power device according to a first embodiment of the present invention. Figure 2A A top view of the metal layer; Figure 2B , which is a schematic diagram of the cross-sectional structure of the semiconductor power device according to the first embodiment of the present invention; the terminal structure of the semiconductor power device according to the embodiment of the present invention is formed in the terminal region 201b, and the terminal region 201b surrounds the peripheral side of the active region 201a.

[0103] The terminal structure includes:

[0104] A plurality of second conductivity type doped field limiting rings 204 are formed in a selected region of the first epitaxial layer 202 lightly doped with the first conductivity type.

[0105] Each field limiting ring 204 is a ring structure formed by connecting multiple field limiting ring straight segments and multiple field limiting ring corner segments end to end. Each adjacent field limiting ring straight segment is connected by a field limiting ring corner segment, and the number of field limiting ring straight segments is the same as the number of field limiting ring corner segments; the field limiting ring straight segments with the same serial number between different field limiting rings 204 are parallel to each other, and the field limiting ring corner segments with the same serial number between different field limiting rings 204 are aligned with each other.

[0106] Each field limiting ring corner section includes an outer corner edge of the field limiting ring and an inner corner edge of the field limiting ring.

[0107] The curvature radii of the outer corner edge of the field limiting ring and the inner corner edge of the field limiting ring are set independently.

[0108] The radius of curvature of the outer corner edge of the field limiting ring is greater than or equal to a first set value. The larger the radius of curvature of the outer corner edge of the field limiting ring, the more the electric field concentration at the edge of the field limiting ring 204 is alleviated and the smaller the electric field strength is. When the radius of curvature of the outer corner edge of the field limiting ring is the first set value, the electric field strength at the edge of the field limiting ring 204 reaches the maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer 202.

[0109] The radius of curvature of the inner corner edge of the field limiting ring is less than or equal to the second set value. The smaller the radius of curvature of the inner corner edge of the field limiting ring is, the larger the area surrounded by the inner edge of the field limiting ring 204 is, and the larger the area of ​​the active area 201a is. When the radius of curvature of the inner corner edge of the field limiting ring is the second set value, the area of ​​the active area 201a reaches the minimum required value.

[0110] In the first embodiment of the present invention, a main junction region 203 doped with the second conductivity type is formed in the active region 201 a , and the main junction region 203 and the first epitaxial layer 202 form a PN main junction.

[0111] The outermost edge of the main junction region 203 is formed by connecting multiple main junction region line edges and multiple main junction region corner edges end to end; the number of main junction region line edges is the same as the number of field limiting ring straight line segments, each main junction region line edge and the field limiting ring straight line segment with the same serial number are parallel to each other, and each main junction region corner edge and the field limiting ring corner segment with the same serial number are aligned with each other.

[0112] The radius of curvature of the corner edge of each main junction region is greater than or equal to a third set value. The larger the radius of curvature of the corner edge of the main junction region, the more alleviated the electric field concentration at the corner edge of the main junction region and the smaller the electric field strength. When the radius of curvature of the corner edge of the main junction region is the third set value, the electric field strength at the corner edge of the main junction region reaches the maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer 202.

[0113] The first embodiment of the present invention further includes a plurality of terminal field plates 206b consisting of a front metal layer.

[0114] A terminal field plate 206 b composed of a front metal layer is disposed on the top of each field limiting ring 204 , and each field limiting ring 204 and the terminal field plate 206 b on the top are connected via a contact hole penetrating the interlayer film 205 .

[0115] like Figure 2A As shown, each terminal field plate 206b is a ring structure formed by connecting multiple terminal field plate straight segments 301 and multiple terminal field plate corner segments 302 end to end, and the number of terminal field plate straight segments 301 is the same as the number of field limiting ring straight segments.

[0116] The coverage area of ​​each terminal field plate straight segment 301 is guaranteed to completely cover the corresponding field limiting ring straight segment at the bottom and extend to the outside of the field limiting ring straight segment.

[0117] The coverage area of ​​each terminal field plate corner segment 302 ensures that the corresponding field limiting ring corner segment at the bottom is fully covered and extends to the outside of the field limiting ring corner segment. In the first embodiment of the present invention, the curvature radius of the terminal field plate outer corner edge 303 of the terminal field plate corner segment 302 can be set synchronously with the outer corner edge of the field limiting ring at the bottom, and the curvature radius of the terminal field plate inner corner edge 304 of the terminal field plate corner segment 302 can be set synchronously with the inner corner edge of the field limiting ring at the bottom; in this way, the electric field line concentration in the corner area of ​​the field limiting ring 204 at the bottom can be alleviated by increasing the curvature radius of the outer corner edge 303 of the terminal field plate, thereby improving the reverse withstand voltage of the device; the curvature radius of the inner corner edge 304 of the terminal field plate can be reduced, and finally the area of ​​the surrounded area can be increased and the area of ​​the active area 201a can be increased.

[0118] In the first embodiment of the present invention, a first electrode 206 a formed by a front metal layer is formed on the top of the active region 201 a , and the first electrode 206 a is connected to the main junction region 203 .

[0119] The first electrode 206 a also extends into the termination region 201 b outside the main junction region 203 and forms a second field plate.

[0120] In the first embodiment of the present invention, the material of the interlayer film 205 includes an oxide layer.

[0121] A second electrode region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer 202, and a second electrode (not shown) composed of a back metal layer is formed on the back side of the second electrode region. In the first embodiment of the present invention, the second electrode region is formed in the thinned semiconductor substrate 201. In some embodiments, the semiconductor substrate 201 adopts a heavily doped structure of the first conductivity type, and the second electrode region is directly composed of the thinned semiconductor substrate 201. In some embodiments, the second electrode region can also be formed by performing back ion implantation of heavily doped first conductivity type on the thinned semiconductor substrate 201.

[0122] In the first embodiment of the present invention, the semiconductor power device includes a fast recovery diode.

[0123] In the first embodiment of the present invention, the first conductivity type is N type, and the second conductivity type is P type, so that the first electrode region is an anode region, and the second electrode region is a cathode region. In other embodiments, the first conductivity type can be P type, and the second conductivity type is N type, so that the first electrode region is a cathode region, and the second electrode region is an anode region.

[0124] In the first embodiment of the present invention, the number of the field limiting ring straight line segments is four, and each two adjacent field limiting ring straight line segments are perpendicular to each other. In other embodiments, the number of the field limiting ring straight line segments can also be set as required.

[0125] The first embodiment of the present invention makes special arrangements for the structure of the corner section of the field limiting ring 204, that is, the corner section of the field limiting ring. The main purpose is to independently arrange the curvature radii of the outer corner edge of the field limiting ring and the inner corner edge of the field limiting ring as required, and to improve the reverse voltage withstand capability of the field limiting ring 204 by enlarging the curvature radius of the outer corner edge of the field limiting ring. This is because, after the curvature radius of the outer corner edge of the field limiting ring is increased, the injection area of ​​the field limiting ring 204 can be enlarged, and the spherical junction part at the corner of the field limiting ring 204 can be fully converted into a parallel junction, thereby improving the reverse bias performance, including improving the reverse breakdown voltage and reducing the reverse leakage current.

[0126] At the same time, the first embodiment of the present invention can increase the area of ​​the active region 201 a and the current density by reducing the curvature radius of the inner corner edge of the field limiting ring.

[0127] The first embodiment of the present invention can also improve the structure of the corner area of ​​the terminal field plate 206b at the top of the field limiting ring 204 synchronously with the structure of the corner area of ​​the field limiting ring 204, which can further alleviate the concentration of electric field lines in the corner area of ​​the field limiting ring 204 and thereby further increase the reverse voltage withstand capability.

[0128] The first embodiment of the present invention can also make a similar arrangement to the outer corner edge of the field limiting ring for the corner edge of the main junction region, which can further increase the reverse voltage withstand capability of the device.

[0129] The first embodiment of the present invention can also make improvements to the corner area structure of the second field plate formed by extending the first electrode 206a at the top of the active area 201a to the outside of the main junction area 203 in synchronization with the corner edge area of ​​the main junction area, which can further concentrate the electric field lines in the corner edge area of ​​the main junction area and thereby further increase the reverse voltage resistance capability.

[0130] Therefore, the first embodiment of the present invention can expand the injection area of ​​the corner region, thereby improving the P / N junction morphology at the turning point of the field limiting ring 204. Combined with the improvement of the field plate synchronization structure in the corner region, the curvature of the P / N junction edge can be increased, thereby improving the reverse withstand voltage capability of the field limiting ring 204. The first embodiment of the present invention can adjust the distribution of the electric field, realize a more uniform longitudinal electric field in the drift region, improve the reverse withstand voltage characteristics of power devices such as fast recovery diodes, and optimize the reverse leakage current, thereby improving the reliability of the device.

[0131] The first embodiment of the present invention can be implemented under existing process capabilities. It only requires modifying the morphology and structure of the device to improve the reverse withstand voltage characteristics of power devices such as fast recovery diodes, thereby increasing the application scenarios of the device and enhancing the reliability of the device.

[0132] The first embodiment of the present invention increases the radius of curvature of the field limiting ring 204 to more fully transform the terminal spherical junction portion of the body region, i.e., the main junction region 203, into a parallel junction, thereby improving the reverse bias performance such as increasing the reverse breakdown voltage and reducing the reverse leakage current, and increasing the area and current density of the active region 201a.

[0133] like Figure 3A , which is a top view of a corner region of a terminal structure of a semiconductor power device according to a second embodiment of the present invention; Figure 3B It is a schematic diagram of the cross-sectional structure of the semiconductor power device of the second embodiment of the present invention; the difference from the terminal structure of the semiconductor power device of the second embodiment of the present invention is that the terminal structure of the semiconductor power device of the second embodiment of the present invention further includes: multiple dielectric layer field plates 207.

[0134] Each dielectric layer field plate 207 is disposed in the interlayer film 205 at the top of each field limiting ring corner segment and each main junction region corner edge, and the material of the dielectric layer field plate 207 is different from that of the interlayer film 205 .

[0135] The dielectric layer field plate 207 at the top of each field limiting ring corner segment extends from the inner side of the outer edge of the terminal field plate corner segment 302 to the outer side.

[0136] The dielectric layer field plate 207 at the top of each main junction corner edge extends from the inner side of the outer edge of the first electrode 206 a to the outer side.

[0137] In some preferred embodiments, the material of the dielectric layer field plate 207 includes polysilicon doped with the second conductivity type.

[0138] In the second embodiment of the present invention, by providing a dielectric layer field plate 207 such as a polysilicon field plate at the top of the field limiting ring corner segment and the top of the main junction region corner edge, the electric field line concentration in the corner region of the field limiting ring 204 and the main junction region 203 can be further alleviated and the reverse voltage withstand capability can be further increased.

[0139] like 4A to 4HAs shown, it is a schematic diagram of the device structure in each step of the method for manufacturing the terminal structure of the semiconductor power device of the embodiment of the present invention. The method for manufacturing the terminal structure of the semiconductor power device of the embodiment of the present invention can manufacture the terminal structure of the semiconductor power device of the first embodiment of the present invention, and can also manufacture the terminal structure of the semiconductor power device of the second embodiment of the present invention. Since the terminal structure of the semiconductor power device of the second embodiment of the present invention has an additional dielectric layer field plate 207, the method for manufacturing the terminal structure of the semiconductor power device of the embodiment of the present invention is described below by taking the formation of the terminal structure of the semiconductor power device of the second embodiment of the present invention as an example. When the method for manufacturing the terminal structure of the semiconductor power device of the embodiment of the present invention is used to form the terminal structure of the semiconductor power device of the first embodiment of the present invention, the step of forming the dielectric layer field plate 207 can be omitted. The method for manufacturing the terminal structure of the semiconductor power device of the embodiment of the present invention comprises the following steps:

[0140] Step 1: Figure 4A As shown, a first epitaxial layer 202 lightly doped with a first conductivity type is formed by epitaxial growth on a semiconductor substrate 201 .

[0141] Step 2: Perform ion implantation of the second conductivity type to form a plurality of field limiting rings 204 in a selected area of ​​the terminal region 201 b , and the terminal region 201 b surrounds the peripheral side of the active region 201 a .

[0142] In the method of the embodiment of the present invention, step 2 includes the following sub-steps:

[0143] like Figure 4A As shown, a field oxide layer 2051 is formed on the surface of the first epitaxial layer 202 .

[0144] In some embodiments, the thickness of the field oxide layer 2051 is about 1 μm.

[0145] like Figure 4A As shown, a photolithography process is performed to form a photoresist pattern 401 to open a formation region for the field limiting ring 204 .

[0146] like Figure 4B As shown, the field oxide layer 2051 in the open area is then removed.

[0147] Afterwards, ion implantation of the field limiting ring 204 is performed using the field oxide layer 2051 as a mask.

[0148] Taking the second conductivity type as P type as an example, the process conditions of ion implantation of the field limiting ring 204 include: implantation impurities include boron, implantation energy is 100keV-120keV, and implantation dose is 1E14cm -2 ~1E15cm -2 In the actual process, the process conditions of the ion implantation of the field limiting ring 204 can be further adjusted according to the device design requirements.

[0149] Each field limiting ring 204 is a ring structure formed by connecting multiple field limiting ring straight segments and multiple field limiting ring corner segments end to end. Each adjacent field limiting ring straight segment is connected by a field limiting ring corner segment, and the number of field limiting ring straight segments is the same as the number of field limiting ring corner segments; the field limiting ring straight segments with the same serial number between different field limiting rings 204 are parallel to each other, and the field limiting ring corner segments with the same serial number between different field limiting rings 204 are aligned with each other.

[0150] Each field limiting ring corner section includes an outer corner edge of the field limiting ring and an inner corner edge of the field limiting ring.

[0151] The curvature radii of the outer corner edge of the field limiting ring and the inner corner edge of the field limiting ring are set independently.

[0152] The radius of curvature of the outer corner edge of the field limiting ring is greater than or equal to a first set value. The larger the radius of curvature of the outer corner edge of the field limiting ring, the more the electric field concentration at the edge of the field limiting ring 204 is alleviated and the smaller the electric field strength is. When the radius of curvature of the outer corner edge of the field limiting ring is the first set value, the electric field strength at the edge of the field limiting ring 204 reaches the maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer 202.

[0153] The radius of curvature of the inner corner edge of the field limiting ring is less than or equal to the second set value. The smaller the radius of curvature of the inner corner edge of the field limiting ring is, the larger the area surrounded by the inner edge of the field limiting ring 204 is, and the larger the area of ​​the active area 201a is. When the radius of curvature of the inner corner edge of the field limiting ring is the second set value, the area of ​​the active area 201a reaches the minimum required value.

[0154] In the method of the embodiment of the present invention, the number of the field-limiting ring straight line segments is four, and each two adjacent field-limiting ring straight line segments are perpendicular to each other. In other embodiments, the number of the field-limiting ring straight line segments can be set as required.

[0155] The method of the embodiment of the present invention further includes:

[0156] Step 3: Perform ion implantation of the second conductivity type to form a main junction region 203 in the active region 201 a . The main junction region 203 and the first epitaxial layer 202 form a PN main junction.

[0157] Step 3 includes the following sub-steps:

[0158] like Figure 4C As shown, a first photoresist pattern 402 is formed by a photolithography process to open the active area 201a, and then the field oxide layer 2051 in the open area is removed.

[0159] Afterwards, ion implantation is performed in the main junction region 203 using the first photoresist pattern 402 as a mask.

[0160] The outermost edge of the main junction region 203 is formed by connecting multiple main junction region line edges and multiple main junction region corner edges end to end; the number of main junction region line edges is the same as the number of field limiting ring straight line segments, each main junction region line edge and the field limiting ring straight line segment with the same serial number are parallel to each other, and each main junction region corner edge and the field limiting ring corner segment with the same serial number are aligned with each other.

[0161] The radius of curvature of the corner edge of each main junction region is greater than or equal to a third set value. The larger the radius of curvature of the corner edge of the main junction region, the more alleviated the electric field concentration at the corner edge of the main junction region and the smaller the electric field strength. When the radius of curvature of the corner edge of the main junction region is the third set value, the electric field strength at the corner edge of the main junction region reaches the maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer 202.

[0162] Later also includes:

[0163] Step 4: forming the cut-off ring 208, including the following steps:

[0164] like Figure 4D As shown, a photoresist pattern 403 is formed by a photolithography process to open a formation area of ​​the stop ring 208, and then the field oxide layer 2051 in the open area is removed.

[0165] Afterwards, ion implantation of the first conductivity type is performed using the photoresist pattern 403 as a mask to form a stop ring 208 .

[0166] The cut-off ring 208 is used to cut off the electric field at the device terminal to prevent the electric field from diffusing to the chip dicing path.

[0167] Afterwards, if Figure 4E As shown, the field limiting ring 204, the main junction region 203 and the stop ring 208 are annealed and driven at the same time.

[0168] Step 5: forming a dielectric layer field plate 207, including the following steps:

[0169] like Figure 4F As shown, a material layer 207 a of a dielectric layer field plate 207 is formed.

[0170] A photolithography process is performed to form a photoresist pattern 404 to cover the formation area of ​​the dielectric layer field plate 207 and to open the outside of the formation area of ​​the dielectric layer field plate 207 .

[0171] like Figure 4G As shown, the material layer 207 a of the dielectric layer field plate 207 is patterned and etched to form a plurality of dielectric layer field plates 207 .

[0172] The function of the dielectric layer field plate 207 is to expand the electric lines of force, ie, the electric field lines, of the P / N junction. In addition, it should be noted that the thickness of the field oxide layer 2051 at the bottom of the dielectric layer field plate 207 has certain requirements and must be able to withstand the voltage applied to the ring.

[0173] Step 6: Figure 4G As shown, an interlayer film 205 is formed.

[0174] In the method of the embodiment of the present invention, the field oxide layer 2051 is a part of the interlayer film 205. Figure 4G The field oxide layer 2051 is no longer shown separately.

[0175] Each dielectric layer field plate 207 is disposed in the interlayer film 205 at the top of each field limiting ring corner segment and each main junction region corner edge, and the material of the dielectric layer field plate 207 is different from that of the interlayer film 205 .

[0176] The dielectric layer field plate 207 at the top of each field limiting ring corner segment extends from the inner side of the outer edge of the terminal field plate corner segment 302 to the outer side.

[0177] The dielectric layer field plate 207 at the top of each main junction corner edge extends from the inside to the outside of the outer edge of the first electrode 206 a .

[0178] In some embodiments, the material of the interlayer film 205 includes an oxide layer; and the material of the dielectric layer field plate 207 includes polysilicon doped with the second conductivity type.

[0179] The interlayer film 205 can effectively prevent the influence of humidity and impurities in the external environment on the reverse leakage current of the high-voltage device by depositing an oxide dielectric layer, namely an oxide layer, and densifying the oxide layer. The interlayer film 205 can also lead to contact holes connected to the field plate.

[0180] The method of the embodiment of the present invention also includes the following steps:

[0181] like Figure 4H As shown, a contact hole is formed through the interlayer film 205 and the front metal layer, and the front metal layer is patterned to form a plurality of terminal field plates 206b and a first electrode 206a and an electrode 206c, and the electrode 206c will be connected to the second electrode at the bottom.

[0182] A terminal field plate 206 b is disposed on the top of each field limiting ring 204 , and each field limiting ring 204 and the terminal field plate 206 b on the top are connected through corresponding contact holes.

[0183] Please also refer to Figure 3A As shown, each terminal field plate 206b is a ring structure formed by connecting multiple terminal field plate straight segments 301 and multiple terminal field plate corner segments 302 end to end, and the number of terminal field plate straight segments 301 is the same as the number of field limiting ring straight segments.

[0184] The coverage area of ​​each terminal field plate straight segment 301 is guaranteed to completely cover the corresponding field limiting ring straight segment at the bottom and extend to the outside of the field limiting ring straight segment.

[0185] The coverage area of ​​each terminal field plate corner segment 302 ensures that the corresponding field limiting ring corner segment at the bottom is completely covered and extends to the outside of the field limiting ring corner segment.

[0186] The first electrode 206 a is connected to the main junction region 203 .

[0187] The first electrode 206 a also extends into the termination region 201 b outside the main junction region 203 and forms a second field plate.

[0188] The front side process is completed. In some embodiments, the front side process further includes:

[0189] Silicon nitride and polyimide passivation layers are deposited, and the passivation layer is etched by photolithography to complete the top structure.

[0190] After the front process is completed, the following back process is also included:

[0191] The semiconductor substrate 201 is thinned and a second electrode region heavily doped with the first conductivity type is formed on the back of the first epitaxial layer 202. The second electrode region is directly composed of the thinned semiconductor substrate 201 heavily doped with the first conductivity type; or, the second electrode region is formed by back-implantation of the thinned semiconductor substrate 201 heavily doped with the first conductivity type. Taking the first conductivity type as N-type as an example, the following steps are included: the back of the semiconductor substrate 201 is thinned to a specific thickness, N-type impurities are injected into the back, and a field stop layer, i.e., the second electrode region, is formed by low-temperature annealing or laser annealing, while ensuring that the surface impurity concentration is high enough to form an ohmic contact; when a substrate with a deep back diffusion layer is selected, back impurity injection and annealing processes may not be performed.

[0192] A back metal layer is formed on the back of the second electrode region, and the back metal layer forms the second electrode. In some embodiments, the back metal layer is deposited by sputtering or evaporation, and then subjected to a minority carrier lifetime control process to improve the reverse recovery characteristics of the diode.

[0193] The device formed by the method of the embodiment of the present invention can improve the P / N junction morphology at the turning point of the field limiting ring, expand the injection area through a new design, and increase the edge curvature of the P / N junction by designing a new field plate, thereby improving the reverse withstand voltage capability of the field limiting ring. The embodiment of the present invention can adjust the distribution of the electric field, realize a more uniform longitudinal electric field in the drift region, improve the reverse withstand voltage characteristics of the fast recovery diode, and optimize the reverse leakage current, thereby improving the reliability of the device.

[0194] The device formed by the method of the embodiment of the present invention can expand the outer corner radius on the basis of the existing traditional planar ring terminal corner, increase the corner area of ​​the outer corner and increase the radius of the outer corner, thereby effectively alleviating the concentrated distribution of the electric field at the edge of the field limiting ring, improving the reverse breakdown characteristics of the device, and improving the overall withstand voltage of the device; at the same time, the curvature radius of the inner side of the corner is reduced, which can expand the area of ​​the inner side, increase the area of ​​the active area, and improve the performance of the device.

[0195] The method of the embodiment of the present invention can also fill a dielectric layer such as P-doped polysilicon at the corner. The filling position is within the outer oxide layer of the corner of the terminal area. The dielectric layer can also alleviate the electric field concentration in the terminal area at the corner of the device, thereby improving the overall withstand voltage, and the inner corner can reduce the radius.

[0196] The method of the embodiment of the present invention improves the reverse withstand voltage characteristics of the fast recovery diode by improving the morphology and structure under the existing process capability conditions, thereby increasing the application scenarios of the device and enhancing the reliability of the device. By enlarging the curvature radius of the field limiting ring, the spherical junction part of the body terminal is more fully transformed into a parallel junction, improving the reverse bias performance (increasing the reverse breakdown voltage and reducing the reverse leakage current, etc.), and increasing the active area and current density.

[0197] The manufacturing process flow of the method of the embodiment of the present invention is fully compatible with the existing general power device FRD process, and the solution is relatively easy to implement.

[0198] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A terminal structure of a semiconductor power device, characterized in that: The terminal structure is formed in the terminal region, and the terminal region surrounds the peripheral side of the active region; The terminal structure comprises: A plurality of second conductivity type doped field limiting rings, each of the field limiting rings being formed in a selected region of the first epitaxial layer lightly doped with the first conductivity type; Each of the field limiting rings is an annular structure formed by connecting a plurality of field limiting ring straight segments and a plurality of field limiting ring corner segments end to end, each adjacent field limiting ring straight segment is connected by a field limiting ring corner segment, and the number of the field limiting ring straight segments is the same as the number of the field limiting ring corner segments; the field limiting ring straight segments with the same serial number between different field limiting rings are parallel to each other, and the field limiting ring corner segments with the same serial number between different field limiting rings are aligned with each other; Each of the field limiting ring corner sections comprises an outer corner edge of the field limiting ring and an inner corner edge of the field limiting ring; The curvature radii of the outer corner edge of the field limiting ring and the inner corner edge of the field limiting ring are independently set; The radius of curvature of the outer corner edge of the field limiting ring is greater than or equal to a first set value. The larger the radius of curvature of the outer corner edge of the field limiting ring, the more the electric field concentration at the edge of the field limiting ring is relieved and the smaller the electric field strength is. When the radius of curvature of the outer corner edge of the field limiting ring is the first set value, the electric field strength at the edge of the field limiting ring reaches the maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer; The radius of curvature of the inner corner edge of the field limiting ring is less than or equal to a second set value. The smaller the radius of curvature of the inner corner edge of the field limiting ring is, the larger the area surrounded by the inner edge of the field limiting ring is, and the larger the area of ​​the active region is. When the radius of curvature of the inner corner edge of the field limiting ring is the second set value, the area of ​​the active region reaches the minimum required value.

2. The terminal structure of a semiconductor power device according to claim 1, characterized in that: A main junction region doped with a second conductive type is formed in the active region, and the main junction region and the first epitaxial layer form a PN main junction; The outermost edge of the main junction region is formed by connecting a plurality of main junction region straight edges and a plurality of main junction region corner edges end to end; the number of the main junction region straight edges is the same as the number of the field limiting ring straight segments, each of the main junction region straight edges and the field limiting ring straight segments with the same serial number are parallel to each other, and each of the main junction region corner edges and the field limiting ring corner segments with the same serial number are aligned with each other; The radius of curvature of each main junction region corner edge is greater than or equal to a third set value. The larger the radius of curvature of the main junction region corner edge, the more alleviated the electric field concentration at the main junction region corner edge and the smaller the electric field strength. When the radius of curvature of the main junction region corner edge is the third set value, the electric field strength at the main junction region corner edge reaches the maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer.

3. The terminal structure of the semiconductor power device according to claim 2, characterized in that: Also included are a plurality of terminal field plates comprised of a front metal layer; A terminal field plate composed of a front metal layer is disposed on the top of each field limiting ring, and each field limiting ring and the terminal field plate on the top are connected via a contact hole passing through the interlayer film; Each of the terminal field plates is a ring structure formed by connecting a plurality of terminal field plate straight segments and a plurality of terminal field plate corner segments end to end, and the number of the terminal field plate straight segments is the same as the number of the field limiting ring straight segments; The coverage area of ​​each of the terminal field plate straight segments ensures that the corresponding field limiting ring straight segments at the bottom are completely covered and extend to the outside of the field limiting ring straight segments; The coverage area of ​​each terminal field plate corner segment ensures that the corresponding field limiting ring corner segment at the bottom is completely covered and extends to the outside of the field limiting ring corner segment.

4. The terminal structure of the semiconductor power device according to claim 3, characterized in that: A first electrode formed by a front metal layer is formed on the top of the active area, and the first electrode is connected to the main junction area; The first electrode also extends into the termination region outside the main junction region and forms a second field plate.

5. The terminal structure of the semiconductor power device according to claim 4, characterized in that: Also includes: multiple dielectric layer field plates; Each of the dielectric layer field plates is arranged in the interlayer film at the corner section of each of the field limiting rings and the top of the corner edge of each of the main junction regions, and the material of the dielectric layer field plate is different from that of the interlayer film; The dielectric layer field plate at the top of each field limiting ring corner segment extends from the inner side of the outer edge of the terminal field plate corner segment to the outer side; The dielectric layer field plate at the top of each corner edge of the main junction region extends from the inner side of the outer edge of the first electrode to the outer side.

6. The terminal structure of the semiconductor power device according to claim 5, characterized in that: The material of the interlayer film includes an oxide layer; the material of the dielectric layer field plate includes polysilicon doped with a second conductivity type.

7. The terminal structure of a semiconductor power device according to claim 2, characterized in that: A second electrode region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer, and a second electrode composed of a back metal layer is formed on the back side of the second electrode region.

8. The terminal structure of the semiconductor power device according to claim 7, characterized in that: Semiconductor power devices include fast recovery diodes.

9. The terminal structure of a semiconductor power device according to any one of claims 1 to 8, characterized in that: The number of the field-limiting ring straight line segments is four, and each two adjacent field-limiting ring straight line segments are perpendicular to each other.

10. A method for manufacturing a terminal structure of a semiconductor power device, characterized in that: The steps include: Epitaxially growing a first epitaxial layer lightly doped with a first conductivity type on a semiconductor substrate; Performing ion implantation of a second conductivity type to form a plurality of field limiting rings in a selected area of ​​a terminal region, wherein the terminal region surrounds a peripheral side of the active region; Each of the field limiting rings is an annular structure formed by connecting a plurality of field limiting ring straight segments and a plurality of field limiting ring corner segments end to end, each adjacent field limiting ring straight segment is connected by a field limiting ring corner segment, and the number of the field limiting ring straight segments is the same as the number of the field limiting ring corner segments; the field limiting ring straight segments with the same serial number between different field limiting rings are parallel to each other, and the field limiting ring corner segments with the same serial number between different field limiting rings are aligned with each other; Each of the field limiting ring corner sections comprises an outer field limiting ring corner edge and an inner field limiting ring corner edge; The curvature radii of the outer corner edge of the field limiting ring and the inner corner edge of the field limiting ring are independently set; The radius of curvature of the outer corner edge of the field limiting ring is greater than or equal to a first set value. The larger the radius of curvature of the outer corner edge of the field limiting ring, the more the electric field concentration at the edge of the field limiting ring is relieved and the smaller the electric field strength is. When the radius of curvature of the outer corner edge of the field limiting ring is the first set value, the electric field strength at the edge of the field limiting ring reaches the maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer; The radius of curvature of the inner corner edge of the field limiting ring is less than or equal to a second set value. The smaller the radius of curvature of the inner corner edge of the field limiting ring is, the larger the area surrounded by the inner edge of the field limiting ring is, and the larger the area of ​​the active region is. When the radius of curvature of the inner corner edge of the field limiting ring is the second set value, the area of ​​the active region reaches the minimum required value.

11. The method for manufacturing a terminal structure of a semiconductor power device according to claim 10, characterized in that: Also includes: Performing ion implantation of a second conductivity type to form a main junction region in the active region, wherein the main junction region and the first epitaxial layer form a PN main junction; The outermost edge of the main junction region is formed by connecting a plurality of main junction region straight edges and a plurality of main junction region corner edges end to end; the number of the main junction region straight edges is the same as the number of the field limiting ring straight segments, each of the main junction region straight edges and the field limiting ring straight segments with the same serial number are parallel to each other, and each of the main junction region corner edges and the field limiting ring corner segments with the same serial number are aligned with each other; The radius of curvature of each main junction region corner edge is greater than or equal to a third set value. The larger the radius of curvature of the main junction region corner edge, the more alleviated the electric field concentration at the main junction region corner edge and the smaller the electric field strength. When the radius of curvature of the main junction region corner edge is the third set value, the electric field strength at the main junction region corner edge reaches the maximum required value of the electric field strength, and the maximum required value of the electric field strength is less than the breakdown electric field strength of the material of the first epitaxial layer.

12. The method for manufacturing a terminal structure of a semiconductor power device according to claim 11, characterized in that: Also includes: forming an interlayer film, a contact hole passing through the interlayer film, and a front metal layer, and patterning the front metal layer to form a plurality of terminal field plates and a first electrode; A terminal field plate is disposed on the top of each field limiting ring, and each field limiting ring and the terminal field plate on the top are connected through corresponding contact holes; Each of the terminal field plates is a ring structure formed by connecting a plurality of terminal field plate straight segments and a plurality of terminal field plate corner segments end to end, and the number of the terminal field plate straight segments is the same as the number of the field limiting ring straight segments; The coverage area of ​​each of the terminal field plate straight segments ensures that the corresponding field limiting ring straight segments at the bottom are completely covered and extend to the outside of the field limiting ring straight segments; The coverage area of ​​each terminal field plate corner segment ensures that the corresponding field limiting ring corner segment at the bottom is fully covered and extends to the outside of the field limiting ring corner segment; The first electrode is connected to the main junction region; The first electrode also extends into the termination region outside the main junction region and forms a second field plate.

13. The method for manufacturing a terminal structure of a semiconductor power device according to claim 12, characterized in that: Before performing the ion implantation of the field limiting ring, the method further comprises: forming a field oxide layer on a surface of the first epitaxial layer; Performing a photolithography process to open the formation area of ​​the field limiting ring, and then removing the field oxide layer in the opened area; Afterwards, ion implantation of the field limiting ring is performed using the field oxide layer as a mask; After the ion implantation of the field limiting ring is completed, the method further comprises: Forming a first photoresist pattern by a photolithography process to open the active area, and then removing the field oxide layer in the open area; Afterwards, ion implantation is performed in the main junction region using the first photoresist pattern as a mask; Afterwards, the field limiting ring and the main junction region are simultaneously annealed.

14. The method for manufacturing a terminal structure of a semiconductor power device according to claim 13, characterized in that: After the field limiting ring and the main junction region are formed, the following further comprises: A material layer forming a dielectric layer field plate; Performing patterned etching on the material layer of the dielectric layer field plate to form a plurality of dielectric layer field plates; Each of the dielectric layer field plates is arranged in the interlayer film at the corner section of each of the field limiting rings and the top of the corner edge of each of the main junction regions, and the material of the dielectric layer field plate is different from that of the interlayer film; The dielectric layer field plate at the top of each field limiting ring corner segment extends from the inner side of the outer edge of the terminal field plate corner segment to the outer side; The dielectric layer field plate at the top of each corner edge of the main junction region extends from the inner side of the outer edge of the first electrode to the outer side; The interlayer film is formed after the dielectric layer field plate is formed, and in the terminal region, the field oxide layer serves as a part of the interlayer film.

15. The method for manufacturing a terminal structure of a semiconductor power device according to claim 14, characterized in that: The material of the interlayer film includes an oxide layer; the material of the dielectric layer field plate includes polysilicon doped with a second conductivity type.

16. The method for manufacturing a terminal structure of a semiconductor power device according to claim 12, characterized in that: After the front process is completed, the following back process is also included: The semiconductor substrate is thinned and a second electrode region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer, wherein the second electrode region is directly composed of the thinned semiconductor substrate heavily doped with the first conductivity type or the second electrode region is formed by back-implanting the thinned semiconductor substrate heavily doped with the first conductivity type; A back metal layer is formed on the back side of the second electrode region, and the back metal layer constitutes a second electrode.

17. The method for manufacturing a terminal structure of a semiconductor power device according to any one of claims 10 to 16, characterized in that: The number of the field-limiting ring straight line segments is four, and each two adjacent field-limiting ring straight line segments are perpendicular to each other.

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