Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes multiple pixel circuits, each pixel circuit including multiple transistors. The display panel also includes a substrate, a first organic layer, and a first metal layer. The first organic layer is disposed on one side of the substrate, and the first metal layer is disposed on the side of the first organic layer facing away from the substrate. The first metal layer includes a first conductor portion, which overlaps with the orthographic projection of at least one transistor in the pixel circuit onto the substrate. The first conductor portion includes a first opening, and the orthographic projection of the first opening onto the substrate at least partially overlaps with the orthographic projection of the first organic layer onto the substrate. In this embodiment, by adding a first opening within the first conductor portion, moisture and other substances remaining in the first organic layer can be released through the first opening, thereby mitigating the risk of film bulging and first conductor portion detachment caused by trapped moisture, and improving the manufacturing yield and reliability of the display panel.

Description

Technical Field

[0001] This application relates to the field of display device technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of science and technology, the display panel industry has also made great progress and achieved diversified development. On this basis, people's requirements for display panels are increasing day by day. How to improve the reliability of display panels while meeting performance needs has become one of the research directions of manufacturers. Summary of the Invention

[0003] This application provides a display panel and a display device that can improve the reliability of the display panel.

[0004] In a first aspect, embodiments of this application provide a display panel including a plurality of pixel circuits, each pixel circuit including a plurality of transistors. The display panel further includes a substrate, a first organic layer, and a first metal layer. The first organic layer is disposed on one side of the substrate, and the first metal layer is disposed on the side of the first organic layer facing away from the substrate. The first metal layer includes a first conductive portion, which overlaps with the orthographic projection of at least one transistor in the pixel circuit onto the substrate. The first conductive portion includes a first opening, and the orthographic projection of the first opening onto the substrate at least partially overlaps with the orthographic projection of the first organic layer onto the substrate.

[0005] Secondly, embodiments of this application provide a display device, which includes the display panel in any of the foregoing embodiments.

[0006] This application provides a display panel and a display device. The first conductor portion, besides transmitting specific signals to meet the operational needs of the display panel, also serves to cover and shield the transistors, reducing the possibility of light emitted by the display panel or ambient light illuminating the transistors due to refraction or reflection. This reduces the adverse effects of light on the transistors and improves the operational reliability of the pixel circuitry. Furthermore, by adding a first opening within the first conductor portion, moisture and other substances remaining in the first organic layer can be released through the opening. This mitigates the risk of film bulging and first conductor portion detachment caused by trapped moisture, thereby improving the manufacturing yield and operational reliability of the display panel. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application;

[0009] Figure 2 This is a schematic cross-sectional view of a display panel in another region, as provided in an embodiment of this application.

[0010] Figure 3 This is a simplified layout diagram of a pixel circuit provided in an embodiment of this application;

[0011] Figure 4a and Figure 4b This is a simplified circuit diagram of two pixel circuits in a display panel provided in an embodiment of this application;

[0012] Figure 5 This is a cross-sectional structural diagram of another display panel provided in an embodiment of this application;

[0013] Figure 6a and Figure 6b This is a schematic diagram of the structure of the first metal layer in a display panel according to another embodiment of this application;

[0014] Figure 7 This is a simplified schematic diagram of the circuit layout in another display panel provided in the embodiments of this application;

[0015] Figure 8 This is a cross-sectional structural diagram of another display panel provided in an embodiment of this application;

[0016] Figure 9 This is a cross-sectional structural diagram of another display panel provided in an embodiment of this application;

[0017] Figure 10 This is a schematic diagram of a partial pixel arrangement structure of a display panel provided in an embodiment of this application;

[0018] Figure 11 This is a cross-sectional structural diagram of another display panel provided in an embodiment of this application;

[0019] Figure 12 This is a cross-sectional structural diagram of another display panel provided in an embodiment of this application;

[0020] Figure 13 This is a cross-sectional structural diagram of another display panel provided in an embodiment of this application;

[0021] Figure 14 This is a schematic diagram of the structure of the second metal layer in a display panel provided in an embodiment of this application;

[0022] Figure 15 This is a schematic diagram illustrating the positional relationship between the first metal layer and the second metal layer in a display panel, as provided in another embodiment of this application.

[0023] Figure 16 This application provides a schematic diagram illustrating the positional relationship between a first metal layer and a first organic layer in a display panel.

[0024] Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0025] Marker explanation:

[0026] 100. Display panel; 200. Display device;

[0027] 10. Substrate;

[0028] 20. First organic layer; 21. Vent hole;

[0029] 30. First metal layer; 31. First conductor portion; 311. First sub-part; 312. Second sub-part; 313. Connecting portion; 32. First opening; 321. First type of opening; 322. Second type of opening; 33. Conducting portion;

[0030] 41. First insulating layer; 42. Second insulating layer; 421. Second opening;

[0031] 50. Second metal layer; 51. Second conductor portion; 52. Third type opening; 53. Fourth type opening; 54. First pad; 55. Second pad;

[0032] 61. First active layer; 611. First active structure; 612. First exposed portion; 62. Second active layer; 621. Second active structure; 622. Second exposed portion;

[0033] P, pixel circuit; P1, pulse width modulation circuit; P2, pulse amplitude modulation circuit; M, transistor; C, repetition circuit group; J, interval region; V, shift register unit; F, light-emitting element;

[0034] X, first direction; Y, second direction; Z, thickness direction. Detailed Implementation

[0035] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0036] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0037] Firstly, please refer to Figures 1 to 3 This application provides a display panel 100, which includes a plurality of pixel circuits P, each pixel circuit P including a plurality of transistors M. The display panel 100 also includes a substrate 10, a first organic layer 20, and a first metal layer 30. The first organic layer 20 is disposed on one side of the substrate 10, and the first metal layer 30 is disposed on the side of the first organic layer 20 opposite to the substrate 10. The first metal layer 30 includes a first conductor portion 31, which overlaps with the orthographic projection of at least one transistor M in the pixel circuit P onto the substrate 10. The first conductor portion 31 includes a first opening 32, and the orthographic projection of the first opening 32 onto the substrate 10 at least partially overlaps with the orthographic projection of the first organic layer 20 onto the substrate 10.

[0038] The display panel 100 is a device for displaying images. The display panel 100 may include light-emitting elements, which are the main components for achieving the light-emitting function. The light-emitting elements can be micro-light-emitting diodes (Micro LEDs) or miniature light-emitting diodes (Mini LEDs), etc. The light-emitting elements can have various structural forms; for example, they can be flip-chips, upright chips, or vertical chips. This application does not limit these possibilities.

[0039] A pixel circuit P is a circuit structure used to drive and control whether a light-emitting element emits light. There are multiple pixel circuits P, each controlling a different light-emitting element to achieve the light-emitting function. Figure 3The diagram illustrates multiple adjacent pixel circuits P forming a repeating circuit group C, with the repeating circuit groups C arranged in an array along multiple directions. The pixel circuit P may include multiple device structures, such as storage capacitors and transistors M. The specific form of the pixel circuit P is not limited in this embodiment. Optionally, please refer to... Figure 4a and Figure 4b , Figure 4a and Figure 4b Two different forms of pixel circuit P are provided for embodiments of this application, wherein, in Figure 4a and Figure 4b In the pixel circuit P, each includes a pulse width modulation circuit P1 and a pulse amplitude modulation circuit P2, and each of the pulse width modulation circuit P1 and the pulse amplitude modulation circuit P2 includes multiple transistors M.

[0040] The substrate 10 is a film layer within the display panel 100 that serves as a support and load-bearing layer. Other film layer structures and device structures are sequentially stacked on the substrate 10. Here, "stacked" refers to the other film layer structures and device structures being sequentially arranged along the thickness direction Z of the substrate 10. The thickness direction Z of the substrate 10 is generally consistent with the thickness direction Z of other film layers. For ease of description, the following embodiments of this application will use the same direction to illustrate the thickness direction Z of the substrate 10 and the thickness direction Z of other film layers.

[0041] The first metal layer 30 is a film layer disposed on one side of the substrate 10 and including a metal conductor material. The first metal layer 30 includes a first conductor portion 31. The first conductor portion 31 can have various shapes and sizes. For example, the orthogonal projection of the first conductor portion 31 onto the substrate 10 can be a full-surface structure, or the first conductor portion 31 can also include multiple sub-structures. The orthogonal projection of a single sub-structure onto the substrate 10 can also be a strip or block structure.

[0042] The first conductor portion 31 can be a conductor structure within the display panel 100 used to transmit a specific signal. The specific type of signal transmitted by the first conductor portion 31 is not limited in this embodiment. Furthermore, the conductor structures of the first conductor portion 31 in different areas can be used to transmit the same potential voltage, or they can be used to transmit different potential voltages.

[0043] The first conductor portion 31 and the orthographic projection of at least one transistor M in the pixel circuit P onto the substrate 10 at least partially overlap. The term "at least partially overlap" here means that there is an overlapping area between the first conductor portion 31 and the orthographic projection of at least one transistor M onto the substrate 10. The orthographic projection of the first conductor portion 31 onto the substrate 10 may overlap with only one transistor M, or the orthographic projection of the first conductor portion 31 onto the substrate 10 may overlap with multiple transistors M simultaneously.

[0044] A transistor M is typically composed of different structures located in different film layers. For example, transistor M may include an active structure located within an active layer, a control terminal located within one of the conductor layers, and a first and second electrode located within other conductor layers. The control terminal controls whether the first and second electrodes are conducting. In this design, the first conductor portion 31, in addition to transmitting specific signals to meet the operational needs of the display panel 100, can also cover and shield the transistor M, reducing the possibility of light emitted by the display panel 100 or ambient light illuminating the transistor M due to refraction or reflection. This reduces the adverse effects of light on the transistor M and improves the operational reliability of the pixel circuit P.

[0045] In some alternative embodiments, the dimensions of the first conductor portion 31 in both the first direction X and the second direction are not less than 40 μm, and the first direction X, the second direction, and the thickness direction Z intersect each other. In this way, the first conductor portion 31 has a bulk metal structure, which helps to improve the coverage and shielding effect of the first conductor portion 31 on the transistor M, and further reduces the adverse effects of light on the transistor M.

[0046] The first organic layer 20 is a film layer comprising organic material disposed on one side of the substrate 10. The first organic layer 20 is disposed between the substrate 10 and the first metal layer 30. The first organic layer 20 can be bonded to the first metal layer 30, or the first organic layer 20 can be spaced apart from the first metal layer 30 in the thickness direction Z. In addition to insulating and separating the first metal layer 30 from other conductive film layers on the side of the first organic layer 20 facing the substrate 10, the first organic layer 20 can also reduce the parasitic capacitance formed between the first metal layer 30 and other conductive film layers on the side of the first organic layer 20 facing the substrate 10, thereby improving the performance and stability of the internal circuit structure of the display panel 100.

[0047] It should be noted that, in addition to the film layer structure mentioned above, the display panel 100 may also contain other film layer structures, such as... Figure 1 As shown, the side of the first organic layer 20 facing the substrate 10 may further include a first conductive functional layer B1 and a second conductive functional layer B2. Both the first conductive functional layer B1 and the second conductive functional layer B2 include conductive materials. The first conductive functional layer B1 may contain signal traces such as data lines and power signal lines, while the second conductive functional layer B2 may contain signal traces such as scan lines and light emission control lines. Alternatively, the first and second terminals of the transistor M may be located within the first conductive functional layer B1, while the control terminal may be located within the second conductive functional layer B2.

[0048] During the fabrication of the display panel 100, multiple film-forming processes are required. During the fabrication of the first organic layer 20, moisture is trapped between the first organic layer 20 and other film layers on its side facing away from the substrate 10, awaiting gas release. Furthermore, at the overlap between the first conductor portion 31 and the first organic layer 20, the first conductor portion 31 hinders the gas release process, increasing the difficulty of gas release. This is especially true for the first conductor portion 31 with a large projected area; for example, when the dimensions of the first conductor portion 31 in both the first direction X and the second direction are not less than 40 μm, the difficulty of gas release is further increased. In this case, the display panel 100 is prone to bulging in localized areas, and there is a risk of the first conductor portion 31 detaching, affecting the fabrication yield and reliability of the display panel 100.

[0049] In view of this, the structure of the first conductor portion 31 has been adjusted in this embodiment. A first opening 32 is added to the first conductor portion 31. The first opening 32 extends through the first conductor portion 31 along the thickness direction Z, and the orthographic projection of the first opening 32 onto the substrate 10 at least partially overlaps with the orthographic projection of the first organic layer 20 onto the substrate 10. In this way, at least a portion of the structure in the first organic layer 20 can be exposed relative to the first conductor portion 31 by means of the first opening 32. Thus, during the manufacturing process corresponding to the first conductor portion 31, moisture and other substances remaining in the first organic layer 20 can be released through the first opening 32, thereby reducing the risk of film bulging and first conductor portion 31 detachment caused by trapped moisture, and improving the manufacturing yield and reliability of the display panel 100.

[0050] It should be noted that the size, shape, and number of the first opening 32 are not limited in this embodiment. There may be only one first opening 32, or there may be multiple first openings 32. When there are multiple first openings 32, the shape and size of the different first openings 32 may be the same or different. For example, the orthographic projection of the first opening 32 onto the substrate 10 may be a regular shape such as a circle, triangle, or square, or it may be an irregular shape. This embodiment does not limit this.

[0051] The present application does not limit the positional relationship between the first opening 32 and the transistor M. The orthographic projection of the first opening 32 onto the substrate 10 can overlap with the orthographic projection of the transistor M onto the substrate 10, or as follows: Figure 2As shown, the projection of the first opening 32 on the substrate 10 may not overlap with the projection of the transistor M on the substrate 10. Furthermore, when there are multiple first openings 32, the projections of each first opening 32 on the substrate 10 may overlap with the projection of the transistor M on the substrate 10, or the projections of each first opening 32 on the substrate 10 may not overlap with the projection of the transistor M on the substrate 10, or some of the projections of the first openings 32 on the substrate 10 may overlap with the projection of the transistor M on the substrate 10, while the projections of other first openings 32 on the substrate 10 may not overlap with the projection of the transistor M on the substrate 10.

[0052] Furthermore, the conductor structures of the first conductor portion 31 on different sides of the first opening 32 can be used to transmit the same potential voltage, or they can be used to transmit different potential voltages; that is, the conductor structures of the first conductor portion 31 on different sides of the first opening 32 can be used to transmit different signals. Further, the conductor structures of the first conductor portion 31 on different sides of the first opening 32 can be connected as a single unit, or they can be disconnected from each other.

[0053] In summary, in this embodiment, the first conductor portion 31, besides transmitting specific signals to meet the operational needs of the display panel 100, also serves to cover and shield the transistor M, reducing the possibility of light emitted by the display panel 100 or ambient light illuminating the transistor M due to refraction or reflection, thus reducing the adverse effects of light on the transistor M and improving the operational reliability of the pixel circuit P. Furthermore, by adding a first opening 32 within the first conductor portion 31, moisture and other substances remaining in the first organic layer 20 can be released through the first opening 32, thereby mitigating the risk of film bulging and detachment of the first conductor portion 31 caused by trapped moisture, and improving the manufacturing yield and operational reliability of the display panel 100.

[0054] In some embodiments, please refer to Figure 5 At least a portion of the orthographic projection of the first opening 32 onto the substrate 10 overlaps at least partially with the orthographic projection of the transistor M in the pixel circuit P onto the substrate 10; and / or, as Figure 2 As shown, at least a portion of the first opening 32 is projected onto the substrate 10 outside the projection of each transistor M in the pixel circuit P onto the substrate 10.

[0055] For the first opening 32, there can be multiple positional relationships between a single first opening 32 and the transistor M. Furthermore, when there are multiple first openings 32, the positional relationships between different first openings 32 and the transistor M can be the same or different. Based on this, depending on actual needs, it is possible to choose a configuration where the orthogonal projections of some or all of the first openings 32 on the substrate 10 overlap with the orthogonal projections of the transistor M in the pixel circuit P on the substrate 10, or alternatively, it is possible to choose a configuration where the orthogonal projections of some or all of the first openings 32 on the substrate 10 do not overlap with the orthogonal projections of the transistor M in the pixel circuit P on the substrate 10.

[0056] It should be noted that when the orthographic projection of a single first opening 32 on the substrate 10 is located outside the orthographic projection of each transistor M in the pixel circuit P on the substrate 10, the orthographic projection of the first opening 32 on the substrate 10 can be located between the orthographic projections of adjacent pixel circuits P on the substrate 10, or the orthographic projection of the first opening 32 on the substrate 10 can also be located on the outer periphery of the orthographic projections of all pixel circuits P on the substrate 10, or the orthographic projection of the first opening 32 on the substrate 10 can also be located within the orthographic projection range of a single pixel circuit P on the substrate 10, and is offset from the orthographic projections of each transistor M on the substrate 10. This application embodiment does not impose any restrictions on this.

[0057] In the embodiments of this application, the first opening 32 and the transistor M can have various positional relationships, and the positional relationships between different first openings 32 and the transistor M can be the same or different. Based on this, by changing the number and relative position of the first openings 32, it is possible to reduce the adverse effects of light on the transistor M while improving the moisture release effect, reducing the risk of film bulging and first conductor portion 31 detachment, thus exhibiting strong flexibility and practicality.

[0058] In some embodiments, please refer to Figure 1 , Figure 2 , Figure 5 as well as Figure 6a The plurality of first openings 32 include a first type of opening 321 and a second type of opening 322, wherein the size of the first type of opening 321 is larger than the size of the second type of opening 322.

[0059] There are multiple first openings 32, which are spaced apart from each other, meaning that adjacent first openings 32 are spaced a certain distance apart and distributed in different areas of the display panel 100, thereby meeting the exhaust needs of the display panel 100 at different locations. The multiple first openings 32 include first-type openings 321 and second-type openings 322. The size of the first-type opening 321 is larger than the size of the second-type opening 322. Here, "size" refers to the projected area on the substrate 10; that is, the projected area of ​​the first-type opening 321 on the substrate 10 is larger than the projected area of ​​the second-type opening 322 on the substrate 10.

[0060] Further, the first type of opening 321 refers to an opening with a corresponding orthographic projection area greater than a first preset value, and the second type of opening 322 refers to an opening with a corresponding orthographic projection area less than the first preset value. The specific size of the first preset value is not limited in this embodiment. Optionally, the first preset value is 40 μm. 2 The number of first-type openings 321 can be multiple, and the shape and size of different first-type openings 321 on the substrate 10 can be the same or different. Similarly, the number of second-type openings 322 can be multiple, and the shape and size of different second-type openings 322 on the substrate 10 can be the same or different.

[0061] Optionally, the number of first-class openings 321 is less than the number of second-class openings 322.

[0062] The positional relationship between the first type of opening 321 and the second type of opening 322 relative to the pixel circuit P is not limited in the embodiments of this application. The orthographic projection of the first type of opening 321 on the substrate 10 may overlap with the orthographic projection of the pixel circuit P on the substrate 10, or they may not overlap. The positional relationship between the second type of opening 322 and the pixel circuit P is similar, and will not be described again in the embodiments of this application.

[0063] In this embodiment, to accommodate the varying needs of different areas of the display panel 100, multiple first openings 32 are configured to include first-type openings 321 and second-type openings 322 of different sizes that are spaced apart from each other. This allows the first-type openings 321 to further enhance gas release at specific locations, improving manufacturing yield. The presence of the second-type openings 322, while meeting gas release requirements, also provides a covering and shielding effect on the underlying film structure through the conductive structure surrounding the second-type openings 322, thus contributing to improved performance of the display panel 100.

[0064] In some embodiments, such as Figure 1 , Figure 2 , Figure 5 as well as Figure 6aAs shown, on the plane perpendicular to the display panel 100, the first type of opening 321 and the pixel circuit P do not overlap; on the plane perpendicular to the display panel 100, at least a portion of the second type of opening 322 overlaps with the pixel circuit P. Wherein, in Figure 6a The middle pixel circuit P is shown in the form of a dashed box.

[0065] The direction perpendicular to the plane of the display panel 100 is the thickness direction Z. Based on this, the first type of opening 321 and the pixel circuit P do not overlap, meaning the orthographic projection of the first type of opening 321 onto the substrate 10 is outside the orthographic projection of the pixel circuit P onto the substrate 10. At least some of the second type of openings 322 overlap with the pixel circuit P, meaning there is an overlap area between the orthographic projections of at least some of the second type of openings 322 onto the substrate 10 and the orthographic projection of the pixel circuit P onto the substrate 10. When there are multiple second type of openings 322, all of them may overlap with the pixel circuit P, or some may overlap with the pixel circuit P while others may not overlap.

[0066] In this embodiment, the first type of opening 321 is a relatively large opening structure. By ensuring that the first type of opening 321 and the pixel circuit P do not overlap, venting can be achieved outside the area where the pixel circuit P is located, improving the gas release effect and reducing the risk of performance degradation caused by a large area of ​​the pixel circuit P being exposed to the first type of opening 321. As for the second type of opening 322, by ensuring that at least a portion of the second type of opening 322 overlaps with the pixel circuit P, the venting needs of the area where the pixel circuit P is located can be met by means of the second type of opening 322. Furthermore, since the second type of opening 322 is a relatively small opening structure, the exposed area of ​​the pixel circuit P at the second type of opening 322 is small. This reduces the degree of performance degradation of the pixel circuit P due to light irradiation and laser bonding, and helps to improve the manufacturing yield and performance of the display panel 100.

[0067] In some embodiments, the orthographic projection of the first type of opening 321 onto the substrate 10 lies between the orthographic projections of adjacent pixel circuits P onto the substrate 10. Figure 6a In the process, multiple pixel circuits P include a first circuit D1 and a second circuit D2, and a portion of the first type of opening 321 is located between the first circuit D1 and the second circuit D2.

[0068] In this embodiment, considering that at least some adjacent pixel circuits P can have a large spacing, the first type of opening 321 is correspondingly disposed between adjacent pixel openings. This design has two advantages: firstly, it can improve the gas release capability of the first conductor portion 31 by using the first type of opening 321, reducing the risk of the first conductor portion 31 detaching; secondly, it can also meet the need for the first type of opening 321 to avoid the pixel circuit P, reducing the risk of performance degradation caused by a large area of ​​the pixel circuit P being exposed to the first type of opening 321.

[0069] It should be noted that there may be only one first-type opening 321 between two adjacent pixel circuits P, or there may be multiple first-type openings 321. This application embodiment does not limit this. Optionally, multiple first-type openings 321 may be provided between two adjacent pixel circuits P in the first direction X, and the multiple first-type openings 321 are arranged side by side and spaced apart along the second direction Y, with the first direction X, the second direction Y and the thickness direction Z intersecting each other.

[0070] In some embodiments, such as Figure 1 , Figure 2 , Figure 5 as well as Figure 6a As shown, multiple pixel circuits P arranged adjacently together form a repeating circuit group C, and multiple repeating circuit groups C are arranged repeatedly; wherein, adjacent repeating circuit groups C are spaced apart to form a gap area J, and the first type of opening 321 is located in the gap area J.

[0071] The display panel 100 contains multiple repeating circuit groups C, and the structural layout of the pixel circuits P in each repeating circuit group C and the arrangement of different pixel circuits P are consistent. The multiple repeating circuit groups C can be arranged along a single direction, or they can be arranged along multiple directions. Optionally, as shown... Figure 6a As shown, a single repeating circuit group C includes a first pixel circuit PX1, a second pixel circuit PX2, and a third pixel circuit PX3 arranged side by side along the first direction X. Multiple repeating circuit groups C are arranged along the first direction X and the second direction Y, respectively. Specifically, the first circuit D1 is the third pixel circuit PX3 in one repeating circuit group C, while the second circuit DP2 is the first pixel circuit PX1 in another repeating circuit group C.

[0072] Furthermore, the display panel 100 may include a pixel unit composed of multiple light-emitting elements. The multiple pixel units are arranged in a repeating manner, wherein the pixel units and the repeating circuit group C are arranged in a corresponding manner. That is, multiple pixel circuits P in a single repeating circuit group C are used to drive multiple light-emitting elements in a single pixel unit, while different pixel circuits P in different repeating circuit groups C are used to drive different light-emitting elements in different pixel units.

[0073] In some alternative embodiments, the arrangement of the multiple pixel circuits P in a single repeating circuit group C is the same as the arrangement of the multiple light-emitting elements F in a single pixel unit, and the arrangement of the multiple repeating circuit groups C is the same as the arrangement of the corresponding pixel unit.

[0074] In this embodiment, the interval J is a region located between adjacent repeating circuit groups C that does not contain pixel circuits P. Compared to the distance between two adjacent pixel circuits P located in a single repeating circuit group C, the distance between two adjacent pixel circuits P located in adjacent repeating circuit groups C is often larger. Based on this, by setting the first type of opening 321 within the interval J, such that the first type of opening 321 is located between two adjacent pixel circuits P in adjacent repeating circuit groups C, the first type of opening 321 can avoid pixel circuits P while having a larger size. This improves the gas release capability of the first conductor portion 31 and reduces the risk of film bulging and detachment of the first conductor portion 31.

[0075] It should be noted that, depending on the actual needs, some of the second type of openings 322 may also be located within the interval J, or there may be no second type of openings 322 within the interval J. This application embodiment does not impose any restrictions on this. Optionally, both first type of openings 321 and second type of openings 322 may exist simultaneously within the interval J, and multiple second type of openings 322 may be located between adjacent first type of openings 321.

[0076] In some embodiments, please refer to Figure 1 , Figure 2 , Figure 5 , Figure 6b as well as Figure 7 The display panel 100 also includes a shift register unit V, which is located between adjacent pixel circuits P. The orthographic projection of the shift register unit V onto the substrate 10 at least partially overlaps with the orthographic projection of the first type of opening 321 onto the substrate 10; and / or, the orthographic projection of the shift register unit V onto the substrate 10 at least partially overlaps with the orthographic projection of the second type of opening 322 onto the substrate 10.

[0077] A shift register unit V is a sequential logic circuit capable of storing and transmitting specific signals. Shift register unit V comprises multiple cascaded shift register circuits, and the connection between these circuits allows the output of one shift register circuit to be either electrically connected to a corresponding signal line or used to provide input signals to the next-level shift register circuit.

[0078] The display panel 100 may include a display area and a bezel area located around the display area. The display area is the region of the display panel 100 used for emitting light, and the light-emitting element F and the corresponding pixel circuit P are both located within the display area. The bezel area, located around the display area, can be used to house some wiring and circuit structures. Furthermore, the shift register unit V is located between adjacent pixel circuits P, meaning the shift register unit V is also located within the display area. This saves the space required to house the shift register unit V within the bezel area, enabling the display panel 100 to achieve a narrow bezel effect, i.e., a higher screen-to-body ratio.

[0079] The specific positions of the multiple shift register circuits within the shift register unit V relative to the pixel circuit P are not limited in the embodiments of this application. For example, taking the first direction X as the row direction and the second direction Y as the column direction, multiple pixel circuits P arranged side-by-side along the first direction X form a circuit row, and multiple pixel circuits P arranged side-by-side along the second direction Y form a circuit column. In this case, as shown... Figure 7 As shown, a single shift register circuit can be located between adjacent circuit rows or between adjacent circuit columns, as long as there is a gap between adjacent shift register circuits in the second direction Y.

[0080] Furthermore, the present application embodiments do not limit the type of signal output by the shift register unit V. For example, the display panel 100 includes scan lines, and the shift register unit V can be electrically connected to the scan lines to provide a scan signal (scan) to the scan lines. Alternatively, the display panel 100 includes light emission control lines, and the shift register unit V can be electrically connected to the light emission control lines to provide a light emission control signal (em) to the light emission control lines.

[0081] Furthermore, in this embodiment, since the shift register unit V is located between adjacent pixel circuits P, the orthographic projection of the shift register unit V onto the substrate 10 can overlap with the first opening 32 on the substrate 10. Furthermore, depending on actual needs, the shift register unit V can be selectively overlapped with at least one of the first type of opening 321 and the second type of opening 322, thereby reducing the risk of bulging or film peeling of the display panel 100 in the area where the shift register unit V is located, and improving the reliability of the display panel 100.

[0082] In some embodiments, please refer to Figure 8 The first organic layer 20 includes an exhaust hole 21, and the first opening 32 at least partially overlaps with the orthographic projection of the exhaust hole 21 onto the substrate 10.

[0083] The vent 21 is a hole-like structure formed by the inward recess of the surface of the first organic layer 20 away from the substrate 10 to achieve the venting function. The vent 21 can completely penetrate the first organic layer 20 along the thickness direction Z, or it can only penetrate a part of the structure of the first organic layer 20 along the thickness direction Z. The vent 21 can have various sizes and shapes. For example, the orthographic projection of the vent 21 onto the substrate 10 can be circular, square, or other regular or irregular shapes.

[0084] The orthographic projections of the first opening 32 and the vent 21 onto the substrate 10 at least partially overlap, meaning the first opening 32 and the vent 21 are positioned correspondingly. Specifically, the orthographic projection of the first opening 32 onto the substrate 10 may completely cover the orthographic projection of the vent 21 onto the substrate 10, or the orthographic projection of the first opening 32 onto the substrate 10 may only cover the orthographic projection of a portion of the structure within the vent 21 onto the substrate 10.

[0085] In this embodiment, by adding an exhaust vent 21 to the display panel 100 and positioning the exhaust vent 21 in correspondence with the position of the first opening 32, moisture and other substances remaining in the first organic layer 20 can move through the exhaust vent 21 to the first opening 32 and be released through the first opening 32. In this way, the cooperation between the first opening 32 and the exhaust vent 21 helps to further reduce the risk of film bulging and first conductor 31 detachment caused by moisture retention, thereby improving the manufacturing yield and reliability of the display panel 100.

[0086] In some embodiments, such as Figure 8 As shown, the orthogonal projection of the vent 21 onto the substrate 10 is located within the orthogonal projection of the first opening 32 onto the substrate 10, and the orthogonal projection area of ​​the vent 21 onto the substrate 10 is smaller than the orthogonal projection area of ​​the first opening 32 onto the substrate 10.

[0087] As can be seen from the accompanying drawings, since the projected area of ​​the exhaust hole 21 is smaller than that of the first opening 32, and the position of the exhaust hole 21 is completely aligned with the first opening 32, the first conductor portion 31 can be completely disposed on the surface of the first organic layer 20 away from the substrate 10. That is, the first conductor portion 31 will not be located inside the exhaust hole 21, and the first organic layer 20 can provide flat support for the first conductor portion 31.

[0088] Furthermore, during the fabrication of the display panel 100, this design also allows the vent hole 21 to be formed after the first opening 32. Specifically, a continuous organic material layer with a full-surface structure can be formed first, and then a first metal layer 30 can be formed on top of the organic material layer. Then, with the shielding effect of the first conductor portion 31 in the first metal layer 30, a portion of the organic material layer at the corresponding first opening 32 can be etched away, thereby forming the first organic layer 20 and the vent hole 21 corresponding to the first opening 32.

[0089] This allows for the formation of vent holes 21 within the first organic layer 20 without the need for a mask, thereby reducing the fabrication difficulty and cost. At the same time, the organic material layer with a full-surface structure can provide a flat and complete surface for the fabrication of the first metal layer 30, thereby reducing the fabrication difficulty of the first metal layer 30 and improving the fabrication reliability of the first metal layer 30.

[0090] In summary, in this embodiment, by positioning the vent 21 entirely within the first opening 32, the first conductor portion 31 is positioned entirely on the surface of the first organic layer 20 facing away from the substrate 10, thus providing flat support for the first conductor portion 31. Furthermore, when gas is released through the vent 21, the first conductor portion 31 is not in the gas release path, thereby reducing the risk of the first conductor portion 31 detaching or bulging relative to the first organic layer 20. Further, this also helps reduce fabrication difficulty and cost, and improves the fabrication reliability of the first metal layer 30.

[0091] In some embodiments, such as Figure 8 As shown, the display panel 100 also includes a first insulating layer 41 disposed on the side of the first metal layer 30 away from the substrate 10, and a portion of the structure in the first insulating layer 41 is located within the first opening 32 and the vent hole 21.

[0092] The first insulating layer 41 is a film structure located on the side of the first metal layer 30 facing away from the substrate 10 and comprising an insulating material. The first insulating layer 41 can have various material compositions; for example, the first insulating layer 41 may include organic insulating materials or inorganic insulating materials. The first insulating layer 41 may be in direct contact with the first metal layer 30, or it may be spaced apart. That is, other film structures may be sandwiched between the first metal layer 30 and the first insulating layer 41, or there may be no other film structures present. This application embodiment does not impose any limitations on this.

[0093] In this embodiment, a portion of the structure in the first insulating layer 41 is located within the first opening 32 and the vent 21. This allows the first insulating layer 41 to provide a relatively flat surface while meeting the insulation requirements of the display panel 100. This reduces the adverse effects of the presence of the vent 21 and the first opening 32 on the fabrication of other film layers located on the side of the first insulating layer 41 away from the substrate 10, and helps to improve the yield and reliability of the display panel 100.

[0094] In some embodiments, the first insulating layer 41 is fitted to the sidewall of the first conductor portion 31 facing the first opening 32.

[0095] In this embodiment, there are no other film structures between the first insulating layer 41 and the first metal layer 30. The first insulating layer 41 can insulate the first conductor portion 31, reducing the risk of short circuit between the first conductor portion 31 and other conductors or semiconductor structures located on the side of the first insulating layer 41 away from the substrate 10, and improving the reliability of signal transmission corresponding to the first conductor portion 31.

[0096] Furthermore, the first insulating layer 41 is also attached to the sidewall of the first conductor portion 31 facing the first opening 32. In this way, during the preparation of other film layers on the side of the first insulating layer 41 away from the substrate 10, the first insulating layer 41 can cover and protect the first conductor layer, thereby reducing the risk of the first conductor portion 31 being etched on the side and the risk of oxidation reaction of the sidewall of the first conductor portion 31, and improving the structural reliability of the first conductor portion 31.

[0097] In some embodiments, please refer to Figure 9 The display panel 100 also includes a second insulating layer 42 disposed between the first metal layer 30 and the first organic layer 20. The second insulating layer 42 includes a second opening 421, which overlaps with the exhaust hole 21 in the orthographic projection of the substrate 10.

[0098] The second insulating layer 42 is a film structure located between the first organic layer 20 and the first metal layer 30 and comprising insulating material. The second insulating layer 42 can have various material compositions; for example, it can include organic insulating materials or inorganic insulating materials. The second insulating layer 42 can be in direct contact with the first metal layer 30, or it can be spaced apart. That is, other film structures can be sandwiched between the second metal layer 50 and the first insulating layer 41, or they may not exist. The relationship between the second insulating layer 42 and the first organic layer 20 is similar, and this application embodiment does not impose any limitations on this.

[0099] The second insulating layer 42 includes a second opening 421, which at least partially overlaps with the orthographic projection of the vent 21 onto the substrate 10, i.e., the second opening 421 and the vent 21 are positioned correspondingly. Further optionally, the second opening 421 at least partially overlaps with the orthographic projection of the first opening 32 onto the substrate 10. Specifically, the orthographic projection of the second opening 421 onto the substrate 10 may completely cover the orthographic projection of the vent 21 onto the substrate 10, or it may only cover the orthographic projection of a portion of the structure within the vent 21 onto the substrate 10.

[0100] In this embodiment, since there is a second insulating layer 42 between the first organic layer 20 and the first metal layer 30, in order to reduce the impact of the second insulating layer 42 on the release of water vapor and other gases in the first organic layer 20, a second opening 421 is added in the second insulating layer 42. The second opening 421 is positioned corresponding to the vent 21. In this way, water vapor and other gases remaining in the first organic layer 20 can move to the first opening 32 through the vent 21 and the second opening 421 in sequence, and be released through the first opening 32. In this way, the cooperation of the first opening 32, the second opening 421 and the vent 21 helps to further reduce the risk of film bulging and first conductor 31 detachment caused by sealing water vapor, and improves the manufacturing yield and reliability of the display panel 100.

[0101] In some embodiments, the second insulating layer 42 comprises an inorganic material.

[0102] Inorganic materials are chemically inert and relatively stable, and they also have a certain ability to isolate water vapor. Based on this, in order to meet the needs of water vapor release, this embodiment of the application provides a second opening 421 in the second insulating layer 42. Water vapor can move to the first opening 32 through the exhaust hole 21 and the second opening 421 in sequence, and be released through the first opening 32. This reduces problems such as bulging caused by water vapor accumulating on the side of the second insulating layer 42 facing the substrate 10, and improves the reliability of the display panel 100.

[0103] In some embodiments, please refer to Figure 10 The display panel 100 also includes a second metal layer 50 disposed on one side of the substrate 10. The second metal layer 50 includes a second conductor portion 51, and the orthographic projection of the second conductor portion 51 on the substrate 10 overlaps with the orthographic projection of at least a portion of the first opening 32 on the substrate 10.

[0104] The second metal layer 50 is a film structure located on the same side of the substrate 10 as the first metal layer 30 and comprising a metal conductor material. The second metal layer 50 may be located on the side of the first metal layer 30 facing the substrate 10, or the second metal layer 50 may be located on the side of the first metal layer 30 away from the substrate 10. Further optionally, the display panel 100 includes a first active layer 61, and both the first metal layer 30 and the second metal layer 50 are located on the side of the first active layer 61 away from the substrate 10.

[0105] The second metal layer 50 includes a second conductor portion 51. Depending on the actual needs, the second conductor portion 51 can be used with the first conductor portion 31 to transmit the same type of signal, or it can also transmit different types of signals. Furthermore, the second conductor portion 51 can be insulated from the first conductor portion 31, or the second conductor portion 51 can be electrically connected to the first conductor portion 31 through a via or the like.

[0106] The specific shape and size of the second conductor portion 51 are not limited in the embodiments of this application. For example, the orthographic projection of the second conductor portion 51 onto the substrate 10 may be a planar structure, or the second conductor portion 51 may include multiple spaced sub-structures. The orthographic projection of a single sub-structure onto the substrate 10 may be a strip or block structure.

[0107] The orthographic projection of the second conductor portion 51 onto the substrate 10 overlaps with the orthographic projection of at least a portion of the first opening 32 onto the substrate 10, meaning there is an overlapping area between the orthographic projection of the second conductor portion 51 onto the substrate 10 and the orthographic projection of at least a portion of the first opening 32 onto the substrate 10. Specifically, the orthographic projection of the second conductor portion 51 onto the substrate 10 may overlap with all the orthographic projections of the first opening 32 onto the substrate 10, or it may overlap with only a portion of the orthographic projections of the first opening 32 onto the substrate 10, while the other orthographic projections of the first opening 32 onto the substrate 10 are located outside the orthographic projection of the second conductor portion 51 onto the substrate 10.

[0108] Furthermore, the overlapping first opening 32 and second conductor portion 51 can have various positional configurations. For example, the orthographic projection of the second conductor portion 51 onto the substrate 10 can completely cover the orthographic projection of the first opening 32 onto the substrate 10, or it can overlap with the orthographic projection of a portion of the structure in the first opening 32 onto the substrate 10, while the orthographic projections of other structures in the first opening 32 onto the substrate 10 are located outside the orthographic projection of the second conductor portion 51 onto the substrate 10. Optionally, the orthographic projection of the second conductor portion 51 onto the substrate 10 completely covers at least a portion of the orthographic projection of the first opening 32 onto the substrate 10.

[0109] In this embodiment, in addition to fulfilling its own signal transmission function, the second conductor portion 51 can also cover and protect other film layer structures on the side of the second metal layer 50 facing the substrate 10, thereby protecting at least a portion of the structure in the transistor M, thereby improving the manufacturing yield of the display panel 100.

[0110] In some embodiments, such as Figure 10 As shown, the display panel 100 also includes a first active layer 61 disposed on the side of the second metal layer 50 facing the substrate 10. The first active layer 61 includes a first active structure 611, and the first active structure 611 includes a first exposed portion 612. The orthographic projection of the first exposed portion 612 on the substrate 10 is located within the first opening 32. The orthographic projection of the second conductor portion 51 on the substrate 10 and the orthographic projection of the first exposed portion 612 on the substrate 10 at least partially overlap.

[0111] The first active layer 61 is a semiconductor film layer located on the side of the first metal layer 30 and the second metal layer 50 facing the substrate 10. Depending on the actual needs, the display panel 100 may include only the first active layer 61, or it may include two semiconductor film layers simultaneously. Specifically, when the display panel 100 includes only the first active layer 61, the pixel circuit P in the display panel 100 may use LTPS technology, which includes only LTPS (Low Temperature Poly-Silicon)-TFT. In this case, the material of the first active layer 61 includes low temperature polysilicon. When the display panel 100 includes two semiconductor film layers simultaneously, the pixel circuit in the display panel 100 may use LTPO technology, which includes both LTPS-TFT and IGZO (Indium Gallium Zinc Oxide)-TFT. In this case, the first active layer 61 may include low temperature polysilicon or metal oxide.

[0112] The first active structure 611 is a semiconductor structure located within the first active layer 61. The first active structure 611 includes a first exposed portion 612 corresponding to the position of the first opening 32. As can be seen from the foregoing, the plurality of first openings 32 include first type openings 321 and second type openings 322 of different sizes. The orthographic projection of the first type opening 321 onto the substrate 10 can be located outside the orthographic projection of the first active structure 611 onto the substrate 10. The orthographic projection of the second type opening 322 onto the substrate 10 overlaps with the orthographic projection of the first active structure 611 onto the substrate 10. The part of the first active structure 611 corresponding to the overlapping area is the first exposed portion 612.

[0113] Furthermore, in this embodiment, the second metal layer 50 is located on the side of the first active layer 61 facing away from the substrate 10, and the orthographic projection of the second conductor portion 51 onto the substrate 10 overlaps with the orthographic projection of the first exposed portion 612 onto the substrate 10. This allows the second conductor portion 51 to protect the first exposed portion 612, reducing the adverse effects of processes such as laser bonding on the first active structure 611, improving the reliability of the first active structure 611 and the yield rate of the display panel 100. Simultaneously, the layout of the first active structure 611 is not limited by the position of the first opening 32, thereby reducing the layout difficulty of the first active structure 611 and improving the display effect and display accuracy.

[0114] In some embodiments, please refer to Figure 11The second metal layer 50 is located on the side of the first metal layer 30 facing the substrate 10. The display panel 100 also includes a second active layer 62 disposed between the second metal layer 50 and the first metal layer 30. The second active layer 62 includes a second active structure 621. The orthographic projection of the second active structure 621 onto the substrate 10 is located outside the orthographic projection of the first exposed portion 612 onto the substrate 10.

[0115] In this embodiment, the display panel 100 includes two semiconductor film layers: a first active layer 61 and a second active layer 62. The pixel circuit P uses LTPO technology. The material of the first active layer 61 may include low-temperature polycrystalline silicon, while the material of the second active layer 62 includes metal oxide.

[0116] The first active layer 61, the first metal layer 30, the second active layer 62, and the second metal layer 50 are stacked sequentially in a direction that gradually moves away from the substrate 10. As can be seen from the foregoing, the first active structure 611 in the first active layer 61 includes a first exposed portion 612 corresponding to the first opening 32, and the second conductor portion 51 in the second metal layer 50 can be correspondingly arranged to the first exposed portion 612 to protect the first exposed portion 612, reduce the risk of damage to the first exposed portion 612 due to processes such as laser bonding, and improve reliability.

[0117] Furthermore, regarding the second active layer 62, since it is located on the side of the second metal layer 50 away from the substrate 10, the second metal layer 50 cannot protect the second active layer 62 during subsequent processes. Therefore, to reduce the risk to the second active layer 62, this embodiment further configures the second active structure 621 in the second active layer 62 such that its orthographic projection onto the substrate 10 is outside the orthographic projection of the first opening 32 onto the substrate 10. Alternatively, the orthographic projection of the second active structure 621 onto the substrate 10 can be completely located within the orthographic projection of the first conductor portion 31 onto the substrate 10. This allows the first conductor portion 31 to protect the second active structure 621, thereby reducing the risk of damage to the second active structure 621 due to processes such as laser bonding and improving reliability.

[0118] In summary, in this embodiment, since the first active layer 61 is located on the side of the first metal layer 30 and the second metal layer 50 facing the substrate 10, some structures in the first active structure 611, such as the first exposed portion 612, can be provided corresponding to the first opening 32, and the second conductor portion 51 is used to protect the first exposed portion 612. As for the second active layer 62, since it is located between the first metal layer 30 and the second metal layer 50, in order to reduce the impact of subsequent processes on the second active layer 62, the orthographic projection of the second active structure 621 on the substrate 10 is set to be outside the orthographic projection of the first exposed portion 612 on the substrate 10. In this way, the first conductor portion 31 is used to protect the second active structure 621. This design can further improve the manufacturing yield and reliability of the display panel 100.

[0119] In some embodiments, please refer to Figure 12 The second metal layer 50 is disposed on the side of the first metal layer 30 away from the substrate 10.

[0120] The first metal layer 30 has a first opening 32. The presence of the first opening 32 can easily have an adverse effect on the underlying film structure in subsequent manufacturing processes. Based on this, in this embodiment, the second metal layer 50 is located on the side of the first metal layer 30 facing away from the substrate 10, that is, the first metal layer 30 is not the metal film layer in the display panel 100 that is furthest from the substrate 10. The second conductor portion 51 is configured such that its orthographic projection on the substrate 10 overlaps with at least a portion of the orthographic projection of the first opening 32 on the substrate 10. In this way, the second conductor portion 51 can protect the portion of the structure exposed relative to the first opening 32 in the other multiple film layers on the side of the first metal layer 30 facing the substrate 10, thereby helping to further improve the yield of the display panel 100.

[0121] The specific positional relationship between the first metal layer 30 and the second metal layer 50, as well as the specific type of signal transmitted by the first conductor portion 31 and the second conductor portion 51, are not limited in the embodiments of this application. Optionally, the second conductor portion 51 includes a first pad and a second pad that are insulated from each other, and the first pad and the second pad are respectively used to fix the two electrodes of the light-emitting element. The first conductor portion 31 can be used to transmit a power supply voltage signal. Based on this, if the power supply voltage signal is a PVDD signal, then both the first pad and the second pad are insulated from the first conductor portion 31; if the power supply voltage signal is a PVEE signal, then one of the first pad and the second pad can be electrically connected to the first conductor portion 31, and the other is insulated from the first conductor portion 31.

[0122] In some embodiments, please refer to Figure 13The display panel 100 also includes a second active layer 62 disposed between the first metal layer 30 and the first active layer 61. The second active layer 62 includes a second active structure 621, and the second active structure 621 includes a second exposed portion 622. The orthographic projection of the second exposed portion 622 onto the substrate 10 is located within the first opening 32. The orthographic projection of the second conductor portion 51 onto the substrate 10 and the orthographic projection of the second exposed portion 622 onto the substrate 10 at least partially overlap.

[0123] The first active layer 61, the second active layer 62, the first metal layer 30, and the second metal layer 50 are sequentially stacked in a direction gradually moving away from the substrate 10. The second active structure 621 is a semiconductor structure located within the second active layer 62. In some cases, depending on the actual layout requirements, the second active structure 621 may include a second exposed portion 622 corresponding to the position of the first opening 32.

[0124] As can be seen from the foregoing, the plurality of first openings 32 include first type openings 321 and second type openings 322 of different sizes. Optionally, the orthographic projection of the first type opening 321 on the substrate 10 may be located outside the orthographic projection of the second active structure 621 on the substrate 10, while the orthographic projection of the second type opening 322 on the substrate 10 and the orthographic projection of the second active structure 621 on the substrate 10 have an overlapping area. The part of the second active structure 621 at the overlapping area is the second exposed part 622.

[0125] Furthermore, in this embodiment, the second metal layer 50 is located on the side of the second active layer 62 facing away from the substrate 10, and the orthographic projection of the second conductor portion 51 onto the substrate 10 overlaps with the orthographic projection of the second exposed portion 622 onto the substrate 10. This allows the second conductor portion 51 to protect the second exposed portion 622, reducing the adverse effects of processes such as laser bonding on the second active structure 621, improving the reliability of the second active structure 621 and the yield rate of the display panel 100. Simultaneously, the layout of the second active structure 621 is not limited by the position of the first opening 32, thereby reducing the layout difficulty of the second active structure 621 and improving the display effect and display accuracy.

[0126] In some embodiments, such as Figure 12 and Figure 13 As shown, the first opening 32, which is at least partially overlapping the first active structure 611, and the second conductor portion 51, which is at least partially overlapping the orthographic projection on the substrate 10, are all first openings 32.

[0127] The first opening 32, which is at least partially overlapping with the first active structure 611, is the first opening 32 that overlaps with the first exposed portion 612 in the orthographic projection on the substrate 10. If there is no other shielding structure in the area corresponding to the first opening 32, the laser can easily pass through the first opening 32 and irradiate the first exposed portion 612 in the subsequent laser bonding process, which may cause damage to the first active structure 611.

[0128] In view of this, in the embodiments of this application, the first opening 32 corresponding to the first exposed portion 612 and the second conductor portion 51 are arranged to overlap in the orthographic projection on the substrate 10, so that the second conductor portion 51 can block the first exposed portion 612, reduce the damage to the first active structure 611 caused by subsequent laser bonding and other processes, and improve the reliability of the display panel 100.

[0129] In some alternative embodiments, the display panel 100 further includes a second active layer 62 disposed between the first metal layer 30 and the first active layer 61. The second active layer 62 includes a second active structure 621, and a first opening 32 of a plurality of first openings 32 that at least partially overlaps with the second active structure 621 and at least partially overlaps with the orthographic projection of the first conductor portion 31 onto the substrate 10.

[0130] In some embodiments, please refer to Figure 12 and Figure 14 The display panel 100 includes a second metal layer 50 on the side opposite to the substrate 10. The second metal layer 50 includes a second conductor portion 51. The second conductor portion 51 includes a third type opening 52 and a fourth type opening 53. The size of the third type opening 52 is larger than the size of the fourth type opening 53.

[0131] Similar to the first metal layer 30, the second metal layer 50 may also have multiple opening structures, including third type openings 52 and fourth type openings 53 of different sizes. The "size" mentioned here refers to the projected area on the substrate 10, that is, the projected area of ​​the third type opening 52 on the substrate 10 is larger than the projected area of ​​the fourth type opening 53 on the substrate 10.

[0132] Furthermore, the third type of opening 52 refers to an opening with a corresponding projected area greater than the second preset value, and the fourth type of opening 53 refers to an opening with a corresponding projected area less than the second preset value. The specific size of the second preset value is not limited in this embodiment. Optionally, the first preset value and the second preset value are the same value. There can be multiple third type openings 52, and the shapes and sizes of different third type openings 52 on the substrate 10 can be the same or different. Similarly, there can be multiple fourth type openings 53, and the shapes and sizes of different fourth type openings 53 on the substrate 10 can be the same or different.

[0133] Combination Figure 6a and Figure 6b Regarding the positional relationship between the third type of opening 52 and the fourth type of opening 53 relative to the first type of opening 321 and the second type of opening 322, this embodiment does not impose limitations. The orthographic projection of the third type of opening 52 onto the substrate 10 can be simultaneously located outside the orthographic projections of the first type of opening 321 and the second type of opening 322 onto the substrate 10, or the orthographic projection of the third type of opening 52 onto the substrate 10 can overlap with the orthographic projection of either the first type of opening 321 or the second type of opening 322 onto the substrate 10. The fourth type of opening 53 is similar, and will not be described in detail in this embodiment.

[0134] In this embodiment, the second metal layer 50 is similar to the first metal layer 30, also including multiple opening structures of different sizes. On this basis, the third type of opening 52 and the fourth type of opening 53 help to further improve the gas release effect of the display panel 100, reduce the risk of water vapor and other substances accumulating on the side of the second metal layer 50 toward the substrate 10 and causing bulging, and improve the yield and reliability of the display panel 100.

[0135] In some embodiments, such as Figure 4a , Figure 4b and Figure 12 As shown, the pixel circuit P includes a low power supply terminal and a high power supply terminal. The low power supply terminal provides a low power supply voltage, and the high power supply terminal provides a high power supply voltage. The first conductor portion 31 is used to transmit the low power supply voltage or the high power supply voltage, and the second conductor portion 51 is used to transmit the low power supply voltage or the high power supply voltage.

[0136] Taking a microled light-emitting element in the display panel 100, which includes a first electrode and a second electrode, as an example, the pixel circuit P will be described below. The pixel circuit P includes a pulse width modulation circuit P1 and a pulse amplitude modulation circuit P2. The pulse width modulation circuit P1 is configured to control the pulse width of the driving current supplied to the light-emitting element based on the pulse width modulation data voltage, and the pulse amplitude modulation circuit P2 is configured to control the amplitude of the driving current supplied to the light-emitting element based on the pulse amplitude modulation data voltage. The pulse width of the driving current can be understood as the duration of the driving current, and the amplitude of the driving current can be understood as the magnitude of the driving current value.

[0137] Furthermore, such as Figure 4a and Figure 4bAs shown, the pixel circuit P may include a pulse width modulation circuit P1 and a pulse amplitude modulation circuit P2. The pixel circuit P generates a driving current under the control of the pulse amplitude modulation circuit P2 and the pulse width modulation circuit P1. The pulse amplitude modulation circuit P2 can be used to control the amplitude of the driving current, and the pulse width modulation circuit P1 can be used to adjust the pulse width of the voltage applied to the second electrode of the light-emitting element F. The pulse width modulation circuit P1 adjusts the actual emission period of the driving current applied to the light-emitting element by adjusting the pulse width of the voltage applied to the second electrode of the light-emitting element F; simultaneously, it can maintain the driving current applied to the light-emitting element F at a constant level to adjust the grayscale or brightness displayed by the light-emitting element F, rather than adjusting the magnitude of the driving current applied to the light-emitting element F. Therefore, the pulse amplitude modulation circuit P2 can provide driving current to the light-emitting element F so that the light-emitting element F is driven with optimal luminous efficiency, and the pulse width modulation circuit P1 adjusts the emission duty cycle of the light-emitting element (i.e., the emission period of the light-emitting element F) to adjust the grayscale or brightness displayed by the light-emitting element F. The output of the pulse width modulation circuit P1 can be directly connected to the control terminal of a driving transistor in the pulse amplitude modulation circuit P2. That is, the electrical signal output from the output of the pulse width modulation circuit P1 is directly written to the control terminal of the driving transistor to adjust the amplitude of the driving current.

[0138] It should be noted that the figure only illustrates one connection method between the pulse width modulation circuit P1 and the pulse amplitude modulation circuit P2. Depending on the actual needs, the two circuits can be connected in various other ways, and this embodiment does not impose any limitations. In some other embodiments, the output terminal of the pulse width modulation circuit P1 can be connected to the pulse amplitude modulation circuit P2 through a first capacitor. Specifically, the pixel circuit P also includes a first capacitor, the first plate of which is electrically connected to the output terminal of the pulse width modulation circuit P1, and the second plate of which is electrically connected to the pulse amplitude modulation circuit P2. The second plate of the first capacitor is connected to the control terminal of the controlled transistor. The controlled transistor can be the driving transistor in the pulse amplitude modulation circuit P2 that generates the driving current, or it can be another transistor in the pulse amplitude modulation circuit P2 connected in series with the driving transistor.

[0139] Furthermore, the specific circuit configurations within the first and second driving circuits are not limited in the embodiments of this application. For example, as shown... Figure 4aAs shown, the pulse width modulation circuit P1 includes a first driving transistor M1, a first gate reset transistor M2, a first data writing transistor M3, a first compensation transistor M4, a first control transistor M6, a third control transistor M5, and a storage capacitor Cst. The third control transistor M5 is connected between the first power supply voltage PWM-Vdd and the first terminal of the first driving transistor M1. The first control transistor M6 is connected between the second terminal of the second driving transistor M1 and the output terminal of the first driving circuit. The first data writing transistor M3 is connected to the first terminal of the second driving transistor M1. The first compensation transistor M4 is connected to the second terminal of the second driving transistor M1 and the control terminal. The first gate reset transistor M2 is connected to the control terminal of the second driving transistor M1. The first plate of the storage capacitor Cst is connected to the control terminal of the first driving transistor M1, and the second plate of the storage capacitor Cst is connected to the sweep frequency signal SWEEP. Specifically, the control terminal of the first gate reset transistor M2 receives the first scan signal PWM-S1, and the gates of the first data writing transistor M3 and the first compensation transistor M4 receive the second scan signal PWM-S2. The gates of the first control transistor M6 and the third control transistor M5 receive the first light emission control signal PWM-EM.

[0140] The pulse amplitude modulation circuit P2 includes a second driving transistor M7, a second gate reset transistor M8, a second data write transistor M9, a second compensation transistor M10, a second control transistor M11, a fourth control transistor M12, and an electrode reset transistor M13. The second control transistor M11 is connected between the second power supply voltage PAM-vdd and the first electrode of the second driving transistor M7. The fourth control transistor M12 is connected between the second electrode of the second driving transistor M7 and the light-emitting element F. The second driving transistor M7 is configured to generate a driving current under the control of its control terminal voltage. The second data write transistor M9 is connected to the first electrode of the second driving transistor M7. The second compensation transistor M10 is connected to the second electrode of the second driving transistor M7 and its control terminal. The second gate reset transistor M8 is connected to the control terminal of the second driving transistor M7. The electrode reset transistor M13 is connected to the second electrode of the light-emitting element F. The fourth control transistor M12 is also connected to the second electrode of the light-emitting element F. The first electrode of the light-emitting element F is connected to the third power supply voltage PVEE. Specifically, the control terminal of the second gate reset transistor M8 receives the third scan signal PAM-S1; the control terminals of the second data write transistor M9, the second compensation transistor M10, and the electrode reset transistor M13 receive the fourth scan signal PAM-S2. The gates of the second control transistor M11 and the fourth control transistor M12 receive the second light emission control signal PAM-EM.

[0141] Or such as Figure 4bAs shown, both the pulse amplitude modulation circuit P2 and the pulse width modulation circuit P1 include an initialization unit 111 / 121, a data writing unit 112 / 122, a threshold compensation unit 113 / 123, a light-emitting control unit 114 / 124, a storage capacitor C1 / C2, and a driving transistor PAM-DR / PWM-DR (wherein, the pulse amplitude modulation circuit P2 includes an initialization unit 111, a data writing unit 112, a threshold compensation unit 113, a light-emitting control unit 114, a storage capacitor C2, and a driving transistor PAM-DR; the pulse width modulation circuit P1 includes an initialization unit 111 / 12 ... threshold compensation unit 113, a threshold compensation unit 114, a light-emitting control unit 114, a storage capacitor C2, and a driving transistor PAM-DR; the pulse width modulation circuit P1 includes an initialization unit 111 / 121, a data writing unit 112, a threshold compensation unit 113, a threshold compensation unit 114, a light-emitting control unit 114, a storage capacitor C2, and a driving transistor PAM-DR The system includes an initialization unit 121, a data writing unit 122, a threshold compensation unit 123, a light-emitting control unit 124, a storage capacitor C2, and a driving transistor PWM-DR. The initialization units 111 / 121 are electrically connected between the initialization signal VREF and the first node N11 / N12. The initialization units 111 / 121 are used to provide the initialization signal VREF to the first node N11 / N12 during the initialization phase. (The initialization signal provided by the initialization signal terminal of the pulse amplitude modulation circuit P2 can be the same as or different from the initialization signal of the pulse width modulation circuit P1.) Data writing units 112 / 122 are electrically connected between the data signal PAM-DATA / PWM-DATA and the first terminal of the driving transistor PAM-DR / PWM-DR. The control terminal of the driving transistor PAM-DR / PWM-DR and the first plate of the storage capacitor C2 / C1 are electrically connected to the first node N11 / N12. Data writing units 112 / 122 are used to provide the data signal PAM-DATA / PWM-DATA to the first node N11 / N12 through the driving transistor PAM-DR / PWM-DR during the data writing phase. Threshold compensation units 113 / 123 are electrically connected between the second terminal of the driving transistor PAM-DR / PWM-DR and the first node N11 / N12. Threshold compensation units 113 / 123 are used to compensate the threshold voltage of the driving transistor PAM-DR / PWM-DR to the first node N11 / N12.

[0142] In the pulse width modulation circuit P1, the second plate of the storage capacitor C1 is electrically connected to the sweep frequency signal SWEEP, and the light emission control unit 124 is electrically connected between the first power supply voltage PWM-vdd and the first node N11 in the pulse amplitude modulation circuit P2. The light emission control unit 124 is used to control the driving transistor PWM-DR to generate driving pulses during the light emission stage.

[0143] In the pulse amplitude modulation circuit P2, the second plate of the storage capacitor C2 is electrically connected to the second power supply signal PAM-vdd, and the light-emitting control unit 114 is electrically connected between the second power supply signal PAM-vdd and the light-emitting element F. The light-emitting control unit 114 is used to control the driving transistor PAM-DR to generate a driving current that flows into the light-emitting element F during the light-emitting stage, so as to drive the light-emitting element F to emit light.

[0144] Based on this, whether Figure 4a The circuit structure shown is still Figure 4b The circuit structure shown includes a third power supply voltage PVEE for all low-level power supply voltages and a power supply voltage PVDD for all high-level power supply voltages. PVDD includes a first power supply voltage PWM-Vdd and a second power supply voltage PAM-Vdd. Furthermore, both the first conductor portion 31 and the second conductor portion 51 can be used to transmit either the low-level or high-level power supply voltage. The first conductor portion 31 and the second conductor portion 51 can simultaneously transmit the same power supply voltage, in which case they can be interconnected via vias. Alternatively, the first conductor portion 31 and the second conductor portion 51 can be used to transmit different signals, in which case they must be insulated from each other.

[0145] In this embodiment of the application, for the specific circuit form of the pixel circuit P, in order to meet the light emission display requirements of the display panel 100, both the first conductor portion 31 and the second conductor portion 51 are configured to transmit low-level power supply voltage or high-level power supply voltage, thereby meeting the power supply voltage transmission requirements and realizing the light emission display function of the display panel 100.

[0146] In some embodiments, the first conductor portion 31 and the second conductor portion 51 transmit different signals.

[0147] In this embodiment, the first conductor portion 31 and the second conductor portion 51 transmit different signals; that is, one of them is used to transmit a low-level power supply voltage, and the other is used to transmit a high-level power supply voltage. The orthographic projections of the first conductor portion 31 and the second conductor portion 51 onto the substrate 10 may overlap. Furthermore, since both the low-level and high-level power supply voltages are constant potentials, even though the first conductor portion 31 and the second conductor portion 51 transmit different signals and have an overlapping area, parasitic capacitance is less likely to occur. This helps to improve the reliability of signal transmission within the first conductor portion 31 and the second conductor portion 51, thereby improving the display effect of the display panel 100.

[0148] In some embodiments, the pixel circuit P includes a pulse amplitude modulation circuit P2 and a pulse width modulation circuit P1. The pulse amplitude modulation circuit P2 is configured to drive the amplitude of the current based on modulation data, and the pulse width modulation circuit P1 is configured to control the pulse width of the driving circuit. The pulse modulation circuit includes a first power supply terminal for providing a first power supply voltage PWM-vdd, and a first conductor portion 31 transmits the first power supply voltage PWM-vdd. The pulse amplitude modulation circuit P2 includes a second power supply terminal for providing a second power supply voltage PAM-vdd, and a second conductor portion 51 transmits the second power supply voltage PAM-vdd.

[0149] In this embodiment, both the first conductor portion 31 and the second conductor portion 51 can be used to transmit the power supply voltage PVDD. However, the difference is that the first conductor portion 31 is used to transmit the first power supply voltage PWM-vdd, and the second conductor portion 51 is used to transmit the second power supply voltage PAM-vdd. On this basis, the first conductor portion 31 and the second conductor portion 51 still need to be insulated from each other. Since both are used to transmit constant voltage potential, even if the first metal layer 30 and the second metal layer 50 are two adjacent metal layers, and the first conductor portion 31 and the second conductor portion 51 have an overlapping area, parasitic capacitance is not easily generated. This helps to improve the reliability of signal transmission inside the display panel 100, improve the display effect and service life.

[0150] In some embodiments, please refer to Figure 12 , Figure 14 and Figure 15 In the direction perpendicular to the plane where the display panel 100 is located, the third type of opening 52 does not overlap with the pixel circuit P; and / or, the fourth type of opening 53 at least partially overlaps with the pixel circuit P.

[0151] The third type of opening 52 does not overlap with the pixel circuit P, meaning that the orthographic projection of the third type of opening 52 onto the substrate 10 can be located outside the orthographic projection of each transistor M in the pixel circuit P onto the substrate 10. The fourth type of opening 53, however, at least partially overlaps with the pixel circuit P, meaning that the orthographic projection of the fourth type of opening 53 onto the substrate 10 overlaps with the orthographic projection of the transistor M in the pixel circuit P onto the substrate 10.

[0152] In this embodiment, the third type of opening 52 is a relatively large opening structure. By ensuring that the third type of opening 52 and the pixel circuit P do not overlap, venting can be achieved outside the area where the pixel circuit P is located, improving the gas release effect and reducing the risk of performance degradation caused by a large area of ​​the pixel circuit P being exposed to the third type of opening 52. As for the fourth type of opening 53, by ensuring that at least a portion of the fourth type of opening 53 overlaps with the pixel circuit P, the venting needs of the area where the pixel circuit P is located can be met by means of the fourth type of opening 53. Furthermore, since the fourth type of opening 53 is a relatively small opening structure, the exposed area of ​​the pixel circuit P at the fourth type of opening 53 is small. This reduces the probability of performance degradation of the pixel circuit P due to light exposure and laser bonding, thereby helping to improve the manufacturing yield and performance of the display panel 100.

[0153] In some alternative embodiments, in a plane direction perpendicular to the display panel 100, the third type of opening 52 does not overlap with the pixel circuit P, and the fourth type of opening 53 at least partially overlaps with the pixel circuit P.

[0154] In some embodiments, the orthographic projection of the third type of opening 52 onto the substrate 10 is located between the orthographic projections of the adjacent pixel circuit P onto the substrate 10.

[0155] In this embodiment, considering that at least some adjacent pixel circuits P can have a large spacing, the third type of opening 52 is correspondingly disposed between adjacent pixel openings. This design has two advantages: firstly, it can improve the gas release capability of the second conductor portion 51 by using the third type of opening 52, reducing the risk of the second conductor portion 51 detaching; secondly, it can also meet the need for the third type of opening 52 to avoid the pixel circuit P, reducing the risk of performance and yield degradation caused by a large area of ​​the pixel circuit P being exposed to the third type of opening 52.

[0156] It should be noted that there may be only one third-type opening 52 between two adjacent pixel circuits P, or there may be multiple third-type openings 52. This application embodiment does not limit this. Optionally, multiple third-type openings 52 may be provided between two adjacent pixel circuits P in the first direction X, and the multiple third-type openings 52 are arranged side by side and spaced apart along the second direction Y.

[0157] In some embodiments, multiple pixel circuits P arranged adjacently together form a repeating circuit group C, and the multiple repeating circuit groups C are arranged repeatedly; wherein, adjacent repeating circuit groups C are spaced apart to form a gap region J, and the third type of opening 52 is located in the gap region J.

[0158] In this embodiment, the interval J is a region located between adjacent repeating circuit groups C that does not contain pixel circuits P. Compared to the distance between two adjacent pixel circuits P located in a single repeating circuit group C, the distance between two adjacent pixel circuits P located in adjacent repeating circuit groups C is often larger. Based on this, by placing the third type of opening 52 within the interval J, such that the third type of opening 52 is located between two adjacent pixel circuits P in adjacent repeating circuit groups C, the third type of opening 52 can avoid pixel circuits P while having a larger size. This improves the gas release capability of the second conductor portion 51 and reduces the risk of film bulging and detachment of the second conductor portion 51.

[0159] In some embodiments, such as Figure 14 and Figure 15 As shown, the second conductor portion 51 includes a first pad 54 and a second pad 55 that are insulated from each other, with the second pad 55 connected to the pixel circuit P. The first pad 54 includes a fourth type opening 53; and / or, the second pad 55 includes a fourth type opening 53.

[0160] In this embodiment, the first metal layer 30 is a metal film layer for connecting with the light-emitting element F. Specifically, the light-emitting element F may include a first electrode and a second electrode. The first pad 54 can be connected and fixed to the first electrode by laser bonding, and the second pad 55 can be connected and fixed to the second electrode by laser bonding.

[0161] The second pad 55 is connected to the pixel circuit P. That is, the second pad 55 is a pad structure required to realize the electrical connection between the pixel circuit P and the first electrode. On this basis, the first pad 54 is used to transmit the third power supply voltage PVEE.

[0162] The dimensions and shapes of the first pad 54 and the second pad 55 are not limited in this embodiment, as long as the first pad 54 and the second pad 55 are insulated from each other. For example, the first pad 54 may be a full-surface structure, and a through-hole structure may be provided in a certain area. The second pad 55 is accommodated in the through-hole structure and is insulated from the first pad 54.

[0163] Furthermore, in this embodiment, since the fourth type of opening 53 is a small opening structure, the fourth type of opening 53 can be set on either the first pad 54 or the second pad 55. That is, depending on the actual needs, the fourth type of opening 53 can be selectively set on at least one of the first pad 54 and the second pad 55 to meet the venting requirements at the second conductor portion 51, which has strong practicality and flexibility.

[0164] It should be noted that in some optional embodiments, a fourth type of opening 53 may be provided on the first pad 54, and a fourth type of opening 53 may also be provided on the second pad 55. Based on this, the size and shape parameters of the fourth type of opening 53 on the first pad 54 may be the same as or different from the size and shape parameters of the fourth type of opening 53 on the second pad 55. This application embodiment does not limit this.

[0165] In some embodiments, the size of the fourth type opening 53 of the first pad 54 is larger than the size of the fourth type opening 53 of the second pad 55.

[0166] The size of the fourth type of opening 53 on the first pad 54 is the area of ​​the orthogonal projection of the fourth type of opening 53 on the first pad 54 onto the substrate 10. Similarly, the size of the fourth type of opening 53 on the second pad 55 is the area of ​​the orthogonal projection of the fourth type of opening 53 on the second pad 55 onto the substrate 10.

[0167] As described above, the first pad 54 can be a full-surface structure, therefore its size is often larger than that of the second pad 55. Based on this, this embodiment addresses the size difference between the first pad 54 and the second pad 55 by setting the size of the fourth type of opening 53 on the first pad 54 to be larger than that on the second pad 55. That is, the larger pad structure has a larger fourth type of opening 53, while the smaller pad structure has a smaller fourth type of opening 53. This design allows the fourth type of opening 53 to be formed on both the first pad 54 and the second pad 55 while still maintaining a certain size to meet the signal transmission requirements. This improves the display reliability of the display panel 100 while also meeting the venting requirements of the second conductor portion 51.

[0168] In some embodiments, such as Figure 14 As shown, the first pad 54 includes an annular fourth type opening 53, and the second pad 55 is located within the annular fourth type opening 53. A third type opening 52 is disposed on the first pad 54 and spaced apart from the annular fourth type opening 53.

[0169] The first pad 54 and the second pad 55 need to be insulated from each other, that is, they need to be designed to be spaced apart from each other. Based on this, in the embodiment of this application, a fourth type of opening 53 in the first pad 54 is formed in the ring shape. The second pad 55 is located inside the ring structure and the ring structure surrounds the second pad 55. The first pad 54 is located outside the ring structure and surrounds the ring structure.

[0170] During the preparation of the second metal layer 50, a fourth type of ring-shaped opening 53 can be formed by etching or other processes. At this time, the conductor structure inside the ring structure is the second pad 55, and the conductor structure outside the ring structure is the first pad 54.

[0171] It should be noted that the shape of other fourth-type openings 53 besides the annular one is not limited in this embodiment. Optionally, the orthographic projection of other fourth-type openings 53 onto the substrate 10 can be circular, square, or other regular or irregular shapes.

[0172] Furthermore, in this embodiment, given that the first pad 54 can have a large size, a third type of opening 52 can be provided on the first pad 54. Based on this, considering that the second pad 55 is smaller and used to connect to the pixel circuit P, the area near the annular fourth type of opening 53 generally corresponds to the area where the pixel circuit P is located. Furthermore, to reduce the adverse effects of the third type of opening 52 on the pixel circuit P, this embodiment also alternates between the third type of opening 52 and the annular fourth type of opening 53, thereby reducing the overlap between the orthographic projection of the third type of opening 52 on the substrate 10 and the pixel circuit P on the substrate 10. This design can improve the venting capability of the second conductor portion 51 while reducing the adverse effects of the third type of opening 52 on the pixel circuit P, thereby improving the performance reliability of the pixel circuit P and the fabrication yield of the display panel 100.

[0173] In some embodiments, such as Figure 6a , Figure 6b , Figure 12 , Figure 14 as well as Figure 15 As shown, the plurality of first openings 32 include a first type of opening 321 and a second type of opening 322, wherein the size of the first type of opening 321 is larger than the size of the second type of opening 322. On a plane perpendicular to the display panel 100, the first type of opening 321 and the pixel circuit P do not overlap, while at least a portion of the second type of opening 322 overlaps with the pixel circuit P. Specifically, on a plane perpendicular to the display panel 100, at least a portion of the second type of opening 322 does not overlap with the fourth type of opening 53, and / or, at least a portion of the first type of opening 321 does not overlap with the third type of opening 52.

[0174] The first conductor portion 31 contains both a first type of opening 321 and a second type of opening 322 of different sizes, and the second conductor portion 51 contains both a third type of opening 52 and a fourth type of opening 53 of different sizes. The first type of opening 321 and the third type of opening 52 are not overlapped with the pixel circuit P, while the second type of opening 322 and the fourth type of opening 53 are at least partially overlapped with the pixel circuit P.

[0175] Based on this, in this embodiment, the second type of opening 322 and the fourth type of opening 53 do not overlap; that is, the second type of opening 322 and the fourth type of opening 53 are not correspondingly arranged, and their orthogonal projections onto the substrate 10 are misaligned. Therefore, in at least a portion of the area where the second type of opening 322 is located, the fourth type of opening 53 will not exist, and a conductor structure in the second conductor portion 51 will correspondingly exist. Similarly, in at least a portion of the area where the fourth type of opening 53 is located, the second type of opening 322 will not exist, and a conductor structure in the first conductor portion 31 will correspondingly exist.

[0176] With the coordinated design of the first conductor portion 31 and the second conductor portion 51, the risk of large-area exposure of other film layers on the side of the first metal layer 30 and the second metal layer 50 facing the substrate 10 due to the corresponding arrangement of the second type of opening 322 and the fourth type of opening 53 can be reduced. This reduces the adverse effects of laser bonding and other processes on the first metal layer 30 and the other film layers on the side of the second metal layer 50 facing the substrate 10, thereby improving the yield and reliability of the display panel 100. The relationship between the first type of opening 321 and the third type of opening 52 is similar and will not be described again in this embodiment.

[0177] It should be noted that the positional relationship between the first type of opening 321 and the fourth type of opening 53 is not limited in this embodiment. For example, the first type of opening 321 and the fourth type of opening 53 can overlap each other, or they can be staggered. Similarly, the positional relationship between the second type of opening 322 and the third type of opening 52 is also not limited in this embodiment.

[0178] Furthermore, for different areas of the display panel 100, the second type of opening 322 and the fourth type of opening 53 may not overlap in some areas, while they may overlap in other areas. Alternatively, the second type of opening 322 and the fourth type of opening 53 may not overlap in any area of ​​the display panel 100.

[0179] In some alternative embodiments, in the region where the pixel circuit P is located, the fourth type of opening 53, projected onto the substrate 10, does not overlap with the second type of opening 322, and both the third type of opening 52 and the first type of opening 321 are located outside the region where the pixel circuit P is located. This design ensures that the pixel circuit P is covered by the conductor structure of at least one of the first conductor portion 31 and the second conductor portion 51 in the region where the pixel circuit P is located, thereby reducing the adverse effects of processes such as laser bonding on the pixel circuit P and improving the reliability of the pixel circuit P.

[0180] In some optional embodiments, the third type of opening 321 and the third type of opening 52 do not overlap in the region between adjacent pixel circuits P. This design allows at least a portion of the corresponding regions of the third type of opening 52 and the first type of opening 321 to be covered by the conductor structures in the first conductor portion 31 and the second conductor portion 51, respectively. This reduces the adverse effects of processes such as laser bonding on other film layer structures of the first metal layer 30 and the second metal layer 50 facing the substrate 10, thereby improving the yield and reliability of the display panel 100.

[0181] In some embodiments, the orthographic projection of a portion of the second type of opening 322 onto the substrate 10 is located between the orthographic projections of adjacent pixel circuits P onto the substrate 10, and the orthographic projections of a plurality of second type openings 322 onto the substrate 10 at least partially overlap with the orthographic projection of the same third type opening 52 onto the substrate 10; and / or, the orthographic projection of a portion of the fourth type of opening 53 onto the substrate 10 is located between the orthographic projections of adjacent pixel circuits P onto the substrate 10, and the orthographic projections of a plurality of fourth type openings 53 onto the substrate 10 at least partially overlap with the orthographic projection of the same first type opening 321 onto the substrate 10.

[0182] Taking the third type of opening 52 as an example, the third type of opening 52 is not set to correspond to the first type of opening 321, but to multiple second type of openings 322. Therefore, water vapor and other substances can move to the third type of opening 52 through multiple second type of openings 322 in sequence and be released from the third type of opening 52. This provides an exhaust path parallel to the thickness direction Z for gas release, reduces the difficulty of gas release, improves the exhaust reliability of the display panel 100, reduces the risk of bulging or peeling of some film layers, and improves the yield rate.

[0183] Furthermore, since the third type of opening 52 is a large-sized opening while the second type of opening 322 is a small-sized opening, the conductive structure between adjacent second type of openings 322 in the area where the third type of opening 52 is located can cover and protect the first metal layer 30 and other film layers of the second metal layer 50 facing the substrate 10. This reduces the adverse effects of processes such as laser bonding on the other film layer structures of the first metal layer 30 and the second metal layer 50 facing the substrate 10, thereby improving the yield of the display panel 100. The first type of opening 321 is similar, and will not be described again in this embodiment.

[0184] In summary, in this embodiment, by not overlapping the third type of opening 52 with the first type of opening 321, and overlapping the third type of opening 52 with multiple second type of openings 322, and overlapping the first type of opening 321 with multiple fourth type of openings 53, small-sized opening structures exist at the locations of the third type of opening 52 and the first type of opening 321 to improve the venting effect of the display panel 100, while conductive structures are also present to cover and protect the first metal layer 30 and other film layers of the second metal layer 50 facing the substrate 10. This helps to further improve the yield and reliability of the display panel 100.

[0185] In some embodiments, in the region between corresponding adjacent pixel circuits P, the orthographic projection of the second type of opening 322 on the substrate 10 at least partially overlaps with the orthographic projection of the fourth type of opening 53 on the substrate 10.

[0186] Considering that the area between adjacent pixel circuits P is a region where no pixel circuit P exists, even if there is an opening structure in the metal layer in this area, it is unlikely to have an adverse effect on the pixel circuit P. In view of this, in the embodiment of this application, the smaller second type opening 322 and the fourth type opening 53 can be at least partially overlapped in the area between adjacent pixel circuits P, thereby helping to improve the ventilation effect of the display panel 100 without affecting the performance of the pixel circuit P.

[0187] In some embodiments, such as Figure 1 As shown, the first conductor portion 31 includes a first sub-portion 311 and a second sub-portion 312 disposed adjacent to both sides of the first opening 32 along the first direction X. The first sub-portion 311 and the second sub-portion 312 transmit the same signal. The first direction X is parallel to the plane where the substrate 10 is located.

[0188] The first sub-part 311 and the second sub-part 312 are conductor structures located on different sides of the first opening 32 along the first direction X of the first conductor portion 31. The first sub-part 311 and the second sub-part 312 transmit the same signal, that is, they are both used to transmit the same potential voltage. The specific relationship between the first sub-part 311 and the second sub-part 312 is not limited in the embodiments of this application. Exemplarily, the first sub-part 311 and the second sub-part 312 can be integrally connected through other conductor structures within the first conductor portion 31, or they can be respectively connected to the same conductor structure in other film layers of the first metal layer 30 facing or away from the substrate 10, or they can be electrically connected through other conductor structures located within the first metal layer 30 to transmit the same signal.

[0189] In this embodiment, the first sub-part 311 and the second sub-part 312 in the first conductor portion 31 are respectively disposed on both sides of the first opening 32, and the first sub-part 311 and the second sub-part 312 transmit the same signal. This enables more conductor structures in the first conductor portion 31 to transmit the same signal, thereby increasing the size of the conductor structures in the first conductor portion 31 used to transmit the same signal, which helps to reduce the resistance and load of the first conductor portion 31 and improve the reliability of signal transmission.

[0190] In some embodiments, please refer to Figure 1 and Figure 16 The first sub-part 311 and the second sub-part 312 are connected as a single unit.

[0191] In this embodiment, the first sub-part 311 and the second sub-part 312 can be integrally connected by a connecting part 313. The connecting part 313 is a conductor structure in which the first conductor part 31 is disposed along the second direction Y on at least one side of the first opening 32, and the two ends of the connecting part 313 in the first direction X are respectively connected to the first sub-part 311 and the second sub-part 312. This design allows the first conductor part 31 to have a whole surface or block structure with the first opening 32, thereby helping to reduce the manufacturing difficulty of the first conductor part 31, reduce the resistance and load of the first conductor part 31, and improve the reliability of signal transmission.

[0192] In some embodiments, such as Figure 1 and Figure 16 As shown, the first metal layer 30 also includes a conductive portion 33 extending along the first direction X. The conductive portion 33 has its orthogonal projection on the substrate 10 located within the first opening 32, and the conductive portion 33 connects the first sub-part 311 and the second sub-part 312.

[0193] In addition to the first conductor portion 31, the first metal layer 30 also includes a conductive portion 33. The conductive portion 33 may be made of the same material as the first conductor portion 31, or it may be made of a different material than the first conductor portion 31. Further optionally, the first conductor portion 31 and the conductive portion 33 may be made of the same material and formed together in the same fabrication process.

[0194] In this embodiment, the conductive portion 33 is located within the first opening 32, and its two ends in the first direction X can be connected to the first sub-part 311 and the second sub-part 312, respectively. As described above, the first sub-part 311 and the second sub-part 312 are integrally connected. Furthermore, the presence of the conductive portion 33 further facilitates signal transmission between the first sub-part 311 and the second sub-part 312, and also further reduces the resistance and load of the first conductor portion 31, thereby improving the reliability of signal transmission.

[0195] In some embodiments, the pixel circuit P includes a pulse amplitude modulation circuit P2 and a pulse width modulation circuit P1. The pulse amplitude modulation circuit P2 is configured to control the amplitude of the drive current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit P1 is configured to control the pulse width of the drive current. The pulse width modulation circuit P1 includes a first power supply terminal for providing a first power supply voltage, and a first conductor portion 31 transmits the first power supply voltage PWM-vdd. The pulse amplitude modulation circuit P2 includes a second power supply terminal PWM-vdd for providing a second power supply voltage PAM-vdd, and the first conductor portion 31 transmits the second power supply voltage PAM-vdd.

[0196] The power supply voltage PVDD includes a first power supply voltage PWM-vdd and a second power supply voltage PAM-vdd. Further, depending on actual needs, the first conductor portion 31 within the first metal layer 30 can be used to transmit one of the first power supply voltage PWM-vdd and the second power supply voltage PAM-vdd. Of course, the first conductor portion 31 can include different conductor structures that are insulated from each other, and these different conductor structures are used respectively to transmit the first power supply voltage PWM-vdd and the second power supply voltage PAM-vdd.

[0197] In this embodiment of the application, for the specific circuit form of the pixel circuit P, in order to meet the light emission display requirements of the display panel 100, the first conductor portion 31 is configured to transmit at least one of the first power supply voltage PWM-vdd and the second power supply voltage PAM-vdd, thereby meeting the transmission requirements of the power supply voltage PVDD and realizing the light emission display function of the display panel 100.

[0198] Secondly, please refer to Figure 17 This application provides a display device 200, which includes the display panel in any of the foregoing embodiments.

[0199] It should be noted that the display device 200 provided in this application embodiment has the beneficial effects of the display panel in any of the foregoing embodiments. For details, please refer to the foregoing description of the beneficial effects of the display panel. This application embodiment will not repeat the description.

[0200] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit the invention. Any person skilled in the art to which this application pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

[0201] The above description is merely a specific embodiment of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, substitutions for other connection methods described above can be made by referring to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application.

Claims

1. A display panel, characterized in that, The display panel includes multiple pixel circuits, each pixel circuit including multiple transistors; the display panel also includes: Substrate; A first organic layer is disposed on one side of the substrate; A first metal layer is disposed on the side of the first organic layer opposite to the substrate. The first metal layer includes a first conductor portion, and the first conductor portion at least partially overlaps with the orthogonal projection of at least one transistor in the pixel circuit onto the substrate. The first conductor portion includes a first opening, and the orthographic projection of the first opening onto the substrate at least partially overlaps with the orthographic projection of the first organic layer onto the substrate. The first opening includes a second type of opening, which at least partially overlaps with the pixel circuit in a direction perpendicular to the plane of the display panel. The display panel further includes a second metal layer, which is disposed on the side of the first metal layer away from the substrate, or the second metal layer is located on the side of the first metal layer facing the substrate. The second metal layer includes a second conductor portion, which includes a fourth type of opening. The second conductor portion includes an insulating first pad and a second pad. The first pad includes an annular fourth type opening. The second pad is located within the annular fourth type opening. The second pad is connected to the pixel circuit. In a direction perpendicular to the plane of the display panel, the annular fourth type opening at least partially overlaps with the pixel circuit. The second type of opening does not overlap with the annular fourth type of opening.

2. The display panel according to claim 1, characterized in that, At least a portion of the orthographic projection of the first opening onto the substrate overlaps at least partially with the orthographic projection of the transistor in the pixel circuit onto the substrate; And / or, At least a portion of the first opening's orthogonal projection onto the substrate lies outside the orthogonal projection of each of the transistors in the pixel circuit onto the substrate.

3. The display panel according to claim 2, characterized in that, The plurality of first openings include a first type of opening and a second type of opening, wherein the size of the first type of opening is larger than the size of the second type of opening.

4. The display panel according to claim 3, characterized in that, In a direction perpendicular to the plane of the display panel, the first type of opening and the pixel circuit do not overlap; In a direction perpendicular to the plane of the display panel, at least a portion of the second type of opening overlaps with the pixel circuit.

5. The display panel according to claim 3, characterized in that, The first type of opening is located between the orthographic projections of the adjacent pixel circuits on the substrate.

6. The display panel according to claim 3, characterized in that, Multiple adjacent pixel circuits together form a repeating circuit group, and the multiple repeating circuit groups are repeatedly arranged; The adjacent repeating circuit groups are spaced apart to form a gap region, and the first type of opening is located within the gap region.

7. The display panel according to claim 3, characterized in that, It also includes a shift register unit, which is located between adjacent pixel circuits; The orthographic projection of the shift register unit on the substrate at least partially overlaps with the orthographic projection of the first type of opening on the substrate; and / or, the orthographic projection of the shift register unit on the substrate at least partially overlaps with the orthographic projection of the second type of opening on the substrate.

8. The display panel according to claim 1, characterized in that, The first organic layer includes venting holes, and the first opening at least partially overlaps with the orthographic projection of the venting holes onto the substrate.

9. The display panel according to claim 8, characterized in that, The orthographic projection of the vent hole onto the substrate is located within the orthographic projection of the first opening onto the substrate, and the orthographic projection area of ​​the vent hole onto the substrate is smaller than the orthographic projection area of ​​the first opening onto the substrate.

10. The display panel according to claim 8, characterized in that, It also includes a first insulating layer disposed on the side of the first metal layer opposite to the substrate, wherein a portion of the structure in the first insulating layer is located within the first opening and the vent hole.

11. The display panel according to claim 10, characterized in that, The first insulating layer is attached to the sidewall of the first conductor portion facing the first opening.

12. The display panel according to claim 8, characterized in that, It also includes a second insulating layer disposed between the first metal layer and the first organic layer, the second insulating layer including a second opening, the second opening being disposed overlapping the vent hole in the orthographic projection of the substrate.

13. The display panel according to claim 12, characterized in that, The second insulating layer comprises inorganic materials.

14. The display panel according to claim 1, characterized in that, The orthographic projection of the second conductor portion onto the substrate at least partially overlaps with the orthographic projection of at least a portion of the first opening onto the substrate.

15. The display panel according to claim 14, characterized in that, It also includes a first active layer disposed on the side of the second metal layer facing the substrate. The first active layer includes a first active structure, the first active structure includes a first exposed portion, the orthographic projection of the first exposed portion on the substrate is located within the first opening, and the orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the first exposed portion on the substrate.

16. The display panel according to claim 15, characterized in that, The display panel further includes a second active layer disposed between the second metal layer and the first metal layer. The second active layer includes a second active structure, and the orthographic projection of the second active structure onto the substrate is located outside the orthographic projection of the first opening onto the substrate.

17. The display panel according to claim 15, characterized in that, It also includes a second active layer disposed between the first metal layer and the first active layer. The second active layer includes a second active structure, the second active structure includes a second exposed portion, the orthographic projection of the second exposed portion on the substrate is located within the first opening, and the orthographic projection of the second conductor portion on the substrate and the orthographic projection of the second exposed portion on the substrate at least partially overlap.

18. The display panel according to claim 15, characterized in that, The first opening, which is at least partially overlapping the first active structure, and the second conductor portion, which is at least partially projected onto the substrate, are all among the plurality of first openings.

19. The display panel according to claim 1, characterized in that, The second conductor portion includes a third type of opening and a fourth type of opening, wherein the size of the third type of opening is larger than the size of the fourth type of opening.

20. The display panel according to claim 19, characterized in that, The pixel circuit includes a low power supply terminal and a high power supply terminal. The low power supply terminal provides a low-level power supply voltage, and the high power supply terminal provides a high-level power supply voltage. The first conductor portion is used to transmit the low-level power supply voltage or the high-level power supply voltage, and the second conductor portion is used to transmit the low-level power supply voltage or the high-level power supply voltage.

21. The display panel according to claim 20, characterized in that, The first conductor portion and the second conductor portion transmit different signals.

22. The display panel according to claim 21, characterized in that, The pixel circuit includes a pulse amplitude modulation circuit and a pulse width modulation circuit. The pulse amplitude modulation circuit is configured to control the amplitude of the drive current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit is configured to control the pulse width of the drive current. The pulse width modulation circuit includes a first power supply terminal, which is used to provide a first power supply voltage, and the first conductor portion transmits the first power supply voltage. The pulse amplitude modulation circuit includes a second power supply terminal for providing a second power supply voltage, and the second conductor portion transmits the second power supply voltage.

23. The display panel according to claim 19, characterized in that, The third type of opening does not overlap with the pixel circuit in a direction perpendicular to the plane from which the display panel is located.

24. The display panel according to claim 23, characterized in that, The third type of opening is located between the orthographic projections of the adjacent pixel circuits on the substrate.

25. The display panel according to claim 24, characterized in that, The second pad includes the fourth type of opening.

26. The display panel according to claim 25, characterized in that, The size of the fourth type opening of the first pad is larger than the size of the fourth type opening of the second pad.

27. The display panel according to claim 26, characterized in that, The third type of opening is disposed on the first pad and spaced apart from the annular fourth type of opening.

28. The display panel according to claim 19, characterized in that, The plurality of first openings includes a first type of opening and a second type of opening, wherein the size of the first type of opening is larger than the size of the second type of opening; In a direction perpendicular to the plane of the display panel, the first type of opening and the pixel circuit do not overlap; In a direction perpendicular to the plane of the display panel, at least a portion of the second type of opening overlaps with the pixel circuit; In a direction perpendicular to the plane of the display panel, at least a portion of the first type of opening and the third type of opening do not overlap.

29. The display panel according to claim 28, characterized in that, The orthographic projection of some of the second type openings on the substrate is located between the orthographic projections of adjacent pixel circuits on the substrate, and the orthographic projections of multiple second type openings on the substrate at least partially overlap with the orthographic projections of the same third type opening on the substrate. And / or, The orthographic projection of some of the fourth type of openings on the substrate is located between the orthographic projections of adjacent pixel circuits on the substrate, and the orthographic projections of multiple fourth type openings on the substrate at least partially overlap with the orthographic projections of the same first type of opening on the substrate.

30. The display panel according to claim 28, characterized in that, In the region between adjacent pixel circuits, the orthographic projection of the second type of opening on the substrate at least partially overlaps with the orthographic projection of the fourth type of opening on the substrate.

31. The display panel according to claim 1, characterized in that, The first conductor portion includes a first sub-portion and a second sub-portion disposed adjacent to each other on both sides of the first opening along a first direction. The first sub-portion and the second sub-portion transmit the same signal. The first direction is parallel to the plane of the substrate.

32. The display panel according to claim 31, characterized in that, The first sub-part and the second sub-part are connected and integrally formed.

33. The display panel according to claim 32, characterized in that, The first metal layer further includes a conductive portion extending along the first direction, wherein the orthographic projection of the conductive portion onto the substrate is located within the first opening, and the conductive portion connects the first sub-part and the second sub-part.

34. The display panel according to claim 1, characterized in that, The pixel circuit includes a pulse amplitude modulation circuit and a pulse width modulation circuit. The pulse amplitude modulation circuit is configured to control the amplitude of the drive current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit is configured to control the pulse width of the drive current. The pulse width modulation circuit includes a first power supply terminal for providing a first power supply voltage, and a first conductor portion for transmitting the first power supply voltage. Alternatively, the pulse amplitude modulation circuit includes a second power supply terminal for providing a second power supply voltage, and a first conductor portion for transmitting the second power supply voltage.

35. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 34.

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