Power device series connection voltage-sharing modulation circuit and method

Abstract

The invention discloses a power device series connection voltage-sharing modulation circuit and method, the circuit comprises a plurality of power devices connected in series, the power side of each power device is provided with a buffer voltage-sharing circuit and / or the driving side of each power device is provided with a clamping voltage-sharing circuit. The buffer voltage-sharing circuit comprises a capacitor C1, a diode D3 and a coupling inductor with at least two windings, the positive electrode of the diode D3 is connected with the drain electrode of the power device, the negative electrode of the diode D3 is connected with the first end of the capacitor C1, and the second end of the capacitor C1 is connected with the source electrode of the power device; the clamping voltage-sharing circuit comprises a capacitor C3, a first backward diode and a second backward diode, the positive electrode of the first backward diode is connected with the grid electrode of the power device through a resistor, and the negative electrode of the first backward diode is connected with the first end of the capacitor C3 and the positive electrode of the second backward diode. The negative electrode of the second backward diode and the second end of the capacitor C3 are connected with the negative electrode of a diode D5. The positive electrode of the diode D5 is connected with the drain electrode of the power device.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a power device series connected voltage-sharing modulation circuit and method. Background Art

[0002] As the core power device of power conversion, high voltage, high current and low loss have always been the core requirements. Compared with silicon semiconductors, silicon carbide has excellent physical properties such as high breakdown field strength and high thermal conductivity, which is very suitable for manufacturing high-voltage and high-power devices. Although silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) is highly expected in high-voltage and high-power applications, the highest voltage level of commercial power devices is 1700V, which is still a certain gap from the device withstand voltage of insulated gate bipolar transistor (IGBT) with a maximum of 6.5kV. In order to solve the problem of insufficient withstand voltage of a single SiC MOSFET power device, the most direct idea is to operate SiC MOSFET in series. However, when the SiC MOSFET is in series operation, due to the possible inconsistency of the internal parameters of each SiC MOSFET and the nonlinear changes of the internal parameters under the influence of the peripheral circuit, it is difficult for the devices in series to maintain a consistent switching speed during the switching process. Devices that are turned on first or turned off last tend to withstand higher voltages than other devices, resulting in overvoltage breakdown and poor safety. Therefore, ensuring balanced voltage division between series-connected SiC MOSFET devices is the key to SiC MOSFET series connection technology. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a power device series voltage equalization modulation circuit and method, which can effectively ensure the safe and stable operation of the series-connected SiC MOSFET power devices.

[0004] The technical solution of the present invention is implemented as follows: the present invention discloses a power device series voltage-equalizing modulation circuit, comprising a plurality of power devices connected in series, a buffer voltage-equalizing circuit is provided on the power side of each power device and / or a clamp voltage-equalizing circuit is provided on the driving side of each power device, the buffer voltage-equalizing circuit comprises a capacitor C1, a diode D3 and a coupled inductor with at least two windings, the positive electrode of the diode D3 is connected to the drain of the power device, the negative electrode of the diode D3 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 is connected to the source of the power device;

[0005] The clamping voltage equalizing circuit includes a capacitor C3, a first reverse diode and a second reverse diode. The positive electrode of the first reverse diode is directly or through a resistor R g2 The cathode of the first reverse diode is connected to the first end of the capacitor C3 and the anode of the second reverse diode respectively; the cathode of the second reverse diode and the second end of the capacitor C3 are both connected to the cathode of the diode D5; and the anode of the diode D5 is connected to the drain of the power device.

[0006] Furthermore, the buffer voltage balancing circuit further includes a coupling inductor, wherein the first winding of the coupling inductor is connected in series with the capacitor C1, and the second winding of the coupling inductor is connected in series with the resistor R g1 In parallel, resistor R g1 The first end is used to receive the driving signal of the power device, and the resistor R g1 The second end is directly or through a resistor R g2 Connect to the gate of the power device.

[0007] Furthermore, the first end of the first winding of the coupled inductor is connected to the second end of the capacitor C1 , and the second end of the first winding of the coupled inductor is connected to the source of the power device.

[0008] Furthermore, after the plurality of power devices are connected in series, the first ends are connected to the positive pole of the DC bus, and the second ends are connected to the negative pole of the DC bus.

[0009] When there are N power devices connected in series, along the current direction of the series loop of the power devices, the third winding is provided on the coupled inductors corresponding to the first power device and the Nth power device, the third winding and the fourth winding are provided on the coupled inductors corresponding to the second power device to the N-1th power device, the third winding of the coupled inductor corresponding to the first power device is connected in parallel with the third winding of the coupled inductor corresponding to the second power device, the fourth winding of the coupled inductor corresponding to the second power device is connected in series with the fourth winding of the coupled inductor corresponding to the third power device, the third winding of the coupled inductor corresponding to the third power device is connected in parallel with the third winding of the coupled inductor corresponding to the fourth power device, and so on, until the third winding of the coupled inductor corresponding to the N-1th power device is connected in parallel with the third winding of the coupled inductor corresponding to the Nth power device;

[0010] or,

[0011] Each coupled inductor is provided with a third winding, and the third windings of the multiple coupled inductors corresponding to the multiple series-connected power devices are connected in parallel;

[0012] or,

[0013] A third winding is provided on each coupled inductor. Along the current direction of the series loop of the power devices, the third winding of the coupled inductor corresponding to the first power device is connected in series with the first winding of the coupled inductor corresponding to the second power device, the first winding of the coupled inductor corresponding to the first power device is connected in series with the third winding of the coupled inductor corresponding to the second power device, and so on, until the third winding of the coupled inductor corresponding to the N-1th power device is connected in series with the first winding of the coupled inductor corresponding to the Nth power device, and the first winding of the coupled inductor corresponding to the N-1th power device is connected in series with the third winding of the coupled inductor corresponding to the Nth power device.

[0014] Furthermore, the voltage preset value of capacitor C1 is set to 105% Vq. When the voltage across the power device is greater than 105% Vq, diode D3 is turned on, and the bus charges capacitor C1 to slow down the rise speed of the drain-source voltage of the power device. Vq is the expected voltage value of the power device.

[0015] When the bus charges capacitor C1, a charging current i s1 , the current i is induced by the coupled inductor p1 , the induced current passes through the driving resistor R g2 Inject current into the gate of the power device to slow down the shutdown speed of the power device.

[0016] Furthermore, the buffer voltage-equalizing circuit further includes a switch tube S1 , a source of the switch tube S1 is connected to the anode of the diode D3 , and a drain of the switch tube S1 is connected to the cathode of the diode D3 .

[0017] Furthermore, the power device series voltage-balanced modulation circuit of the present invention further includes a capacitor energy return control circuit and a second voltage sampling circuit for detecting the voltage across the capacitor C1 and a current sampling circuit for detecting the current in the power device series loop, the capacitor energy return control circuit includes a drive circuit and a first comparator and a second comparator, the positive input terminal of the first comparator receives a reference voltage, the negative input terminal of the first comparator is connected to the output terminal of the second voltage sampling circuit, and the output terminal of the first comparator is connected to the first input terminal of the AND gate;

[0018] The positive input terminal of the second comparator receives the reference current, the negative input terminal of the second comparator is connected to the output terminal of the current sampling circuit, the output terminal of the second comparator is connected to the input terminal of the NOT gate, the output terminal of the NOT gate is connected to the second input terminal of the AND gate, the output terminal of the AND gate is connected to the input terminal of the drive circuit, and the output terminal of the drive circuit is connected to the gate of the switch tube S1.

[0019] Furthermore, the conduction time of the switch tube S1 is set to The conduction time is arranged within the dead time before the power device is turned on, so that at the dead time before the MOS tube is turned on, the energy stored in the capacitor C1 is released to the power supply through the switch tube S1 to the preset voltage value of the capacitor C1; U j is the reference voltage, R refers to the total resistance of the buffer voltage equalization circuit, C refers to the capacitance of capacitor C1, and U C Refers to the voltage V across capacitor C1 C1 ;

[0020] The reference voltage is a preset voltage value of the capacitor C1; the reference current is 0.

[0021] Furthermore, the power device series voltage-equalizing modulation circuit of the present invention also includes a control module and a first voltage sampling circuit for detecting the voltage across each power device. The output end of the first voltage sampling circuit is connected to the input end of the control module. The control module is used to receive the voltage output by the first voltage sampling circuit to obtain the voltage across each power device. An intelligent model is provided in the control module. The intelligent model is used to receive the voltage across multiple power devices, output a corresponding drive signal delay or a drive signal voltage modulation signal and superimpose it on the original drive signal of each power device to form a new drive signal for driving each power device.

[0022] Furthermore, the first voltage sampling circuit includes a first voltage sensor, a resistor R j1 and resistor R c1 , resistor R j1 The first end is connected to the drain of the power device, and the resistor R j1 The second end of the resistor R c1 The first end of the resistor R c1 The second end of is connected to the source of the power device, and the first voltage sensor is used to collect the resistance R c1 The voltage across both ends.

[0023] Furthermore, the clamping voltage equalizing circuit further includes a resistor R1, and the resistor R1 is connected in parallel with the capacitor C3.

[0024] The present invention discloses a method for modulating power device series voltage sharing, comprising the following steps:

[0025] Obtain the expected voltage value of each power device;

[0026] Sample the actual voltage value across each power device and calculate the voltage imbalance corresponding to each power device;

[0027] When the voltage imbalance corresponding to the power device is greater than the set value, a series voltage equalization modulation step is performed, specifically including: obtaining the voltage across each power device;

[0028] The voltage across each power device is input into the intelligent model, and the intelligent model outputs a corresponding driving signal delay or driving signal voltage modulation signal which is superimposed on the original driving signal of each power device to form a new driving signal for driving each power device.

[0029] Furthermore, the voltage imbalance Where V s (n) is the actual measured value across the nth power device, V q is the expected voltage value of the power device, V q =U / n, where n is the number of power devices in series and U is the total voltage that the devices in series are subjected to;

[0030] Set the on-time of the snubber circuit reflux switch The conduction time is arranged within the dead time before the power device is turned on. This process is to release the energy stored in capacitor C1 (C2) to the power supply through switch tube S1 (S2) at the dead time before the MOS tube is turned on, and the release voltage is 105% Vq.

[0031] Compared with the prior art, the present invention has the following beneficial effects: the power device series voltage-equalizing modulation method of the present invention is mainly divided into two parts: power side voltage-equalizing modulation and drive side voltage-equalizing modulation. The power side voltage-equalizing modulation controls the dynamic voltage-equalizing of the series power devices through a buffer circuit composed of a switch tube, a diode, a capacitor, and a coupled inductor; the drive side voltage-equalizing modulation first uses a clamp composed of a reverse diode and a capacitor to dynamically adjust dv / dt. Secondly, the present invention also obtains the voltage value at both ends of each power device, and modulates the driving signal of each power device through a deep reinforcement learning algorithm, thereby realizing the dynamic voltage-equalizing of the power device. In addition, the premise for the circuit to undergo series voltage-equalizing modulation is that the voltage imbalance η is greater than the set value (such as 5%). The patented method effectively solves the problem of unbalanced voltage division of series power devices, realizes dynamic balance during the operation of each power device, effectively ensures the safe and stable operation of the series-connected SiC MOSFET power devices, and lays the foundation for low-voltage devices to build medium- and high-voltage high-power converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A flow chart of a method for voltage-sharing modulation of power devices in series connection provided by an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of a power device series voltage-sharing modulation circuit provided by a first embodiment of the present invention;

[0034] Figure 3 A schematic diagram of a power device series voltage-sharing modulation circuit provided by a second embodiment of the present invention;

[0035] Figure 4A schematic diagram of a power device series voltage-sharing modulation circuit provided by a third embodiment of the present invention;

[0036] Figure 5 A control schematic diagram of a closed-loop control pressure balancing method for the driving side provided by an embodiment of the present invention;

[0037] Figure 6 A schematic diagram of a capacitor energy return control circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Embodiment 1

[0040] See also Figures 1 to 6 , the embodiment of the present invention discloses a power device series voltage-equalizing modulation circuit, comprising a plurality of power devices connected in series, a buffer voltage-equalizing circuit is provided on the power side of each power device and / or a clamp voltage-equalizing circuit is provided on the driving side of each power device, the buffer voltage-equalizing circuit comprises a capacitor C1, a diode D3 and a coupled inductor with at least two windings, the positive electrode of the diode D3 is connected to the drain of the power device, the negative electrode of the diode D3 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 is connected to the source of the power device;

[0041] The clamping voltage equalizing circuit includes a capacitor C3, a first reverse diode and a second reverse diode. The positive electrode of the first reverse diode is directly or through a resistor R g2 The cathode of the first reverse diode is connected to the first end of the capacitor C3 and the anode of the second reverse diode respectively; the cathode of the second reverse diode and the second end of the capacitor C3 are both connected to the cathode of the diode D5; and the anode of the diode D5 is connected to the drain of the power device.

[0042] The power device of an embodiment is a SiC MOSFET power device.

[0043] The power device series voltage-sharing modulation circuit of the present invention further comprises a coupling inductor, wherein the first winding of the coupling inductor is connected in series with the capacitor C1, and the second winding of the coupling inductor is connected in series with the resistor R g1 In parallel, resistor R g1 The first end is used to receive the driving signal of the power device, and the resistor R g1 The second end is directly or through a resistor Rg2 Connect to the gate of the power device.

[0044] The first end of the first winding of the coupled inductor in this embodiment is connected to the second end of the capacitor C1 , and the second end of the first winding of the coupled inductor is connected to the source of the power device.

[0045] After multiple power devices are connected in series, the first end is connected to the positive pole of the DC bus, and the second end is connected to the negative pole of the DC bus. The preset voltage value of capacitor C1 is set to 105% Vq. When the voltage across the power device is greater than 105% Vq, diode D3 is turned on, and the bus charges capacitor C1 to slow down the rising speed of the drain-source voltage of the power device.

[0046] When the bus charges capacitor C1, a charging current i s1 , the current i is induced by the coupled inductor p1 , the induced current passes through the driving resistor R g2 Inject current into the gate of the power device to slow down the shutdown speed of the power device.

[0047] Furthermore, the buffer voltage-equalizing circuit further includes a switch tube S1 , a source of the switch tube S1 is connected to the anode of the diode D3 , and a drain of the switch tube S1 is connected to the cathode of the diode D3 .

[0048] Furthermore, the power device series voltage-balanced modulation circuit of the present invention further includes a capacitor energy return control circuit and a second voltage sampling circuit for detecting the voltage across the capacitor C1 and a current sampling circuit for detecting the current in the power device series loop, the capacitor energy return control circuit includes a drive circuit and a first comparator and a second comparator, the positive input terminal of the first comparator receives a reference voltage, the negative input terminal of the first comparator is connected to the output terminal of the second voltage sampling circuit, and the output terminal of the first comparator is connected to the first input terminal of the AND gate;

[0049] The positive input terminal of the second comparator receives the reference current, the negative input terminal of the second comparator is connected to the output terminal of the current sampling circuit, the output terminal of the second comparator is connected to the input terminal of the NOT gate, the output terminal of the NOT gate is connected to the second input terminal of the AND gate, the output terminal of the AND gate is connected to the input terminal of the drive circuit, and the output terminal of the drive circuit is connected to the gate of the switch tube S1.

[0050] Furthermore, the conduction time of the switch tube S1 is set to The conduction time is arranged within the dead time before the power device is turned on, so that at the dead time before the MOS tube is turned on, the energy stored in the capacitor C1 is released to the power supply through the switch tube S1 to the preset voltage value of the capacitor C1. jis the reference voltage, R refers to the total resistance of the buffer voltage equalization circuit (the total resistance of the buffer circuit loop (including S1, C1, D3 and the first winding of the coupled inductor)), C refers to the capacitance of capacitor C1, and U C Refers to the voltage V across capacitor C1 C1 .

[0051] Furthermore, the reference voltage is a preset voltage value of the capacitor C1.

[0052] When U j When Vq is 105%,

[0053] Furthermore, the reference current is zero.

[0054] Furthermore, the power device series voltage-equalizing modulation circuit of the present invention also includes a control module and a first voltage sampling circuit for detecting the voltage across each power device. The output end of the first voltage sampling circuit is connected to the input end of the control module. The control module is used to receive the voltage output by the first voltage sampling circuit to obtain the voltage across each power device. An intelligent model is provided in the control module. The intelligent model is used to receive the voltage across multiple power devices, output a corresponding drive signal delay or a drive signal voltage modulation signal and superimpose it on the original drive signal of each power device to form a new drive signal for driving each power device.

[0055] Furthermore, the first voltage sampling circuit includes a first voltage sensor, a resistor R j1 and resistor R c1 , resistor R j1 The first end is connected to the drain of the power device, and the resistor R j1 The second end of the resistor R c1 The first end of the resistor R c1 The second end of is connected to the source of the power device, and the first voltage sensor is used to collect the resistance R c1 The voltage across both ends.

[0056] Furthermore, the clamping voltage equalizing circuit further includes a resistor R1, and the resistor R1 is connected in parallel with the capacitor C3.

[0057] Embodiment 2

[0058] Based on Example 1, see Figure 2When there are N power devices connected in series, along the current direction of the power device series loop, the third winding is provided on the coupled inductors corresponding to the first power device and the Nth power device, and the third winding and the fourth winding are provided on the coupled inductors corresponding to the second power device to the N-1th power device. The third winding of the coupled inductor corresponding to the first power device is connected in parallel with the third winding of the coupled inductor corresponding to the second power device, the fourth winding of the coupled inductor corresponding to the second power device is connected in series with the fourth winding of the coupled inductor corresponding to the third power device, the third winding of the coupled inductor corresponding to the third power device is connected in parallel with the third winding of the coupled inductor corresponding to the fourth power device, and so on, until the third winding of the coupled inductor corresponding to the N-1th power device is connected in parallel with the third winding of the coupled inductor corresponding to the Nth power device.

[0059] In one embodiment, N is 4.

[0060] Embodiment 3

[0061] Based on Example 1, see Figure 3 Each coupled inductor is provided with a third winding, and the third windings of the multiple coupled inductors corresponding to the multiple series-connected power devices are connected in parallel.

[0062] Embodiment 4

[0063] Based on Example 1, see Figure 4 , each coupled inductor is provided with a third winding. Along the current direction of the series loop of the power devices, the third winding of the coupled inductor corresponding to the first power device is connected in series with the first winding of the coupled inductor corresponding to the second power device, the first winding of the coupled inductor corresponding to the first power device is connected in series with the third winding of the coupled inductor corresponding to the second power device, and so on, until the third winding of the coupled inductor corresponding to the N-1th power device is connected in series with the first winding of the coupled inductor corresponding to the Nth power device, and the first winding of the coupled inductor corresponding to the N-1th power device is connected in series with the third winding of the coupled inductor corresponding to the Nth power device.

[0064] In one embodiment, N is 2.

[0065] Embodiment 5

[0066] See also Figures 1 to 6 The embodiment of the present invention discloses a method for modulating voltage sharing of power devices in series, comprising the following steps:

[0067] Calculate the expected voltage value of each power device;

[0068] Sample the actual voltage value across each power device and calculate the voltage imbalance corresponding to each power device;

[0069] When the voltage imbalance corresponding to the power device is greater than a set value (the set value is set as required, such as 5%), a series voltage equalization modulation step is performed to control the dynamic voltage equalization of the power device.

[0070] The power device of an embodiment is a SiC MOSFET power device.

[0071] The series voltage-sharing modulation step is performed, specifically including: obtaining the voltage across each power device;

[0072] The voltage across each power device is input into the intelligent model, and the intelligent model outputs a corresponding driving signal delay or driving signal voltage modulation signal which is superimposed on the original driving signal of each power device to form a new driving signal for driving each power device.

[0073] Furthermore, the voltage imbalance Among them, V s (n) is the actual measured value across the nth power device, V q is the expected voltage value of the power device, V q =U / n, where n is the number of power devices in series and U is the total voltage that the series devices are subjected to.

[0074] See also Figure 4 , the principle of power side buffering and voltage balancing is as follows:

[0075] Set the capacitor of the buffer voltage equalization circuit (such as Figure 4 The preset voltage value of C1 and C2 in the buffer voltage equalization circuit is 105% Vq. When the voltage across the power device is greater than 105% Vq, the diode of the buffer voltage equalization circuit (such as Figure 2 D3 and D4 in the buffer voltage balancing circuit are turned on, and the busbar supplies the buffer voltage balancing circuit (such as Figure 4 C1, C2) charging, slowing down the power devices (such as Figure 4 The drain-source voltage rise rate of MOS1 and MOS2 in the circuit.

[0076] Design the coupled inductor parameters. When the bus provides the capacitor of the buffer voltage-sharing circuit (such as Figure 4 When C1 and C2 in the circuit are charged, a charging current (such as Figure 4 i s1 、i s2 ), and the current is induced by the coupled inductor (such as Figure 4 i p1 、i p2 ), the induced current passes through the driving resistor (such as Figure 4 R g2 , R g4 ) to power devices (such as Figure 2 The gate injection current of MOS1 and MOS2 in the circuit slows down the power devices (such as Figure 2 The turn-off speed of MOS1 and MOS2 in the circuit.

[0077] Set up a buffer voltage balancing circuit with a reflux switch device, i.e., a switch tube (such as Figure 4 The conduction time of S1 and S2 in The conduction time is arranged within the dead time before the power device is turned on. This process is to increase the capacitor (such as Figure 4 The energy stored in C1 and C2 in the circuit is passed through the switch tube (such as Figure 4 S1, S2 in the circuit) to release the voltage to the power supply, and release the voltage to the capacitor of the buffer voltage balancing circuit (such as Figure 4 The preset value of the voltage of C1 and C2 is 105% Vq.

[0078] See also Figure 2 , the principle of clamping and equalizing voltage on the driving side is as follows:

[0079] Design the first reverse diode of the clamping voltage equalization circuit (such as Figure 4 Z1, Z3) and the second reverse diode (such as Figure 4 The reverse voltages of Z2 and Z4 in the figure are respectively the first preset value (105% V q ) and the second preset value (130%V q ).

[0080] When the voltage across the two ends of the power device, ie, the MOS tube (ie, the drain-source voltage), is higher than the first preset value (105% V q ), the first reverse diode (such as Figure 4 Z1 and Z3 in the circuit are turned on, and the capacitor of the voltage-equalizing circuit (such as Figure 4 C3 and C4 in the circuit are connected in parallel to the drain and gate of the power device, i.e., the MOS tube, so that the drain and gate equivalent capacitance of the power device, i.e., the MOS tube, increases and dv / dt decreases. The slope of dv / dt can be changed by changing the capacitance value.

[0081] When the voltage across the two ends of the power device, ie, the MOS tube (ie, the drain-source voltage), is higher than the second preset value (130% V q ), the first reverse diode and the second reverse diode are turned on at the same time, such as Z1 and Z2 are turned on at the same time or / and Z3 and Z4 are turned on at the same time, and current is injected into the gate of the corresponding power device, i.e., the MOS tube, to slow down the shutdown speed of the power device, i.e., the MOS tube.

[0082] The principle of closed-loop control pressure balancing on the drive side is as follows:

[0083] like Figure 4 As shown, R c1 , R c2 The voltages at both ends are V1 and V2, and we can calculate

[0084] V s (MOS1), V s Substitute (MOS2) into the intelligent agent, i.e., the intelligent model, established by the deep reinforcement learning algorithm to find out the states of the driving signal actions of the switch tubes MOS1 and MOS2 (which may be driving signal delay or driving signal voltage adjustment).

[0085] The power device series voltage-equalizing modulation method of the present invention is mainly divided into two parts: power-side voltage-equalizing modulation and drive-side voltage-equalizing modulation. The power-side voltage-equalizing modulation controls the dynamic voltage-equalizing of the series power devices through a buffer circuit composed of a switch tube, a diode, a capacitor, and a coupled inductor; the drive-side voltage-equalizing modulation first uses a clamp composed of a reverse diode and a capacitor to dynamically adjust dv / dt. Secondly, the present invention also obtains the voltage value at both ends of each power device, and modulates the driving signal of each power device through a deep reinforcement learning algorithm, thereby realizing dynamic voltage-equalizing of the power device. In addition, the premise for the circuit to undergo series voltage-equalizing modulation is that the voltage imbalance η is greater than the set value (such as 5%). This patented method effectively solves the problem of unbalanced voltage division of series power devices, realizes dynamic balance during the operation of each power device, effectively ensures the safe and stable operation of the series-connected SiC MOSFET power devices, and lays the foundation for low-voltage devices to build medium- and high-voltage high-power converters.

[0086] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A power device series voltage-balanced modulation circuit, characterized in that : comprising a plurality of power devices connected in series, a buffer voltage-equalizing circuit is provided on the power side of each power device and / or a clamp voltage-equalizing circuit is provided on the driving side of each power device, the buffer voltage-equalizing circuit comprises a capacitor C1, a diode D3 and a coupled inductor with at least two windings, the positive electrode of the diode D3 is connected to the drain of the power device, the negative electrode of the diode D3 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 is connected to the source of the power device; The clamping voltage equalizing circuit includes a capacitor C3, a first reverse diode and a second reverse diode. The positive electrode of the first reverse diode is directly or through a resistor R g2 The cathode of the first reverse diode is connected to the first end of the capacitor C3 and the anode of the second reverse diode respectively; the cathode of the second reverse diode and the second end of the capacitor C3 are both connected to the cathode of the diode D5; and the anode of the diode D5 is connected to the drain of the power device.

2. The power device series voltage-sharing modulation circuit according to claim 1, characterized in that: The buffer voltage balancing circuit also includes a coupling inductor, wherein the first winding of the coupling inductor is connected in series with the capacitor C1, and the second winding of the coupling inductor is connected in series with the resistor R g1 In parallel, resistor R g1 The first end is used to receive the driving signal of the power device, and the resistor R g1 The second end is directly or through a resistor R g2 Connect to the gate of the power device.

3. The power device series voltage-sharing modulation circuit according to claim 2, characterized in that: When there are N power devices connected in series, along the current direction of the series loop of the power devices, the third winding is provided on the coupled inductors corresponding to the first power device and the Nth power device, the third winding and the fourth winding are provided on the coupled inductors corresponding to the second power device to the N-1th power device, the third winding of the coupled inductor corresponding to the first power device is connected in parallel with the third winding of the coupled inductor corresponding to the second power device, the fourth winding of the coupled inductor corresponding to the second power device is connected in series with the fourth winding of the coupled inductor corresponding to the third power device, the third winding of the coupled inductor corresponding to the third power device is connected in parallel with the third winding of the coupled inductor corresponding to the fourth power device, and so on, until the third winding of the coupled inductor corresponding to the N-1th power device is connected in parallel with the third winding of the coupled inductor corresponding to the Nth power device; or, Each coupled inductor is provided with a third winding, and the third windings of the multiple coupled inductors corresponding to the multiple series-connected power devices are connected in parallel; or, A third winding is provided on each coupled inductor. Along the current direction of the series loop of the power devices, the third winding of the coupled inductor corresponding to the first power device is connected in series with the first winding of the coupled inductor corresponding to the second power device, the first winding of the coupled inductor corresponding to the first power device is connected in series with the third winding of the coupled inductor corresponding to the second power device, and so on, until the third winding of the coupled inductor corresponding to the N-1th power device is connected in series with the first winding of the coupled inductor corresponding to the Nth power device, and the first winding of the coupled inductor corresponding to the N-1th power device is connected in series with the third winding of the coupled inductor corresponding to the Nth power device.

4. The power device series voltage-sharing modulation circuit according to claim 1, 2 or 3, characterized in that: The buffer voltage-sharing circuit further includes a switch tube S1 , a source of the switch tube S1 is connected to the anode of the diode D3 , and a drain of the switch tube S1 is connected to the cathode of the diode D3 .

5. The power device series voltage-sharing modulation circuit according to claim 4, characterized in that: It also includes a capacitor energy return control circuit and a second voltage sampling circuit for detecting the voltage across the capacitor C1 and a current sampling circuit for detecting the current in the series loop of the power device. The capacitor energy return control circuit includes a drive circuit and a first comparator and a second comparator. The positive input terminal of the first comparator receives a reference voltage, the negative input terminal of the first comparator is connected to the output terminal of the second voltage sampling circuit, and the output terminal of the first comparator is connected to the first input terminal of the AND gate; The positive input terminal of the second comparator receives the reference current, the negative input terminal of the second comparator is connected to the output terminal of the current sampling circuit, the output terminal of the second comparator is connected to the input terminal of the NOT gate, the output terminal of the NOT gate is connected to the second input terminal of the AND gate, the output terminal of the AND gate is connected to the input terminal of the drive circuit, and the output terminal of the drive circuit is connected to the gate of the switch tube S1.

6. The power device series voltage-sharing modulation circuit according to claim 3, characterized in that: The conduction time of the switch tube S1 is set to The conduction time is arranged within the dead time before the power device is turned on, so that at the dead time before the MOS tube is turned on, the energy stored in the capacitor C1 is released to the power supply through the switch tube S1 to the preset voltage value of the capacitor C1, U j is the reference voltage, R refers to the total resistance of the buffer voltage equalization circuit, C refers to the capacitance of capacitor C1, and U C Refers to the voltage V across capacitor C1 C1 ; The reference voltage is a preset voltage value of the capacitor C1; the reference current is 0.

7. The power device series voltage-sharing modulation circuit according to claim 1, characterized in that: It also includes a control module and a first voltage sampling circuit for detecting the voltage across each power device. The output end of the first voltage sampling circuit is connected to the input end of the control module. The control module is used to receive the voltage output by the first voltage sampling circuit to obtain the voltage across each power device. An intelligent model is provided in the control module. The intelligent model is used to receive the voltage across multiple power devices, output a corresponding drive signal delay or a drive signal voltage modulation signal and superimpose it on the original drive signal of each power device to form a new drive signal for driving each power device.

8. The power device series voltage-sharing modulation circuit according to claim 1, characterized in that: The clamping voltage equalizing circuit further includes a resistor R1, and the resistor R1 is connected in parallel with the capacitor C3.

9. A method for modulating voltage sharing in series with power devices, characterized in that : Includes the following steps: Obtain the expected voltage value of each power device; Sample the actual voltage value across each power device and calculate the voltage imbalance corresponding to each power device; When the voltage imbalance corresponding to the power device is greater than the set value, a series voltage equalization modulation step is performed, specifically including: obtaining the voltage across each power device; The voltage across each power device is input into the intelligent model, and the intelligent model outputs a corresponding driving signal delay or driving signal voltage modulation signal which is superimposed on the original driving signal of each power device to form a new driving signal for driving each power device.

10. The method for voltage-sharing modulation of power devices in series according to claim 9, characterized in that: Voltage unbalance Where V s (n) is the actual measured value across the nth power device, V q is the expected voltage value of the power device, V q =U / n, where n is the number of power devices in series and U is the total voltage that the series devices are subjected to.

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