Semiconductor device

Abstract

The invention relates to a semiconductor device. A field plate electrode FP and a gate electrode GE are formed in the plurality of trenches TR1. The peripheral trench TR2 surrounds the plurality of trenches TR1 in a plan view. A field plate electrode FP (lead-out portion FPa) is formed in the peripheral trench TR2. The peripheral trench TR2 has an extension portion TR2a extending in the Y direction, an extension portion TR2b extending in the X direction, and a corner portion TR2c extending in a direction different from the X and Y directions in a plan view and connecting the extension portion TR2a and the extension portion TR2b. In the Y direction, the distance L2 between the extension TR2b and the end 10 of the trench TR1 closest to the extension TR2a is longer than the distance L3 between the extension TR2b and the end 10 of the other trench TR1.

Description

Technical Field

[0001] The disclosure of Japanese Patent Application No. 2023-113605 filed on July 11, 2023 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Background Art

[0002] The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices including a gate electrode and a field plate electrode within a trench.

[0003] In a semiconductor device including a semiconductor element such as a power MOSFET (metal oxide semiconductor field effect transistor), a trench gate structure is applied in which a gate electrode is embedded in a trench. As a type of trench gate structure, a split gate structure has been developed in which a field plate electrode is formed at the lower portion of the trench and a gate electrode is formed at the upper portion of the trench. The source potential is supplied to the field plate electrode from the source electrode. By extending the depletion layer in the drift region using the field plate electrode, the concentration of the drift region can be increased and the resistance of the drift region can be reduced.

[0004] In addition, the periphery of the semiconductor device is configured to improve the withstand voltage. For example, in Patent Document 1, a peripheral trench is formed to surround a cell region in which a plurality of MOSFETs are formed. A field plate electrode is also formed in the peripheral trench.

[0005] One publicly available technique is listed below.

[0006] [Patent Document 1] Japanese Laid-Open Patent Application No. 2021-82770 Summary of the invention

[0007] The peripheral trench extends in the X direction and the Y direction in a plan view to surround the cell region. However, in the corner where the peripheral trench in the X direction and the peripheral trench in the Y direction intersect each other, the depletion layer extending from both the X direction and the Y direction in the cell region and the depletion layer extending from the end of the trench tend to overlap each other locally, compared with the plane portion of the peripheral trenches that are independent in the X direction and the Y direction, respectively. Therefore, the charge balance is biased, and phenomena such as partial depletion or electric field concentration may occur. That is, there is a problem that the breakdown voltage may be reduced near the corner.

[0008] The main purpose of the present application is to increase the breakdown voltage around the peripheral trench by reducing the overlap of the depletion layer around the corner where the peripheral trench in the X direction and the peripheral trench in the Y direction intersect, thereby stabilizing the breakdown voltage of the semiconductor device.

[0009] Other objects and novel features will become clear from the description of this specification and the accompanying drawings. A typical embodiment among the embodiments disclosed in this application will be briefly described below.

[0010] A semiconductor device according to an embodiment includes: a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a plurality of trenches formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate to the lower surface of the semiconductor substrate, the plurality of trenches extending in a first direction in a plan view and adjacent to each other in a second direction orthogonal to the first direction in a plan view; a plurality of first field plate electrodes respectively formed in the plurality of trenches and electrically insulated from the semiconductor substrate; a plurality of first gate electrodes respectively formed above the plurality of first field plate electrodes and electrically insulated from the semiconductor substrate and the plurality of field plate electrodes; a peripheral trench formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, the peripheral trench extending in the first direction and the second direction to surround the plurality of trenches in a plan view; and a second field plate electrode formed in the peripheral trench and electrically insulated from the semiconductor substrate. The peripheral trench includes: a first extension extending in the first direction; a second extension extending in the second direction; and a corner extending in a direction different from the first direction and the second direction in a plan view and interconnecting the first extension and the second extension. The plurality of grooves include: a first groove closest to the first extension portion in the second direction; and a second groove closest to the first extension portion next to the first groove in the second direction. The first groove has a first end portion located near the second extension portion in the first direction. The second groove has a second end portion located near the second extension portion in the first direction. In the first direction, a distance between the first end portion and the second extension portion is longer than a distance between the second end portion and the second extension portion.

[0011] A semiconductor device according to an embodiment includes: a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a plurality of trenches formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate to the lower surface of the semiconductor substrate, the plurality of trenches extending in a first direction in a plan view and adjacent to each other in a second direction orthogonal to the first direction in a plan view; a plurality of first field plate electrodes respectively formed in the plurality of trenches and electrically insulated from the semiconductor substrate; a plurality of first gate electrodes respectively formed above the plurality of first field plate electrodes and electrically insulated from the semiconductor substrate and the plurality of field plate electrodes; a peripheral trench formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, the peripheral trench extending in the first direction and the second direction to surround the plurality of trenches in a plan view; and a second field plate electrode formed in the peripheral trench and electrically insulated from the semiconductor substrate. The peripheral trench includes: a first extension extending in the first direction; a second extension extending in the second direction; and a corner extending in a direction different from the first direction and the second direction in a plan view and interconnecting the first extension and the second extension. The plurality of grooves include: a first groove closest to the first extension portion in the second direction; and a second groove closest to the first extension portion next to the first groove in the second direction. The first groove has a first end portion located near the second extension portion in the first direction. The second groove has a second end portion located near the second extension portion in the first direction. The shape of the first end portion is different from the shape of the second end portion.

[0012] A semiconductor device according to an embodiment includes: a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a plurality of trenches formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate to the lower surface of the semiconductor substrate, the plurality of trenches extending in a first direction in a plan view and adjacent to each other in a second direction orthogonal to the first direction in the plan view; a plurality of first field plate electrodes respectively formed in the plurality of trenches and electrically insulated from the semiconductor substrate; a plurality of first gate electrodes respectively formed above the plurality of first field plate electrodes and electrically insulated from the semiconductor substrate and the plurality of field plate electrodes; a peripheral trench formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, the peripheral trench extending in the first direction and the second direction to surround the plurality of trenches in the plan view; a second field plate electrode formed in the peripheral trench and electrically insulated from the semiconductor substrate; and a first impurity region formed in the semiconductor substrate between the plurality of trenches and the peripheral trench and having a second conductivity type opposite to the first conductivity type. The peripheral trench includes: a first extension extending in a first direction; a second extension extending in a second direction; and a corner extending in a direction different from the first direction and the second direction and interconnecting the first extension and the second extension in a plan view. The plurality of trenches include a first trench closest to the first extension in the second direction. A second impurity region is formed in the semiconductor substrate between the corner and the first trench. The impurity concentration of the second impurity region is higher than the impurity concentration of the first impurity region.

[0013] According to one embodiment, a breakdown voltage of a semiconductor device can be stabilized. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a plan view indicating a semiconductor device in a first embodiment;

[0015] Figure 2 is a main portion plan view indicating a semiconductor device in a first embodiment;

[0016] Figure 3 is a main portion plan view indicating a semiconductor device in a first embodiment;

[0017] Figure 4 is a cross-sectional view indicating a semiconductor device in a first embodiment;

[0018] Figure 5 is a main part plan view showing the periphery of the corner portion of the peripheral groove in the first embodiment;

[0019] Figure 6 is a main portion plan view showing a depletion layer extending around a corner of a peripheral trench in the first embodiment;

[0020] Figure 7 is a graph indicating the measurement results of the present inventors;

[0021] Figure 8 is a cross-sectional view showing a manufacturing process of the semiconductor device in the first embodiment;

[0022] Fig. 9 It is a graphic Figure 8 A cross-sectional view of the subsequent manufacturing process;

[0023] Fig.10 It is a graphic Fig. 9 A cross-sectional view of the subsequent manufacturing process;

[0024] Fig.11 It is a graphic Fig.10 A cross-sectional view of the subsequent manufacturing process;

[0025] Fig.12 It is a graphic Fig.11 A cross-sectional view of the subsequent manufacturing process;

[0026] Fig.13 It is a graphic Fig.12 A cross-sectional view of the subsequent manufacturing process;

[0027] Fig.14 It is a graphic Fig.13 A cross-sectional view of the subsequent manufacturing process;

[0028] Fig.15 It is a graphic Fig.14 A cross-sectional view of the subsequent manufacturing process;

[0029] Fig.16 It is a graphic Fig.15 A cross-sectional view of the subsequent manufacturing process;

[0030] Fig.17 is a main part plan view showing the periphery of the corner portion of the peripheral groove in the second embodiment;

[0031] Fig.18 is a main portion plan view showing a depletion layer extending around a corner of a peripheral trench in the second embodiment;

[0032] Fig.19 is a main part plan view showing the periphery of the corner portion of the peripheral groove in the third embodiment;

[0033] Fig. 20 is a main portion plan view showing a depletion layer extending around a corner of a peripheral trench in a third embodiment;

[0034] Fig.21 is a cross-sectional view indicating a semiconductor device in a third embodiment;

[0035] Fig. 22 is a main part plan view showing the periphery of the corner portion of the peripheral groove in the fourth embodiment;

[0036] Fig.23 is a main portion plan view showing a depletion layer extending around a corner of a peripheral trench in a fourth embodiment;

[0037] Fig.24 is a main part plan view showing the periphery of the corner portion of the peripheral groove in the inspection example; and

[0038] Fig.25 is a main portion plan view showing a depletion layer extending around a corner of a peripheral trench in an inspection example. DETAILED DESCRIPTION

[0039] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings. In all the drawings used to explain the embodiments, components having the same function are represented by the same reference numerals, and their repeated description is omitted. In the following embodiments, the description of the same or similar components is not repeated in principle unless it is particularly necessary.

[0040] In addition, the X direction, Y direction and Z direction described in the present application intersect each other and are orthogonal to each other. In the present application, the Z direction is described as the vertical direction, height direction or thickness direction of a specific structure. In addition, the "plan view" used in the present application means that the plane formed by the X direction and the Y direction is a "plane" and the "plane" is viewed from the Z direction.

[0041] (First embodiment)

[0042] <Structure of semiconductor devices>

[0043] The following will refer to Figures 1 to 7 A semiconductor device 100 in a first embodiment is described. The semiconductor device 100 includes a trench gate structure MOSFET as a semiconductor element. The MOSFET of the first embodiment has a split gate structure including a gate electrode GE and a field plate electrode FP in a trench TR1.

[0044] Figure 1 is a plan view of a semiconductor chip serving as the semiconductor device 100 . Figure 2 and Figure 3 yes Figure 1 An enlarged essential part plan view of region 1A is shown. Figure 3 Shows Figure 2 The structure below mainly shows a trench gate structure formed in a semiconductor substrate SUB. In addition, Figure 2 The positions of the holes CH1, CH2, and CH3 shown by the dotted lines in FIG. Figure 3The positions of the holes CH1, CH2, and CH3 shown are consistent. Figure 4 It is along Figure 2 and Figure 3 Cross-sectional views along lines AA and BB are shown.

[0045] Figure 5 and Figure 6 Shows Figure 3 An enlarged periphery of a corner TR2c of a peripheral trench TR2 is shown. Although the main feature of the present application lies in the configuration around the corner TR2c, such feature is described in detail below.

[0046] Figure 1 1 shows a wiring pattern mainly formed over a semiconductor substrate SUB. The semiconductor device 100 has a cell region CR and a peripheral region OR surrounding the cell region CR in a plan view. In the cell region CR, main semiconductor elements such as a plurality of MOSFETs are formed. The peripheral region OR is used to connect the gate wiring GW to the gate electrode GE to form a peripheral trench TR2 used as a termination region, etc. Figure 1 and Figure 2 As shown, most of the cell region CR is covered by the source electrode SE. In a plan view, the gate wiring GW surrounds the source electrode SE in a top view. Although not shown here, the source electrode SE and the gate wiring GW are covered by a protective film such as a polyimide film. An opening is provided in a portion of the protective film, and the source electrode SE and the gate wiring GW exposed in the opening become a source pad SP and a gate pad GP. An external connection member is connected to the source pad SP and the gate pad GP, so that the semiconductor device 100 is electrically connected to another semiconductor chip, a lead frame, a wiring substrate, etc. The external connection member is, for example, a wire made of aluminum, gold, or copper, or a clip made of a copper plate.

[0047] like Figure 3 As shown, a plurality of trenches TR1 are formed in the semiconductor substrate SUB of the cell region CR. The plurality of trenches TR1 are formed in a stripe shape, extend in the Y direction, and are adjacent to each other in the X direction.

[0048] like Figure 4 As shown, in the trench TR1, a field plate electrode FP is formed at a lower portion of the trench TR1, and a gate electrode GE is formed at an upper portion of the trench TR1. The field plate electrode FP and the gate electrode GE extend in the Y direction along the trench TR1.

[0049] Furthermore, a part of the field plate FP forms a lead-out portion FPa. The field plate electrode FP constituting the lead-out portion FPa is formed not only in the lower portion of the trench TR1 but also in the upper portion of the trench TR1 within the trench TR1.

[0050] like Figure 3 As shown, a peripheral trench TR2 is formed in the semiconductor substrate SUB of the peripheral region OR. In the X direction, a plurality of trenches TR1 and the peripheral trench TR2 are arranged at the same pitch. In addition, the width of the peripheral trench TR2 is similar to the width of the trench TR1. The peripheral trench TR2 extends in the Y direction and the X direction to surround the plurality of trenches TR1 in a plan view. The peripheral trench TR2 has a corner TR2c at a portion where a portion extending in the Y direction intersects a portion extending in the X direction. A field plate electrode FP (lead-out portion FPa) is formed in the peripheral trench TR2.

[0051] Here, although two peripheral trenches TR2 are exemplified, the number of the peripheral trenches TR2 may be one or three or more.

[0052] A hole CH3 is formed on each lead portion FPa of the cell region CR and the peripheral region OR. The lead portion FPa is electrically connected to the source electrode SE via the hole CH3. In the peripheral region OR, a hole CH2 is formed on the gate electrode GE, and the gate electrode GE is electrically connected to the gate wiring GW via the hole CH2.

[0053] The following will refer to Figure 4 A cross-sectional configuration of the semiconductor device 100 is described.

[0054] Note that except for the different reference numerals TR2 of the grooves, Figure 2 and Figure 3 The cross-sectional view along the CC line shown is substantially the same as the cross-sectional view along the BB line. Therefore, hereinafter, the description of the cross-sectional view along the BB line includes the description of the cross-sectional view along the CC line.

[0055] like Figure 4 As shown, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB has a low-concentration n-type drift region NV. In the first embodiment, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The semiconductor substrate SUB can be a stack of an n-type silicon substrate and an n-type semiconductor layer grown on the n-type silicon substrate while introducing phosphorus (P) by an epitaxial growth method. In this case, the low-concentration n-type semiconductor layer constitutes the drift region NV, and the high-concentration n-type silicon substrate constitutes the drain region ND.

[0056] An n-type drain region ND is formed at the lower portion of the semiconductor substrate SUB. The drain region ND has a higher impurity concentration than the drift region NV. The drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB. The drain electrode DE is composed of a single-layer metal film, such as an aluminum film, a titanium film, a nickel film, a gold film or a silver film, or a laminated film having these metal films laminated accordingly. The drain region ND and the drain electrode DE are formed above the cell region CR and the peripheral region OR. The drain potential is supplied from the drain electrode DE to the semiconductor substrate SUB (drain region ND, drift region NV).

[0057] In the semiconductor substrate SUB, a plurality of trenches TR1 are formed, which reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. The depth of each trench TR1 is, for example, above 5 μm (5 micrometers) and below 10 μm (10 micrometers). In the trench TR1, a field plate electrode FP is formed at the lower portion of the trench TR1 via an insulating film IF1. In addition, in the trench TR1, a gate electrode GE is formed above the field plate electrode FP via a gate insulating film GI. Each of the field plate electrode FP and the gate electrode GE is formed of, for example, an n-type doped polysilicon film.

[0058] The position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP. The gate insulating film GI is formed in the trench TR1 on the insulating film IF1. The insulating film IF2 is formed to cover the field plate electrode FP exposed from the insulating film IF1. The gate electrode GE is also formed between the field plate electrode FP exposed from the insulating film IF1 and the semiconductor substrate SUB via the gate insulating film GI and the insulating film IF2.

[0059] An insulating film IF1 is formed between the semiconductor substrate SUB and the field plate electrode FP. An insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. A gate insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. The semiconductor substrate SUB, the gate electrode GE and the field plate electrode FP are electrically insulated from each other by these insulating films.

[0060] The insulating film IF1, the insulating film IF2, and the gate insulating film GI are made of, for example, a silicon oxide film. The thickness of the insulating film IF1 is greater than the thickness of each of the insulating film IF2 and the gate insulating film GI. In the trench TR1, the thickness of the insulating film IF1 is, for example, greater than 400 nm and less than 600 nm. In the trench TR1, the thickness of the insulating film IF2 and the gate insulating film GI is, for example, greater than 50 nm and less than 100 nm, respectively. These thicknesses are thicknesses in the X direction.

[0061] A p-type body region PB is formed in the semiconductor substrate SUB, and the p-type body region reaches a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. The depth of the body region PB from the upper surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR1 from the upper surface TS of the semiconductor substrate SUB. In the body region PB, an n-type source region NS is formed. The source region NS has a higher impurity concentration than the drift region NV.

[0062] The interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB so as to cover the trench TR1. The interlayer insulating film IL is formed of, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, greater than or equal to 700 nm and less than or equal to 900 nm.

[0063] A hole CH1 is formed in the interlayer insulating film IL. The hole CH1 extends through the interlayer insulating film IL and the source region NS and reaches the body region PB. At the bottom of the hole CH1, a high concentration diffusion region PR is formed in the body region PB. The high concentration diffusion region PR has a higher impurity concentration than the body region PB. The high concentration diffusion region PR is provided mainly to reduce the contact resistance with the source electrode SE and prevent latch-up.

[0064] The source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is electrically connected to the source region NS, the body region PB, and the high-concentration diffusion region PR via the hole CH1, and supplies a source potential to these impurity regions.

[0065] like Figure 4 As shown in the BB cross section of FIG. 1 , a part of the field plate electrode FP forms the lead portion FPa of the field plate electrode FP. The position of the upper surface of the insulating film IF1 in contact with the lead portion FPa is higher than the position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the lead portion FPa. The insulating film IF2 is formed on the side surface of the lead portion FPa. In addition, a body region PB in contact with the trench TR1 in which the lead portion FPa is formed is formed in the semiconductor substrate SUB, but the source region NS is not formed in the body region PB.

[0066] like Figure 4 As shown in the BB cross section of FIG. 1 , the interlayer insulating film IL has a hole CH3 extending through the interlayer insulating film IL and reaching the lead-out portion FPa. The source electrode SE is electrically connected to the lead-out portion FPa via the hole CH3 and supplies a source potential to the field plate electrode FP.

[0067] Although not shown here, the interlayer insulating film IL has a hole CH2 extending through the interlayer insulating film IL and reaching the gate electrode GE. The gate wiring GW is electrically connected to the gate electrode GE via the hole CH2, and supplies a gate potential to the gate electrode GE.

[0068] The source electrode SE is also embedded in the hole CH1 and the hole CH3. The gate wiring GW is also embedded in the hole CH2. The source electrode SE and the gate wiring GW are made of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium tungsten film, and the conductive film is, for example, an aluminum alloy film to which copper or silicon is added.

[0069] The source electrode SE and the gate wiring GW may be formed by a plug layer filling the inside of the holes CH1, CH2, CH3 and a wiring layer formed on the interlayer insulating film IL. In this case, the wiring layer is formed by a barrier metal film and a conductive film. The plug layer is formed by, for example, a stacked film of a barrier metal film such as a titanium nitride film and a conductive film such as a tungsten film.

[0070] <Main features of the first embodiment>

[0071] Figure 5 1 is a main portion plan view showing the periphery of the corner TR2c of the peripheral trench TR2. Figure 6 A depletion layer extending around the corner TR2c is shown.

[0072] like Figure 5 As shown, the peripheral trench TR2 has an extension portion TR2a extending in the Y direction, an extension portion TR2b extending in the X direction, and a corner portion TR2c connecting the extension portion TR2a and the extension portion TR2b to each other. The corner portion TR2c extends in a direction different from the Y direction and the X direction in a plan view, and extends in a direction inclined at 45 degrees to the Y direction and the X direction, for example.

[0073] When such a corner TR2c is not provided, the extension TR2a and the extension TR2b are connected at a right angle. In this case, a change in the thickness of the insulating film IF1 tends to occur at the right angle portion, and a defect of embedding of the field plate electrode FP tends to occur. In addition, since the distance from the right angle portion to the trench TR1 is long, it is difficult for the depletion layer extending from the right angle portion to reach the depletion layer from the trench TR1 closest to the extension TR2a. The portion where the depletion layer does not diffuse in this way causes a partial breakdown voltage drop. Therefore, in order to prevent the occurrence of these defects, it is preferred that a corner TR2c is provided in the peripheral trench TR2.

[0074] In the following description, when describing Figure 5 and Figure 6When the outer periphery of the corner TR2c is shown, the groove TR1 closest to the extension TR2a in the X direction is referred to as "the closest groove TR1", and the grooves TR1 other than the closest groove TR1 are referred to as "other grooves TR1". Here, as one of the other grooves TR1, the groove TR1 adjacent to the closest groove TR1 in the X direction on the opposite side of the extension TR2a is exemplified. That is, as one of the other grooves TR1, the groove TR1 next closest to the extension TR2a in the X direction after the closest groove TR1 is exemplified.

[0075] In addition, when describing Figure 6 When the depletion layer is shown, the depletion layer extending from the field plate electrode FP in the trench TR1 to the drift region NV can be referred to as “the depletion layer from the trench TR1 ”, and the depletion layer extending from the field plate electrode FP in the peripheral trench TR2 to the drift region NV can be referred to as “the depletion layer from the peripheral trench TR2 ”.

[0076] like Figure 5 As shown, each of the plurality of grooves TR1 has an end 10 close to the extension TR2b in the Y direction. However, in the Y direction, the position of the end 10 closest to the groove TR1 is retracted from the position of the end 10 of the other grooves TR1 by a distance L1. In other words, in the Y direction, the distance L2 between the end 10 closest to the groove TR1 and the extension TR2b is longer than the distance L3 between the end 10 of the other grooves TR1 and the extension TR2b. In other words, in the Y direction, the end 10 closest to the groove TR1 is farther away from the extension TR2b than the end 10 of the other grooves TR1.

[0077] The reason for this will be described below with reference to an inspection example. Fig.24 and Fig.25 A semiconductor device of an inspection example studied by the present inventors is shown.

[0078] like Fig.24 As shown, in the inspection example, in the Y direction, the distance L3 between the end 10 closest to the groove TR1 and the extension TR2b is the same as the distance L3 between the end 10 of the other grooves TR1 and the extension TR2b. Fig.25 As shown, the depletion layers diffuse from the trench TR1 and the peripheral trench TR2 respectively, but there is a "transition region" in which the depletion layer from the corner TR2c and its periphery and the depletion layer from the nearest trench TR1 overlap to a large extent.

[0079] Here, in the split gate structure MOSFET, it is known that impact ionization occurs near the bottom of each of the trench TR1 and the peripheral trench TR2 at the time of avalanche breakdown, and hot holes generated at this time are injected into the insulating film IF1. When avalanche breakdown is repeated and such hot hole injection is accumulated in the insulating film IF1, the charge balance of the cell region changes and the breakdown voltage becomes unstable.

[0080] The portion that the depletion layer does not reach is the cause of a partial breakdown voltage drop. In order to prevent the generation of such a portion, preferably, the depletion layer from the trench TR1 and the depletion layer from the peripheral trench TR2 overlap to some extent. However, in the case of Fig.25 In the “transition region” shown, impact ionization tends to occur from a low electric field due to electric field concentration, and many hot holes are injected into the insulating film IF1.

[0081] In the first embodiment, the distance L2 is longer than the distance L3. Figure 5 As shown in , in order to suppress the generation of such a "transition area". Figure 6 As shown, the overlap between the depletion layer from the corner TR2c and its periphery and the depletion layer from the closest trench TR1 is reduced, so that the impact ionization is mitigated and the number of hot holes injected into the insulating film IF1 can be suppressed. That is, according to the first embodiment, the breakdown voltage around the peripheral trench TR2 can be improved, and the breakdown voltage of the semiconductor device 100 can be stabilized.

[0082] Figure 7 is a graph showing the relationship between the drain current Id and the drain voltage Vd, and shows the results measured by the inventors of the present application after performing several breakdown operations on the inspection example and the first embodiment. Figure 7 As shown, it can be seen that in the inspection example, when the drain voltage Vd is low, the drain current Id starts to flow. That is, in the inspection example, it has been found that there is a region with a local low withstand voltage in the cell. On the other hand, it can be seen that such a problem can be suppressed in the first embodiment.

[0083] <Method for manufacturing semiconductor device>

[0084] The following will refer to Figures 8 to 16 Respective manufacturing processes included in the manufacturing method of the semiconductor device 100 are described.

[0085] First, if Figure 8 As shown, an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS is prepared. As described above, the semiconductor substrate SUB may be a stack of an n-type silicon substrate and an n-type semiconductor layer formed on the silicon substrate by epitaxial growth.

[0086] Next, a trench TR1 is formed in the semiconductor substrate SUB to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. In order to form the trench TR1, for example, a silicon oxide film is first formed on the semiconductor substrate SUB by, for example, CVD (chemical vapor deposition). Next, the silicon oxide film is patterned by photolithography and an anisotropic etching process to form a hard mask HM. Next, an anisotropic etching process is performed using the hard mask HM as a mask to form the trench TR1 in the semiconductor substrate SUB. Thereafter, the hard mask HM is removed by a wet etching process, for example, using a hydrofluoric acid solution.

[0087] Next, if Fig. 9 As shown, an insulating film IF1 is formed in the trench TR1 and on the upper surface TS of the semiconductor substrate SUB. The insulating film IF1 is, for example, a silicon oxide film formed by thermal oxidation. The insulating film IF1 may be a stacked film of a first silicon oxide film formed by thermal oxidation and a second silicon oxide film formed on the first silicon oxide film by CVD.

[0088] Next, a conductive film CF1 is formed on the insulating film IF1 by, for example, CVD to fill the inside of the trench TR1. The conductive film CF1 is, for example, an n-type polysilicon film. In order to satisfactorily fill the inside of the trench TR1 with the conductive film CF1, the conductive film CF1 may be formed multiple times (for example, twice, including forming a first polysilicon film and forming a second polysilicon film).

[0089] Next, if Fig.10 As shown, the conductive film CF1 located outside the trench TR1 is removed by a polishing process using, for example, CMP (Chemical Mechanical Polishing). As a result, the conductive film CF1 remaining in the trench TR1 is formed as the field plate electrode FP.

[0090] Next, if Fig.11 As shown, the other portion of the field plate electrode FP is selectively removed so that a portion of the field plate electrode FP is left as the lead-out portion FPa.

[0091] Specifically, first, as shown in the BB cross section, a resist pattern RP1 is formed, which selectively covers a portion of the field plate electrode FP that becomes the lead-out portion FPa. Next, an etching process using, for example, SF6 gas is performed using the resist pattern RP1 as a mask to remove the portion of the field plate electrode FP that does not become the lead-out portion FPa. That is, as shown in the AA cross section, another portion of the field plate electrode FP that does not become the lead-out portion FPa is selectively retracted toward the bottom of the trench TR1. The non-retracted portion of the field plate electrode FP becomes the lead-out portion FPa. Thereafter, the resist pattern RP1 is removed by an ashing process.

[0092] Next, if Fig.12 As shown, the insulating film IF1 is isotropically etched using a solution containing hydrofluoric acid. As a result, the insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB is removed, and the insulating film IF1 located in the trench TR1 is retracted toward the bottom of the trench TR1, so that the position of the upper surface of the insulating film IF1 located in the trench TR1 in the cross-sectional view is lower than the position of the upper surface of the field plate electrode FP.

[0093] At this time, the position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP except the lead-out portion FPa is lower than the position of the lower surface of the insulating film IF1 in contact with the lead-out portion FPa. In addition, as shown in the BB cross section, since the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB is removed, the position of the upper surface of the lead-out portion FPa is higher than the position of the upper surface TS of the semiconductor substrate SUB.

[0094] Next, if Fig.13 As shown, by performing thermal oxidation treatment, the gate insulating film GI is formed in the trench TR1 located on the insulating film IF1, and the insulating film IF2 is formed to cover the field plate electrode FP exposed from the insulating film IF1.

[0095] Next, a conductive film CF2 is formed on the gate insulating film GI and the insulating film IF2 by, for example, a CVD method so as to fill the inside of the trench TR1. The conductive film CF2 is, for example, an n-type polysilicon film.

[0096] Next, if Fig.14 As shown, the conductive film CF2 is polished using a CMP method. As a result, the thickness of the conductive film CF2 is reduced, and the upper surface of the conductive film CF2 is flattened. Next, an anisotropic etching process is performed on the conductive film CF2 to remove the conductive film CF2 located outside the trench TR1. Therefore, the conductive film CF2 remaining in the trench TR1 is formed as the gate electrode GE on the field plate electrode FP.

[0097] In order to completely remove the conductive film CF2 outside the trench TR1, an anisotropic etching process is performed by over-etching. Therefore, as shown in the AA cross section, the position of the upper surface of the gate electrode GE is slightly lower than the position of the upper surface TS of the semiconductor substrate SUB. In addition, the conductive film CF2 formed on the insulating film IF2 in contact with the lead-out portion FPa is removed by the anisotropic etching process.

[0098] Next, if Fig.15 As shown, a p-type body region PB is selectively formed on the semiconductor substrate SUB in the cell region CR by introducing, for example, boron (B) through photolithography and ion implantation.

[0099] Next, arsenic (As) is introduced by photolithography and ion implantation, for example, to selectively form an n-type source region NS in the body region PB of the cell region CR. Note that the source region NS is not formed in the body region PB adjacent to the lead-out portion FPa. Thereafter, the semiconductor substrate SUB is heat-treated to diffuse the impurities contained in the source region NS and the body region PB.

[0100] Next, if Fig.16 As shown, first, an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR1.

[0101] Next, holes CH1, CH2, and CH3 are formed in the interlayer insulating film IL. First, on the interlayer insulating film IL, a resist pattern is formed, the resist pattern having a pattern for opening the semiconductor substrate SUB in which the source region NS is formed. Next, an anisotropic etching process is performed using the resist pattern as a mask to form a hole CH1 extending through the interlayer insulating film IL and the source region NS and reaching the inside of the body region PB. Next, boron (B), for example, is introduced into the body region PB at the bottom of the hole CH1 by an ion implantation method to form a p-type high-concentration diffusion region PR. Thereafter, the resist pattern is removed by an ashing process.

[0102] Next, on the interlayer insulating film IL, a resist pattern is formed, which has a pattern opening on the lead-out portion FPa and the gate electrode GE. Next, an anisotropic etching process is performed using the resist pattern as a mask to form a hole CH3 extending through the interlayer insulating film IL and reaching the lead-out portion FPa. Although not shown here, in the step of forming the hole CH3, a hole CH2 extending through the interlayer insulating film IL and reaching the gate electrode GE is also formed. Thereafter, the resist pattern is removed by an ashing process.

[0103] Note that any one of the formation of the hole CH1 and the formation of the hole CH2 and the hole CH3 may be performed first.

[0104] Next, the source electrode SE is formed on the interlayer insulating film IL so as to fill the insides of the holes CH1 and CH3 , and the gate wiring GW is formed on the interlayer insulating film IL so as to fill the inside of the hole CH2 .

[0105] Specifically, first, a first barrier metal film is formed in the holes CH1, CH2, and CH3 and on the interlayer insulating film IL by sputtering. The first barrier metal film is formed of, for example, a titanium tungsten film. Next, a first conductive film is formed on the first barrier metal film by sputtering. The first conductive film is, for example, an aluminum alloy film to which copper or silicon is added. Next, a source electrode SE and a gate wiring GW are formed by patterning the first barrier metal film and the first conductive film.

[0106] Next, although not shown here, a protective film made of, for example, a polyimide film is formed on the source electrode SE and the gate wiring GW by, for example, a coating method. By forming openings in portions of the protective film, regions of the source electrode SE and the gate wiring GW that become the source pad SP and the gate pad GP are exposed.

[0107] After that, the following manufacturing process is used to obtain Figure 4 The structure shown. First, the lower surface BS of the semiconductor substrate SUB is polished as needed. Next, arsenic (As) or the like is introduced into the lower surface BS of the semiconductor substrate SUB by ion implantation to form an n-type drain region ND. When the semiconductor substrate SUB is composed of a stack of an n-type silicon substrate and an n-type semiconductor layer, the high-concentration n-type silicon substrate forms the drain region ND, and therefore the formation of the drain region ND by the above-mentioned ion implantation can be omitted. Next, a drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB by sputtering.

[0108] (Second embodiment)

[0109] The following will refer to Fig.17 and Fig.18 A semiconductor device 100 in the second embodiment is described. Note that in the following description, the difference from the first embodiment will be mainly described, and the description of the overlap with the first embodiment will be omitted.

[0110] In the first embodiment, in order to suppress Fig.25 The “transition region” shown is generated so that the end 10 closest to the trench TR1 is farther away from the extension TR2 b in the Y direction than the end 10 in the other trenches TR1 .

[0111] In the second embodiment, if Fig.17 As shown, the shape of the end 10 closest to the trench TR1 is different from the shape of the end 10 of the other trenches TR1. For example, the shape of the end 10 closest to the trench TR1 is recessed away from the corner TR2c. In other words, the width of the end 10 closest to the trench TR1 in the X direction is narrower than the width of the closest trench TR1 other than the end 10 in the X direction, and it continuously narrows toward the extension TR2b.

[0112] In order to change the shape of the end portion 10 closest to the trench TR1, the Figure 8 The pattern of the hard mask HM is shown.

[0113] In the second embodiment as well as the first embodiment, the generation of the “transition region” can be suppressed, and the breakdown voltage around the peripheral trench TR2 can be increased. Therefore, the breakdown voltage of the semiconductor device 100 can be stabilized.

[0114] In addition, when the second embodiment Fig.18 The first embodiment Figure 6 When compared, the second embodiment has higher uniformity of overlap of depletion layers extending from the respective trenches TR1, TR2. Therefore, in the second embodiment, the breakdown voltage around the peripheral trench TR2 is more easily stabilized than in the first embodiment.

[0115] On the other hand, if end portion 10 closest to trench TR1 is too thin, it is difficult to satisfactorily embed insulating film IF1 and field plate electrode FP in end portion 10. Therefore, the first embodiment is superior to the second embodiment in terms of embeddability of insulating film IF1 and field plate electrode FP.

[0116] (Third Embodiment)

[0117] The following will refer to Figures 19 to 21 A semiconductor device 100 in the third embodiment is described. Note that in the following description, the difference from the first embodiment will be mainly described, and the description of the overlap with the first embodiment will be omitted. Fig.21 It is along Fig.19 Cross-sectional view of line DD.

[0118] In the third embodiment, if Fig.19 As shown, the distance between the end 10 closest to the trench TR1 and the extension TR2b and the distance between the end 10 of another trench TR1 and the extension TR2b are the same distance L3. Fig.19 and Fig.21 As shown, a floating region PF as a p-type impurity region is formed in the semiconductor substrate SUB located between the corner TR2 c and the area closest to the trench TR1 .

[0119] The impurity concentration of the floating region PF is higher than the impurity concentration of the p-type body region PB. In addition, the depth of the floating region PF from the upper surface TS of the semiconductor substrate SUB is deeper than the depth of the p-type body region PB from the upper surface TS of the semiconductor substrate SUB. The floating region PF is physically separated from the body region PB, is not electrically connected to the source electrode SE, and is electrically floating.

[0120] In order to form such a floating region PF, an additional ion implantation step is performed. Fig.15 Before and after the manufacturing process of the body region PB, impurities such as boron (B) are selectively implanted into the semiconductor substrate SUB located between the corner TR2c and the closest trench TR1 using photolithography and ion implantation. As a result, a floating region PF is formed.

[0121] like Fig. 20As shown, by providing such a floating region PF, the expansion of the depletion layer from the corner TR2c and its periphery and the expansion of the depletion layer from the end 10 closest to the trench TR1 are suppressed. Therefore, in the third embodiment as well as the first embodiment, the generation of the "excess region" can be suppressed, and the breakdown voltage around the peripheral trench TR2 can be improved. Therefore, the breakdown voltage of the semiconductor device 100 can be stabilized.

[0122] (Fourth embodiment)

[0123] The following will refer to Fig. 22 and Fig.23 A semiconductor device 100 in a fourth embodiment is described. Note that in the following description, the difference from the first embodiment will be mainly described, and the description of the overlap with the first embodiment will be omitted.

[0124] like Fig. 22 As shown, the end 10 closest to the trench TR1 of the fourth embodiment is farther away from the extension TR2b than the end 10 of the other trenches TR1. The trench TR3 is formed in the semiconductor substrate SUB between the end 10 closest to the trench TR1 and the extension TR2b to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. The trench TR3 is formed in the manufacturing process of the trench TR1 and the peripheral trench TR2, but is not connected with the trench TR1 and the peripheral trench TR2, and is formed as an independent trench.

[0125] A floating gate electrode FG is formed in the trench TR3. The floating gate electrode FG is electrically isolated from the semiconductor substrate SUB and electrically floats. The floating gate electrode FG is formed to relax the electric field around the corner TR2c.

[0126] The internal structure of the trench TR3 may be the same as the internal structure of the trench TR1 of the cell region CR, or may be composed of an insulating film IF1, a gate insulating film GI, an insulating film IF2, a field plate electrode FP, and a gate electrode GE. In this case, the field plate electrode FP and the gate electrode GE become floating gate electrodes FG, respectively, and there are two floating gate electrodes FG in the trench TR3.

[0127] Furthermore, the internal structure of the trench TR3 may be composed of the insulating film IF1 and the field plate electrode FP (lead-out portion FPa) and the inside of the peripheral trench TR2 of the peripheral region OR. In this case, the field plate electrode FP (lead-out portion FPa) becomes the floating gate electrode FG.

[0128] However, when the trench TR3 and the floating gate electrode FG are simply provided, there is a case where the depletion layer of any of the closest trench TR1 , other trenches TR1 , or the peripheral trench TR2 does not reach a position.

[0129] Therefore, if Fig.23 As shown, it is preferred that the shape of the trench TR3 is adjusted so that all depletion layers from the closest trench TR1, other trenches TR1, or peripheral trenches TR2 overlap with the floating gate electrode FG in a plan view. Therefore, if necessary, the shape of the trench TR3 is adjusted to be similar to the closest trench TR1, other trenches TR1, or peripheral trenches TR2.

[0130] For example, Fig. 22 As shown, in the Y direction, the distance L4 between the trench TR3 and the extension TR2b and the distance L6 between the trench TR3 and the end 10 closest to the trench TR1 are shorter than the distance L5 between the end 10 of the other trench TR1 and the extension TR2b. In addition, in the X direction, the distance L7 between the trench TR3 and the extension TR2a and the distance L8 between the trench TR3 and the other trench TR1 are shorter than the distance L9 between the closest trench TR1 and the extension TR2a and the distance L10 between the closest trench TR1 and the other trench TR1.

[0131] In the fourth embodiment as well as the first embodiment, the generation of the “transition region” can be suppressed, and the breakdown voltage around the peripheral trench TR2 can be increased. Therefore, the breakdown voltage of the semiconductor device 100 can be stabilized.

[0132] Although the present invention has been described in detail based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist thereof.

Claims

1. A semiconductor device, comprising: A semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a plurality of trenches formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate to the lower surface of the semiconductor substrate, the plurality of trenches extending in a first direction in a plan view and adjacent to each other in a second direction orthogonal to the first direction in a plan view; a plurality of first field plate electrodes, respectively formed in the plurality of trenches and electrically insulated from the semiconductor substrate; a plurality of first gate electrodes, respectively formed above the plurality of first field plate electrodes and respectively electrically insulated from the semiconductor substrate and the plurality of field plate electrodes; a peripheral trench formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, the peripheral trench extending in the first direction and the second direction to surround the plurality of trenches in a plan view; as well as a second field plate electrode formed in the peripheral trench and electrically insulated from the semiconductor substrate, Wherein the peripheral groove comprises: A first extending portion extending in the first direction; A second extending portion extending in the second direction; and a corner portion extending in a direction different from the first direction and the second direction in a plan view and interconnecting the first extending portion and the second extending portion, The plurality of grooves include: a first groove, closest to the first extension portion in the second direction; and a second groove, after the first groove in the second direction and next to the first extension, wherein the first groove has a first end portion located near the second extension portion in the first direction, wherein the second groove has a second end portion located near the second extension portion in the first direction, and In the first direction, a distance between the first end and the second extending portion is longer than a distance between the second end and the second extending portion. 2 . The semiconductor device according to claim 1 , wherein a gate potential is supplied to the plurality of first gate electrodes, and a source potential is supplied to the second field plate electrode and the plurality of first field plate electrodes. 3 . The semiconductor device according to claim 1 , wherein the corner portion extends in a direction inclined by 45 degrees to the first direction and the second direction in a plan view.

4. The semiconductor device according to claim 1, in, In the semiconductor substrate between the first end portion and the second extension portion, a third trench is formed to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, and A floating gate electrode electrically isolated from the semiconductor substrate is formed in the third trench.

5. The semiconductor device according to claim 4, in, In the first direction, a distance between the third groove and the second extension portion and a distance between the third groove and the first end portion are shorter than the distance between the second end portion and the second extension portion, and In the second direction, a distance between the third groove and the first extension portion and a distance between the third groove and the second groove are shorter than a distance between the first groove and the first extension portion and a distance between the first groove and the second groove.

6. The semiconductor device according to claim 4, wherein a gate potential is supplied to the plurality of first gate electrodes, wherein a source potential is supplied to the second field plate electrode and the plurality of first field plate electrodes, and Wherein the floating gate electrode is electrically floating. 7 . The semiconductor device according to claim 4 , wherein the corner portion extends in a direction inclined by 45 degrees to the first direction and the second direction in a plan view.

8. A semiconductor device comprising: A semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a plurality of trenches formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate to the lower surface of the semiconductor substrate, the plurality of trenches extending in a first direction in a plan view and adjacent to each other in a second direction orthogonal to the first direction in a plan view; a plurality of first field plate electrodes, respectively formed in the plurality of trenches and electrically insulated from the semiconductor substrate; a plurality of first gate electrodes, respectively formed above the plurality of first field plate electrodes and respectively electrically insulated from the semiconductor substrate and the plurality of field plate electrodes; a peripheral trench formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, the peripheral trench extending in the first direction and the second direction to surround the plurality of trenches in a plan view; as well as a second field plate electrode formed in the peripheral trench and electrically insulated from the semiconductor substrate, Wherein the peripheral groove comprises: A first extending portion extending in the first direction; A second extending portion extending in the second direction; and a corner portion extending in a direction different from the first direction and the second direction in a plan view and interconnecting the first extending portion and the second extending portion, The plurality of grooves include: a first groove, closest to the first extension portion in the second direction; and a second groove, after the first groove in the second direction and next to the first extension, wherein the first groove has a first end portion located near the second extension portion in the first direction, wherein the second groove has a second end portion located near the second extension portion in the first direction, and The shape of the first end is different from the shape of the second end. 9 . The semiconductor device according to claim 8 , wherein the first end portion has a shape that is recessed toward a direction away from the corner portion. 10 . The semiconductor device according to claim 8 , wherein a width of the first end portion in the second direction is narrower than a width of the first trench except for the first end portion in the second direction and is continuously narrowed toward the second extension portion.

11. The semiconductor device according to claim 8, wherein a gate potential is supplied to the plurality of first gate electrodes, and The source potential is supplied to the second field plate electrode and the plurality of first field plate electrodes. 12 . The semiconductor device according to claim 8 , wherein the corner portion extends in a direction inclined by 45 degrees to the first direction and the second direction in a plan view.

13. A semiconductor device comprising: A semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a plurality of trenches formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate to the lower surface of the semiconductor substrate, the plurality of trenches extending in a first direction in a plan view and adjacent to each other in a second direction orthogonal to the first direction in a plan view; a plurality of first field plate electrodes, respectively formed in the plurality of trenches and electrically insulated from the semiconductor substrate; a plurality of first gate electrodes, respectively formed above the plurality of first field plate electrodes and respectively electrically insulated from the semiconductor substrate and the plurality of field plate electrodes; a peripheral trench formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, the peripheral trench extending in the first direction and the second direction to surround the plurality of trenches in a plan view; as well as a second field plate electrode formed in the peripheral trench and electrically insulated from the semiconductor substrate; as well as a first impurity region formed in the semiconductor substrate between the plurality of trenches and the peripheral trench and having a second conductivity type opposite to the first conductivity type, Wherein the peripheral groove comprises: A first extending portion extending in the first direction; A second extending portion extending in the second direction; and a corner portion extending in a direction different from the first direction and the second direction in a plan view and interconnecting the first extension portion and the second extension portion, wherein the plurality of grooves include a first groove closest to the first extension portion in the second direction, wherein a second impurity region is formed in the semiconductor substrate between the corner portion and the first trench, and The impurity concentration of the second impurity region is higher than the impurity concentration of the first impurity region. 14 . The semiconductor device according to claim 13 , wherein a depth of the second impurity region from the upper surface of the semiconductor substrate is deeper than a depth of the first impurity region from the upper surface of the semiconductor substrate.

15. The semiconductor device according to claim 13, The plurality of grooves further includes a second groove, the second groove is located after the first groove in the second direction and is next to the first extension portion. The first groove includes a first end portion, and the first end portion is located near the second extension portion in the first direction. wherein the second groove includes a second end portion, the second end portion is located near the second extension portion in the first direction, and in, In the first direction, a distance between the first end and the second extension portion is the same as a distance between the second end and the second extension portion.

16. The semiconductor device according to claim 13, wherein a gate potential is supplied to the plurality of first gate electrodes, wherein a source potential is supplied to the second field plate electrode and the plurality of first field plate electrodes, and The first impurity region and the second impurity region are electrically floating. 17 . The semiconductor device according to claim 13 , wherein the corner portion extends in a direction inclined by 45 degrees to the first direction and the second direction in a plan view.

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