Semiconductor structure and power diode

Abstract

The invention provides a semiconductor structure and a power diode. The semiconductor structure comprises a substrate; the epitaxial layer is located on the surface of the substrate; the first groove is located in the epitaxial layer; the first injection region is located on the side wall and the bottom surface of the first groove, and the doping type of the first injection region is different from that of the epitaxial layer; the second groove is located in the epitaxial layer, the second groove and the first groove are arranged at intervals, and the depth of the second groove is different from that of the first groove; the second injection region is located on the side wall and the bottom surface of the second groove, and the doping type of the second injection region is different from that of the epitaxial layer; the first conductive layer is located in the first groove, in the second groove and on the surface, away from the substrate, of the epitaxial layer, and the first conductive layer makes contact with the first injection region and the second injection region. The problem of poor performance of a semiconductor structure in the prior art is at least solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a power diode. Background Art

[0002] Power diodes are the most basic building blocks in the field of power electronics. Their unidirectional conductivity can be used for rectification, clamping, and freewheeling in high-voltage circuits. With the development of electronic power technology, higher technical requirements are placed on power diodes. Currently, power diodes using traditional structures and processes often only have high reverse breakdown voltages, while other characteristics are not very good. Summary of the invention

[0003] The main purpose of the present application is to provide a semiconductor structure and a power diode, so as to at least solve the problem of poor performance of the semiconductor structure in the prior art.

[0004] To achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor structure is provided, comprising: a substrate; an epitaxial layer located on the surface of the substrate; a first trench located in the epitaxial layer; a first injection region located on the sidewalls and bottom surface of the first trench, the first injection region having a different doping type from that of the epitaxial layer; a second trench located in the epitaxial layer, spaced apart from the first trench, the depth of the second trench being different from that of the first trench; a second injection region located on the sidewalls and bottom surface of the second trench, the second injection region having a different doping type from that of the epitaxial layer; a first conductive layer located in the first trench, in the second trench and on the surface of the epitaxial layer away from the substrate, the first conductive layer being in contact with the first injection region and the second injection region, respectively.

[0005] Optionally, the second groove includes a first sub-groove and a second sub-groove which are connected, the first sub-groove is located on a side of the second sub-groove close to the substrate, the width of the first sub-groove is smaller than the width of the second sub-groove, and the depth of the first sub-groove is smaller than the depth of the second sub-groove; the second injection region is located on the side walls of the first sub-groove, on the bottom surface of the first sub-groove, on the side walls of the second sub-groove, and on the bottom surface of the second sub-groove.

[0006] Optionally, a depth of the second sub-groove is the same as a depth of the first groove, and a width of the second sub-groove is greater than a width of the first groove.

[0007] Optionally, the first conductive layer includes: a first conductive sublayer located in the first groove, in contact with the first injection region on the side walls and the bottom surface of the first groove, the surface of the first conductive sublayer away from the substrate being flush with the surface of the epitaxial layer away from the substrate; a second conductive sublayer located in the second groove, on the surface of the first conductive sublayer away from the substrate and on the surface of the epitaxial layer away from the substrate, in contact with the second injection region on the side walls and the bottom surface of the second groove; a third conductive sublayer located on the surface of the second conductive sublayer away from the substrate.

[0008] Optionally, the material of the first conductive sublayer includes nickel, the material of the second conductive sublayer includes titanium, and the material of the third conductive sublayer includes aluminum.

[0009] Optionally, the semiconductor structure further includes: a second conductive layer located on a surface of the substrate away from the epitaxial layer.

[0010] Optionally, the second conductive layer includes: a fourth conductive sublayer located on the surface of the substrate away from the epitaxial layer; a fifth conductive sublayer located on the surface of the fourth conductive sublayer away from the substrate; and a sixth conductive sublayer located on the surface of the fifth conductive sublayer away from the substrate.

[0011] Optionally, the material of the fourth conductive sublayer includes titanium, the material of the fifth conductive sublayer includes nickel, and the material of the sixth conductive sublayer includes silver.

[0012] Optionally, materials of the substrate and the epitaxial layer include silicon carbide respectively.

[0013] According to another aspect of the present application, a power diode is provided, comprising: any one of the semiconductor structures described above.

[0014] By applying the technical solution of the present application, in the semiconductor structure of the present application, a first trench and a second trench of different depths are formed in the epitaxial layer, and a first injection region is formed on the sidewall and bottom surface of the first trench, and a second injection region is formed on the sidewall and bottom surface of the second trench. The doping types of the first injection region and the second injection region are different from those of the epitaxial layer, thereby forming a PN junction, and forming a first conductive layer that contacts the first injection region, the second injection region and the epitaxial layer respectively. The present application sets trenches of different depths in the epitaxial layer, and forms ion injection regions in trenches of different depths. On the basis of ensuring that the forward voltage drop of the device is low, the reverse leakage current of the device is ensured to be low, thereby improving the performance and stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present application is shown;

[0017] Figure 2 A schematic diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0018] Figures 3 to 8 A schematic diagram of a structure obtained after each process step of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown.

[0019] The drawings include the following reference numerals:

[0020] 10. substrate; 11. epitaxial layer; 12. first injection region; 13. second injection region; 14. first conductive layer; 15. first conductive sublayer; 16. second conductive sublayer; 17. third conductive sublayer; 18. second conductive layer; 19. fourth conductive sublayer; 20. fifth conductive sublayer; 21. sixth conductive sublayer; 22. intermediate epitaxial layer; 23. first trench; 24. second sub-trench; 25. first sub-trench; 26. second trench. DETAILED DESCRIPTION

[0021] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] As introduced in the background technology, the prior art has the problem of poor performance of semiconductor structures. To solve this technical problem, the embodiments of the present application provide a semiconductor structure and a power diode.

[0025] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0026] An embodiment of the present application provides a semiconductor structure. Figure 1 Schematically shows a cross-sectional structure diagram of a semiconductor structure provided according to an embodiment of the present application. Figure 1 As shown, the semiconductor structure comprises:

[0027] Substrate 10;

[0028] Specifically, the conductivity type of the substrate 10 may be P type or N type.

[0029] An epitaxial layer 11 is located on the surface of the substrate 10;

[0030] Specifically, the epitaxial layer 11 is located on one side surface of the substrate 10 , and the conductivity type of the epitaxial layer 11 can be P type or N type.

[0031] A first trench, located in the epitaxial layer 11;

[0032] A first implantation region 12, located on the sidewalls and bottom surface of the first trench, wherein the first implantation region 12 and the epitaxial layer 11 have different doping types;

[0033] Specifically, the first implantation region 12 is located in the epitaxial layer 11 and wraps around the sidewall and bottom of the first trench. The first implantation region 12 and the epitaxial layer 11 have different doping types, so that the first implantation region 12 and the epitaxial layer 11 form a PN junction.

[0034] a second trench, located in the epitaxial layer 11, spaced apart from the first trench, and having a depth different from that of the first trench;

[0035] Specifically, the depth is the depth of the first trench and the second trench in the thickness direction of the semiconductor structure.

[0036] A second implantation region 13, located on the sidewalls and bottom surface of the second trench, wherein the second implantation region 13 and the epitaxial layer 11 have different doping types;

[0037] Specifically, the second implantation region 13 is located in the epitaxial layer 11 and surrounds the sidewall and bottom of the second trench. The second implantation region 13 and the epitaxial layer 11 have different doping types, so that the second implantation region 13 and the epitaxial layer 11 form a PN junction.

[0038] The first conductive layer 14 is located in the first trench, the second trench and on the surface of the epitaxial layer 11 away from the substrate 10 , and the first conductive layer 14 is in contact with the first implantation region 12 and the second implantation region 13 , respectively.

[0039] Through the embodiments, in the semiconductor structure of the present application, a first trench and a second trench of different depths are formed in the epitaxial layer, and a first injection region is formed on the sidewall and bottom surface of the first trench, and a second injection region is formed on the sidewall and bottom surface of the second trench. The doping types of the first injection region and the second injection region are different from those of the epitaxial layer, thereby forming a PN junction, and forming a first conductive layer that contacts the first injection region, the second injection region, and the epitaxial layer, respectively. The present application sets trenches of different depths in the epitaxial layer, and forms ion injection regions in trenches of different depths. On the basis of ensuring that the forward voltage drop of the device is low, the reverse leakage current of the device is ensured to be low, thereby improving the performance and stability of the device.

[0040] Specifically, the doping type of the substrate can be set to be the same as the doping type of the epitaxial layer. The doping concentration of the substrate is greater than the doping concentration of the epitaxial layer. The first injection region and the second injection region are both high-doping regions, and the doping concentrations of the two can be the same or different.

[0041] In one alternative, Figure 4 As shown, the second groove 26 includes a first sub-groove 25 and a second sub-groove 24 that are connected. The first sub-groove 25 is located on a side of the second sub-groove 24 close to the substrate 10. The width of the first sub-groove 25 is smaller than the width of the second sub-groove 24. The depth of the first sub-groove 25 is smaller than the depth of the second sub-groove 24. That is, the second groove is in a "T" shape. Figure 1As shown, the second injection region 13 is located on the sidewalls of the first sub-groove, on the bottom surface of the first sub-groove, on the sidewalls of the second sub-groove, and on the bottom surface of the second sub-groove. In this embodiment, by providing a "T"-shaped groove and forming a second injection region that wraps the "T"-shaped groove, when the semiconductor structure is reverse biased, the second injection region can protect the first injection region in the first groove due to the deep depletion layer of the second injection region; and the width and depth of the first sub-groove are both small, so that the second injection region located in the first sub-groove is small, which can further ensure that the forward conduction current of the semiconductor structure is large and the device has a strong high-voltage resistance.

[0042] Specifically, the width is the width of the first sub-groove and the second sub-groove in a direction perpendicular to the thickness of the semiconductor structure. The orthographic projection of the first sub-groove on the substrate is located in the orthographic projection of the second sub-groove on the substrate.

[0043] In a more specific embodiment, the depth of the second sub-groove is the same as the depth of the first groove, and the width of the second sub-groove is greater than the width of the first groove. By setting the depth of the second sub-groove to be the same as that of the first groove, under the premise of minimum chip area, the device has a strong current capacity and a large depletion region area, and the area of ​​the semiconductor structure is not wasted; in addition, by setting the width of the second sub-groove to be greater than the width of the first groove, the difficulty of manufacturing the first sub-groove is ensured to be relatively small, thereby avoiding the problem of high process cost of the overall device.

[0044] The first conductive layer serves as an electrode terminal of the semiconductor structure. In actual application, the first conductive layer can be a single-layer film structure or a multi-layer film structure.

[0045] In order to further improve the device performance of the semiconductor structure, in some other exemplary embodiments of the present application, Figure 1As shown, the first conductive layer 14 includes: a first conductive sublayer 15, located in the first groove, in contact with the first injection region 12 on the sidewall and bottom of the first groove, and the surface of the first conductive sublayer 15 away from the substrate 10 is flush with the surface of the epitaxial layer 11 away from the substrate; a second conductive sublayer 16, located in the second groove, on the surface of the first conductive sublayer 15 away from the substrate 10 and on the surface of the epitaxial layer 11 away from the substrate 10, in contact with the second injection region 13 on the sidewall and bottom of the second groove; a third conductive sublayer 17, located on the surface of the second conductive sublayer 16 away from the substrate 10. In this embodiment, the first conductive sublayer is formed in the first groove, and forms an ohmic contact with the first injection region. The second conductive sublayer is formed on the surface of the epitaxial layer and in the second groove, and forms a Schottky contact with the epitaxial layer and an ohmic contact with the second injection region. Compared with the planar structure, the groove structure makes the contact area between the first conductive sublayer and the first injection region, and the contact area between the second conductive sublayer and the second injection region larger, and the ohmic discharge area is larger, thereby ensuring that the semiconductor device has a strong surge resistance capability. In addition, by forming ohmic contact and Schottky contact, the surge resistance capability of the device is further improved, and the forward voltage drop of the device is further reduced while ensuring the voltage resistance performance of the device.

[0046] Specifically, the second conductive sublayer is located in the first sub-groove and the second sub-groove, and contacts the second injection region on the sidewall and bottom of the first sub-groove and the second injection region on the sidewall and bottom of the second sub-groove respectively. The surface of the second conductive sublayer away from the substrate is a plane.

[0047] Those skilled in the art can flexibly set the specific materials of the first conductive sublayer, the second conductive sublayer and the third conductive sublayer according to actual needs, such as a film layer formed by a single conductive material or a film layer formed by mixing multiple conductive materials. In this embodiment, the material of the first conductive sublayer includes nickel, the material of the second conductive sublayer includes titanium, and the material of the third conductive sublayer includes aluminum.

[0048] Furthermore, the first conductive sublayer is a nickel layer, the second conductive sublayer is a titanium layer, and the third conductive sublayer is an aluminum layer. Since nickel is resistant to high temperatures and has good mechanical properties, titanium has good corrosion resistance and electrical conductivity, and aluminum has high electrical conductivity and thermal conductivity, the three together can ensure the electrode stability and electrical conductivity of the semiconductor device, and the laminated structure of the nickel layer, titanium layer and aluminum layer can ensure the resistance performance of the device, so that the device has good electrical conductivity and stability, and can also improve the thermal resistance performance of the device, reduce heat conduction, and protect the device from high temperature; in addition, the titanium layer can also provide protection and extend the service life of the semiconductor device, thereby further ensuring the performance and reliability of the device.

[0049] In some embodiments of the present application, Figure 2 A schematic cross-sectional structure diagram of a semiconductor structure according to another embodiment of the present application is shown as an example. Figure 2 As shown, the semiconductor structure further includes: a second conductive layer 18, which is located on the surface of the substrate 10 away from the epitaxial layer 11. In this embodiment, the second conductive layer is formed on the back side of the substrate as another electrode terminal of the semiconductor structure.

[0050] In actual application, the second conductive layer may be a single-layer film structure or a multi-layer film structure.

[0051] According to some other optional schemes of this application, such as Figure 2 As shown, the second conductive layer 18 includes: a fourth conductive sublayer 19, located on the surface of the substrate 10 away from the epitaxial layer 11; a fifth conductive sublayer 20, located on the surface of the fourth conductive sublayer 19 away from the substrate 10; and a sixth conductive sublayer 21, located on the surface of the fifth conductive sublayer 20 away from the substrate 10. By forming a plurality of stacked conductive sublayers as the second conductive layer, the second conductive layer is guaranteed to have high structural strength and physical properties such as thermal conductivity and electrical conductivity, thereby further ensuring good device performance of the semiconductor structure.

[0052] Specifically, an ohmic contact is formed between the fourth conductive sublayer 19 and the substrate 10 .

[0053] Those skilled in the art can flexibly set the specific materials of the fourth conductive sublayer, the fifth conductive sublayer and the sixth conductive sublayer according to actual needs, such as a film layer formed by a single conductive material or a film layer formed by mixing multiple conductive materials. In this embodiment, the material of the fourth conductive sublayer includes titanium, the material of the fifth conductive sublayer includes nickel, and the material of the sixth conductive sublayer includes silver.

[0054] Furthermore, the fourth conductive sublayer is a titanium layer, the fifth conductive sublayer is a nickel layer, and the sixth conductive sublayer is a silver layer. Since titanium, nickel, and silver each have different conductive properties and chemical properties, their laminated structure can effectively reduce the resistance of the electrode and improve the current transmission efficiency. In addition, the laminated structure of titanium, nickel, and silver can also improve the corrosion resistance of the electrode and extend the service life of the semiconductor structure, thereby improving the performance and reliability of the device.

[0055] Alternatively, if Figure 1 and Figure 2 As shown, the semiconductor structure may include only one first trench and one first injection region, or may include multiple first trenches and multiple first injection regions, the multiple first trenches are arranged in the epitaxial layer at intervals, and the first injection regions are located one-to-one on the sidewalls and bottom surface of the first trench. Similarly, the semiconductor structure may include only one second trench and one second injection region, or may include multiple second trenches and multiple second injection regions, the multiple second trenches are arranged in the epitaxial layer at intervals, and the second injection regions are located one-to-one on the sidewalls and bottom surface of the second trench. In the case where there are multiple first trenches and multiple second trenches respectively, the multiple first trenches may be located on the same side of the multiple second trenches; the first trenches and the second trenches may also be arranged alternately at intervals, and those skilled in the art may flexibly set their specific arrangement according to actual conditions.

[0056] Those skilled in the art can select any suitable material as the substrate material of the present application according to the actual device requirements, such as selecting a silicon substrate, a silicon carbide substrate, a silicon germanium substrate, an SOI substrate or a GOI substrate, etc. Similarly, those skilled in the art can select any suitable material as the epitaxial layer material of the present application according to the actual device requirements, such as silicon, silicon germanium, silicon carbide, silicon nitride or gallium nitride, etc.

[0057] In the present application, the materials of the substrate and the epitaxial layer respectively include silicon carbide.

[0058] More specifically, the substrate is a silicon carbide substrate, and the epitaxial layer is a silicon carbide epitaxial layer, that is, the semiconductor structure of the present application is a silicon carbide device. The wide bandgap and high critical breakdown electric field of silicon carbide materials themselves make them ideal semiconductor materials for making electronic devices that are resistant to high temperatures, high power, and radiation. The critical breakdown field strength of silicon carbide materials is 10 times that of silicon materials, and the bandgap and thermal conductivity of silicon carbide materials are both 3 times that of silicon materials. The concentration of intrinsic carriers is only one-tenth of that of silicon materials. These excellent physical properties make semiconductor power devices made of silicon carbide materials have great advantages in high-frequency, high-temperature, high-power, and high-irradiation environments.

[0059] Silicon carbide materials can form different crystal structures under different environments. Currently, the three commonly used crystal structures are 3C-SiC, 4H-SiC, and 6H-SiC. 4H-SiC materials have become the mainstream material for manufacturing semiconductor devices due to their higher bandgap width, hole mobility, and lower intrinsic carrier concentration.

[0060] It should be noted that the specific materials of the substrate, the epitaxial layer, the first conductive layer and the second conductive layer are not limited to the materials described above. Those skilled in the art can flexibly set them according to actual needs, and this application does not impose any specific restrictions on this.

[0061] In an exemplary embodiment of the present application, Figure 2As shown, the substrate 10 is an N-type silicon carbide substrate, the epitaxial layer 11 is an N-type silicon carbide epitaxial layer, and the doping concentration of the silicon carbide epitaxial layer is less than the doping concentration of the silicon carbide substrate; the semiconductor structure includes two first trenches and one second trench, the two first trenches are spaced apart and located on both sides of the second trench, the P-type first injection region 12 is located in the first trench one by one, specifically on the sidewall and bottom surface of the first trench, and the second trench includes a first sub-groove and a second sub-groove connected in a direction away from the substrate 10 The width and depth of the first sub-groove are respectively smaller than the width and depth of the second sub-groove, the width of the second sub-groove is larger than the width of the first groove, and the depth of the second sub-groove is the same as the depth of the first groove; the second P-type injection region 13 sequentially covers the sidewall of the second sub-groove, the bottom surface of the second sub-groove, the sidewall of the first sub-groove and the bottom surface of the second sub-groove; the first conductive sub-layer 15 is located in the first groove in a one-to-one correspondence and contacts the first injection region 12, and the first conductive sub-layer 15 is away from the substrate 1 0 is flush with the surface of the epitaxial layer 11 away from the substrate 10; the second conductive sublayer 16 is located in the first sub-groove and the second sub-groove, and contacts the second injection region 13 therein, the second conductive sublayer 16 is also in contact with the surface of the epitaxial layer 11 away from the substrate 10 and the surface of the first conductive sublayer 15 away from the substrate 10, respectively, and the surface of the second conductive sublayer 16 away from the substrate 10 is a plane; the third conductive sublayer 17 is located on the surface of the second conductive sublayer 16 away from the substrate 10, the first conductive sublayer 15, the second conductive sublayer 16 and the third conductive sublayer 17 constitute a first conductive layer 14, and the first conductive layer 14 serves as an anode of the semiconductor structure; the fourth conductive sublayer 19, the fifth conductive sublayer 20 and the sixth conductive sublayer 21 are sequentially stacked on the surface of the substrate 10 away from the epitaxial layer 11 in a direction away from the substrate 10, the fourth conductive sublayer 19, the fifth conductive sublayer 20 and the sixth conductive sublayer 21 constitute a second conductive layer 18, and the second conductive layer 18 serves as a cathode of the semiconductor structure.

[0062] An embodiment of the present application further provides a power diode, which includes any one of the semiconductor structures described above.

[0063] The power diode includes any one of the semiconductor structures, which has grooves of different depths in the epitaxial layer, and ion implantation regions are formed in the grooves of different depths. On the basis of ensuring that the forward voltage drop of the device is low, the reverse leakage current of the device is ensured to be low, thereby improving the performance and stability of the power diode and solving the problem of poor device performance of the power diode in the prior art.

[0064] In a specific embodiment, the power diode is a silicon carbide power diode. Silicon carbide material has the advantages of large bandgap, high thermal conductivity, high breakdown field strength, high electron saturation drift velocity, etc., and is particularly suitable for making high-power, high-frequency, and high-temperature semiconductor power devices.

[0065] The embodiment of the present application further provides a method for manufacturing the semiconductor structure, comprising the following steps:

[0066] Step S1: forming an initial epitaxial layer on the substrate 10, and forming a first trench 23 and a second sub-trench 24 spaced apart on the surface of the initial epitaxial layer by dry etching, wherein the first trench 23 and the second sub-trench 24 have the same depth, and the width of the first trench 23 is smaller than the second sub-trench 24, and the remaining initial epitaxial layer forms an intermediate epitaxial layer 22, and the following is obtained: Figure 3 The structure shown;

[0067] If the second sub-groove 24 is too deep, the current carrying capacity of the device will be reduced. In the present application, the depths of the first groove 23 and the second sub-groove 24 are set to be the same to ensure the voltage resistance of the device without wasting the device area. The width is set to prepare for the subsequent second-order groove process. If the width is too small, the process cost will increase.

[0068] Step S2: Figure 4 As shown, the middle epitaxial layer 22 is further dry-etched along the second sub-groove 24 to form a first sub-groove 25 below the second sub-groove 24. The depth and width of the first sub-groove 25 are respectively smaller than the depth and width of the second sub-groove 24. The first sub-groove 25 and the second sub-groove 24 constitute a second groove 26. The remaining middle epitaxial layer 22 forms an epitaxial layer 11.

[0069] Under the premise of minimizing the chip area, the width and depth settings can ensure the current capacity of the device and increase the depletion region area.

[0070] Step S3: ion implantation is performed on the first trench 23 and the second trench 26 to form a first implantation region 12 on the bottom and side of the first trench 23, and a second implantation region 13 on the bottom and side of the second trench 26. Figure 5 As shown;

[0071] The first implantation region 12 and the second implantation region 13 are formed by trench etching followed by implantation, which reduces the ion implantation capability requirement, increases the depth of the first implantation region 12 and the second implantation region 13, simplifies the process, and reduces the manufacturing cost.

[0072] Step S4: Figure 5 and Figure 6As shown, the first conductive sublayer 15 is filled in the first trench 23 and annealed at a temperature greater than 900° C. to form an ohmic contact;

[0073] Step S5: Figure 6 and Figure 7 As shown, a second conductive sublayer 16 is formed in the second trench 26 and on the exposed surface of the first conductive sublayer 15 and the epitaxial layer 11;

[0074] Step S6: Figure 8 As shown, the third conductive sublayer 17 is prepared on the surface of the second conductive sublayer 16 away from the substrate 10 by a high-temperature preparation method, the preparation temperature is greater than 400° C., and thermal annealing is performed during the preparation of the third conductive sublayer 17, the second conductive sublayer 16 and the surface of the epitaxial layer 11 form a Schottky contact, and the first conductive sublayer 15, the second conductive sublayer 16 and the third conductive sublayer 17 constitute the first conductive layer 14;

[0075] Step S7: On the surface of the substrate 10 away from the epitaxial layer 11, a fourth conductive sublayer 19, a fifth conductive sublayer 20 and a sixth conductive sublayer 21 are sequentially prepared, the fourth conductive sublayer 19 forms an ohmic contact with the substrate 10, and the fourth conductive sublayer 19, the fifth conductive sublayer 20 and the sixth conductive sublayer 21 constitute the second conductive layer 18, and the Figure 2 The structure shown.

[0076] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0077] From the above description, it can be seen that the embodiments described in this application achieve the following technical effects:

[0078] In the semiconductor structure of the present application, a first trench and a second trench of different depths are formed in the epitaxial layer, and a first injection region is formed on the sidewall and bottom surface of the first trench, and a second injection region is formed on the sidewall and bottom surface of the second trench. The doping types of the first injection region and the second injection region are different from those of the epitaxial layer, thereby forming a PN junction, and forming a first conductive layer that contacts the first injection region, the second injection region and the epitaxial layer respectively. The present application sets trenches of different depths in the epitaxial layer, and forms ion injection regions in trenches of different depths. On the basis of ensuring that the forward voltage drop of the device is low, the reverse leakage current of the device is ensured to be low, thereby improving the performance and stability of the device.

[0079] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; an epitaxial layer located on the surface of the substrate; A first trench located in the epitaxial layer; A first implantation region, located on the sidewalls and bottom surface of the first trench, wherein the first implantation region and the epitaxial layer have different doping types; a second trench, located in the epitaxial layer and spaced apart from the first trench, wherein the depth of the second trench is different from the depth of the first trench; A second implantation region, located on the sidewalls and bottom surface of the second trench, wherein the second implantation region and the epitaxial layer have different doping types; The first conductive layer is located in the first trench, in the second trench, and on the surface of the epitaxial layer away from the substrate, and the first conductive layer is in contact with the first implantation region and the second implantation region respectively.

2. The semiconductor structure according to claim 1, characterized in that: The second groove comprises a first sub-groove and a second sub-groove that are connected, the first sub-groove is located at a side of the second sub-groove close to the substrate, the width of the first sub-groove is smaller than the width of the second sub-groove, and the depth of the first sub-groove is smaller than the depth of the second sub-groove; The second implantation region is located on a sidewall of the first sub-trench, on a bottom surface of the first sub-trench, on a sidewall of the second sub-trench, and on a bottom surface of the second sub-trench.

3. The semiconductor structure according to claim 2, characterized in that: The depth of the second sub-groove is the same as that of the first groove, and the width of the second sub-groove is greater than that of the first groove.

4. The semiconductor structure according to claim 1, characterized in that The first conductive layer comprises: a first conductive sublayer, located in the first trench and in contact with the first injection region on the sidewall and bottom of the first trench, wherein a surface of the first conductive sublayer away from the substrate is flush with a surface of the epitaxial layer away from the substrate; a second conductive sublayer located in the second trench, on a surface of the first conductive sublayer away from the substrate and on a surface of the epitaxial layer away from the substrate, and in contact with the second injection region on the sidewall and bottom of the second trench; The third conductive sublayer is located on a surface of the second conductive sublayer away from the substrate.

5. The semiconductor structure according to claim 4, characterized in that: The material of the first conductive sublayer includes nickel, the material of the second conductive sublayer includes titanium, and the material of the third conductive sublayer includes aluminum.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The semiconductor structure further comprises: The second conductive layer is located on the surface of the substrate away from the epitaxial layer.

7. The semiconductor structure according to claim 6, characterized in that: The second conductive layer comprises: a fourth conductive sublayer, located on a surface of the substrate away from the epitaxial layer; a fifth conductive sublayer, located on a surface of the fourth conductive sublayer away from the substrate; The sixth conductive sublayer is located on a surface of the fifth conductive sublayer away from the substrate.

8. The semiconductor structure according to claim 7, characterized in that: The material of the fourth conductive sublayer includes titanium, the material of the fifth conductive sublayer includes nickel, and the material of the sixth conductive sublayer includes silver.

9. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The materials of the substrate and the epitaxial layer respectively include silicon carbide.

10. A power diode, characterized in that: include: The semiconductor structure according to any one of claims 1 to 9.

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