Gate drive circuit, display panel and display device

Abstract

The invention discloses a gate drive circuit, which comprises N cascaded starting-stage gate drive units, and the Nth starting-stage gate drive unit comprises an Nth virtual starting circuit and an Nth starting effective-stage gate drive circuit; the Nth-stage starting effective-stage gate driving circuit comprises a pull-up control unit, a pull-up unit and a pull-down unit; the Nth-stage virtual starting circuit is connected with a starting signal and the pull-up control unit, the pull-up control unit and the pull-down unit are respectively connected with a grid signal point, and the pull-up unit and the pull-down unit are respectively connected with an Nth-stage horizontal scanning line; and the Nth-stage virtual starting circuit is used for providing starting voltage for the pull-up control unit, so that the working voltage periods of the gate signal points of the cascaded gate driving units are consistent. According to the invention, the virtual starting circuit is added to provide the starting voltage for the pull-up control unit, so that the working voltage periods of the gate signal points of the cascaded gate driving units are consistent with each other, and the problem of abnormal display of the panel is solved.

Description

Technical Field

[0001] The present invention relates to the field of liquid crystal display technology, and in particular to a gate drive circuit, a display panel and a display device. Background Art

[0002] With the development of liquid crystal display screens, more and more liquid crystal display panels adopt a narrow-border design, using GOA (Gate Driver on Array) circuits instead of IC (integrated circuit) circuits to drive horizontal scan lines to reduce costs, and the resulting products are more suitable for borderless display panels.

[0003] The GOA circuit integrates the gate row scanning drive circuit on the thin film transistor array substrate, and scans the gate to open all the thin film transistors electrically connected to this horizontal scanning line, so that the signal voltage on the data line can be written into the pixel. When the GOA circuit is started, a signal is required to give the starting GOA circuit a starting voltage so that it can work normally. However, this may cause some node voltage cycles of the starting effective level to be different from other levels, which may cause display abnormalities in long-term use or harsh environments. Summary of the invention

[0004] In view of at least some of the problems and shortcomings in the prior art, an embodiment of the present invention discloses a gate drive circuit, a display panel and a display device to solve the problem that the node voltage of the starting effective level GOA in the existing GOA circuit is different from the node voltages of other levels GOA, resulting in display abnormality.

[0005] On the one hand, an embodiment of the present invention provides a gate driving circuit, for example, including multiple cascaded gate driving units, each stage of the gate driving unit is configured to drive a scan line, the multiple cascaded gate driving units include N cascaded starting-level gate driving units and multiple non-starting valid-level gate driving units cascaded with the N-th starting-level gate driving unit, wherein the N-th starting-level gate driving unit includes: an N-th virtual starting circuit and an N-th starting valid-level gate driving circuit; the N-th starting valid-level gate driving circuit includes: a pull-up control unit, a pull-up unit and a pull-down unit; the N-th virtual starting circuit is connected to a start signal, the N-th virtual starting circuit is connected to the pull-up control unit, the pull-up control unit is connected to a gate signal point, the pull-down unit is connected to the gate signal point and the N-th horizontal scan line, and the pull-up unit is connected to the N-th horizontal scan line; the N-th virtual starting circuit is used to provide a starting voltage for the pull-up control unit so that the operating voltage cycle of the gate signal point of each cascaded gate driving unit is consistent.

[0006] The embodiment of the present invention adds a virtual start circuit before the pull-up control unit in the starting effective stage gate driving unit. The virtual start circuit is used to provide a start voltage to the pull-up control unit, so that the working voltage cycles of the gate signal points of each cascaded gate driving unit are consistent with each other, thereby solving the problem of abnormal panel display.

[0007] In one embodiment of the present invention, the Nth level virtual start circuit includes a virtual pull-up unit and a virtual pull-down unit, the virtual pull-up unit and the virtual pull-down unit each include at least one transistor, the at least one transistor included in the virtual pull-up unit is connected to the start signal and the timing signal, and is connected to the pull-up control unit, and the at least one transistor included in the virtual pull-down unit is connected to the N+nth level horizontal scan line and the pull-up control unit, n≥1; wherein the timing signal includes m lines, n is a positive integer, and n=m / 2, N is a positive integer, and 1≤N≤m / 2.

[0008] In one embodiment of the present invention, the starting voltage includes a virtual stage pass voltage and a virtual scan voltage.

[0009] In one embodiment of the present invention, the virtual pull-up unit includes a first transistor and a second transistor, the first end of the first transistor is connected to the start signal, the second end of the first transistor is connected to the timing signal, the third end of the first transistor is connected to the virtual level transmission signal point and is used to output the virtual level transmission voltage to the pull-up control unit; the first end of the second transistor is connected to the virtual level transmission signal point, the second end of the second transistor is connected to the first transistor, and the third end of the second transistor is connected to the virtual scan signal point and is used to output the virtual scan voltage to the pull-up control unit.

[0010] In one embodiment of the present invention, the virtual pull-down unit includes a third transistor and a fourth transistor, the first end of the third transistor is connected to the N+n-th level horizontal scan line, the second end of the third transistor is connected to the virtual level signal point, and the third end of the third transistor is connected to a negative voltage; the first end of the fourth transistor is connected to the N+n-th level horizontal scan line, the second end of the fourth transistor is connected to the virtual scan signal point, and the third end of the fourth transistor is connected to a negative voltage.

[0011] In one embodiment of the present invention, the first end of the pull-up control unit is connected to the virtual stage transmission signal point, the second end of the pull-up control unit is connected to the virtual scanning signal point, and the third end of the pull-up control unit is connected to the gate signal point.

[0012] In one embodiment of the present invention, during the time period when the start signal and the timing signal connected to the virtual pull-up unit are both the second voltage H2, the Nth virtual start circuit outputs the virtual stage pass voltage and the virtual scan voltage, and the voltage of the gate signal point is converted from the low voltage H0 to the first voltage H1, wherein H0

[0013] In one embodiment of the present invention, during the time period when the start signal connected to the virtual pull-up unit is the second voltage H2 and the timing signal connected to the virtual pull-up unit is the low voltage H0, the voltage of the gate signal point changes from the first voltage H1 to the third voltage H3, and the voltage of the N-th level horizontal scan line is the second voltage H2 so that the virtual level pass voltage and the virtual scan voltage are pulled down to the low voltage H0, wherein H0

[0014] On the other hand, an embodiment of the present invention provides a display panel, for example, including the gate driving circuit as described above.

[0015] In another aspect, an embodiment of the present invention provides a display device, for example, including the display panel as described above.

[0016] ​​It can be seen from the above that the above technical features of the present invention can have one or more of the following beneficial effects: the gate driving circuit provided by the embodiment of the present invention adds a virtual starting circuit before the pull-up control unit in the starting effective stage gate driving unit, and the virtual starting circuit is used to provide a starting voltage to the pull-up control unit, so that the operating voltage cycles of the gate signal points of each cascaded gate driving unit are consistent with each other, thereby solving the problem of abnormal panel display. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0018] Figure 1 It is a schematic diagram of the traditional gate drive circuit stage transmission operation of 12 timing signals (CK) in the related art.

[0019] Figure 2 Based on Figure 1 The figure shows a schematic diagram of the input signal voltage waveform, the working node voltage waveform in the circuit, and the output voltage waveform of the traditional gate drive circuit stage transmission relationship during actual operation.

[0020] Figure 3 A schematic diagram of an exemplary circuit module of an Nth starting-stage gate driving unit provided in an embodiment of the present invention.

[0021] Figure 4 for Figure 3 An exemplary circuit module diagram of the Nth level virtual start circuit.

[0022] Figure 5 for Figure 3 Schematic diagram of an exemplary circuit module of the Nth starting effective stage gate driving circuit.

[0023] Figure 6 A schematic diagram of an input signal voltage waveform, a node voltage waveform, and an output voltage waveform of the gate driving circuit provided by an embodiment of the present invention during actual operation. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] The directional terms mentioned in the embodiments of the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only references to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention. For the purpose of understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present invention is not limited to this. When a component such as a layer, film, region or substrate is referred to as "on" another component, the component may be directly on the other component, or there may be an intermediate component. In addition, in the specification, "on..." means above or below the target component, and does not mean that it must be on the top based on gravity.

[0027] In addition, the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.

[0028] First, in one embodiment of the present invention, see Figure 1 , Figure 1 The figure is a schematic diagram of the conventional gate drive circuit stage transmission operation of 12 timing signals CK in the related art. For example, the timing signal CK refers to a timing signal line that can generate the timing signal CK, and the timing signal line is connected to the timing drive circuit of the display panel. The 12 timing signals CK can be understood as having 12 timing signal lines, and each timing signal line generates a timing signal CK. Further. Figure 1 In the figure, the red line is the level transmission signal STN required for the gate drive circuit to work. The level transmission signals ST1 to ST6 in the first 6-level gate drive units are provided by the start signal STV, and the start signal STV provides the start voltage for the pull-up control unit in the first 6-level gate drive units. Figure 1In the embodiment, starting from the 7th-level gate driving unit, the starting voltage required in its pull-up control unit is generated by the associated previous-level gate driving unit, and at the same time, the scanning voltage G7 output by the 7th-level gate driving unit will serve as a starting voltage of the pull-down unit of the 1st-level gate driving unit, so that it can pull the G1 voltage of the 1st-level gate driving unit down to a negative voltage.

[0029] In accordance with the above, Figure 2 Based on Figure 1 The schematic diagram of the gate drive circuit stage transmission relationship is shown as follows: the actual input working voltage waveform, the working node voltage waveform in the circuit, and the output voltage waveform. Figure 2 It can be seen that the start signal STV provides a start voltage to the pull-up control unit of the first 6 gate drive units. Taking the first gate drive unit corresponding to CK1 as an example, the start signal STV is cut to the second voltage H2 at time t1, and the voltage Q1 at the gate signal point of the first gate drive unit is cut from the H0 level to the first voltage H1. During the time period t1 to t2, the voltage Q1 at the gate signal point of the first gate drive unit is kept at the H1 level. During the time period t2 to t3, CK1 is the second voltage H2. At this time, the voltage Q1 at the gate signal point of the first gate drive unit is pulled up to the third voltage H3, and the scanning voltage G1 output by the first gate drive unit is also the second voltage H2.

[0030] Since the starting voltage of the pull-up control unit is generated by the associated previous gate driving unit starting from the 7th level gate driving unit, the voltage Q at the gate signal point starting from the 7th level gate driving unit to the last level of the gate driving unit, in the H1 voltage holding time period, is the same as the time length of the scanning voltage G output by the corresponding gate driving unit. When the start signal STV is cut to a high level at time t1, Q2~Q6 also cuts from H0 to the first voltage H1, and when its corresponding level CK is not cut to a high level, it is maintained at the first voltage H1. It can be seen from this that the holding time of Q2~Q6 at the H1 voltage is greater than the holding time of the other level Qn nodes at the H1 high level, and G2~G6 is analogous to this. When CK2~CK6 is cut to the second voltage H2, G2~G6 output the second voltage H2 and turn on the scan lines in sequence.

[0031] That is, in each frame, the holding time of Q2-Q6 at the H1 voltage is longer than that of other rows. Such long-term repeated voltage drop cycles cause the electrical characteristics of the gate drive circuit to drift more easily, thereby causing abnormal output of the gate drive circuit.

[0032] In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a gate driving circuit, which, for example, includes a plurality of cascaded gate driving units, wherein each gate driving unit is configured to drive a scan line. Specifically, the plurality of cascaded gate driving units include N cascaded starting-stage gate driving units and a plurality of non-starting valid-stage gate driving units cascaded with the Nth starting-stage gate driving unit. For example, in the plurality of cascaded gate driving units, the first to Nth stage gate driving units are starting-stage gate driving units, and the N+1th stage gate driving unit and subsequent gate driving units are non-starting valid-stage gate driving units. For example, the number of N is consistent with the number of timing signals CK, and the timing signal CK is connected to the timing driving circuit of the display panel.

[0033] Figure 3 For example, it is an exemplary circuit module schematic diagram of the N-th level starting gate driving unit. Specifically, the N-th level starting gate driving unit 10 includes: the N-th level virtual starting circuit 100 and the N-th level starting effective level gate driving circuit 11, and the N-th level starting effective level gate driving circuit 11 includes a pull-up control unit 200, a pull-up unit 300 and a pull-down unit 400. Among them, the N-th level virtual starting circuit 100 is connected to the start signal STV, and the N-th level virtual starting circuit 100 is also connected to the pull-up control unit 200, the pull-up control unit 200 is connected to the gate signal point Q (N), the pull-down unit 400 is connected to the gate signal point Q (N) and the N-th level horizontal scan line G (N), and the pull-up unit 300 is connected to the N-th level horizontal scan line G (N). For example, the voltage at the gate signal point Q (N) is defined as the node voltage QN, and the voltage at the N-th level horizontal scan line G (N) is defined as the scan voltage GN. The virtual start circuit 100 is used to provide a start voltage for the pull-up control unit to make the working voltage cycle of the gate signal point of each cascaded gate driving unit consistent. For example, the start voltage includes a virtual stage transmission voltage and a virtual scanning voltage.

[0034] The embodiment of the present invention adds a virtual start circuit before the pull-up control unit in the starting effective stage gate driving unit. The virtual start circuit is used to provide a start voltage to the pull-up control unit, so that the working voltage cycles of the gate signal points of each cascaded gate driving unit are consistent with each other, thereby solving the problem of abnormal panel display.

[0035] Further, the Nth stage virtual start circuit 100 includes a virtual pull-up unit 110 and a virtual pull-down unit 120, and each of the virtual pull-up unit and the virtual pull-down unit includes at least one transistor. Figure 4 , Figure 4For example, it is an exemplary circuit module schematic diagram of the N-th virtual start circuit 100. The virtual pull-up unit 110 includes a first transistor T1 and a second transistor T2, the first end (for example, the gate end) of the first transistor T1 is connected to the start signal STV, the second end (for example, the source end) of the first transistor T1 is connected to the timing signal CK, and the third end (for example, the drain end) of the first transistor T1 is connected to the virtual level transmission signal point (for example, dummy STN in the figure) and is used to output the virtual level transmission voltage to the gate end of the pull-up control unit 200 as the gate voltage of the pull-up control unit 200. Wherein, the virtual level transmission voltage is, for example, the level transmission voltage outputted by the N-th virtual start circuit 100. The first end (for example, the gate end) of the second transistor T2 is connected to the virtual level transmission signal point, the second end (for example, the source end) of the second transistor T2 is connected to the first transistor, and the third end (for example, the drain end) of the second transistor T2 is connected to the virtual scanning signal point (for example, dummyGN in the figure) and is used to output the virtual scanning voltage to the source end of the pull-up control unit 200 as the source voltage of the pull-up control unit 200. The virtual scan voltage is, for example, a scan voltage output by the Nth stage virtual start circuit 100 .

[0036] Further, see Figure 4 , the virtual pull-down unit 120 includes a third transistor T3 and a fourth transistor T4, the first end (e.g., gate end) of the third transistor T3 is connected to the N+nth level horizontal scan line G(N+n), wherein n≥1, the second end (e.g., source end) of the third transistor T3 is connected to the virtual level signal point, and the third end (e.g., drain end) of the third transistor T3 is connected to the negative voltage VSS. The first end (e.g., gate end) of the fourth transistor T4 is connected to the N+nth level horizontal scan line G(N+n), the second end (e.g., source end) of the fourth transistor T4 is connected to the virtual scan signal point, and the third end (e.g., drain end) of the fourth transistor T4 is connected to the negative voltage VSS. wherein n≥1. specifically, the timing signal CK includes m, n is a positive integer, and n=M / 2, N is a positive integer, and 1≤N≤m / 2, for example, the number of N is, for example, m / 2, and N is, for example, any positive integer from 1 to m / 2.

[0037] By connecting the drains of the third transistor T3 and the fourth transistor T4 to the negative voltage VSS, when the third transistor T3 and the fourth transistor T4 are turned on, the voltages of the virtual level signal point and the virtual scanning signal point can be pulled to a negative voltage, thereby reducing the influence of noise on the voltages of the virtual level signal point and the virtual scanning signal point, thereby enhancing the stability of the gate voltage and the source voltage of the pull-up control unit 200 in the N-th starting effective level gate driving unit 10. For example, when there is a voltage on the N+n-th level horizontal scanning line G(N+n), the third transistor T3 and the fourth transistor T4 are turned on. That is, when the timing signal CK in the N+n-th level gate driving unit corresponding to the N+n-th level horizontal scanning line G(N+n) is switched to a high level, the third transistor T3 and the fourth transistor T4 are turned on.

[0038] Further, see Figure 5 , Figure 5 For example, the schematic diagram of an exemplary circuit module of the Nth level start effective level gate driving circuit is shown. The Nth level start effective level gate driving circuit 11 includes a pull-up control unit 200, a pull-up unit 300 and a pull-down unit 400. The pull-up control unit 200 includes, for example, a fifth transistor T5, a first end (for example, a gate end) of the fifth transistor T5 is connected to the virtual level signal transmission point (for example Figure 4 in dummy STN, Figure 5 The second end (eg, source end) of the fifth transistor T5 is connected to the virtual scanning signal point (eg, Figure 4 in dummy GN, Figure 5GN-m in the figure, the third end (for example, the drain end) of the fifth transistor T5 is connected to the gate signal point Q(N). The pull-up unit 300, for example, includes a sixth transistor T6 and a seventh transistor T7, the gate end of the sixth transistor T6 is connected to the gate signal point Q(N), the source end of the sixth transistor T6 is connected to the timing signal CK, and the drain end of the sixth transistor T6 outputs the stage transfer signal STN. The gate end of the seventh transistor T7 is connected to the gate signal point Q(N), the source end of the seventh transistor T7 is connected to the timing signal CK, and the drain end of the seventh transistor T7 is connected to the Nth level horizontal scan line G(N) and outputs the scan voltage GN. The pull-down unit 400, for example, includes an eighth transistor T8 and a ninth transistor T9, the gate end of the eighth transistor T8 is connected to the N+nth level horizontal scan line G(N+n), the source end of the eighth transistor T8 is connected to the gate signal point Q(N), and the drain end of the eighth transistor T8 is connected to the negative voltage VSS. The gate terminal of the ninth transistor T9 is connected to the N+nth level horizontal scan line G(N+n), the source terminal of the ninth transistor T9 is connected to the Nth level horizontal scan line G(n), and the drain terminal of the ninth transistor T9 is connected to the negative voltage VSS. Therefore, when the timing signal CK in the N+nth level gate driving unit corresponding to the N+nth level horizontal scan line G(N+n) is switched to a high level (i.e., there is a voltage at the N+nth level horizontal scan line), the eighth transistor T8 and the ninth transistor T9 are turned on, and the voltage at the gate signal point Q(N) and the voltage at the Nth level horizontal scan line G(N) can be pulled down to the negative voltage VSS.

[0039] The embodiment of the present invention adds a virtual start circuit before the pull-up control unit in the starting effective stage gate driving unit. The virtual start circuit is used to provide a start voltage to the pull-up control unit, so that the working voltage cycles of the gate signal points of each cascaded gate driving unit are consistent with each other, thereby solving the problem of abnormal panel display.

[0040] The following takes a gate driving circuit composed of 12 timing signals CK and 6 groups of virtual start circuits as an example, and compares it with the traditional gate driving circuit of the 12 timing signals CK mentioned above to illustrate the solution provided by the present invention in detail.

[0041] In addition, the following takes a gate drive circuit composed of 12 timing signals CK and 6 sets of virtual start circuits as an example. Specifically, the first 6 start-level gate drive units respectively include virtual start circuits, the gate end of the first transistor T1 in the virtual start circuit is connected to the start signal STV, and the source ends of the first transistor T1 and the second transistor T2 in the virtual start circuit are respectively connected to CK1 to CK6.

[0042] Figure 6The gate drive circuit provided by the embodiment of the present invention is actually working, and the input signal voltage waveform, node voltage waveform and output voltage waveform are shown. Figure 6 As shown in the figure, the start signal STV is switched from the low level H0 to the second voltage H2, and CK1~CK6 are switched from the low level H0 to the second voltage H2. In the time period when the start signal STV and the timing signal CK are both the second voltage H2, the virtual pull-up units of the 6 groups of virtual start circuits respectively output the virtual stage transfer voltage ST1 (dummy ST1)~virtual stage transfer voltage ST6 (dummy ST6) and the virtual scanning voltage (dummy G1)~virtual scanning voltage (dummy G6). The output signals are respectively connected to the gate terminal and the source terminal of the fifth transistor T5 in the associated pull-up control unit, thereby providing a starting voltage for the pull-up control units of the first 6 starting valid stages of the gate drive circuit.

[0043] Specifically, during the time period t1 to t2, the virtual stage transmission voltage ST1 (dummy ST1) and the virtual scanning voltage (dummy G1) are both the second voltage H2. At this time, the node voltage Q1 at the gate gate signal point Q(1) of the first-stage starting effective stage gate driving unit is switched from H0 to the intermediate voltage H1, wherein H0

[0044] In the time period t2 to t3 (i.e., the time period in which the start signal STV connected to the virtual pull-up unit of the first-level virtual start circuit in the first-level start-level gate driving unit is the second voltage H2, and the timing signal CK1 connected to the virtual pull-up unit in the first-level start effective level gate driving unit is the low level H0), the voltage Q1 of the gate signal point in the first-level start effective level gate driving unit changes from the first voltage H1 to the third voltage H3, and at this time, the voltage G1 of the first-level horizontal scan line is the second voltage H2, so that the virtual level transmission voltage ST1 (dummy ST1) and the virtual scan voltage (dummy G1) are pulled down to the low level H0 through the third transistor T3 and the fourth transistor T4 in the virtual start circuit, wherein H0

[0045] As can be seen from the above, the time Q2-Q6 maintains at the H1 level is the same as the time of other row node voltages Qn, which can avoid that Q2-Q6 is at the H1 level longer than other rows in each frame. That is, the working voltage cycle of the gate signal points of multiple cascaded starting effective stage gate driving units is consistent.

[0046] ​​To summarize, the embodiment of the present invention adds a virtual start circuit before the pull-up control unit in the starting effective stage gate driving unit. The virtual start circuit is used to provide a starting voltage to the pull-up control unit, so that the operating voltage cycles of the gate signal points of each cascaded gate driving unit are consistent with each other, thereby solving the problem of abnormal panel display.

[0047] In addition, the present invention further provides a display panel, for example. The display panel includes the aforementioned gate driving circuit, which will not be described in detail here.

[0048] Furthermore, the present invention also provides a display device, for example, and the display device includes the aforementioned display panel, which will not be described in detail here.

[0049] It can be understood that the aforementioned embodiments are merely exemplary descriptions of the present invention. The technical solutions of the various embodiments can be arbitrarily combined and used in combination, provided that the technical features do not conflict, the structures do not contradict, and the purpose of the present invention is not violated.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate driving circuit, comprising a plurality of cascaded gate driving units, each of which is configured to drive a scan line, characterized in that: The plurality of cascaded gate driving units include N cascaded starting-stage gate driving units and a plurality of non-starting effective-stage gate driving units cascaded with the N-th starting-stage gate driving unit, wherein the N-th starting-stage gate driving unit includes: an N-th virtual starting circuit and an N-th starting effective-stage gate driving circuit; the N-th starting effective-stage gate driving circuit includes: a pull-up control unit, a pull-up unit and a pull-down unit; The Nth level virtual start circuit is connected to the start signal, the Nth level virtual start circuit is connected to the pull-up control unit, the pull-up control unit is connected to the gate signal point, the pull-down unit is connected to the gate signal point and the Nth level horizontal scan line, and the pull-up unit is connected to the Nth level horizontal scan line; The Nth stage virtual start circuit is used to provide a start voltage for the pull-up control unit, so that the operating voltage cycle of the gate signal point of each of the cascaded gate driving units is consistent.

2. The gate driving circuit according to claim 1, wherein: The Nth level virtual start circuit includes a virtual pull-up unit and a virtual pull-down unit, each of the virtual pull-up unit and the virtual pull-down unit includes at least one transistor, the at least one transistor included in the virtual pull-up unit is connected to the start signal and the timing signal, and is connected to the pull-up control unit, and the at least one transistor included in the virtual pull-down unit is connected to the N+nth level horizontal scan line and the pull-up control unit, n≥1; The timing signal includes m signals, n is a positive integer, and n=m / 2, N is a positive integer, and 1≤N≤m / 2.

3. The gate driving circuit according to claim 2, characterized in that: The starting voltage includes a virtual stage pass voltage and a virtual scan voltage.

4. The gate driving circuit according to claim 3, characterized in that: The virtual pull-up unit includes a first transistor and a second transistor, the first end of the first transistor is connected to the start signal, the second end of the first transistor is connected to the timing signal, and the third end of the first transistor is connected to the virtual level transmission signal point and is used to output the virtual level transmission voltage to the pull-up control unit; The first end of the second transistor is connected to the virtual level signal point, the second end of the second transistor is connected to the first transistor, and the third end of the second transistor is connected to the virtual scan signal point and is used to output the virtual scan voltage to the pull-up control unit.

5. The gate driving circuit according to claim 4, characterized in that: The virtual pull-down unit comprises a third transistor and a fourth transistor, wherein a first end of the third transistor is connected to the N+nth level horizontal scan line, a second end of the third transistor is connected to the virtual level signal transmission point, and a third end of the third transistor is connected to a negative voltage; The first end of the fourth transistor is connected to the N+nth level horizontal scan line, the second end of the fourth transistor is connected to the virtual scan signal point, and the third end of the fourth transistor is connected to a negative voltage.

6. The gate driving circuit according to claim 5, characterized in that: The first end of the pull-up control unit is connected to the virtual stage transmission signal point, the second end of the pull-up control unit is connected to the virtual scanning signal point, and the third end of the pull-up control unit is connected to the gate signal point.

7. The gate driving circuit according to claim 6, characterized in that: In the time period when the start signal connected to the virtual pull-up unit and the timing signal are both the second voltage H2, the Nth virtual start circuit outputs the virtual stage pass voltage and the virtual scan voltage, and the voltage of the gate signal point is converted from the low voltage H0 to the first voltage H1, wherein H0 <H1<H2。 8. The gate driving circuit according to claim 7, wherein: In the time period when the start signal connected to the virtual pull-up unit is the second voltage H2 and the timing signal connected to the virtual pull-up unit is the low voltage H0, the voltage of the gate signal point changes from the first voltage H1 to the third voltage H3, and the voltage of the N-th level horizontal scan line is the second voltage H2 so that the virtual level pass voltage and the virtual scan voltage are pulled down to the low voltage H0, wherein H0 <H1<H2<H3。 9. A display panel, characterized in that: Comprising a gate drive circuit as described in any one of claims 1-8.

10. A display device, characterized in that: Comprising a display panel as claimed in claim 9.

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