Virtual channel counter device based on single-port RAM and its application

Abstract

The present invention provides a virtual channel counter device based on a single-port RAM, comprising a host computer software and an FPGA unit that cooperate with each other, the FPGA unit comprising a register and an external source file data frame generation module, a virtual channel identifier extraction module, a delay module, a single-port RAM, an AOS data unit processing module and an AOS data frame generation module that are serially connected in sequence, the AOS data frame generation module comprising a FIFO memory that serves as a temporary storage function; the output end of the host computer software is connected to the input end of the external source file data frame generation module, the output end of the external source file data frame generation module is also connected to the input end of the AOS data frame generation module, the register is connected to the external source file data frame generation module, and the output end of the delay module is also connected to the input end of the AOS data unit processing module.

Description

Technical Field

[0001] The present disclosure relates to the field of satellite measurement and control and satellite testing, and in particular to a virtual channel counter device based on a single-port RAM and an application method thereof. Background Art

[0002] Satellite testing is based on establishing a satellite-to-ground communication channel between the ground test system and the satellite, exchanging information between the satellite and the ground through the satellite-to-ground communication channel, and completing various satellite test items. On the one hand, the ground test system sends ground remote control commands to the satellite through the satellite-to-ground communication channel to set and control the status of the satellite; on the other hand, the ground test system receives telemetry data transmitted from the satellite through the satellite-to-ground communication channel to obtain the current health status of the satellite, receives digital data transmitted from the satellite, and analyzes the operating status and results of the satellite payload. During satellite testing, a satellite usually requires a ground measurement and control communication node and a ground digital communication node. The ground measurement and control communication node is used to establish measurement and control connections between the satellite and the ground, and the ground digital communication node is used to establish digital connections between the satellite and the ground.

[0003] AOS (Advanced Orbiting Systems) data format is the most commonly used data format in the field of satellite measurement and control and satellite testing.

[0004] Virtual Channel (VC) divides the physical channel into multiple logical channels. Each logical channel only supports one service and data type, and is assigned an identifier to distinguish each other. Each logical channel occupies the physical channel by time division multiplexing, so that multiple higher-level user data share a space physical channel. Such a logical channel is a virtual channel. During the ground test, the data frame sent is generated by the satellite simulator. The internal data source can be used, and external source files are often used to simulate different satellite data. The generation of external data frames is flexible and convenient. According to the test needs, a variety of frame structures can be designed. Different virtual channel identifiers are added to the header of each frame. Multiple data frames are placed in a data source file, and the upper computer software writes them into FPAG (Field Programmable Gate Array) through DAM (Direct Memory Access). In order to test the correctness of the equipment, it is necessary to re-count the data frames with different virtual channel identifiers to check whether the link between the sender and the receiver is working properly, whether the signal-to-noise ratio is stable, and whether there is frame loss. When the FPGA receives an external source file, it generates an external source file data frame, and the external source file data frame has a virtual channel identifier VCID (Virtual Channel Identifier), which represents the type identifier of the virtual channel.

[0005] When recounting different virtual channels due to a disconnection in the virtual channel identifier, the traditional method is to use FIFO (First in First Out) to cache data, extract the virtual channel identifier, and then count the virtual channel frames. This greatly wastes hardware FPGA resources and increases processing latency.

[0006] In this regard, there is currently no technical solution on the market to solve the above technical problems. Summary of the invention

[0007] In view of the above technical problems in the related art, the present disclosure proposes a virtual channel counter device based on a single-port RAM, which can overcome the above deficiencies in the prior art.

[0008] To achieve the above technical objectives, the technical solution of the present disclosure is implemented as follows:

[0009] The first object of the present disclosure is to provide a virtual channel counter device based on a single-port RAM, comprising a host computer software and an FPGA unit that cooperate with each other, the FPGA unit comprising a register and an external source file data frame generation module, a virtual channel identifier extraction module, a delay module, a single-port RAM, an AOS data unit processing module and an AOS data frame generation module that are serially connected in sequence, and the AOS data frame generation module comprises a FIFO memory that serves as a temporary storage function;

[0010] The output end of the host computer software is connected to the input end of the external source file data frame generation module, the output end of the external source file data frame generation module is also connected to the input end of the AOS data frame generation module, the register is connected to the external source file data frame generation module, and the output end of the delay module is also connected to the input end of the AOS data unit processing module;

[0011] Upper computer software: used to set several system parameters, each of which includes frame length, frame format, and data rate, send the required system parameters to the register, select and transmit the external data file to the external file data frame generation module;

[0012] An external source file data frame generation module receives an external source data file, generates an external source file data frame according to the system parameters sent to the register, and transmits the data frame to the virtual channel identifier extraction module and the AOS data frame generation module respectively;

[0013] Virtual channel identifier extraction module: receiving an external source file data frame, extracting a corresponding virtual signal identifier from the external source file data frame, and passing it to the delay module;

[0014] Delay module: used to set the delay control value, perform delay processing on the received virtual signal identifier, and pass it to the single-port RAM and AOS data unit processing module;

[0015] Single-port RAM: receiving a virtual signal identifier after delay processing, generating a virtual channel frame count value corresponding to the virtual signal identifier, and transmitting the virtual channel frame count value to an AOS data unit processing module;

[0016] AOS data unit processing module: receives the virtual signal identifier from the delay module, receives the virtual channel frame count value from the single-port RAM, processes the correspondence between the virtual signal identifier and the virtual channel frame count value, synchronizes the corresponding virtual signal identifier and the virtual channel frame count value, completes the logic control of the input and output ends of the single-port RAM, and transmits the synchronized virtual channel identifier and virtual channel frame count value to the AOS data frame generation module;

[0017] AOS data frame generation module: receives the external file data frame transmitted by the external file data frame generation module, and temporarily stores it in the FIFO memory; also receives the corresponding virtual signal identifier and virtual channel frame count value processed and transmitted by the AOS data unit processing module, inserts the corresponding virtual channel identifier and virtual channel frame count into the temporarily stored external file data frame, thereby generating and outputting the AOS data frame.

[0018] During implementation, the virtual channel identifier extraction module, the delay module, the single-port RAM, and the AOS data unit processing module perform counting operations on the external source file data frames, and the AOS data frame generation module completes the insertion of the temporarily stored external source file data frames and the counting results (corresponding virtual channel identifiers, virtual channel frame counts, representing corresponding VCIDs, VCID frame counts), thereby generating and outputting AOS data frames. The AOS data frame generation module and the FIFO memory can be coordinated using existing technologies, which is common knowledge in the industry. The host computer software sets system parameters, which is common knowledge or customary means. The present disclosure does not make improvements to this, and it can be implemented using existing technologies.

[0019] Preferably, the host computer software transmits the external source data file to the external source file data frame generation module through DMA (Direct Memory Access).

[0020] Preferably, the delay module extracts a 6-bit virtual channel identifier from a fixed position of the virtual channel identifier in each of the external source file data frames, and performs delay processing on the extracted virtual channel identifier;

[0021] The delayed virtual channel identifier is input as the input terminal addr of the RAM.

[0022] Preferably, the output terminal douta of the single-port RAM 405 is connected to the input terminal dina, and the value of the output terminal douta is first increased by 1 when being transmitted to the input terminal dina, so the value of the input terminal dina is updated to the value of the output terminal douta plus 1.

[0023] Preferably, in the delay processing of the delay module, the virtual signal identifier is delayed by one system clock cycle.

[0024] Preferably, the frequency of a system clock is 200 MHz.

[0025] Preferably, the system parameters are set according to the frame length, frame format and data rate of the specified user.

[0026] Preferably, the frame length, frame format and data rate of the external source file data frame are consistent with the frame length, frame format and data rate of the system parameters sent to the register.

[0027] The second object of the present disclosure is to provide an application method of the virtual channel counter device based on a single-port RAM, comprising the following steps:

[0028] S1 Pre-order preparation: setting the system parameters through the host computer software and sending them to the register of the FPGA unit; the FPGA unit initializes the input terminal din value of the single-port RAM to 0;

[0029] S2 generates a data frame stream: the host computer software continuously transmits the exogenous data file selected locally to the exogenous file data frame generation module, and the exogenous file data frame generation module continuously generates a plurality of exogenous file data frame sets, and sequentially transmits the continuously generated exogenous file data frame sets to the virtual channel identifier extraction module and the AOS data frame generation module; wherein each of the exogenous file data frame sets includes a plurality of exogenous file data frames;

[0030] S3 starts external iteration: the virtual channel identifier extraction module and the AOS data frame generation module receive one of the external source file data frame sets in sequence respectively, and use it as the current frame set, the current frame set represents a single external source file data frame set being processed by the FPGA unit, and the AOS data frame generation module temporarily stores the current frame set in the FIFO memory; the external iteration is the sequential iteration operation performed on all the external source file data frame sets generated by the upper computer software, specifically S3--S13;

[0031] S4 starts inner iteration: the virtual channel identifier extraction module sequentially extracts an external source file data frame from the current frame set as the current frame, that is, starts a single counting operation for the current frame; the inner iteration is an iterative operation performed on all external source file data frames in the current frame set, specifically S4-S10;

[0032] S5 identifies VCID:

[0033] S5.1: First, the virtual channel identifier extraction module extracts the virtual channel identifier in the current frame, and the virtual channel identifier is recorded as VCID, that is, identifies the type of virtual channel to which the current frame belongs;

[0034] S5.2: Then, the VCID is passed to the delay module by the virtual channel identifier extraction module, and the delay module performs delay processing on the VCID;

[0035] S5.3: Finally, the delay module transmits the VCID after delay processing to the single-port RAM and the AOS data unit processing module respectively;

[0036] S6 generates an address: the address end addr of the single-port RAM receives the VCID transmitted by S4, thereby taking the VCID as the addr value;

[0037] S7: the output end douta value of the single-port RAM is used as the virtual channel frame count value corresponding to the addr value; the virtual channel frame count value represents the counter value under the virtual channel type to which the current frame belongs, and is used to count the current frame according to the virtual channel type represented by the VCID;

[0038] S8 executes counting: the output end douta value of the single-port RAM is output, and the output end douta value is increased by 1 during the output process, and is transmitted to the input end dina and the AOS data unit processing module of the single-port RAM respectively; therefore, the input end dina value is updated to the value after the output end douta value is increased by 1, and similarly, the AOS data unit processing module also obtains the value after the output end douta value is increased by 1; thereby, the virtual channel frame count value under the VCID is increased by 1---that is, the current counting operation of the current frame is included in the result;

[0039] S9 corresponds VCID and count value: the AOS data unit processing module processes the received output end douta value plus 1 and the VCID into a corresponding relationship and stores them, the output end douta value plus 1 represents the virtual channel frame count value after the current frame count corresponding to the addr value, and the VCID is used as the addr value, so the VCID and the virtual channel frame count value correspond to each other, thereby realizing the correspondence between the virtual signal identifier VCID and the virtual channel frame count value after this count;

[0040] S10 determines whether to end the inner iteration: if the current frame is the last external source file data frame extracted from the current frame set, it means that the current frame set has been processed and the inner iteration should be ended, and then continue to S11; otherwise, it means that the current frame set has not been processed and the inner iteration should be continued, so return to S4;

[0041] S11 synchronization processing: the AOS data unit processing module synchronizes all corresponding address end addr values ​​and virtual channel frame counts respectively to ensure that the corresponding relationship between the corresponding address end addr values ​​and the virtual channel frame counts is consistent, and then transmits all synchronized corresponding virtual channel identifiers and virtual channel frame count values ​​to the AOS data frame generation module;

[0042] S12 outputs AOS: the AOS data frame generation module receives the corresponding virtual signal identifier and virtual channel frame count value transmitted by the AOS data unit processing module, continues to insert the corresponding virtual channel identifier and virtual channel frame count into the external source file data frame temporarily stored in the FIFO memory, and finally generates and outputs AOS data;

[0043] S13 determines whether to end the external iteration: if the host computer software has stopped generating work, and the current frame set is the last external source file data frame set received by the virtual channel identifier extraction module, it means that all the external source file data frame sets have been processed, so the work is stopped; otherwise, it means that there are other external source file data frame sets that have not been processed, so return to S3.

[0044] Preferably, the S2 specifically includes the following steps:

[0045] S2.1: The host computer software selects the external data file from the local computer;

[0046] S2.2: The host computer software transmits the external data file to the external file data frame generation module;

[0047] S2.3: the external source file data frame generation module generates a plurality of external source file data frame sets according to the system parameters and based on the external source data file;

[0048] S2.4: The host computer software transmits all the external source file data frame sets to the virtual channel identifier extraction module in sequence, thereby ensuring that the virtual channel identifier extraction module can process them in sequence.

[0049] Preferably, the S5 specifically includes the following steps:

[0050] S5.1: The virtual channel identifier extraction module extracts the virtual channel identifier VCID in the current frame to identify the type of VCID to which the current frame belongs;

[0051] S5.2: the virtual channel identifier extraction module performs delay processing on the VCID;

[0052] S5.3: The virtual channel identifier extraction module transmits the delayed VCID to the single-port RAM.

[0053] Compared with the prior art, the present invention has the following beneficial effects: (a) The present invention provides a virtual channel counter device based on a single-port RAM, which solves the problem in the prior art that the virtual channel frame counting is performed after the virtual channel identifier is extracted due to the use of FIFO to cache data, thereby causing a huge waste of hardware FPGA resources and increasing the system processing delay.

[0054] (ii) The present disclosure adopts a method based on a single-port RAM to implement virtual channel frame counting under different virtual channel identifiers.

[0055] (III) The present disclosure uses a single-port RAM module to concisely and quickly implement virtual channel frame counting under different virtual channel identifiers. This method has extremely low FPGA resource occupancy and reduces system processing delay.

[0056] (iv) The present disclosure can flexibly adapt to various satellite simulation test requirements according to different modulation modes, frame lengths, frame formats and data rates.

[0057] (V) The present disclosure adopts a modular design, and the number of users can be easily increased when needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 It is a structural schematic diagram of a virtual channel counter device based on a single-port RAM according to an embodiment of the present disclosure.

[0060] Figure 2 This is a principle block diagram of the single-port RAM described in the embodiment of the present disclosure, which is the prior art.

[0061] Figure 3 This is a schematic diagram of the composition of the first 5 bytes of the header of the external file data frame described in an embodiment of the present disclosure. The fixed position of the virtual channel identifier in the external file data frame can be clearly seen, which is existing common knowledge.

[0062] Figure 4 The invention discloses an application of a virtual channel counter device based on a single-port RAM according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0064] like Figure 1-4 As shown, in order to facilitate the understanding of the above technical solutions of the present disclosure, the above technical solutions of the present disclosure are described in detail below through specific usage methods.

[0065] The first object of the present disclosure is to provide a virtual channel counter device based on a single-port RAM, comprising a host computer software 401 and an FPGA unit that cooperate with each other, the FPGA unit comprising a register 408 and an external source file data frame generation module 402, a virtual channel identifier extraction module 403, a delay module 404, a single-port RAM 405, an AOS data unit processing module 406 and an AOS data frame generation module 407 that are serially connected in sequence, and the AOS data frame generation module 407 comprises a FIFO memory 4071 that serves as a temporary storage function;

[0066] The output end of the host computer software 401 is connected to the input end of the external file data frame generation module 402, the output end of the external file data frame generation module 402 is also connected to the input end of the AOS data frame generation module 407, the register 408 is connected to the external file data frame generation module 402, and the output end of the delay module 404 is also connected to the input end of the AOS data unit processing module 406;

[0067] The upper computer software 401 is used to set a number of system parameters, each of which includes a frame length, a frame format, and a data rate, and sends the required system parameters to the register 408, and selects and transmits an external data file to the external file data frame generation module 402;

[0068] The external source file data frame generation module 402 receives the external source data file, generates the external source file data frame according to the system parameters sent to the register 408, and transmits it to the virtual channel identifier extraction module 403 and the AOS data frame generation module 407 respectively;

[0069] The virtual channel identifier extraction module 403 receives an external file data frame, extracts a corresponding virtual signal identifier from the external file data frame, and transmits the virtual signal identifier to the delay module 404;

[0070] Delay module 404: used to set the delay control value, perform delay processing on the received virtual signal identifier, and pass it to the single-port RAM 405 and the AOS data unit processing module 406;

[0071] Single-port RAM 405: receiving a virtual signal identifier after delay processing, generating a virtual channel frame count value corresponding to the virtual signal identifier, and transmitting the virtual channel frame count value to the AOS data unit processing module 406;

[0072] AOS data unit processing module 406: receives the virtual signal identifier from the delay module 404, receives the virtual channel frame count value from the single-port RAM 405, processes the correspondence between the virtual signal identifier and the virtual channel frame count value, synchronizes the corresponding virtual signal identifier and the virtual channel frame count value, completes the logic control of the input end and the output end of the single-port RAM 405, and transmits the synchronized virtual channel identifier and the virtual channel frame count value to the AOS data frame generation module 407;

[0073] AOS data frame generation module 407: receives the external file data frame transmitted by the external file data frame generation module 402, and temporarily stores it in the FIFO memory 4071; also receives the corresponding virtual signal identifier and virtual channel frame count value processed and transmitted by the AOS data unit processing module 406, inserts the corresponding virtual channel identifier and virtual channel frame count into the temporarily stored external file data frame, thereby generating and outputting the AOS data frame.

[0074] During implementation, the virtual channel identifier extraction module, the delay module, the single-port RAM, and the AOS data unit processing module perform counting operations on the external source file data frames, and the AOS data frame generation module completes the insertion of the temporarily stored external source file data frames and the counting results (corresponding virtual channel identifiers, virtual channel frame counts, representing corresponding VCIDs, VCID frame counts), thereby generating and outputting AOS data frames. The AOS data frame generation module and the FIFO memory can be coordinated using existing technologies, which is common knowledge in the industry. The host computer software sets system parameters, which is common knowledge or customary means. The present disclosure does not make improvements to this, and it can be implemented using existing technologies.

[0075] In one embodiment, the host computer software 401 transmits the external source data file to the external source file data frame generation module 402 through DMA (Direct Memory Access).

[0076] In one embodiment, the delay module 404 extracts a 6-bit virtual channel identifier from a fixed position of the virtual channel identifier in each of the external source file data frames, and performs delay processing on the extracted virtual channel identifier;

[0077] The delayed virtual channel identifier is input as the input terminal addr of the RAM.

[0078] In one embodiment, the output terminal douta of the single-port RAM 405 is connected to the input terminal dina, and the output terminal douta value is first increased by 1 during the process of being transmitted to the input terminal dina, so the input terminal dina value is updated to the value of the output terminal douta plus 1.

[0079] In one embodiment, in the delay process of the delay module 404 , the virtual signal identifier is delayed by one system clock cycle.

[0080] In one embodiment, the frequency of a system clock is 200 MHz.

[0081] In one embodiment, the system parameters are set according to the frame length, frame format, and data rate of the specified user.

[0082] In one embodiment, the frame length, frame format, and data rate of the external file data frame are consistent with the frame length, frame format, and data rate of the system parameters sent to the register 408.

[0083] The second object of the present disclosure is to provide an application method of the virtual channel counter device based on a single-port RAM, comprising the following steps:

[0084] S1 Pre-sequence preparation: the system parameters are set by the host computer software 401 and sent to the register 408 of the FPGA unit; the FPGA unit initializes the input terminal din value of the single-port RAM 405 to 0;

[0085] S2 generates a data frame stream: the host computer software 401 continuously transmits the exogenous data file selected locally to the exogenous file data frame generation module 402, and the exogenous file data frame generation module 402 continuously generates a plurality of exogenous file data frame sets, and sequentially transmits the continuously generated exogenous file data frame sets to the virtual channel identifier extraction module 403 and the AOS data frame generation module 407; wherein each of the exogenous file data frame sets includes a plurality of exogenous file data frames;

[0086] S3 starts external iteration: the virtual channel identifier extraction module 403 and the AOS data frame generation module 407 receive one of the external source file data frame sets in sequence respectively, and use it as the current frame set, the current frame set represents a single external source file data frame set being processed by the FPGA unit, and the AOS data frame generation module 407 temporarily stores the current frame set in the FIFO memory 4071; the external iteration is the sequential iteration operation performed on all the external source file data frame sets generated by the upper computer software, specifically S3--S13;

[0087] S4 starts inner iteration: the virtual channel identifier extraction module 403 sequentially extracts an external source file data frame from the current frame set as the current frame, that is, starts a single counting operation for the current frame; the inner iteration is an iterative operation performed on all external source file data frames in the current frame set, specifically S4-S10;

[0088] S5 identifies VCID:

[0089] S5.1: First, the virtual channel identifier extraction module 403 extracts the virtual channel identifier in the current frame, which is recorded as VCID, that is, identifies the type of virtual channel to which the current frame belongs;

[0090] S5.2: Then, the VCID is passed to the delay module 404 by the virtual channel identifier extraction module 403, and the delay module 404 performs delay processing on the VCID;

[0091] S5.3: Finally, the delay module 404 transmits the delayed VCID to the single-port RAM 405 and the AOS data unit processing module 406 respectively; (in the subsequent S6-S8, the single-port RAM (405) counts the current frame according to the VCID; in S9, the AOS data unit processing module (406) first stores the VCID, and then performs corresponding processing with the subsequent counting result of the single-port RAM (405));

[0092] S6 generates an address: the address end addr of the single-port RAM 405 receives the VCID transmitted by S4, and thus uses the VCID as the addr value;

[0093] S7: the output end douta value of the single-port RAM 405 is used as the virtual channel frame count value corresponding to the addr value; the virtual channel frame count value represents the counter value under the virtual channel type to which the current frame belongs, and is used to count the current frame according to the virtual channel type represented by the VCID;

[0094] S8 executes counting: the output end douta value of the single-port RAM 405 is output, and the output end douta value is increased by 1 during the output process, and is transmitted to the input end dina of the single-port RAM 405 and the AOS data unit processing module 406 respectively; therefore, the input end dina value is updated to the value after the output end douta value is increased by 1, and similarly, the AOS data unit processing module 406 also obtains the value after the output end douta value is increased by 1; thereby, the virtual channel frame count value under the VCID is increased by 1---that is, the current counting operation of the current frame is included in the result;

[0095] S9 corresponds VCID and count value: the AOS data unit processing module 406 processes the received output end douta value plus 1 and the VCID into a corresponding relationship and stores them. The output end douta value plus 1 represents the virtual channel frame count value after the current frame count corresponding to the addr value, and the VCID is used as the addr value. Therefore, the VCID and the virtual channel frame count value correspond to each other, thereby realizing the correspondence between the virtual signal identifier VCID and the virtual channel frame count value after this count;

[0096] S10 determines whether to end the inner iteration: if the current frame is the last external source file data frame extracted from the current frame set, it means that the current frame set has been processed and the inner iteration should be ended, and then continue to S11; otherwise, it means that the current frame set has not been processed and the inner iteration should be continued, so return to S4;

[0097] S11 synchronization processing: the AOS data unit processing module 406 synchronizes all corresponding address end addr values ​​and virtual channel frame counts respectively to ensure that the corresponding relationship between the corresponding address end addr values ​​and the virtual channel frame counts is consistent, and then transmits all synchronized corresponding virtual channel identifiers and virtual channel frame count values ​​to the AOS data frame generating module 407;

[0098] S12 Output AOS: The AOS data frame generation module 407 receives the corresponding virtual signal identifier and virtual channel frame count value transmitted by the AOS data unit processing module 406, and continues to insert the corresponding virtual channel identifier and virtual channel frame count into the external source file data frame temporarily stored in the FIFO memory 4071, and finally generates and outputs AOS data;

[0099] S13 determines whether to end the external iteration: if the host computer software 401 has stopped generating work, and the current frame set is the last external source file data frame set received by the virtual channel identifier extraction module 403, it means that all the external source file data frame sets have been processed, so the work is stopped; otherwise, it means that there are other external source file data frame sets that have not been processed, so return to S3.

[0100] In one embodiment, S2 specifically includes the following steps:

[0101] S2.1: The host computer software 401 selects the external data file from the local computer;

[0102] S2.2: The host computer software 401 transmits the external data file to the external file data frame generation module 402;

[0103] S2.3: the external source file data frame generation module 402 generates a plurality of external source file data frame sets according to the system parameters and based on the external source data file;

[0104] S2.4: The host computer software 401 transmits all the external source file data frame sets to the virtual channel identifier extraction module 403 in sequence, thereby ensuring that the virtual channel identifier extraction module 403 can process them in sequence.

[0105] In one embodiment, the S5 specifically includes the following steps:

[0106] S5.1: The virtual channel identifier extraction module 403 extracts the virtual channel identifier VCID in the current frame to identify the type of VCID to which the current frame belongs;

[0107] S5.2: The virtual channel identifier extraction module 403 performs delay processing on the VCID;

[0108] S5.3: The virtual channel identifier extraction module 403 transmits the delayed VCID to the single-port RAM 405.

[0109] The present disclosure can be further supplemented and understood in conjunction with the following structural principles and theoretical principles:

[0110] Structural principle: The virtual channel counter device based on single-port RAM includes:

[0111] The upper computer software 401 sends the set parameters to the register 408 corresponding to the FPGA, transfers the local external source data file to the FPGA through DMA (Direct Memory Access), and the FPGA generates an external source file data frame.

[0112] The external source file data generating module 402 generates an external source file data frame according to the set parameters and frame format and the external source data read in through the DAM.

[0113] The virtual channel identifier extraction module 403 extracts the virtual signal identifier from the corresponding data position according to the frame length and the frame format.

[0114] The delay module 404 delays the virtual channel identifier by one system clock cycle according to the set delay control value.

[0115] The single-port RAM module 405 is used to generate a data frame count value corresponding to each virtual channel identifier.

[0116] AOS data unit processing module 406, used to process the correspondence between the virtual channel identifier and the virtual channel frame count, and complete the logic control of the input and output ends of the single-port RAM;

[0117] The AOS data frame generating module 407 is used to insert a new virtual channel identifier and a virtual channel frame count, and output an AOS data frame.

[0118] In the present disclosure, the delayed virtual channel identifier is used as the address addr of the single-port RAM 405, and the initial value of the input terminal dina of the RAM is 0. The virtual channel identifier VCID of each external source file data frame is extracted once as the address addr of the single-port RAM, and then the output terminal douta of the RAM is increased by one and used as the new dina of the current addr, so as to realize the virtual channel frame count value corresponding to the current VCID to be increased by 1 and updated. The input terminal dina value of the single-port RAM 405 (i.e., the output terminal douta value + 1) can be used as the data value corresponding to each address addr. The AOS data unit processing module 406 processes the received output terminal douta value after 1 is increased with the VCID into a corresponding relationship and stores it. The output terminal douta value after 1 is increased represents the virtual channel frame count value corresponding to the addr value after the current frame count, and the VCID is used as the addr value, so the VCID and the virtual channel frame count value correspond to each other, thereby realizing that the virtual signal identifier VCID after the corresponding count corresponds to the virtual channel frame count value.

[0119] According to the set delay control value, the RAM output end and the position where the dummy fill frame count is placed in the data frame are adjusted to be aligned in terms of delay.

[0120] The AOS data frame generation module 407 generates a new AOS data frame according to the above alignment in time delay.

[0121] Working principle: In order to solve the problem in the prior art that different virtual channels are recounted due to the incompatibility of virtual channel identifiers, FIFO (First in First) is used. The invention provides a virtual channel counter device based on a single-port RAM, which comprises: generating an external source file data frame according to parameters set by a host computer, each external source file data frame contains a corresponding virtual channel identifier, the host computer monitors and sends the external source file into the FPGA, extracts and delays the VCID (virtual channel identifier) ​​in the data frame, and uses it as the address signal addr of the single-port RAM; each virtual channel identifier VCID corresponds to an independent virtual channel, that is, each address of the single-port RAM corresponds to a virtual channel, and the virtual channel is counted; the virtual channel identifier of each frame of data is extracted once as the address of the single-port RAM, the output value of the output terminal douta of the RAM is increased by one, and is used as the input of the RAM input terminal dina corresponding to the next external source data frame with the same VCID, so as to realize that all external source file data frames are counted according to different virtual channel identifiers, and a new AOS (Advanced Orbiting System) data frame is generated. The method provided in the embodiment of the present invention realizes a counting method based on a single-port RAM with extremely low resource occupancy rate, so that data frames in each AOS (Advanced Orbiting System) transmission data unit can be counted according to the virtual channel identifier.

[0122] Generate an external file data frame according to the parameters set by the host computer. Each frame of the external file data frame contains a corresponding virtual channel identifier. The host computer monitors and sends the external file to the FPGA, extracts and delays the VCID (virtual channel identifier) ​​in the data frame, and uses it as the address signal addr of the single-port RAM; each virtual channel identifier VCID corresponds to an independent virtual channel, that is, each time or when each frame is processed, the address of the single-port RAM corresponds to a virtual channel, and the virtual channel is counted; the virtual channel identifier of each frame of data is extracted once as the address of the single-port RAM, and the output value of the output end douta of the RAM is increased by one, and is used as the input of the RAM input end dina corresponding to the next external data frame with the same VCID, thereby realizing that all external file data frames are counted according to different virtual channel identifiers, and a new AOS (Advanced Orbiting System) data frame is generated. The method provided in the embodiment of the present invention realizes a counting method based on a single-port RAM with extremely low resource occupancy rate, so that the data frames in each AOS (Advanced Orbiting System) transmission data unit can be counted according to the virtual channel identifier.

[0123] For example, the following application of the virtual channel counter device is for the VCID, addr, RAM input terminal dina, RAM output terminal douta, and douta added by one in S1-S13, and the input terminal dina value is updated to the output terminal douta value after counting, as shown in the following Table 1.

[0124]

[0125] Table 1

[0126] Referring to Table 1, the addr value and virtual channel frame count in the present disclosure indicate that in a counting operation, different external file data frames are counted in units of VCID types; each VCID is a separate address addr value, and the address addr value represents a VCID; as for the corresponding data value stored in a certain address addr (i.e., a certain VCID), it is the counter value of the external file data frames under this VCID obtained by statistics - that is, the total number of external file data frames under this VCID.

[0127] For the sake of simplicity and ease of understanding, only three VCIDs are listed in Table 1 above, corresponding to three addrs - 0x1, 0x2, and 0x3F (0X represents hexadecimal, such as 0x3f represents decimal 63). Each VCID is a separate address addr value, and the address addr value represents a VCID. The corresponding data value stored in each address addr (representing a certain VCID) is the counter value of the external source file data frame under this VCID - that is, the total number of external source file data frames under this VCID. Therefore, each VCID (addr) represents the virtual channel identifier of a specific data frame, and the virtual channel identifier represents a specific virtual channel type. In this method, there are 2 virtual channel identifiers. 6 -1=63. The frame count range for each VCID (addr) is 0 to (2 24 -1), which is sufficient to meet actual needs; even if each VCID (addr) counts to the maximum value (2 24 -1), the single-port RAM will still automatically start counting from 0, which is common knowledge. If the current frame is identified as 0x1, that is, the first type of virtual channel identifier, each time 0x1 is extracted, the corresponding data stored at address 0x1 will be increased by 1, and the final accumulated number is the total number of data frames with VCID 0x1; similarly, each time 0x2 is extracted, the corresponding data stored at address 0x2 will be increased by 1, and the final accumulated number is the total number of data frames with VCID 0x2.

[0128] In summary, through the unique design of the present invention, compared with the prior art, (i) the present invention provides a virtual channel counter device based on a single-port RAM, which solves the problem in the prior art that the virtual channel frame counting is performed after the virtual channel identifier is extracted due to the use of FIFO to cache data, thereby causing a huge waste of hardware FPGA resources and increasing the system processing delay; (ii) the present invention adopts a method based on a single-port RAM to realize the virtual channel frame counting under different virtual channel identifiers; (iii) the present invention uses a single-port RAM module to simply and quickly realize the virtual channel frame counting under different virtual channel identifiers. This method has an extremely low FPGA resource occupancy rate and reduces the system processing delay; (iv) the present invention can flexibly adapt to various satellite simulation test requirements for different modulation modes, frame lengths, frame formats and data rates; (v) the present invention adopts a modular design, so the number of users can be easily increased when needed.

[0129] The above are only preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A virtual channel counter device based on a single-port RAM, characterized in that: The system comprises a host computer software (401) and an FPGA unit that cooperate with each other, wherein the FPGA unit comprises a register (408) and an external source file data frame generation module (402), a virtual channel identifier extraction module (403), a delay module (404), a single-port RAM (405), an AOS data unit processing module (406) and an AOS data frame generation module (407) that are sequentially connected in series, wherein the AOS data frame generation module (407) comprises a FIFO memory (4071) that performs a temporary storage function; The output end of the host computer software (401) is connected to the input end of the external file data frame generation module (402), the output end of the external file data frame generation module (402) is also connected to the input end of the AOS data frame generation module (407), the register (408) is connected to the external file data frame generation module (402), and the output end of the delay module (404) is also connected to the input end of the AOS data unit processing module (406); The upper computer software (401) is used to set a number of system parameters, each of which includes a frame length, a frame format, and a data rate, and sends the required system parameters to the register (408), and selects and transmits an external data file to the external file data frame generation module (402); An external source file data frame generation module (402): receives an external source data file, generates an external source file data frame according to the system parameters sent to the register (408), and transmits the frame to the virtual channel identifier extraction module (403) and the AOS data frame generation module (407); Virtual channel identifier extraction module (403): receives an external file data frame, extracts a corresponding virtual signal identifier from the external file data frame, and transmits it to a delay module (404); Delay module (404): used to set a delay control value, perform delay processing on the received virtual signal identifier, and pass it to the single-port RAM (405) and the AOS data unit processing module (406); Single-port RAM (405): receiving the virtual signal identifier after delay processing, generating a virtual channel frame count value corresponding to the virtual signal identifier, and transmitting the virtual channel frame count value to the AOS data unit processing module (406); The AOS data unit processing module (406) receives the virtual signal identifier from the delay module (404), receives the virtual channel frame count value from the single-port RAM (405), processes the correspondence between the virtual signal identifier and the virtual channel frame count value, synchronizes the corresponding virtual signal identifier and the virtual channel frame count value, completes the logic control of the input end and the output end of the single-port RAM (405), and transmits the synchronized virtual channel identifier and the virtual channel frame count value to the AOS data frame generation module (407); AOS data frame generation module (407): receives the external file data frame transmitted by the external file data frame generation module (402), and temporarily stores it in the FIFO memory (4071); In addition, the corresponding virtual signal identifier and virtual channel frame count value processed and transmitted by the AOS data unit processing module (406) are received, and the corresponding virtual channel identifier and virtual channel frame count are inserted into the temporarily stored external source file data frame, thereby generating and outputting the AOS data frame.

2. The virtual channel counter device based on single-port RAM according to claim 1, characterized in that: The host computer software (401) transmits the external data file to the external file data frame generation module (402) through DMA.

3. The virtual channel counter device based on single-port RAM according to claim 1, characterized in that: In the delay processing of the delay module (404), the virtual signal identifier is delayed by one system clock cycle.

4. The virtual channel counter device based on single-port RAM according to claim 3, characterized in that The delay module (404) extracts a 6-bit virtual channel identifier from a fixed position of the virtual channel identifier in each of the external source file data frames, and delays the extracted virtual channel identifier by one system clock cycle, where one system clock is 200 MHz; The delayed virtual channel identifier is input as the input terminal addr of the RAM.

5. The single-port RAM-based virtual channel counter device according to claim 1, characterized in that: The output terminal douta of the single-port RAM (405) is connected to the input terminal dina.

6. The single-port RAM-based virtual channel counter device according to claim 1, characterized in that ,The system parameters are set according to the frame length, frame format and data rate of the ,specified user.

7. The single-port RAM-based virtual channel counter device according to claim 1, characterized in that , the frame length, frame format and data rate of the external file data frame are consistent with the frame length, frame format and data rate of the system parameters sent to the register (408).

8. The application method of the virtual channel counter device based on single-port RAM according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1 pre-sequence preparation: the system parameters are set by the host computer software (401) and sent to the register (408) of the FPGA unit; the FPGA unit initializes the input terminal din value of the single-port RAM (405) to 0; S2 generates a data frame stream: the host computer software (401) continuously transmits the external source data file selected locally to the external source file data frame generation module (402), and the external source file data frame generation module (402) continuously generates a plurality of external source file data frame sets, and sequentially transmits the continuously generated external source file data frame sets to the virtual channel identifier extraction module (403) and the AOS data frame generation module (407); wherein each of the external source file data frame sets includes a plurality of external source file data frames; S3 starts external iteration: the virtual channel identifier extraction module (403) and the AOS data frame generation module (407) respectively receive one of the external source file data frame sets in sequence and use it as the current frame set, the current frame set represents a single external source file data frame set being processed by the FPGA unit, and the AOS data frame generation module (407) temporarily stores the current frame set in the FIFO memory (4071); S4 starts internal iteration: the virtual channel identifier extraction module (403) sequentially extracts an external source file data frame from the current frame set as the current frame, that is, starts a single counting operation for the current frame; S5 identifies VCID: S5.1: First, the virtual channel identifier extraction module (403) extracts the virtual channel identifier in the current frame, which is recorded as VCID, that is, identifies the type of virtual channel to which the current frame belongs; S5.2: Then, the VCID is passed by the virtual channel identifier extraction module (403) to the delay module (404), and the delay module (404) performs delay processing on the VCID; S5.3: Finally, the delay module (404) transmits the VCID after delay processing to the single-port RAM (405) and the AOS data unit processing module (406) respectively; S6 generates an address: the address end addr of the single-port RAM (405) receives the VCID transmitted by S4, and thus uses the VCID as the addr value; S7: prepare counting: the output end douta value of the single-port RAM (405) is used as the virtual channel frame count value corresponding to the addr value; the virtual channel frame count value represents the counter value under the virtual channel type to which the current frame belongs, and is used to count the current frame according to the virtual channel type represented by the VCID; S8 executes counting: the output end douta value of the single-port RAM (405) is output, and the output end douta value is increased by 1 during the output process, and is transmitted to the input end dina and the AOS data unit processing module (406) of the single-port RAM (405) respectively; therefore, the input end dina value is updated to the value of the output end douta value plus 1, and similarly, the AOS data unit processing module (406) also obtains the value of the output end douta value plus 1; thereby, the virtual channel frame count value under the VCID is increased by 1, that is, the current counting operation of the current frame is included in the result; S9: Corresponding VCID and count value: the AOS data unit processing module (406) processes the received output end douta value plus 1 and the VCID into a corresponding relationship and stores them. The output end douta value plus 1 represents the virtual channel frame count value after the current frame count corresponding to the addr value, and the VCID is used as the addr value. Therefore, the VCID and the virtual channel frame count value correspond to each other, thereby realizing the correspondence between the virtual signal identifier VCID and the virtual channel frame count value after this count; S10 determines whether to end the inner iteration: if the current frame is the last external source file data frame extracted from the current frame set, it means that the current frame set has been processed and the inner iteration should be ended, and then continue to S11; otherwise, it means that the current frame set has not been processed and the inner iteration should be continued, so return to S4; S11 synchronization processing: the AOS data unit processing module (406) synchronizes all corresponding address end addr values ​​and virtual channel frame counts respectively to ensure that the corresponding relationship between the corresponding address end addr values ​​and the virtual channel frame counts remains consistent, and then transmits all synchronized corresponding virtual channel identifiers and virtual channel frame count values ​​to the AOS data frame generating module (407); S12 outputs AOS: the AOS data frame generation module (407) receives the corresponding virtual signal identifier and virtual channel frame count value transmitted by the AOS data unit processing module (406), and continues to insert the corresponding virtual channel identifier and virtual channel frame count into the external source file data frame temporarily stored in the FIFO memory (4071), and finally generates and outputs AOS data; S13 determines whether to end the external iteration: if the host computer software (401) has stopped generating work, and the current frame set is the last external source file data frame set received by the virtual channel identifier extraction module (403), it means that all the external source file data frame sets have been processed, so the work is stopped; otherwise, it means that there are other external source file data frame sets that have not been processed, so return to S3.

9. The method of application according to claim 8, characterized in that The S2 specifically includes the following steps: S2.1: the host computer software (401) selects the external data file from the local computer; S2.2: the host computer software (401) transfers the external data file to the external file data frame generation module (402); S2.3: the external source file data frame generation module (402) generates a plurality of external source file data frame sets according to the system parameters and based on the external source data file; S2.4: The host computer software (401) transmits all the external source file data frame sets to the virtual channel identifier extraction module (403) in sequence, thereby ensuring that the virtual channel identifier extraction module (403) can process them in sequence.

10. The method of use according to claim 8, characterized in that The S5 specifically includes the following steps: S5.1: The virtual channel identifier extraction module (403) extracts the virtual channel identifier VCID in the current frame, and completes the identification of the VCID type to which the current frame belongs; S5.2: the virtual channel identifier extraction module (403) performs delay processing on the VCID; S5.3: The virtual channel identifier extraction module (403) transmits the VCID after delay processing to the single-port RAM (405).

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