Three-dimensional memory, preparation method thereof and memory system

Abstract

The invention provides a three-dimensional memory, a preparation method thereof, a memory system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem that the three-dimensional memory is damaged in the manufacturing process. The three-dimensional memory provided by the invention comprises a laminated structure and a channel structure. The laminated structure comprises gate layers and dielectric layers which are alternately laminated. The channel structure penetrates through the laminated structure. Wherein the gate layer comprises a gate conductive layer and a gate barrier layer, the gate barrier layer is at least located between the gate conductive layer and the channel structure, and the material of the gate conductive layer comprises Mo. According to the gate conductive layer disclosed by the invention, the use of metal tungsten can be avoided, and WF6 can be prevented from being used as a precursor in the manufacturing process of the three-dimensional memory, so that the problem that the three-dimensional memory is damaged in the manufacturing process is favorably solved, the three-dimensional memory is favorably protected, and the three-dimensional memory is prevented from being damaged.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a three-dimensional memory and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to increase storage density by arranging storage cells three-dimensionally on a substrate.

[0004] However, the related art still has the problem of damaging the three-dimensional memory during the manufacturing process of the three-dimensional structure memory. Summary of the invention

[0005] The embodiments of the present disclosure provide a three-dimensional memory and a preparation method and a storage system thereof, aiming to improve the problem of damaging the three-dimensional memory during the manufacturing process in related technologies.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a three-dimensional memory is provided, comprising a stacked structure and a channel structure. The stacked structure comprises a gate layer and a dielectric layer alternately stacked. The channel structure runs through the stacked structure. The gate layer comprises a gate conductive layer and a gate barrier layer, the gate barrier layer is at least located between the gate conductive layer and the channel structure, and the gate conductive layer is made of Mo.

[0008] In the related art, the gate conductive layer includes the material tungsten (W), and W is usually deposited by chemical vapor deposition. The tungsten of the chemical vapor deposition method can be prepared by using tungsten fluoride (WF6) as a precursor. In the process of depositing W, gaseous fluorine is produced, which will destroy the oxide. Since the material of the channel structure includes oxide, the gaseous fluorine will destroy the channel structure and cause great damage to the storage device. Here, "precursor" means that "precursor" is a specially treated compound used to synthesize and prepare other substances.

[0009] Here, "the material of the gate conductive layer includes Mo" means that the gate conductive layer only includes metal molybdenum (Mo) material, or the gate conductive layer includes Mo and other conductive materials. Through the above configuration, the gate conductive layer of the present disclosure can avoid using metal tungsten (W), and can avoid using WF6 as a precursor in the production process of the three-dimensional memory. Therefore, it is beneficial to improve the problem of damaging the three-dimensional memory during the production process, and it is beneficial to protect the three-dimensional memory and avoid the three-dimensional memory from being damaged.

[0010] In addition, in the related art, the gate layer can be constructed as a word line, and reducing the word line resistance can improve the speed of programming and erasing. Since the resistance of Mo is lower than that of W, the word line resistance in the present disclosure is lower than that in the related art, which is conducive to improving the speed of programming and erasing of the three-dimensional memory.

[0011] In some embodiments, the gate barrier layer is made of a high dielectric constant material.

[0012] In some embodiments, the gate barrier layer is made of HfO 2 .

[0013] In some embodiments, the gate barrier layer has a ferroelectric phase structure.

[0014] On the other hand, a method for preparing a three-dimensional memory is provided, comprising: forming an initial stacked structure, the initial stacked structure comprising a sacrificial layer and a dielectric layer alternately stacked. Forming a channel structure, the channel structure running through the initial stacked structure. Replacing the sacrificial layer with a gate layer. The gate layer comprises a gate conductive layer and a gate barrier layer, the gate barrier layer is at least located between the gate conductive layer and the channel structure, and the material of the gate conductive layer comprises Mo.

[0015] In some embodiments, replacing the sacrificial layer with the gate layer comprises: removing the sacrificial layer to form a gate gap, depositing HfO2 in the gate gap to form the gate barrier layer, and depositing Mo in the gate gap to form the gate conductive layer.

[0016] In some embodiments, the preparation method further includes: performing a heat treatment on the gate barrier layer so that the crystal phase structure of the gate barrier layer is in a ferroelectric phase.

[0017] In some embodiments, depositing Mo in the gate gap includes: using MoCl5 as a precursor and adopting a chemical vapor deposition process to form the gate conductive layer.

[0018] In some embodiments, depositing HfO2 in the gate gap includes: forming the gate barrier layer using an atomic layer deposition process.

[0019] On the other hand, a storage system is provided, comprising the three-dimensional memory as described in some embodiments above, and a controller, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0020] On the other hand, an electronic device is provided, comprising a circuit board and the storage system as described above, wherein the circuit board is electrically connected to the storage system.

[0021] It can be understood that the beneficial effects that can be achieved by the method for preparing the three-dimensional memory, the storage system, and the electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the three-dimensional memory described above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0023] Figure 1 is a block diagram of an electronic device according to some embodiments;

[0024] Figure 2 is a block diagram of a storage system according to some embodiments;

[0025] Figure 3 is a block diagram of a storage system according to some other embodiments;

[0026] Figure 4 is a schematic diagram of the structure of a three-dimensional memory according to some embodiments;

[0027] Figure 5 is an equivalent circuit diagram of a memory cell string according to some embodiments;

[0028] Figure 6 The simulation results of Mo atoms and HfO2 molecules obtained by first-principles calculations;

[0029] Figure 7 The simulation results of Mo atoms and ZrO2 molecules obtained by first-principles calculations;

[0030] Figure 8 The simulation results of Mo atoms and Al2O3 molecules obtained by first-principles calculations;

[0031] Fig. 9The simulation results of Mo atoms and SiO2 molecules obtained by first-principles calculations are shown in Figure 2.

[0032] Fig.10 The simulation results of Mo atoms and HfO2 molecules before and after heat treatment obtained by first-principles calculations;

[0033] Fig.11 is a principle diagram of the internal electric field of a three-dimensional memory in an erased state according to some embodiments;

[0034] Fig.12 is a schematic diagram of the internal electric field of a three-dimensional memory in a programming state according to some embodiments;

[0035] Fig.13 is a flow chart of a method for manufacturing a three-dimensional memory according to some embodiments;

[0036] Fig.14 A schematic structural diagram of a substrate formed in a method for manufacturing a three-dimensional memory according to some embodiments;

[0037] Fig.15 A schematic diagram of a structure for forming a stacked structure in a method for manufacturing a three-dimensional memory according to some embodiments;

[0038] Fig.16 A schematic diagram of a structure for forming a channel structure in a method for manufacturing a three-dimensional memory according to some embodiments;

[0039] Fig.17 is a flow chart of a method for manufacturing a three-dimensional memory according to some embodiments;

[0040] Fig.18 A schematic diagram of a structure for forming a gate gap in a method for manufacturing a three-dimensional memory according to some embodiments;

[0041] Fig.19 FIG. 4 is a schematic structural diagram of forming a gate layer in a method for manufacturing a three-dimensional memory according to some embodiments. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0043] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0045] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0046] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0047] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0048] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0049] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0050] As used in the present disclosure, whether a component (e.g., layer, structure, or device) is "on," "above," or "below" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate of the semiconductor structure in a direction perpendicular to the substrate when the substrate is located in the lowest plane of the semiconductor structure in a direction perpendicular to the substrate. The same concept is applied throughout the present disclosure to describe spatial relationships.

[0051] The transistors provided in the embodiments of the present disclosure may all be N-type transistors, or may all be P-type transistors, or a portion may be N-type transistors and the other portion may be P-type transistors.

[0052] Some embodiments of the present disclosure provide an electronic device 5000 . Figure 1 FIG. 5 is a block diagram of an electronic device 5000 provided in some embodiments of the present disclosure. Figure 1 As shown, the electronic device 5000 includes a storage system 3000 and a circuit board 4000. The storage system 3000 is electrically connected to the circuit board 4000. In addition, the electronic device 5000 may also include at least one of a central processing unit (CPU) and a cache.

[0053] Exemplarily, the electronic device 5000 can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0054] Some embodiments of the present disclosure further provide a storage system 3000. The storage system 3000 can be applied to the above-mentioned electronic device 5000. Of course, the storage system 3000 can also be applied to other electronic devices, and the present disclosure does not limit this.

[0055] Figure 2 3000 is a block diagram of a storage system 3000 provided in some embodiments of the present disclosure. Figure 2 As shown, the storage system 3000 includes a controller 2000 and a three-dimensional memory 1000. The controller 2000 is coupled to the three-dimensional memory 1000 and is configured to control the three-dimensional memory 1000 to store data. The storage system 3000 can be integrated into various types of storage devices, for example, included in the same package (for example, a universal flash storage (Universal Flash Storage, referred to as UFS) package or an embedded multimedia card (Embedded Multi Media Card, referred to as eMMC) package). That is, the storage system 3000 can be applied to and packaged into different types of electronic products, for example, mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (Virtual Reality, referred to as VR) devices, augmented reality (AugmentedReality, referred to as AR) devices, or any other suitable electronic devices having storage therein.

[0056] In some embodiments, Figure 2 As shown, the memory system 3000 includes a controller 2000 and a three-dimensional memory 1000, and the memory system 3000 can be integrated into a memory card.

[0057] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0058] In other embodiments, Figure 3 As shown, the storage system 3000 includes a controller 2000 and a plurality of three-dimensional memories 1000, and the storage system 3000 is integrated into a solid state drive (SSD).

[0059] In the storage system 3000, in some embodiments, the controller 2000 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices 5000 such as personal computers, digital cameras, mobile phones, etc.

[0060] In other embodiments, the controller 2000 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0061] In some embodiments, the controller 2000 may be configured to manage data stored in the three-dimensional memory 1000 and communicate with an external device (e.g., a host). In some embodiments, the controller 2000 may also be configured to control operations of the three-dimensional memory 1000, such as read, erase, and program operations. In some embodiments, the controller 2000 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 1000, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 2000 is also configured to process error correction codes regarding data read from or written to the three-dimensional memory 1000.

[0062] Of course, the controller 2000 may also perform any other suitable functions, such as formatting the three-dimensional memory 1000; for example, the controller 2000 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0063] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics 5000 (IDE) protocol, and Firewire protocol.

[0064] The controller may be, for example, a central processing unit (CPU), a general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. Some embodiments of the present disclosure provide a three-dimensional memory 1000. The three-dimensional memory 1000 may be applied to the above-mentioned storage system 3000. Of course, the three-dimensional memory 1000 may be applied to other storage systems, and the present disclosure does not limit this.

[0065] The present disclosure provides a three-dimensional memory, Figure 4 FIG. 1 is a schematic diagram of the structure of a three-dimensional memory provided according to some embodiments of the present disclosure. Figure 4 As shown, the three-dimensional memory 1000 includes a stacked structure 100, a channel structure 200 and a substrate 300. The stacked structure 100 includes gate layers 110 and dielectric layers 120 that are alternately stacked. The channel structure 200 runs through the stacked structure 100.

[0066] refer to Figure 4 , the channel structure 200 may include a barrier layer 210, a storage layer 220, a tunneling layer 230 and a channel layer 240 which are stacked in sequence. Exemplarily, the channel layer 240 may be made of amorphous silicon, polycrystalline silicon or single crystal silicon. Exemplarily, the tunneling layer 230 may include an insulating material, including but not limited to silicon oxide, silicon nitride or silicon oxynitride, or a combination of the above materials. Exemplarily, the thickness of the tunneling layer 230 may be 5nm-15nm, and the electrons or holes in the channel layer 240 may tunnel through the tunneling layer 230 to the storage layer 220 of the three-dimensional memory 1000. Exemplarily, the storage layer 220 may be used to store charges for operating the three-dimensional memory 1000, and the storage or removal of charges in the storage layer 220 determines the switching state of the semiconductor channel. The thickness of the storage layer 220 may be 3nm-15nm. Exemplarily, the material of the barrier layer 210 may include silicon oxide, silicon nitride or a high dielectric constant insulating material, or a combination of multiple materials. For example, a silicon oxide layer or a composite layer of silicon oxide, silicon nitride, and silicon oxide with a thickness of 4nm-15nm, that is, a layered structure of oxide-nitride-oxide (ONO). In some embodiments, the barrier layer 210 may further include a high-K dielectric layer (e.g., aluminum oxide with a thickness of 1nm-5nm).

[0067] The stacked structure 100 may cover the outer sidewall of the channel structure 200. Since the gate layer 110 and the dielectric layer 120 may be alternately stacked along the first direction X, the gate layers 110 may be spaced apart from each other along the first direction X. In this embodiment, the gate layer 110 includes a gate conductive layer 111 and a gate barrier layer 112, the gate barrier layer 112 is at least located between the gate conductive layer 111 and the channel structure 200, and the material of the gate conductive layer 111 includes Mo.

[0068] Exemplarily, the gate barrier layer 112 may be located between the gate conductive layer 111 and the channel structure 200. Alternatively, the gate barrier layer 112 may be partially located between the gate conductive layer 111 and the channel structure 200, and partially located at the top and bottom of the gate conductive layer 111. The top of the gate conductive layer 111 refers to a portion of the gate conductive layer 111 away from the substrate 300, and the bottom of the gate conductive layer 111 refers to a portion of the gate conductive layer 111 close to the substrate.

[0069] The gate barrier layer 112 can prevent electron leakage and improve the reliability of the semiconductor structure. Exemplarily, the gate barrier layer 112 may include, for example, a metal oxide or a metal nitride. The metal oxide may include aluminum oxide, and the metal nitride may include titanium nitride, tantalum nitride, or tungsten nitride.

[0070] refer to Figure 4 and Figure 5 , Figure 4 The structure in the embodiment can constitute a memory cell string 400. The memory cell string 400 may include a plurality of transistors T, a transistor T (eg Figure 5 The transistors T1 to T6 in the embodiment may be set as a memory cell, and these transistors T are connected together to form a memory cell string 400. A transistor T (for example, each transistor T) may be formed by a channel structure 200 and a gate layer 110 surrounding the channel structure 200. The gate layer 110 is configured to control the conduction state of the transistor.

[0071] Further, along the first direction X, the bottommost gate layer 110 among the multiple gate layers 110 is constructed as a source select gate SGS, which is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 400. The topmost gate layer 110 among the multiple gate layers 110 is constructed as a drain select gate SGD, which is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 400. The middle gate layer 110 among the multiple gate layers 110 can be constructed as multiple word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (for example, transistor T) in the memory cell string 400 can be completed.

[0072] In the related art, the gate conductive layer 111 includes a material tungsten (W), and W is usually deposited by a chemical vapor deposition process. The tungsten of the chemical vapor deposition method can be prepared by using tungsten fluoride (WF6) as a precursor. During the deposition of W, gaseous fluorine is generated, which can destroy oxides. Since the material of the channel structure 200 includes oxides, gaseous fluorine can destroy the channel structure and cause significant damage to the memory device.

[0073] To solve the above problems, in some embodiments, the gate conductive layer 111 may further include an adhesive layer (not shown in the figure). The adhesive layer may cover at least a portion of the surface of the gate conductive layer 111 and be located between the gate conductive layer 111 and the channel structure 200. By increasing the thickness of the adhesive layer, the gas fluorine is blocked. However, with the iteration of technology, the device size of the three-dimensional memory 1000 is shrinking. Increasing the thickness of the adhesive layer is not conducive to reducing the size of the three-dimensional memory 1000.

[0074] Moreover, with the iteration of technology, the programming and erasing speed of the three-dimensional memory 1000 should also be continuously improved. In the related art, since W is easily oxidized, the resistance of W increases after oxidation, resulting in a decrease in the programming and erasing speed of the three-dimensional memory 1000.

[0075] In view of this, the gate conductive layer 111 in this embodiment is made of Mo. It should be noted that “the gate conductive layer 111 is made of Mo” means that the gate conductive layer 111 is made of metal molybdenum (Mo), or the gate conductive layer 111 includes metal molybdenum (Mo) and other conductive materials.

[0076] The gate conductive layer 111 provided in this embodiment avoids the use of W in the gate conductive layer 111, and can avoid the use of WF6 as a precursor in the manufacturing process of the three-dimensional memory 1000, thereby avoiding the generation of gaseous fluorine when depositing W, which is beneficial to improving the problem of damaging the three-dimensional memory 1000 during the manufacturing process, and is beneficial to protecting the three-dimensional memory 1000 and avoiding the three-dimensional memory 1000 from being damaged.

[0077] At the same time, the gate layer 110 can be constructed as a word line. Reducing the word line resistance can improve the programming and erasing speed. Since the resistance of Mo is smaller than the resistance of W, the word line resistance in the present disclosure is lower than the word line resistance in the related art, which is beneficial to improving the programming and erasing speed of the three-dimensional memory 1000.

[0078] In some embodiments, the material of the gate barrier layer 112 includes a high dielectric constant material. Exemplarily, the gate barrier layer 112 can be composed of one material of oxides such as HfO2, ZrO2, Al3O2 or SiO2. Alternatively, the gate barrier layer 112 can be composed of a combination of multiple materials of oxides such as HfO2, ZrO2, Al3O2 or SiO2. The gate barrier layer 112 can cover a portion of the surface of the gate conductive layer 111 to insulate the gate conductive layer 111 from the channel structure 200 to prevent electron leakage.

[0079] Here, the concepts that appear in the embodiments of the present disclosure are briefly described. "First principles calculation": The basic idea of ​​first principles calculation is to regard a system composed of multiple atoms as a system composed of multiple electrons and atomic nuclei, and to handle the problem in a "non-empirical" manner to the maximum extent possible based on the basic principles of quantum mechanics.

[0080] Figure 6 This is the simulation result diagram of Mo atoms and HfO2 molecules obtained by first-principles calculation. Figure 6 Figure (1) shows the simulation results of Mo atoms and HfO2 molecules in the initial state. Figure 6 Figure (2) in Figure 1 shows the simulation results after the Mo atom and HfO2 molecule come into contact. Figure 6 As can be seen from Figures (1) and (2) in the figure, after Mo atoms come into contact with HfO2, the distribution positions of Mo atoms and HfO2 in space do not change significantly. Although the crystal structure of Mo atoms and HfO2 molecules undergoes a slight deformation, the overall crystal structure is still relatively regular, and the diffusion degree of O atoms is relatively weak.

[0081] Figure 7 This is the simulation result diagram of Mo atoms and ZrO2 molecules obtained by first-principles calculation. Figure 7 Figure (1) in the middle shows the simulation results of Mo atoms and ZrO2 molecules in the initial state. Figure 7Figure (2) shows the simulation results after the Mo atom and ZrO2 molecule come into contact. Figure 7 It can be seen from Figures (1) and (2) that after Mo atoms come into contact with ZrO2 molecules, the crystal structure of Mo atoms and ZrO2 molecules changes, and the overall regularity of the crystal structure is poor, and the degree of diffusion of O atoms is large.

[0082] Figure 8 This is the simulation result diagram of Mo atoms and Al2O3 molecules obtained by first-principles calculation. Figure 8 Figure (1) in the middle shows the simulation results of Mo atoms and Al2O3 molecules in the initial state. Figure 8 Figure (2) shows the simulation results after the Mo atom and Al2O3 molecule come into contact. Figure 8 As can be seen from Figures (1) and (2) in the figure, after the Mo atoms come into contact with the Al2O3 molecules, the crystal structure of the Mo atoms and the Al2O3 molecules undergoes significant changes, the regularity of the crystal structure is poor, and the diffusion degree of O atoms is large.

[0083] Fig. 9 This is the simulation result diagram of Mo atoms and SiO2 molecules obtained by first-principles calculation. Fig. 9 Figure (1) in the middle shows the simulation results of Mo atoms and SiO2 molecules in the initial state. Fig. 9 Figure (2) shows the simulation results after the Mo atom and SiO2 molecule come into contact. Fig. 9 As can be seen from Figures (1) and (2) in the figure, after the Mo atoms and SiO2 molecules come into contact, the crystal structure of the Mo atoms and SiO2 molecules undergoes significant changes, the regularity of the crystal structure is poor, and the degree of diffusion of O atoms is large.

[0084] Combination Figure 6 , Figure 7 , Figure 8 and Fig. 9 It can be seen that the degree of change of the crystal structure of Mo after contacting HfO2, ZrO2, Al2O3 and SiO2 is different, and the diffusion degree of O atoms is also different. Among them, when Mo contacts HfO2, the diffusion degree of O atoms is relatively weak, and the crystal structure of Mo and HfO2 is relatively regular. In summary, when Mo contacts HfO2, the crystal structure of Mo and HfO2 is relatively stable, which makes Mo not easily oxidized.

[0085] As described in the above embodiments, the gate conductive layer 111 includes Mo. When Mo is oxidized, the resistance of the gate conductive layer 111 increases, that is, the resistance of the word line increases, thereby reducing the programming and erasing speed of the three-dimensional memory 1000. In some embodiments, the material of the gate barrier layer 112 includes HfO2. From the above analysis, it can be seen that when the gate conductive layer 111 includes Mo, when Mo contacts HfO2, the diffusion degree of O atoms is relatively weak, and the crystal structure of Mo atoms and HfO2 molecules is relatively regular. It can be seen that when the material of the gate barrier layer 112 only includes HfO2, the diffusion degree of O atoms is relatively weak, which is conducive to improving the oxidation phenomenon of the gate conductive layer 111, and thus is conducive to improving the programming and erasing speed of the three-dimensional memory 1000.

[0086] In some embodiments, Fig.10 The simulation results of Mo atoms and HfO2 molecules before and after heat treatment obtained by first-principles calculations. Fig.10 Figure (1) shows the simulation results of Mo atoms and HfO2 molecules before heat treatment. Fig.10 Figure (2) shows the simulation results of Mo atoms and HfO2 molecules after heat treatment. Fig.10 Figure (3) is a schematic diagram of the crystal phase structure of HfO2 molecules before heat treatment. Fig.10 Figure (4) in Figure 1 is a schematic diagram of the crystal structure of HfO2 molecules after heat treatment. Fig.10 As shown in FIG. 1 , when the gate barrier layer 112 includes HfO 2 , the HfO 2 may be subjected to a heat treatment. Fig.10 As shown in Figures (3) and (4), before HfO2 is heat-treated, the crystal structure of HfO2 is a tetragonal phase; after HfO2 is heat-treated, the crystal structure of HfO2 is a ferroelectric phase. That is, the crystal structure of the gate barrier layer 112 after heat treatment is a ferroelectric phase.

[0087] According to research, if you want to save power when the storage device is not working, and at the same time, ensure that the storage device does not lose information and can start quickly, you need to keep the storage device powered at a low voltage, that is, consume very little power to save information. Figure 4 and Fig.11 When the three-dimensional memory 1000 is in an erase state, after the crystal phase structure of the gate barrier layer 112 is in a ferroelectric phase, the gate barrier layer 112 will be polarized to generate a built-in electric field, and the side of the gate barrier layer 112 close to the channel structure 200 will be enriched with positive charges, so that electrons are generated in the channel structure 200, and the electrons are retained in the channel structure, so that electrons can be supplemented for the above process, which is beneficial to improving the erase speed of the three-dimensional memory 1000.

[0088] Research has found that the three-dimensional memory 1000 has power consumption caused by leakage current, and the power consumption caused by leakage current is different in different states. Figure 4 and Fig.12 When the three-dimensional memory 1000 is in a programming state, after the crystal phase structure of the gate barrier layer 112 is in a ferroelectric phase, the gate barrier layer 112 will be polarized to generate a built-in electric field, and the side of the gate barrier layer 112 close to the channel structure 200 will be enriched with negative charges, so that holes are generated in the channel structure 200. The electrons in the gate conductive layer 111 will be neutralized by the holes generated in the channel structure 200, thereby improving the leakage current and facilitating the improvement of the write speed of the three-dimensional memory 1000.

[0089] In some embodiments, reference Fig.13 The present disclosure also provides a method for preparing a three-dimensional memory 1000, including: S100-S300.

[0090] S100, forming an initial stacked structure, wherein the initial stacked structure includes sacrificial layers and dielectric layers that are alternately stacked.

[0091] In this embodiment, reference Fig.14 , a substrate 300 may be formed first. The substrate 300 may be made of single crystal silicon or other suitable materials, such as but not limited to silicon germanium, germanium, silicon-on-insulator thin film, etc.

[0092] After forming the substrate 300, refer to Fig.15 On the substrate 300 , an initial stacked structure 100 is formed along a first direction X. The initial stacked structure 100 includes sacrificial layers 130 and dielectric layers 120 that are alternately stacked.

[0093] The sacrificial layer 130 and the dielectric layer 120 are made of two different materials, and under the same process conditions, the etching rate of the sacrificial layer 130 is different from the etching rate of the dielectric layer 120. In some examples, the sacrificial layer 130 includes a nitride (e.g., silicon nitride), and the dielectric layer 120 includes an oxide (e.g., silicon oxide).

[0094] S200 , forming a channel structure, wherein the channel structure penetrates the initial stacked structure.

[0095] refer to Fig.16 , a channel structure 200 is formed, and the channel structure 200 penetrates the initial stacked structure 100 , that is, the channel structure 200 penetrates the sacrificial layer 130 and the dielectric layer 120 .

[0096] After forming the stacked structure, the method further includes: forming a channel hole 260 that penetrates the stacked structure. After forming the channel hole 260 , the method further includes: filling the channel hole 260 with a channel material to form the channel structure 200 .

[0097] refer to Fig.16 , for example, an oxide-nitride-oxide-polysilicon (OxiDe-NitriDe-OxiDe-Poly, ONOP) structure may be sequentially stacked in the channel hole 260. In this case, the material of the barrier layer 210 may include, for example, silicon oxide, the material of the storage layer 220 may include, for example, silicon nitride, the material of the tunneling layer 230 may include, for example, silicon oxide, and the material of the channel layer 240 may include, for example, polysilicon. In the above steps, a thin film deposition process such as CVD, PVD or ALD may also be used to form a filling layer 250, such as silicon oxide, in the channel hole formed with the storage layer 220 and the channel layer 240. The channel structure having the barrier layer 210, the storage layer 220, the tunneling layer 230, the channel layer 240 and the filling layer 250 may be referred to as an "ONOPO" structure.

[0098] S300, replacing the sacrificial layer with a gate layer; wherein the gate layer includes a gate conductive layer and a gate barrier layer, the gate barrier layer is at least located between the gate conductive layer and the channel structure, and the material of the gate conductive layer includes Mo.

[0099] Then, refer to Fig.16 , Fig.18 and Fig.19 , the sacrificial layer 130 is etched to remove the sacrificial layer 130. After removing the sacrificial layer 130, a gate layer 110 is formed at the position where the sacrificial layer 130 is removed. The gate layer 110 includes a gate conductive layer 111 and a gate barrier layer 112, and the gate barrier layer 112 is at least located between the gate conductive layer 111 and the channel structure 200. Exemplarily, the gate barrier layer 112 may be located between the gate conductive layer 111 and the channel structure 200. Alternatively, the gate barrier layer 112 may be partially located between the gate conductive layer 111 and the channel structure 200, and partially located at the top and bottom of the gate conductive layer 111. The top of the gate conductive layer 111 refers to the portion of the gate conductive layer 111 away from the substrate 300, and the bottom of the gate conductive layer 111 refers to the portion of the gate conductive layer 111 close to the substrate. After removing the sacrificial layer 130, a gate barrier layer 112 is formed. After forming the gate barrier layer 112, a gate conductive layer 111 is formed in the gap of the gate barrier layer 112. The gate conductive layer 111 is formed of a material including Mo.

[0100] The gate conductive layer 111 of the three-dimensional memory 1000 manufactured according to the method provided in this embodiment can be made entirely of metal molybdenum (Mo), or the gate conductive layer 111 can be made of metal molybdenum Mo and other metal materials, which can avoid using W in the gate conductive layer 111. In this way, there is no need to use the precursor WF6, which is beneficial to improving the problem of generating fluorine gas when depositing W, and is beneficial to protecting the memory device and preventing the memory device from being damaged.

[0101] In some embodiments, reference Fig.17 , replacing the sacrificial layer 130 with the gate layer 110 includes: S310 to S330.

[0102] S310 , removing the sacrificial layer to form a gate gap.

[0103] refer to Fig.16 and Fig.18 , the sacrificial layer 130 is removed by wet etching or dry etching to form a gate gap 140.

[0104] S320 , depositing HfO 2 in the gate gap to form a gate barrier layer.

[0105] refer to Figure 4 and Fig.19 , HfO2 may be deposited in the gate gap 140 by a thin film deposition process such as CVD, PVD or ALD to form a gate barrier layer 112. Exemplarily, HfO2 may be deposited at one end of the gate gap 140 close to the channel structure 200 to form the gate barrier layer 112. Alternatively, HfO2 may be partially deposited at one end of the gate gap 140 close to the channel structure 200, and partially deposited at the top and bottom of the gate gap 140 to form the gate barrier layer 112, leaving part of the gate gap 140.

[0106] S330 , depositing Mo in the gap between the gate electrodes to form a gate conductive layer.

[0107] After the gate barrier layer 112 is formed, a thin film deposition process such as CVD, PVD or ALD may be used to deposit Mo in a portion of the gate gap 140 that is retained to form a gate conductive layer 111 .

[0108] The gate barrier layer 112 of the three-dimensional memory formed by the above method includes HfO2 and the gate conductive layer 111 includes Mo, avoiding the use of W in the gate conductive layer 111. In this way, it is possible to avoid the use of WF6, avoiding the generation of gaseous fluorine when depositing W, which is beneficial to improving the problem of damaging the three-dimensional memory during the manufacturing process, and is beneficial to protecting the memory device and avoiding damage to the memory device. In addition, the resistance of Mo is smaller than the resistance of W. When Mo is used in the gate conductive layer 111, it is beneficial to reduce the resistance value of the word line, thereby improving the programming and erasing speed of the three-dimensional memory. In addition, as can be seen from the foregoing, when HfO2 contacts Mo, the diffusion degree of O atoms is weak, which is beneficial to improving the oxidation phenomenon of the gate conductive layer 111, and further beneficial to improving the programming and erasing speed of the three-dimensional memory 1000.

[0109] In some embodiments, reference Figure 4 and Fig.19The preparation method further includes: after HfO2 is deposited by a thin film deposition process, heat-treating the gate barrier layer 112 so that the crystal phase structure of the gate barrier layer 112 is in a ferroelectric phase. When the gate barrier layer 112 includes HfO2, the crystal phase structure of the gate barrier layer 112 can be made into a ferroelectric phase by heat-treating the gate barrier layer 112. The manufacturing process is simple. As can be seen from the foregoing, when HfO2 contacts Mo, the diffusion degree of O atoms is weak, which is conducive to improving the oxidation phenomenon of the gate conductive layer 111, and further conducive to improving the programming and erasing speed of the three-dimensional memory 1000.

[0110] In some embodiments, reference Figure 4 and Fig.19 , Mo is deposited in the gate gap, including: using MoCl5 as a precursor and adopting a chemical vapor deposition process to form a gate conductive layer 111.

[0111] Through research, it is found that by using MoCl5 as a precursor and then using a chemical vapor deposition process to deposit Mo, the gate conductive layer 111 can be efficiently formed. In addition, MoCl5 does not produce gas that damages the channel structure, which is beneficial to improving the problem of fluorine gas damaging the three-dimensional memory 1000 during the manufacturing process of the three-dimensional memory 1000, and is beneficial to protecting the three-dimensional memory 1000 and preventing the three-dimensional memory 1000 from being damaged.

[0112] In some embodiments, reference Figure 4 and Fig.19 , depositing HfO2 in the gate gap, including: forming a gate barrier layer 112 using an atomic layer deposition process.

[0113] Exemplarily, the process of forming HfO2 can also use other thin film deposition processes, including but not limited to chemical vapor deposition, physical vapor deposition and electroplating processes. As can be seen from the foregoing, when HfO2 contacts Mo, the diffusion degree of O atoms is weak, and HfO2 as the gate barrier layer 112 and Mo as the gate conductive layer 111 are relatively compatible, which is beneficial to improve the oxidation phenomenon of the gate conductive layer 111, and further beneficial to improve the programming and erasing speed of the three-dimensional memory 1000.

[0114] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A three-dimensional memory, characterized in that: include: Overlay The stacked structure comprises a gate layer and a dielectric layer which are alternately stacked; A channel structure, penetrating the stacked structure; The gate layer includes a gate conductive layer and a gate barrier layer, the gate barrier layer is at least located between the gate conductive layer and the channel structure, and the gate conductive layer is made of Mo.

2. The three-dimensional memory according to claim 1, characterized in that: The material of the gate barrier layer includes a high dielectric constant material.

3. The three-dimensional memory according to claim 2, characterized in that: The material of the gate barrier layer includes HfO2.

4. The three-dimensional memory according to claim 3, characterized in that: The crystal phase structure of the gate barrier layer is in a ferroelectric phase.

5. A method for preparing a three-dimensional memory, characterized in that: include: forming an initial stacked structure, wherein the initial stacked structure includes sacrificial layers and dielectric layers alternately stacked; forming a channel structure, wherein the channel structure penetrates the initial stacked structure; replacing the sacrificial layer with a gate layer; The gate layer includes a gate conductive layer and a gate barrier layer, the gate barrier layer is at least located between the gate conductive layer and the channel structure, and the gate conductive layer is made of Mo.

6. The preparation method according to claim 5, characterized in that: The replacing the sacrificial layer with the gate layer comprises: removing the sacrificial layer to form a gate gap; Depositing HfO2 in the gate gap to form the gate barrier layer; Mo is deposited in the gate gap to form the gate conductive layer.

7. The preparation method according to claim 6, characterized in that: The preparation method further comprises: performing heat treatment on the gate barrier layer so that the crystal phase structure of the gate barrier layer is in a ferroelectric phase.

8. The preparation method according to claim 6, characterized in that: The step of depositing Mo in the gate gap comprises: The gate conductive layer is formed by using MoCl5 as a precursor and a chemical vapor deposition process.

9. The preparation method according to claim 8, characterized in that: The step of depositing HfO2 in the gate gap comprises: The gate barrier layer is formed by an atomic layer deposition process.

10. A storage system, characterized in that: include: A three-dimensional memory, wherein the three-dimensional memory is the three-dimensional memory according to any one of claims 1 to 4; The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

11. An electronic device, characterized in that: It comprises a circuit board and the storage system as claimed in claim 10, wherein the circuit board is electrically connected to the storage system.

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