155results about How to "Increase erasing speed" patented technology

Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.

Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.

A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.

The invention provides a data writing method for writing data sequentially in a cross-point memory cell array having a variable resistive element whose electric resistance is changed by application of an electric stress. When data is sequentially written in memory cells in the same row or column, the writing order of the memory cells to be written is determined according to the length from an electric connection point to a selected memory cell to be written and the increase/decrease direction of the electric resistance of each selected memory cell changed by data writing, the electric connection point being between a write voltage applying circuit, which applies a data writing voltage to a same wiring of the selected word line or bit line connected to the selected memory cell, and the same wiring, and the data writing is executed based on the determined writing order.

Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.

Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder. By applying a potential to a select gate electrode SG of a memory cell having a source region MS and a drain region MD and to the source region MS and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select transistor and an end of an n-type doped region ME disposed under the memory gate electrode MG, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film SIN by a negative potential applied to the memory gate electrode MG, and thereby an erase operation is performed.

The invention provides a method and a device for erasing script, and is characterized in that the script is divided into more than one lines, and the determination of the existence of a line in the lines which goes cross an erasing area is taken as a basis on which the decision about whether the script goes cross the erasing area can be made. In the scheme provided by the invention, to find out whether the script crosses the erasing area is converted into the detection about whether the lines following the division of the script cross the erasing area, and if one of the lines goes cross the erasing area, the decision can be made that the script goes cross the erasing area. As only part of the lines of the script need to verified, all that is needed is to verify whether the line crosses the erasing area, and the amount of calculation is correspondingly reduced, so that the script erasing speed is effectively increased, and the script erasing performance is improved. Meanwhile, as not all the points comprising the script are required to be searched and verified, the occupancy of a CPU and the consumption of resources are reduced during the process of erasure.

An electrical switching device comprises a switching element and a heating device for heating the switching element. The switching element comprises a first electrode, a second electrode, and an electrolyte layer arranged between and contact-connected to the first and second electrode. The switching element is configured to establish a conducting path between the first and second electrodes via the electrolyte layer by conduction elements having diffused from the first electrode into the electrolyte layer.

A nonvolatile semiconductor memory device includes a semiconductor substrate, a select gate formed above the semiconductor substrate, a floating gate formed above the semiconductor substrate and an erase gate positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating gate.

A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.

A method for operating an integrated circuit memory device includes applying a verify procedure in which the page of data and one or more bits from a set of replacement cells are matched with a pattern in parallel to indicate a verify result, where the page of data is “unrepaired” and may include one or more bits from defective bit lines. While matching to indicate a verify result, the one or more bits from defective bit lines in the page are masked. Flash memory and other memory devices implement the method.

The present invention relates to a semiconductor device, a memory array and a fabrication method thereof, and more particularly to a semiconductor device having a stacked array structure (referred to as a STAR structure: a STacked ARray structure) applicable to not only a switch device but also a memory device, a NAND flash memory array using the same as a memory device and a fabrication method thereof.

The invention discloses a nonvolatile memory erase method and a nonvolatile memory erase device. The method comprises the steps that: a target erasing target is subjected to a preprogramming operation, wherein the preprogramming operation is that 0 is written into memory units of the target erase object; whether the preprogramming operation is successful is examined, wherein the examining is that whether currents of the memories in the target erase object processed through the preprogramming operation under a certain gate voltage are all smaller than a target current value which is a current value with current margin; if the preprogramming operation is successful, a next step is executed, and if not, the progress is turned back to the execution of the preprogramming operation; the target erase object is subjected to an erase operation, wherein the erase operation is that 1 is written into memory units of the target erase object; and the target erase object is subjected to an over-erase examine operation, wherein the over-erase examine operation is that threshold voltage of memory units in the target erase object is adjusted. With the method and device provided by the invention, nonvolatile memory erase speed can be improved, and memory performance can be improved.

The invention discloses a preparation method of a high-speed low-power-consumption phase change memory. In the method, a superlattice film material with rapid phase change speed and low heat conductivity is used as a phase change material, and an inductive coupling plasma dry method is used to etch the material so as to form a phase change memory unit with good appearance, steep and straight side wall and good consistency. The preparation method comprises the following steps of: (1) washing a substrate; (2) successively depositing a metal film and an insulation layer film; (3) depositing a superlattice film phase change material; (4) gluing and photoetching to form photoresist serving as an etched mask; (5) etching the superlattice film material with inductive coupling plasma etching equipment; (6) removing the etched mask; and (7) successively depositing an insulation layer film and a metal film. According to the invention, the prepared phase change memory has high speed and low power consumption through utilizing the characteristics of the inductive coupling plasma dry method etching on the superlattice phase change film material, such as anisotropism, consistency and the like; and the preparation method disclosed by the invention can be well applied to superintegrated and large-scale industrialized production.

A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, inter-gate dielectric layer, a tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. Each of the second stacked gate structure has a select gate dielectric layer, a select gate and a second cap layer. The control gate is between each of the first stacked gate structures, and between each of the second stacked gate structures and the adjacent first stacked gate structure. The floating gate is between the control gate and substrate. The inter-gate dielectric layer is disposed between the control and floating gates. The tunnel oxide is between the floating gate and substrate. The doping regions are disposed under the first stacked gate structure, and the source/drain regions are in the exposed substrate.

The invention discloses an erasing method for a non-volatile memory. The method comprises the following steps of: selecting a target, namely, selecting 2n to-be-erased adjacent memory blocks in the non-volatile memory, wherein n is a natural number; performing pre-programming operation, namely, pre-programming the 2n adjacent memory blocks in groups; erasing, namely, simultaneously erasing the 2n adjacent memory blocks; checking the erasing, namely, checking whether the 2n adjacent memory blocks are successfully erased in groups, if so, performing soft programming operation, and otherwise, returning to the erasing step; and performing the soft programming operation, namely, performing the soft programming operation on the adjacent memory blocks in groups. The method can save erasing time and improve erasing speed and erasing efficiency.

The invention discloses a unit structure of an MTP (Multi-Time Programmable) device. The unit structure comprises a selection transistor, a programming transistor and an erasure capacitor, wherein the selection transistor and the programming transistor are located in the same n well; a source electrode of the selection transistor is used as a drain end, and a gate electrode of the selection transistor is used as a selection end; a drain electrode of the selection transistor is connected with the source electrode of the programming transistor; the gate electrode of the programming transistor extends out to form a floating gate; the floating gate is used as a lower polar plate of the erasure capacitor; the drain electrode of the programming transistor is connected with the n well to be used as a programming end; and an upper polar plate of the erasure capacitor is made of metal and used as an erasure end. The unit structure of the MTP device can be used for obviously reducing a layout area of the unit structure of the MTP device and obviously increasing the erasure voltage, therefore, the erasure speed is improved and the error programming is reduced.