A hardware description language pre-compilation method and related equipment

Abstract

The present application discloses a hardware description language precompilation method and related equipment, including: obtaining a target hardware description language file; inputting the target hardware description language file into a preprocessing algorithm unit to obtain a preprocessed target hardware description language file, wherein the preprocessing algorithm unit includes a code format and structure management module, a modular processing and management module, a conditional processing and macro definition module, and a code generation and instantiation module, each module includes one or more processing components, and each of the processing components is constructed based on different regular expressions; encapsulating and saving the preprocessed target hardware description language file to obtain a precompiled hardware description language file.

Description

Technical Field

[0001] The present specification relates to the field of electronic design automation, and more specifically, the present application relates to a hardware description language pre-compilation method and related equipment. Background Art

[0002] As digital circuits and system designs become increasingly complex, Verilog and its preprocessing technology are becoming more and more widely used in the field of hardware design. Verilog plays a vital role in both simple digital logic design and complex system-level design. Verilog is an indispensable tool in FPGA (Field-Programmable Gate Array) and ASIC (Application-Specific Integrated Circuit) design. In recent years, with the rapid development of emerging technologies such as 5G, Artificial Intelligence (AI) and the Internet of Things (IoT), higher performance and functional requirements have been put forward for hardware design, which has led to the continuous evolution of Verilog and its preprocessing technology to support more advanced design methods and verification technologies.

[0003] In large-scale hardware design projects, manually writing and managing Verilog code may become lengthy and complex due to the expansion of the project size, which in turn leads to a decrease in the readability and maintainability of the code. Although there are some tools and methods that can automatically generate Verilog code, these tools often rely on specific software environments or specialized tool chains, and the generated code is poorly readable and requires further manual preprocessing to meet the needs of the project.

[0004] Therefore, it is necessary to propose a hardware description language precompilation method and related equipment to reduce the dependence on a specific software environment, enable code precompilation and optimization under more flexible conditions, improve the readability and reusability of the hardware description language code, and thus meet the requirements of modern hardware design for automation and efficiency. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In a first aspect, the present application proposes a hardware description language pre-compilation method, comprising:

[0007] Get the target hardware description language file;

[0008] Inputting the target hardware description language file into a preprocessing algorithm unit to obtain a preprocessed target hardware description language file, wherein the preprocessing algorithm unit includes a code format and structure management module, a modular processing and management module, a conditional processing and macro definition module, and a code generation and instantiation module, each module includes one or more processing components, and each of the processing components is constructed based on different regular expressions;

[0009] The preprocessed target hardware description language file is packaged and saved to obtain a precompiled hardware description language file.

[0010] In a feasible implementation manner, the above-mentioned preprocessing algorithm unit is established based on Python language;

[0011] The code format and structure management module includes a header file processing component and a format unification component. The header file processing component is used to standardize the header file of the code, and the format unification component is used to standardize the format of the code.

[0012] The modular processing and management module includes a module name processing component and a multi-module processing component. The module name processing component is used to standardize the name and delete unreadable comment content. The multi-module processing component is used to split the hardware description language of the module into independent files so that the independent file includes only one module.

[0013] The condition processing and macro definition module includes a first condition processing module and a second condition processing module, wherein the first condition processing module is used to filter the code actually running, and the second condition processing module is used to include code branches that meet the conditions;

[0014] The code generation and instantiation module includes a repetitive structure processing module and an instantiation part processing module. The repetitive structure processing module is used to expand the repetitive structure based on the number of repetitions, and the instantiation part is used to standardize the format of the instantiation code.

[0015] In a feasible implementation manner, the processing steps of the format unification component include:

[0016] Match module declaration lines to extract module name, parameter list, and port list;

[0017] Format the module line, replacing commas in the above parameter list and the above port list with newline characters;

[0018] Reconstruct and save the formatted module lines into the list of processed code lines.

[0019] In a feasible implementation manner, the processing steps of the module name processing component include:

[0020] Control the above module name processing component to remove single-line comments and blank lines;

[0021] Control the above name processing component to mark the start and end statements of multi-line comments;

[0022] Clear the comments between the above start statement and the above end statement to get valid code.

[0023] In a feasible implementation, it also includes:

[0024] Input the above precompiled hardware description language file into the simulation model to obtain the simulation error result;

[0025] Extract error type statistics and error location statistics based on the above simulation error results;

[0026] Determine the problem regular expression based on the above error type statistics;

[0027] Determine the problem sentence block based on the above error position statistical information, wherein the above problem sentence block is the area corresponding to the specific sentence combination form;

[0028] Perform expression update processing based on the regular expression of the above problem;

[0029] Sentence block splitting processing is performed based on the above-mentioned problem sentence block, and preprocessing operation based on the above-mentioned preprocessing algorithm unit is performed again based on the split sentences.

[0030] In a feasible implementation manner, the above-mentioned determining the problem statement block based on the above-mentioned error position statistical information includes:

[0031] Calculate the multi-factor proximity score and the sentence block complexity score based on the above error location statistics;

[0032] The problem sentence block is determined based on the multi-factor proximity score and the sentence block complexity score.

[0033] In a feasible implementation, the multi-factor proximity score is determined based on the following formula:

[0034]

[0035] in, is the multi-factor proximity score, is the distance weight coefficient, is the error type similarity weight coefficient, is the nested level difference weight coefficient, is the distance between the line numbers of the two errors i and j. It is the nesting level difference of the error statement. for the similarity of the error types;

[0036] The complexity score of the above statement block Determined based on the following formula:

[0037]

[0038] in, is the weight of the nesting depth, is the nesting level of statement blocks, is the overall weight of the operator, is the weight of the i-th type of operator, is the number of operators of type i in the statement block, is the weight of variable reference and scope, is the scope weight of the j-th variable, is the number of times the jth variable is referenced in the statement block, is the data-dependent weight, Score the data dependency complexity, is the weight of logical complexity, Score the complexity of logical expressions;

[0039] The above data relies on complexity score Determined based on the following formula:

[0040]

[0041] in, Indicates the length of the lth dependency chain;

[0042] The complexity score of the above logical expression is Determined based on the following formula:

[0043]

[0044] in, is the number of edges in the control flow graph, N is the number of nodes in the control flow graph, and P is the number of connected components.

[0045] In a second aspect, the present application proposes a hardware description language pre-compilation device, comprising:

[0046] A first acquisition unit, used for acquiring a target hardware description language file;

[0047] A second acquisition unit is used to input the target hardware description language file into a preprocessing algorithm unit to obtain a preprocessed target hardware description language file, wherein the preprocessing algorithm unit includes a code format and structure management module, a modular processing and management module, a conditional processing and macro definition module, and a code generation and instantiation module, each module includes one or more processing components, and each of the processing components is constructed based on different regular expressions;

[0048] The third acquisition unit is used to encapsulate and save the preprocessed target hardware description language file to obtain a precompiled hardware description language file.

[0049] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is used to implement the steps of the hardware description language precompilation method of any one of the above-mentioned first aspects when executing the computer program stored in the memory.

[0050] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the hardware description language precompilation method of any one of the first aspects is implemented.

[0051] In summary, the hardware description language pre-compilation method proposed in this application, in view of the deficiencies in the background technology, significantly improves the readability, reusability and processing efficiency of the HDL code by optimizing the code format, modular management, conditional processing, code generation and encapsulation. In the related art, the format of the HDL code often has problems of inconsistency due to the personal habits of the developer, such as confusing indentation, irregular comments, etc., especially in large projects, this phenomenon will increase the difficulty of reading the code. This application uses a code format and structure management module to automatically format the code using regular expressions, unify the specifications of indentation, alignment and comments, and make the code logic clearer and more intuitive. This optimization not only improves the readability of the code, but also effectively reduces the complexity of subsequent maintenance, especially in a multi-person collaborative environment. In traditional designs, HDL files are often too lengthy and lack modular management, which makes it difficult to reuse the code, and testing and verification become complicated. The modular processing and management module of this application can automatically identify multiple modules in the file, split them into independent files reasonably, or divide the code in the module into blocks according to the functional logic. This modular design makes each module independent, which can be easily transplanted to other projects and tested and verified separately. Through modular management, not only the reuse rate of code is improved, but also the complexity of the system is reduced, which provides convenience for subsequent expansion and maintenance. In complex hardware design, conditional compilation instructions are widely used, but the resulting code redundancy and structural complexity will affect development efficiency. This application automatically parses conditional compilation instructions through conditional processing and macro definition modules, and intelligently judges the code blocks to be retained or deleted in combination with the current macro definition situation, thereby streamlining the code. This method can reduce irrelevant code and improve the simplicity of code. At the same time, it avoids the mistakes of manual deletion through automated processing, further improving development efficiency. In traditional HDL design, the instantiation of common modules (such as multiplexers and register arrays) needs to be manually written, which is not only time-consuming but also error-prone. The code generation and instantiation module provided in this application can automatically generate module code or instantiate parameterized modules according to design requirements. This improvement greatly reduces duplication of work and makes the design process more efficient and flexible. Developers only need to provide templates or configuration parameters to quickly generate high-quality code that meets the requirements, further optimizing the efficiency of hardware design. In the related art, the code generated by the preprocessing tools of HDL files is often complex in structure and has redundancy problems, which increases the time for subsequent compilation and simulation. This application encapsulates and saves modules to integrate the optimized code into precompiled files with unified structure and concise content. These files not only enable faster subsequent compilation and simulation, but also facilitate project management and maintenance, further improving the overall efficiency of hardware design. Through automated preprocessing methods, this application integrates code formatting, modularization, conditional compilation processing and code generation into an integrated process.Compared with traditional manual writing and preprocessing methods, this application significantly improves the efficiency, accuracy and flexibility of HDL code development, and is particularly suitable for complex hardware design requirements such as FPGA and ASIC. This method provides more intelligent and efficient technical support for modern hardware design. The technical solution of this application forms a complete and efficient HDL precompilation method from code optimization, modularization, conditional processing to automatic generation and packaging. Compared with the background technology, this solution solves the problems of lengthy code, inconsistent format, insufficient modularization and low manual processing efficiency. It not only significantly improves the design efficiency, but also reduces development and maintenance costs, providing innovative solutions for complex projects in the field of hardware design. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0053] Figure 1 A schematic diagram of a process flow of a hardware description language pre-compilation method provided in an embodiment of the present application;

[0054] Figure 2 A schematic diagram of the structure of a hardware description language pre-compilation device provided in an embodiment of the present application;

[0055] Figure 3 A schematic diagram of the structure of a hardware description language precompiled electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0057] See also Figure 1 , is a flow chart of a hardware description language pre-compilation method provided in an embodiment of the present application, the method comprising:

[0058] S110, obtaining a target hardware description language file;

[0059] Exemplarily, a target hardware description language file that needs to be precompiled is obtained, such as a Verilog file and a VHDL file. These hardware description language files describe the logical function and structure of the circuit and are the core part of the hardware design of FPGA and ASIC.

[0060] S120, inputting the target hardware description language file into a preprocessing algorithm unit to obtain a preprocessed target hardware description language file, wherein the preprocessing algorithm unit includes a code format and structure management module, a modular processing and management module, a conditional processing and macro definition module, and a code generation and instantiation module, each module includes one or more processing components, and each of the processing components is constructed based on different regular expressions;

[0061] Exemplarily, the target HDL (Hardware Description Language) file is input into the preprocessing algorithm unit for processing. The preprocessing algorithm unit is responsible for formatting, optimizing and structural management of the file content. The processing algorithm unit includes a code format and structure management module, a modular processing and management module, a conditional processing and macro definition module, and a code generation and instantiation module.

[0062] The code format and structure management module is used to ensure the formatting and consistency of the code and improve the readability of the code. This includes the standardization of code indentation, blank lines and comments, and the use of regular expressions to correct inconsistent code formats. For example, uniform indentation and alignment of the code makes multi-layer nested and logically complex code more readable.

[0063] The modular processing and management module is used to identify and split multiple modules in a file, save them as separate files, or divide different parts of a module into reasonable blocks. It can improve the maintainability and reusability of the code, and facilitate modular testing and verification. For example, a file containing multiple modules can be split into independent files so that each file contains only one module, which is easy to manage and reuse.

[0064] The conditional processing and macro definition module is used to process conditional compilation instructions and macro definitions in the code, such as ifdef, ifndef, else, endif, etc. These instructions are used to select code between different configurations. Conditional compilation instructions are identified through regular expressions, and which code blocks need to be retained or deleted are determined based on the current macro definition. For code branches that are only needed in specific situations, conditional compilation is used to selectively retain them, thereby reducing irrelevant code and enhancing the simplicity of the code.

[0065] The code generation and instantiation module is used to automatically generate code or instantiate modules according to design requirements, avoiding manual repetitive code writing. You can generate instances of common modules based on templates, or generate code based on specific parameters. For example: automatically instantiate common modules such as multiplexers and register arrays, and parameterize them as needed, making the design more efficient and flexible.

[0066] Each module contains one or more processing components, each of which is built based on different regular expressions, which are used to match, replace or delete specific code blocks. The use of regular expressions can help accurately identify and process specific syntax and structures in the code.

[0067] S130: Encapsulate and save the preprocessed target hardware description language file to obtain a precompiled hardware description language file.

[0068] Exemplarily, the preprocessed HDL (Hardware Description Language) files are packaged and saved to generate the final precompiled files. These files are optimized to facilitate subsequent compilation and simulation. Generate optimized precompiled HDL files to facilitate subsequent hardware design, simulation and verification processes. These files remove redundancy, maintain a unified structure and format, and are easy to manage and maintain.

[0069] In summary, the hardware description language pre-compilation method proposed in this application, in view of the deficiencies in the background technology, significantly improves the readability, reusability and processing efficiency of the HDL code by optimizing the code format, modular management, conditional processing, code generation and encapsulation. In the related art, the format of the HDL code often has problems of inconsistency due to the personal habits of the developer, such as confusing indentation, irregular comments, etc., especially in large projects, this phenomenon will increase the difficulty of reading the code. This application uses a code format and structure management module to automatically format the code using regular expressions, unify the specifications of indentation, alignment and comments, and make the code logic clearer and more intuitive. This optimization not only improves the readability of the code, but also effectively reduces the complexity of subsequent maintenance, especially in a multi-person collaborative environment. In traditional designs, HDL files are often too lengthy and lack modular management, which makes it difficult to reuse the code, and testing and verification become complicated. The modular processing and management module of this application can automatically identify multiple modules in the file, split them into independent files reasonably, or divide the code in the module into blocks according to the functional logic. This modular design makes each module independent, which can be easily transplanted to other projects and tested and verified separately. Through modular management, not only the reuse rate of code is improved, but also the complexity of the system is reduced, which provides convenience for subsequent expansion and maintenance. In complex hardware design, conditional compilation instructions are widely used, but the resulting code redundancy and structural complexity will affect development efficiency. This application automatically parses conditional compilation instructions through conditional processing and macro definition modules, and intelligently judges the code blocks to be retained or deleted in combination with the current macro definition situation, thereby streamlining the code. This method can reduce irrelevant code and improve the simplicity of code. At the same time, it avoids the mistakes of manual deletion through automated processing, further improving development efficiency. In traditional HDL design, the instantiation of common modules (such as multiplexers and register arrays) needs to be manually written, which is not only time-consuming but also error-prone. The code generation and instantiation module provided in this application can automatically generate module code or instantiate parameterized modules according to design requirements. This improvement greatly reduces duplication of work and makes the design process more efficient and flexible. Developers only need to provide templates or configuration parameters to quickly generate high-quality code that meets the requirements, further optimizing the efficiency of hardware design. In the related art, the code generated by the preprocessing tools of HDL files is often complex in structure and has redundancy problems, which increases the time for subsequent compilation and simulation. This application encapsulates and saves modules to integrate the optimized code into precompiled files with unified structure and concise content. These files not only enable faster subsequent compilation and simulation, but also facilitate project management and maintenance, further improving the overall efficiency of hardware design. Through automated preprocessing methods, this application integrates code formatting, modularization, conditional compilation processing and code generation into an integrated process.Compared with traditional manual writing and preprocessing methods, this application significantly improves the efficiency, accuracy and flexibility of HDL code development, and is particularly suitable for complex hardware design requirements such as FPGA and ASIC. This method provides more intelligent and efficient technical support for modern hardware design. The technical solution of this application forms a complete and efficient HDL precompilation method from code optimization, modularization, conditional processing to automatic generation and packaging. Compared with the background technology, this solution solves the problems of lengthy code, inconsistent format, insufficient modularization and low manual processing efficiency. It not only significantly improves the design efficiency, but also reduces development and maintenance costs, providing innovative solutions for complex projects in the field of hardware design.

[0070] In some examples, the preprocessing algorithm unit is established based on Python language;

[0071] The code format and structure management module includes a header file processing component and a format unification component. The header file processing component is used to standardize the header file of the code, and the format unification component is used to standardize the format of the code.

[0072] The modular processing and management module includes a module name processing component and a multi-module processing component. The module name processing component is used to standardize the name and delete unreadable comment content. The multi-module processing component is used to split the hardware description language of the module into independent files so that the independent file includes only one module.

[0073] The condition processing and macro definition module includes a first condition processing module and a second condition processing module, wherein the first condition processing module is used to filter the code actually running, and the second condition processing module is used to include code branches that meet the conditions;

[0074] The code generation and instantiation module includes a repetitive structure processing module and an instantiation part processing module. The repetitive structure processing module is used to expand the repetitive structure based on the number of repetitions, and the instantiation part is used to standardize the format of the instantiation code.

[0075] Exemplarily, in order to improve the readability and consistency of the code, this application introduces a header file processing component and a format unification component. The header file processing component manages the header file content uniformly by standardizing the header file order and format of the code. For example, it can remove redundant header files or arrange header files according to standard rules to make the code structure clearer. The format unification component focuses on adjusting the overall format of the code, including standardized processing of indentation, alignment, blank lines, and comments. This component ensures a clear presentation of the code logic, making developers more efficient when reading and maintaining the code.

[0076] In order to solve the problem of complex module management and difficulty in reuse in large HDL files, this application designs a module name processing component and a multi-module processing component. The main task of the module name processing component is to standardize module names and delete unreadable comments in the code. This function can enhance the standardization and ease of use of the code and avoid development problems caused by confusing naming or invalid comments. The multi-module processing component is responsible for automatically splitting multiple modules in the HDL file to generate independent files, each of which contains only one module. This splitting method not only facilitates the individual testing and verification of modules, but also improves the reusability of modules to meet the needs of complex projects.

[0077] In hardware design, conditional compilation instructions are an indispensable part, but redundant code will increase the maintenance burden. This application efficiently manages the conditional compilation logic through the first conditional processing module and the second conditional processing module. The first conditional processing module can automatically filter out the actual running code, and remove unenabled code blocks by parsing conditional compilation instructions (such as ifdef and ifndef) to reduce code redundancy. The second conditional processing module ensures that the code branches that meet the conditions are fully retained, ensures the logical correctness of the generated code, and lays the foundation for subsequent compilation and simulation.

[0078] In order to reduce duplication of work and improve the efficiency of code generation, this application designs a repetitive structure processing module and an instantiation part processing module. The repetitive structure processing module can automatically expand the repetitive structure in the code based on the number of repetitions, such as the instantiation of a register array or a multiplexer. This automatic expansion method significantly reduces the amount of manual operations required by developers. The instantiation part processing module standardizes the format of the instantiation code, including parameter alignment and indentation optimization, to ensure that the instantiation code style is unified and easy to maintain.

[0079] After all modules are processed together, the optimized HDL files are packaged into clearly structured precompiled files. These files are not only standardized in format and logically complete, but also have redundant parts removed, providing reliable support for subsequent hardware design processes (such as simulation, verification, and implementation).

[0080] Through the integration and optimization of these functional modules, the present application scheme effectively improves the preprocessing efficiency and code quality of HDL files. The code format and structure management module improves the readability and consistency of the code. The modular processing and management module enhances the reusability and testing convenience of the module. The conditional processing and macro definition module simplifies the code structure through automatic screening and branch retention. The code generation and instantiation module realizes efficient processing of repeated structure expansion and standardized instantiation code. The optimized precompiled file finally generated provides efficient and standardized support for subsequent design. This preprocessing method runs through all aspects of code optimization, forming an efficient and intelligent HDL precompilation solution that fully adapts to the needs of modern hardware design, especially in complex projects.

[0081] In some examples, the processing steps of the format unification component include:

[0082] Match module declaration lines to extract module name, parameter list, and port list;

[0083] Format the module line, replacing commas in the above parameter list and the above port list with newline characters;

[0084] Reconstruct and save the formatted module lines into the list of processed code lines.

[0085] Exemplarily, find the module declaration lines in the HDL file and identify the key information therein. The module declaration usually contains the module name, parameter list and port list. By using pattern matching (such as regular expressions), it is possible to identify which lines in the file are module declarations and extract different parts of these lines.

[0086] In this process, three types of information are extracted from the module declaration line: module name, parameter list, and port list. Module name is the unique identifier of the module, representing the name of the module. The parameter list is the configurable parameters of the module, usually used to specify attributes such as width and depth that can be set when instantiating. The port list lists the input, output, and in / out ports of the module, defining how the module connects to the outside world.

[0087] Once the module name, parameter list, and port list are extracted, the information can be formatted. The goal of formatting is to improve readability and make the code structure clearer. This includes but is not limited to parameter list formatting and port list formatting.

[0088] In many HDL files, parameters are usually written in a row. To make the code easier to read, put each parameter on a separate line. This makes the separation between parameters more obvious and easier to view and modify later.

[0089] The port list formatting is similar to the parameter list. Ports are usually written on a single line, which can be messy when there are many ports. Separating each port into a separate line allows you to clearly see the name, type (such as input, output, or bidirectional), and other information of each port. This helps you understand the interface definition of the module. In this way, each entry in the parameter and port lists can occupy a separate line, making the code more layered.

[0090] After formatting is complete, the module name, parameter list, and port list are reassembled into a formatted module declaration. The reassembled module declaration follows the following structure: the first line contains the module name, followed by the formatted parameter list, one parameter per line, followed by the formatted port list, also one port per line.

[0091] Then, the refactored module lines are stored in a list, waiting for subsequent processing, such as writing them back to the file. In this way, the entire module declaration becomes neat and clear, making it easier to read and maintain.

[0092] In some examples, the processing steps of the module name processing component include:

[0093] Control the above module name processing component to remove single-line comments and blank lines;

[0094] Control the above name processing component to mark the start and end statements of multi-line comments;

[0095] Clear the comments between the above start statement and the above end statement to get valid code.

[0096] For example, in the code, single-line comments and blank lines are often redundant content, which can easily confuse or interfere with the extraction of module names. Therefore, the first step is to delete these irrelevant information, such as single-line comments and blank lines. Single-line comments usually start with a specific symbol (such as / / ), and the following content is a comment. By detecting whether there is a comment symbol at the beginning of each line, these lines can be deleted. Some files may contain redundant blank lines. In order to reduce the length of the code and improve readability, you can directly delete the blank lines to make the code more compact. After deleting single-line comments and blank lines, the code will become more streamlined, retaining only valid code lines for subsequent processing.

[0097] In HDL files, in addition to single-line comments, there may also be multi-line comments. Multi-line comments are usually contained in specific symbol pairs, such as Indicates the start of a multi-line comment. Indicates the end. Therefore, when processing multi-line comments, you need to mark the beginning of the multi-line comment and the end of the multi-line comment.

[0098] Marker symbol to identify the start of a comment (e.g. ), and record its position. Find the corresponding comment end symbol (for example ), to mark the end of the comment range. This marking method can help accurately identify the scope of the comment, ensuring that only the comment content is deleted in subsequent steps without affecting the valid code.

[0099] After marking the range of multi-line comments, the next step is to clear these comments while ensuring that valid code is not accidentally deleted. The cleaning process includes:

[0100] 1. Delete all contents between the start tag and the end tag. These contents belong to the comment part and have no effect on the module definition.

[0101] 2. Keep valid codes: When clearing comments, you need to ensure that valid codes are not deleted by mistake. To this end, you can set some preset fields or conditions to exclude comments that may contain important information. For example, some comment lines may contain key descriptions of code definitions, which can be retained through conditional judgment.

[0102] Through this process, the final extracted code no longer contains comments, but only retains the actual module definition content, which can be used for further analysis and formatting.

[0103] In some examples, this also includes:

[0104] Input the above precompiled hardware description language file into the simulation model to obtain the simulation error result;

[0105] Extract error type statistics and error location statistics based on the above simulation error results;

[0106] Determine the problem regular expression based on the above error type statistics;

[0107] Determine the problem sentence block based on the above error position statistical information, wherein the above problem sentence block is the area corresponding to the specific sentence combination form;

[0108] Perform expression update processing based on the regular expression of the above problem;

[0109] Sentence block splitting processing is performed based on the above-mentioned problem sentence block, and preprocessing operation based on the above-mentioned preprocessing algorithm unit is performed again based on the split sentences.

[0110] Exemplarily, a precompiled HDL file (such as a Verilog or VHDL file) is input into a simulation model (such as ModelSim, VCS) for running. Errors that may occur when the HDL code is running in the simulation environment are detected, such as syntax errors, timing errors, or signal conflicts. The simulation error results include but are not limited to the type and location of each error. This information is usually recorded in the form of logs or error messages.

[0111] Extract and count various error classes from simulation error results. Record the frequency of each type of error and summarize the location (code line or module) where the error occurred. Provide statistical information about error distribution to facilitate analysis of the source of the error and identify the type and location of high-frequency errors.

[0112] Based on the common error types in the statistical information, determine which regular expressions have problems and correct them, thereby further improving the efficiency and accuracy of the pre-compilation operation.

[0113] Based on the error location statistics, find the code blocks where errors frequently occur and determine the specific locations of the problem statements. Analyze the context, structure, and logical relationships of these problem blocks and group them into specific areas. Focus on these areas containing errors to avoid interfering with other irrelevant code parts and optimize subsequent repair work. Use the corrected regular expressions to automatically find and precompile again. This enables automated error repair and handles simple or known error patterns, thereby reducing the workload of manual repair.

[0114] For complex code blocks, split them into smaller logical units. For example, if the combination of multiple statements in a piece of code causes an error, you can gradually split it into independent statements for testing and analysis. The smaller statement blocks after splitting help with more detailed error repair.

[0115] Reapply the preprocessing algorithm to the split code blocks, including re-detection, repair, and optimization. This process may require multiple iterations until the code can pass the simulation test successfully. Ensure that the updated code quality meets the requirements of the simulation model and complete the entire error repair and code optimization process.

[0116] The method proposed in this embodiment uses an automated method to determine which processing components have problems with their regular expressions based on the statistical information of simulation errors, and reminds the designer to correct the regular expressions. And based on the statistical information of the basic error position, it is determined which are the problem statement blocks, and the problem statement blocks are split, and can be gradually split into independent statements for testing and analysis. At the same time, the regular expressions of the problems that occur in the pre-compilation process can be located according to the error type, so as to modify the regular expressions to improve the accuracy of the next pre-compilation.

[0117] In some examples, determining the problem statement block based on the error location statistical information includes:

[0118] Calculate the multi-factor proximity score and the sentence block complexity score based on the above error location statistics;

[0119] The problem sentence block is determined based on the multi-factor proximity score and the sentence block complexity score.

[0120] Exemplarily, a multi-factor proximity score is used to evaluate the correlation and similarity of different error locations.

[0121] The block complexity score is used to assess the complexity of a code block in order to focus on the parts that may be more complex and error-prone. In HDL code, errors within the same fragment may be caused by the same type of problem. For example, a variable definition error in the same module may cause a series of errors. By calculating the physical distance (number of lines of code) between the errors, you can determine which error locations are "adjacent". Generally, the closer the errors are, the more likely they are to be related. There may be many different types of errors in HDL code (such as port mismatch, data type mismatch, etc.). Similar error types may point to the same source of the problem. Scoring the similarity of different error types will generally give higher weights to similar error types. Structures such as modules, loops, or conditional statements in HDL code may be nested at different levels. Higher levels of nesting mean more complex logical structures and are more likely to cause errors. By comparing the nesting levels of two errors, you can assess whether they may come from the same code structure. Combining the above factors, a multi-factor proximity score is obtained, which indicates the strength of the association between each error. The higher the proximity score, the more likely these errors are to belong to the same source of the problem.

[0122] In HDL code, complex combinatorial logic, nested structures, long conditional statements, etc. can make the code more difficult to debug and more prone to errors. The complexity score is calculated by analyzing the structural characteristics of the code, such as the depth of nesting, the number of operands, the complexity of the logical expression, etc. Different complexity factors may have different effects on the probability of errors. For example, deep nesting may be more error-prone than long expressions, so different factors can be given different weights. The complexity score is summarized according to the weight system. The higher the complexity score, the more complex the code block is and the higher the potential for errors. By calculating the multi-factor proximity score and the complexity score, a more accurate score can be obtained to determine which code areas are more likely to contain problems.

[0123] When determining the problem statement block, the two scores calculated above are combined as the basis for the final judgment. First, select the error location group with a higher multi-factor proximity score, which is more likely to be related to the same problem. Secondly, in each group of errors with a high proximity score, give priority to the statement block with a higher complexity score. This can focus on the code snippets that are complex and appear in the error cluster. The combined results of the multi-factor proximity score and the complexity score help to assign a priority to each code block. A statement block with a higher priority means that the code snippet has a higher probability of causing a problem, so it can be checked and fixed first.

[0124] In addition, it can be dynamically adjusted during the debugging process to recalculate the proximity and complexity scores based on actual conditions, thereby more accurately identifying problem statement blocks.

[0125] This embodiment effectively locates the problem statement blocks in the HDL code by combining the proximity score and the complexity score. The proximity score helps determine which errors are closer in physical location or logical relationship and may belong to the same problem source. The complexity score focuses on the structural complexity of the code. More complex code is often more prone to errors. Ultimately, based on the combination of these two scores, the problem area is found quickly and accurately, and then it is determined which processing components may have problems that cause the precompiled code to still have problems, so that the regular expression of the corresponding processing component is corrected.

[0126] In some examples, the multi-factor proximity score is determined based on the following formula:

[0127]

[0128] in, is the multi-factor proximity score, is the distance weight coefficient, is the error type similarity weight coefficient, is the nested level difference weight coefficient, is the distance between the line numbers of the two errors i and j. It is the nesting level difference of the error statement. is the similarity of the error type.

[0129] The complexity score of the above statement block Determined based on the following formula:

[0130]

[0131] in, is the weight of the nesting depth, is the nesting level of statement blocks, is the overall weight of the operator, is the weight of the i-th type of operator, is the number of operators of type i in the statement block, is the weight of variable reference and scope, is the scope weight of the j-th variable, is the number of times the jth variable is referenced in the statement block, is the data-dependent weight, Score the data dependency complexity, is the weight of logical complexity, Score the complexity of logical expressions;

[0132] The above data relies on complexity score Determined based on the following formula:

[0133]

[0134] in, Indicates the length of the lth dependency chain;

[0135] The complexity score of the above logical expression is Determined based on the following formula:

[0136]

[0137] in, is the number of edges in the control flow graph, N is the number of nodes in the control flow graph, and P is the number of connected components.

[0138] Exemplarily, the above-mentioned scoring formula can be used to quantitatively analyze and evaluate the risk of errors in the code. Multi-factor proximity scoring helps identify similar error locations. Statement block complexity scoring helps identify code blocks with complex structures. Data dependency complexity scoring and logical expression complexity scoring further refine the complexity factors and evaluate the complexity of data flow and logic flow respectively. These scores can be used for automated code analysis and debugging, helping developers to prioritize the code areas that are most likely to have problems, improve debugging efficiency and code quality, and further determine which processing components may have problems that cause the precompiled code to still have problems, thereby correcting the regular expressions of the corresponding processing components. Further determine which processing components may have problems that cause the precompiled code to still have problems, thereby correcting the regular expressions of the corresponding processing components.

[0139] It should be noted that through code parsing, HDL code or other language code is decomposed into basic blocks. This can be achieved through a syntax parser (Parser), which decomposes the code into the smallest syntax units (Tokens), such as variables, operators, keywords, etc. The syntax structure of the code is analyzed to generate an Abstract Syntax Tree (AST) to identify the syntax structure of the code. The code is divided into multiple basic blocks according to control statements (such as if, for, while, case). Each basic block represents a code segment that is executed in a straight line (excluding control flow transfer instructions).

[0140] After parsing the basic blocks, the relationship between the basic blocks, i.e., control flow edges, is established according to the control structure of the code. The control flow is established based on the following but not limited to the following rules:

[0141] If a basic block A will directly enter basic block B after execution, then an edge is connected from A to B in the control flow graph.

[0142] If statements cause control flow to branch. In an if statement, the if condition acts as a basic block. When the condition is true, the control flow is directed to the execution block; when it is false, it is directed to another execution path. For, while and other loops introduce loop edges. When the loop end condition fails, it is directed to the next instruction; if the condition is satisfied, it jumps back to the beginning of the loop.

[0143] A goto statement or similar flow control statements in HDL can jump directly to a specified label, which is connected to the basic block of the target label by an edge in the control flow graph.

[0144] After the basic blocks and control flow relationships are determined, a control flow graph can be generated. Each basic block is a node. According to the control flow relationship, add edges between each pair of basic blocks with control flow transfers. Clarify the start and end nodes of the graph for subsequent analysis.

[0145] like Figure 2 As shown, the present application proposes a hardware description language pre-compilation device, comprising:

[0146] A first acquisition unit 21 is used to acquire a target hardware description language file;

[0147] A second acquisition unit 22 is used to input the target hardware description language file into a preprocessing algorithm unit to obtain a preprocessed target hardware description language file, wherein the preprocessing algorithm unit includes a code format and structure management module, a modular processing and management module, a conditional processing and macro definition module, and a code generation and instantiation module, each module includes one or more processing components, and each of the processing components is constructed based on different regular expressions;

[0148] The third acquisition unit 23 is used to encapsulate and save the preprocessed target hardware description language file to obtain a precompiled hardware description language file.

[0149] The hardware description language pre-compiler may further perform the following steps:

[0150] In some examples, the preprocessing algorithm unit is established based on Python language;

[0151] The code format and structure management module includes a header file processing component and a format unification component. The header file processing component is used to standardize the header file of the code, and the format unification component is used to standardize the format of the code.

[0152] The modular processing and management module includes a module name processing component and a multi-module processing component. The module name processing component is used to standardize the name and delete unreadable comment content. The multi-module processing component is used to split the hardware description language of the module into independent files so that the independent file includes only one module.

[0153] The condition processing and macro definition module includes a first condition processing module and a second condition processing module, wherein the first condition processing module is used to filter the code actually running, and the second condition processing module is used to include code branches that meet the conditions;

[0154] The code generation and instantiation module includes a repetitive structure processing module and an instantiation part processing module. The repetitive structure processing module is used to expand the repetitive structure based on the number of repetitions, and the instantiation part is used to standardize the format of the instantiation code.

[0155] In some examples, the processing steps of the format unification component include:

[0156] Match module declaration lines to extract module name, parameter list, and port list;

[0157] Format the module line, replacing commas in the above parameter list and the above port list with newline characters;

[0158] Reconstruct and save the formatted module lines into the list of processed code lines.

[0159] In some examples, the processing steps of the module name processing component include:

[0160] Control the above module name processing component to remove single-line comments and blank lines;

[0161] Control the above name processing component to mark the start and end statements of multi-line comments;

[0162] Clear the comments between the above start statement and the above end statement to get valid code.

[0163] In some examples, this also includes:

[0164] Input the above precompiled hardware description language file into the simulation model to obtain the simulation error result;

[0165] Extract error type statistics and error location statistics based on the above simulation error results;

[0166] Determine the problem regular expression based on the above error type statistics;

[0167] Determine the problem sentence block based on the above error position statistical information, wherein the above problem sentence block is the area corresponding to the specific sentence combination form;

[0168] Perform expression update processing based on the regular expression of the above problem;

[0169] Sentence block splitting processing is performed based on the above-mentioned problem sentence block, and preprocessing operation based on the above-mentioned preprocessing algorithm unit is performed again based on the split sentences.

[0170] In some examples, determining the problem statement block based on the error location statistical information includes:

[0171] Calculate the multi-factor proximity score and the sentence block complexity score based on the above error location statistics;

[0172] Determine the problem sentence block based on the multi-factor proximity score and the sentence block complexity score;

[0173] The above multi-factor proximity score is determined based on the following formula:

[0174]

[0175] in, is the multi-factor proximity score, is the distance weight coefficient, is the error type similarity weight coefficient, is the nested level difference weight coefficient, is the distance between the line numbers of the two errors i and j. It is the nesting level difference of the error statement. is the similarity of the error type.

[0176] In some examples, the above block complexity score Determined based on the following formula:

[0177]

[0178] in, is the weight of the nesting depth, is the nesting level of statement blocks, is the overall weight of the operator, is the weight of the i-th type of operator, is the number of operators of type i in the statement block, is the weight of variable reference and scope, is the scope weight of the j-th variable, is the number of times the jth variable is referenced in the statement block, is the data-dependent weight, Score the data dependency complexity, is the weight of logical complexity, Score the complexity of logical expressions;

[0179] The above data relies on complexity score Determined based on the following formula:

[0180]

[0181] in, Indicates the length of the lth dependency chain;

[0182] The complexity score of the above logical expression is Determined based on the following formula:

[0183]

[0184] in, is the number of edges in the control flow graph, N is the number of nodes in the control flow graph, and P is the number of connected components.

[0185] like Figure 3 As shown, an embodiment of the present application also provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor, and when the processor 320 executes the computer program 311, the steps of any method of pre-compiling the above-mentioned hardware description language are implemented.

[0186] Since the electronic device introduced in this embodiment is a device used to implement a hardware description language precompilation device in the embodiment of the present application, based on the method introduced in the embodiment of the present application, the technical personnel in this field can understand the specific implementation mode of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment used by the technical personnel in this field to implement the method in the embodiment of the present application is within the scope of protection of this application.

[0187] In the specific implementation process, when the computer program 311 is executed by the processor, it can achieve Figure 1 Any implementation manner in the corresponding embodiments.

[0188] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0189] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0190] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0191] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0192] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0193] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the hardware description language pre-compilation process in the corresponding embodiment.

[0194] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (SSD)), etc.

[0195] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0196] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0197] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0198] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0199] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0200] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for precompiling a hardware description language, characterized in that: include: Get the target hardware description language file; Inputting the target hardware description language file into a preprocessing algorithm unit to obtain a preprocessed target hardware description language file, wherein the preprocessing algorithm unit includes a code format and structure management module, a modular processing and management module, a conditional processing and macro definition module, and a code generation and instantiation module, each module includes one or more processing components, and each of the processing components is constructed based on different regular expressions; Encapsulating and saving the preprocessed target hardware description language file to obtain a precompiled hardware description language file; The preprocessing algorithm unit is established based on Python language; The code format and structure management module includes a header file processing component and a format unification component, wherein the header file processing component is used to standardize the header file of the code, and the format unification component is used to standardize the format of the code; The modular processing and management module includes a module name processing component and a multi-module processing component, wherein the module name processing component is used to standardize the name and delete unreadable comment content, and the multi-module processing component is used to split the hardware description language of the module into independent files so that the independent files only include one module; The condition processing and macro definition module includes a first condition processing module and a second condition processing module, wherein the first condition processing module is used to filter the code actually running, and the second condition processing module is used to include code branches that meet the conditions; The code generation and instantiation module includes a repetitive structure processing module and an instantiation part processing module, wherein the repetitive structure processing module is used to expand the repetitive structure based on the number of repetitions, and the instantiation part processing module is used to standardize the format of the instantiation code; Also includes: Inputting the precompiled hardware description language file into the simulation model to obtain a simulation error result; Extracting error type statistics and error location statistics based on the simulation error results; Determine a problem regular expression based on the error type statistical information; Determine a problem sentence block based on the error position statistical information, wherein the problem sentence block is a region corresponding to a specific sentence combination form; Perform expression update processing based on the problem regular expression; Sentence block splitting processing is performed based on the problem sentence block, and preprocessing operation is performed again based on the preprocessing algorithm unit based on the split sentences.

2. The hardware description language pre-compilation method according to claim 1, characterized in that: The processing steps of the format unification component include: Match module declaration lines to extract module name, parameter list, and port list; Format the module line, replacing commas in the parameter list and the port list with newline characters; Reconstruct and save the formatted module lines into the list of processed code lines.

3. The hardware description language pre-compilation method according to claim 1, characterized in that: The processing steps of the module name processing component include: Control the module name processing component to delete single-line comments and blank lines; Control the module name processing component to mark the start statement and the end statement of a multi-line comment; Clear the comments between the start statement and the end statement to obtain valid code.

4. The hardware description language pre-compilation method according to claim 1, characterized in that: The determining the problem statement block based on the error position statistical information includes: Calculate a multi-factor proximity score and a sentence block complexity score based on the error position statistical information; The problem sentence block is determined based on the multi-factor proximity score and the sentence block complexity score.

5. The hardware description language pre-compilation method according to claim 4, characterized in that: The multi-factor proximity score is determined based on the following formula: in, is the multi-factor proximity score, is the distance weight coefficient, is the error type similarity weight coefficient, is the nested level difference weight coefficient, is the distance between the line numbers of the two errors i and j, It is the nesting level difference of the error statement. for the similarity of the error types; The complexity score of the block Determined based on the following formula: in, is the weight of the nesting depth, is the nesting level of statement blocks, is the overall weight of the operator, is the weight of the i-th type of operator, is the number of operators of type i in the statement block, is the weight of variable reference and scope, is the scope weight of the j-th variable, is the number of times the jth variable is referenced in the statement block, is the data-dependent weight, Score the data dependency complexity, is the weight of logical complexity, Score the complexity of logical expressions; The data dependency complexity score Determined based on the following formula: in, Indicates the length of the lth dependency chain; The complexity score of the logical expression Determined based on the following formula: in, is the number of edges in the control flow graph, N is the number of nodes in the control flow graph, and P is the number of connected components.

6. A hardware description language precompiler, characterized in that: include: A first acquisition unit, used for acquiring a target hardware description language file; A second acquisition unit is used to input the target hardware description language file into a preprocessing algorithm unit to obtain a preprocessed target hardware description language file, wherein the preprocessing algorithm unit includes a code format and structure management module, a modular processing and management module, a conditional processing and macro definition module, and a code generation and instantiation module, each module includes one or more processing components, and each of the processing components is constructed based on different regular expressions; A third acquisition unit is used to encapsulate and save the preprocessed target hardware description language file to obtain a precompiled hardware description language file; The preprocessing algorithm unit is established based on Python language; The code format and structure management module includes a header file processing component and a format unification component, wherein the header file processing component is used to standardize the header file of the code, and the format unification component is used to standardize the format of the code; The modular processing and management module includes a module name processing component and a multi-module processing component, wherein the module name processing component is used to standardize the name and delete unreadable comment content, and the multi-module processing component is used to split the hardware description language of the module into independent files so that the independent files only include one module; The condition processing and macro definition module includes a first condition processing module and a second condition processing module, wherein the first condition processing module is used to filter the code actually running, and the second condition processing module is used to include code branches that meet the conditions; The code generation and instantiation module includes a repetitive structure processing module and an instantiation part processing module, wherein the repetitive structure processing module is used to expand the repetitive structure based on the number of repetitions, and the instantiation part processing module is used to standardize the format of the instantiation code; Also includes: Inputting the precompiled hardware description language file into the simulation model to obtain a simulation error result; Extracting error type statistics and error location statistics based on the simulation error results; Determine a problem regular expression based on the error type statistical information; Determine a problem sentence block based on the error position statistical information, wherein the problem sentence block is a region corresponding to a specific sentence combination form; Perform expression update processing based on the problem regular expression; Sentence block splitting processing is performed based on the problem sentence block, and preprocessing operation is performed again based on the preprocessing algorithm unit based on the split sentences.

7. An electronic device comprising: A memory and a processor, wherein the processor is used to implement the steps of the hardware description language precompilation method according to any one of claims 1 to 5 when executing a computer program stored in the memory.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the hardware description language pre-compilation method according to any one of claims 1 to 5 are implemented.

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