Array substrate, display panel and display

Abstract

The present application relates to the field of display technology and discloses an array substrate, a display panel and a display. The scheme simulates the structure of a gate drive circuit area, and an electrostatic protection area including a first metal layer and a second metal layer is set on the side of the gate drive circuit area of ​​the array substrate away from the display area. The first metal layer is provided with a plurality of first metal wires, and the second metal layer is provided with a plurality of second metal wires arranged to overlap with the first metal wires. Each second metal wire is connected to a corresponding first metal wire. By configuring at least two first metal wires to be connected to different voltages, a voltage difference can be formed between the first metal layer and the second metal layer, thereby forming an electric field between the first metal layer and the second metal layer. The electric field is used to capture static electricity, thereby protecting the internal circuit of the gate drive circuit area and preventing the internal circuit of the gate drive circuit area from being damaged by static electricity.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display. Background Art

[0002] With the rapid development of LCD (Liquid Crystal Display) technology, LCD products have been widely used in mobile phones, automotive displays, central control systems, smart homes, smart offices, watches, bracelets, and many other fields. After the array manufacturing process is completed, the motherboard of LCD products needs to be cut into medium or small boards, or the medium board needs to be cut into small boards before the subsequent manufacturing process can be carried out.

[0003] Before cutting the mid-board into small boards, it needs to be tested. Only after the test is normal can it be cut and subsequently bonded with driver ICs (Integrated Circuits). During testing, it is necessary to set metal test lines on the mid-board. The metal test lines are connected to the signal transmission lines in the gate drive circuit area through vias. By connecting the metal probes of the test fixture to the metal test lines, the drive signal is transmitted to the signal transmission lines, thereby testing whether the substrate is abnormal.

[0004] When the middle board is cut into small boards, metal test lines will remain in each small board area. The remaining metal test lines will be connected to the signal transmission lines through vias. After the small board is bound to the driver IC, when the driver IC outputs the gate drive signal, each metal test line will be assigned a different gate drive signal and form an electric field at the intersection with other signal transmission lines. This will increase the ability of the signal transmission line to capture static electricity. The stronger the ability to capture static electricity, the stronger the energy level of static electricity breaking through the surrounding medium, which will make the internal circuit of the gate drive circuit area easily damaged by static electricity. Summary of the Invention

[0005] In order to solve the above problems, the present application provides an array substrate, a display panel and a display.

[0006] According to one aspect of an embodiment of the present application, an array substrate is disclosed, which includes a display area and a non-display area, wherein the non-display area includes a gate drive circuit area and an electrostatic protection area, and the gate drive circuit area is arranged on one side of the display area; the electrostatic protection area is arranged on a side of the gate drive circuit area away from the display area, and the electrostatic protection area includes a first metal layer and a second metal layer, the first metal layer includes a plurality of first metal wires, and the second metal layer includes a plurality of second metal wires, the second metal wires are arranged to overlap with the first metal wires, and each second metal wire is connected to a corresponding first metal wire, and at least two first metal wires are configured to be used for connecting to different voltages to form a voltage difference between the first metal layer and the second metal layer.

[0007] In an exemplary embodiment, the gate drive circuit area includes a transmission line layer and a test line layer, the transmission line layer includes a plurality of signal transmission lines, the signal transmission lines are connected to the scanning lines of the display area to transmit the gate drive signals to the scanning lines, the test line layer includes a plurality of metal test lines, the metal test lines are overlapped with the signal transmission lines, and each of the metal test lines is connected to a corresponding signal transmission line; the first metal layer and the transmission line layer are located on the same layer, and the second metal layer and the test line layer are located on the same layer.

[0008] In an exemplary embodiment, an overlapping area between the second metal line and the first metal line is greater than or equal to an overlapping area between the metal test line and the signal transmission line.

[0009] In an exemplary embodiment, the width of the first metal line is greater than or equal to the width of the signal transmission line.

[0010] In an exemplary embodiment, a distance between a first metal line adjacent to the gate driving circuit area in the electrostatic protection area and the gate driving circuit area is greater than or equal to a distance between two adjacent first metal lines in the electrostatic protection area.

[0011] In an exemplary embodiment, a distance between two adjacent second metal lines is less than or equal to a distance between two adjacent metal test lines.

[0012] In an exemplary embodiment, the first metal layer includes three first metal wires extending along a first direction, and the three first metal wires are spaced apart in a second direction; the second metal layer includes three second metal wires extending along the second direction, and the three second metal wires are spaced apart in the first direction.

[0013] In an exemplary embodiment, one of the three first metal wires is configured to be used for accessing a DC voltage of a first level, one of the first metal wires is configured to be used for accessing an AC voltage that periodically switches between the first level and a second level, and one of the first metal wires is configured to be used for accessing a DC voltage of the second level.

[0014] In an exemplary embodiment, the second metal line includes a plurality of sub-metal lines, the plurality of sub-metal lines extend in the same direction and are arranged at intervals, and the plurality of sub-metal lines are respectively connected to the same first metal line.

[0015] In an exemplary embodiment, the electrostatic protection area further includes a first insulating layer, which is arranged between the first metal layer and the second metal layer. The first insulating layer is provided with a plurality of vias, and the second metal wire is connected to the first metal wire through the vias.

[0016] According to one aspect of an embodiment of the present application, a display panel is disclosed. The display panel includes the array substrate as described above and a color filter substrate. The color filter substrate is arranged opposite to the array substrate.

[0017] According to one aspect of an embodiment of the present application, a display is disclosed, comprising the display panel as described above and a backlight module, wherein the backlight module is arranged opposite to the display panel and is used to provide backlight for the display panel.

[0018] The technical solutions provided by the embodiments of the present application include at least the following beneficial effects:

[0019] The present application simulates the structure of the gate drive circuit area, and sets an electrostatic protection area including a first metal layer and a second metal layer on the side of the gate drive circuit area away from the display area. The first metal layer is set to include multiple first metal wires, and the second metal layer is set to include multiple second metal wires overlapping with the first metal wires. Each second metal wire is connected to a corresponding first metal wire. By configuring at least two first metal wires to be connected to different voltages, a voltage difference can be formed between the first metal layer and the second metal layer, thereby forming an electric field between the first metal layer and the second metal layer. The electric field is used to capture static electricity, thereby protecting the internal circuit of the gate drive circuit area and preventing the internal circuit of the gate drive circuit area from being damaged by static electricity.

[0020] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0022] Figure 1 Schematic diagram showing a middle plate before being cut into small plates.

[0023] Figure 2 The figure schematically shows the composition of a liquid crystal display provided in one embodiment of the present application.

[0024] Figure 3 The figure schematically shows a liquid crystal display panel provided in one embodiment of the present application.

[0025] Figure 4The schematic diagram of the array substrate provided in the first embodiment of the present application is schematically shown.

[0026] Figure 5 Another angle diagram of the array substrate provided in the first embodiment of the present application is schematically shown.

[0027] Figure 6 A partial structural diagram of a gate drive circuit area in an embodiment of the present application is schematically shown.

[0028] Figure 7 The diagram schematically shows the formation of an electric field in an electrostatic protection zone according to an embodiment of the present application.

[0029] Figure 8 The schematic diagram of the electrostatic protection area provided in the second embodiment of the present application is schematically shown.

[0030] Figure 9 The schematic diagram of the electrostatic protection area provided in the third embodiment of the present application is schematically shown.

[0031] Figure 10 The schematic diagram of the electrostatic protection area provided in the fourth embodiment of the present application is schematically shown.

[0032] The following are the descriptions of the reference numerals:

[0033] 101, mid-board; 102, metal test line; 103, CT pad; 104, signal transmission line; 105, QT signal line; 106, cutting line; 200, liquid crystal display panel; 21, array substrate; 21a, display area; 21b, non-display area; 21b1, gate drive circuit area; 21b11, transmission line layer; 211, signal transmission line; 21b12, test line layer; 212, metal test line; 21b13, second insulating layer; 21b2, electrostatic protection area; 21b21, first metal layer; 213 / 213a / 213b / 213c, first metal wire; 21b22, second metal layer; 214 / 214a / 214b / 214c, second metal wire; 2141 / 2142, sub-metal wire; 21b23, first insulating layer; 215, via; 22, color filter substrate; 23, liquid crystal; 300, backlight module. DETAILED DESCRIPTION

[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0035] The terms "comprise," "include," and "have," and any variations thereof, are intended to cover but not exclude inclusion; for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to the product or device.

[0036] In the description of this application, it should be understood that the terms "left", "right", "top", "row", "column", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.

[0037] Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first," "second," or "third" may explicitly or implicitly include one or more features. Throughout the description of this application, unless otherwise specified, "plurality" means two or more.

[0038] The manufacturing process for the Liquid Crystal Display Panel (LCDP) in an LCD generally includes the array process, color film process, cell process, and module assembly process. After the array process is completed, the motherboard needs to be cut into medium or small boards, or the medium board needs to be cut into small boards before the subsequent processes can be carried out. Among them, the small board is the smallest display unit formed after the motherboard is cut once, and the medium board is composed of multiple small boards and requires a second cutting to form the small boards.

[0039] Before cutting the middle board into small boards, it is necessary to conduct a middle board test (Quarter Test, QT). After the QT test is normal, cutting and subsequent bonding of driver ICs can be carried out. Figure 1 As shown, before performing the QT test, metal test lines 102 and cell test pads (CT pads) 103 need to be set on the middle board 101. The number of metal test lines 102 and CT pads 103 is the same as the number of signal transmission lines 104 in the gate drive circuit area and corresponds one-to-one with the signal transmission lines 104. Among them, the metal test lines 102 are set on the top layer, and the metal test lines 102 and the internal circuits of the gate drive circuit area are overlapped. The closer the metal test lines 102 are to the area of ​​the middle board 101 that serves as the edge of the small board, the more signal transmission lines 104 they cross. Figure 1CT pad 103 is connected to metal test line 102, and a via (not shown) is provided on CT pad 103. Metal test line 102 is connected to signal transmission line 104 through the via on CT pad 103. During testing, the metal probe of the test fixture is connected to metal test line 102, and the QT signal line 105 transmits a drive signal to metal test line 102, thereby transmitting the drive signal to signal transmission line 104, thereby testing whether midboard 101 is abnormal.

[0040] When the middle board 101 is cut into small boards along the cutting line 106, although the metal test line 102 at the cutting line 106 will be cut, the part of the metal test line 102 located inside the cutting line 106 will still remain in each small board area. The top layer where the remaining metal test line 102 is located serves as a bridging layer, which is exposed to the outside and carries high and low electrical signals. The greater the signal pressure difference between its charged signal and the signal transmission line 104, the stronger its ability to attract and capture static electricity, and the stronger the energy level of static electricity breaking through the surrounding medium, which makes the bridging layer a key area for electrostatic damage, and further makes the internal circuit of the gate drive circuit area easily damaged by static electricity.

[0041] In related technologies, static electricity is dissipated by coating the back of the color filter (CF) substrate with indium tin oxide (ITO) and then with Ag (silver), or by setting a grounding wire around the substrate through a metal film layer to dissipate static electricity. This is done to prevent static electricity from damaging the internal circuits of the gate drive circuit area. Due to the strong demand for full-screen narrow-frame products, the frame of display products continues to shrink, and the array wiring is constantly approaching the edge of the substrate. Coating ITO on the back of the CF substrate can only partially shield static electricity, while setting a grounding wire around the substrate through a metal film layer to dissipate static electricity is insufficient because there are insulating layers such as the gate insulator (GI) above the grounding wire.

[0042] To this end, the present application provides an array substrate, a display panel and a display. By simulating the routing structure of the gate drive circuit area, an electrostatic protection area is set on the side of the gate drive circuit area away from the display area. An electric field is formed in the electrostatic protection area to capture static electricity, thereby protecting the internal circuit of the gate drive circuit area and preventing the internal circuit of the gate drive circuit area from being damaged by static electricity.

[0043] Figure 2 The figure schematically shows the composition of a liquid crystal display provided in one embodiment of the present application. Figure 3 The figure schematically shows a liquid crystal display panel provided in one embodiment of the present application.

[0044] like Figure 2As shown, the liquid crystal display includes a liquid crystal display panel 200 and a backlight module 300 , and the backlight module 300 is arranged opposite to the liquid crystal display panel 200 .

[0045] The backlight module 300 is used to provide backlight for the liquid crystal display panel 200 .

[0046] like Figure 3 As shown, the liquid crystal display panel 200 includes an array substrate 21, a color filter substrate 22, and liquid crystals 23. The color filter substrate 22 is disposed opposite to the array substrate 21, and the liquid crystals 23 are disposed between the color filter substrate 22 and the array substrate 21.

[0047] It is understandable that the liquid crystal display may further include other components besides the liquid crystal display panel 200 and the backlight module 300 .

[0048] The array substrate of the present application is described in detail below.

[0049] Figure 4 The schematic diagram of the array substrate provided in the first embodiment of the present application is schematically shown. Figure 5 Another angle diagram of the array substrate provided in the first embodiment of the present application is schematically shown. Figure 6 A partial structural diagram of a gate drive circuit area in an embodiment of the present application is schematically shown.

[0050] like Figure 4 and Figure 5 As shown, the array substrate 21 includes a display area 21a and a non-display area 21b. Among them, the display area 21a is provided with a plurality of scan lines (not shown in the figure), a plurality of data lines (not shown in the figure), a plurality of sub-pixel units (not shown in the figure), a common electrode (not shown in the figure), etc. The scan lines extend in the row direction and are used to transmit gate drive signals to the sub-pixel units. The data lines extend in the column direction and are used to transmit pixel drive signals to the sub-pixel units. The data lines and the scan lines are overlapped and respectively arranged in different layers. The plurality of sub-pixel units are arranged in a matrix into multiple rows and columns, and a sub-pixel unit is provided in the area separated by every two adjacent scan lines and two adjacent data lines. The plurality of sub-pixel units are all connected to the common electrode.

[0051] The common electrode is used to output a common voltage. The liquid crystal molecules between the sub-pixel unit and the common electrode rotate according to the voltage difference between the common voltage of the common electrode and the pixel drive signal received by the sub-pixel unit to control the transmittance of the liquid crystal molecules and thus achieve the effect of controlling the display brightness.

[0052] It is understood that the array substrate 21 may further include a driving unit (not shown in the figure), which includes a gate driving unit and a pixel driving unit. The gate driving unit is connected to multiple scan lines to selectively apply a positive voltage to a scan line, thereby turning on the sub-pixel units on the scan line. The pixel driving unit is connected to multiple data lines to output pixel driving signals to corresponding sub-pixel units, thereby lighting up the corresponding sub-pixel units.

[0053] like Figure 4 and Figure 5 As shown, the non-display area 21b includes a gate drive circuit area (Gate Driven on Array, GOA) 21b1 and an electrostatic protection area 21b2. The gate drive circuit area 21b1 is arranged on one side of the display area 21a, and the electrostatic protection area 21b2 is arranged on the side of the gate drive circuit area 21b1 away from the display area 21a. Figure 4 Taking the angle shown as an example, the gate drive circuit area 21b1 is set on the left side of the display area 21a, and the electrostatic protection area 21b2 is set on the left side of the gate drive circuit area 21b1; when the angle is changed, the gate drive circuit area 21b1 can be set on the right side of the display area 21a, and the electrostatic protection area 21b2 is set on the right side of the gate drive circuit area 21b1. This application does not limit this.

[0054] like Figures 4 to 6 As shown, the gate drive circuit area 21b1 includes a transmission line layer 21b11 and a test line layer 21b12. The transmission line layer 21b11 includes a plurality of signal transmission lines 211. The signal transmission lines 211 are connected to the scan lines of the display area 21a to transmit gate drive signals to the scan lines of the display area 21a, thereby turning on the sub-pixel units on the corresponding scan lines.

[0055] It is understood that the number of signal transmission lines 211 can be the same as the number of scan lines in the display area 21a, that is, each signal transmission line 211 can be connected to a scan line in a one-to-one correspondence. The number of signal transmission lines 211 can also be different from the number of scan lines in the display area 21a, that is, each signal transmission line 211 can be connected to multiple scan lines. When each signal transmission line 211 is connected to multiple scan lines, the gate drive signal is transmitted to the corresponding multiple scan lines using the signal transmission line 211, thereby turning on the sub-pixel units on the corresponding multiple scan lines.

[0056] The test line layer 21b12 includes a plurality of metal test lines 212, each of which is connected to a corresponding signal transmission line 211. In this embodiment, the number of metal test lines 212 is the same as the number of signal transmission lines 211, and the number of metal test lines 212 connected to the number of signal transmission lines 211 is one-to-one. The metal test lines 212 and the signal transmission lines 211 are arranged to overlap.

[0057] As described above, the metal test line 212 is a metal line provided on the midboard before the QT test and used to transmit a driving signal to the signal transmission line 211 to test whether the midboard is abnormal.

[0058] It should be noted that the metal test line 212 and the signal transmission line 211 are arranged on different layers of the array substrate 21, and the metal test line 212 and the signal transmission line 211 are arranged to overlap. The metal test line 212 and the signal transmission line 211 can be overlapped on different planes, or the metal test line 212 and the signal transmission line 211 can be crossed on different planes, etc.

[0059] exist Figure 5 In the illustrated embodiment, the gate driver circuit region 21b1 is provided with a second insulating layer 21b13, which is disposed between the transmission line layer 21b11 and the test line layer 21b12. The gate driver circuit region 21b1 is provided with multiple CT pads, each of which has vias extending through the second insulating layer 21b13. Each metal test line 212 is connected to a corresponding signal transmission line 211 through a via.

[0060] like Figures 4 to 6 As shown, the electrostatic protection area 21b2 includes a first metal layer 21b21 and a second metal layer 21b22. The first metal layer 21b21 includes a plurality of first metal wires 213, at least two of which are configured to be connected to different voltages.

[0061] The second metal layer 21b22 includes a plurality of second metal lines 214, each of which is connected to a corresponding first metal line 213. In this embodiment, the number of second metal lines 214 is the same as the number of first metal lines 213, and the second metal lines 214 are connected to the first metal lines 213 in a one-to-one correspondence. The second metal lines 214 and the first metal lines 213 are arranged to overlap.

[0062] By overlapping the second metal wire 214 with the first metal wire 213 and configuring at least two first metal wires 213 to be used for receiving different voltages, a voltage difference can be formed between the first metal layer 21b21 and the second metal layer 21b22. The voltage difference is used to form an electric field to capture static electricity, thereby protecting the internal circuit of the gate drive circuit area 21b1 and preventing the internal circuit of the gate drive circuit area 21b1 from being damaged by static electricity.

[0063] It should be noted that the second metal wire 214 and the first metal wire 213 are arranged on different layers of the array substrate 21, and the second metal wire 214 and the first metal wire 213 are arranged to overlap. The second metal wire 214 and the first metal wire 213 can be overlapped on different planes, or the second metal wire 214 and the first metal wire 213 can be crossed on different planes, etc.

[0064] In this embodiment, the first metal layer 21b21 and the transmission line layer 21b11 are located on the same layer, and the second metal layer 21b22 and the test line layer 21b12 are located on the same layer. That is, the first metal line 213 and the signal transmission line 211 are formed on the same metal layer, and the second metal line 214 and the metal test line 212 are formed on the same metal layer.

[0065] By setting the first metal line 213 and the signal transmission line 211 on the same layer, and setting the second metal line 214 and the metal test line 212 on the same layer, the electrostatic protection area 21b2 can better divide the static charge and reduce the static electricity entering between the transmission line layer 21b11 and the test line layer 21b12, thereby protecting the signal transmission line 211 and other circuits inside the gate drive circuit area 21b1 from electrostatic damage.

[0066] In one embodiment, the second metal layer 21b22, the test line layer 21b12, and the common electrode layer of the display area 21a are located in the same layer. That is, the second metal line 214, the metal test line 212, and the common electrode are formed in the same metal layer. Of course, the second metal line 214, the metal test line 212, and the common electrode can also be formed in different metal layers, which is not limited in this application.

[0067] exist Figure 5 In the illustrated embodiment, the electrostatic protection region 21b2 further includes a first insulating layer 21b23 disposed between the first metal layer 21b21 and the second metal layer 21b22. A plurality of vias 215 are provided on the first insulating layer 21b23. Each second metal line 214 is connected to a corresponding first metal line 213 via a via 215. Second metal lines 214 that are not connected via vias 215 are insulated from the first metal lines 213.

[0068] Of course, in other embodiments, each second metal line 214 may also be connected to a corresponding first metal line 213 through other methods.

[0069] In one embodiment, each second metal line 214 includes multiple sub-metal lines, which extend in the same direction and are spaced apart. Each of the sub-metal lines is connected to the same first metal line 213. By configuring the second metal line 214 to include multiple sub-metal lines, the electric field formed between the first metal layer 21b21 and the second metal layer 21b22 can be made more uniform. Of course, in other embodiments, the second metal line 214 can also be a single metal line.

[0070] The plurality of sub-metal wires may be two sub-metal wires or three or more sub-metal wires. Figure 4 In the illustrated embodiment, each second metal line 214 includes two sub-metal lines 2141 and 2142 . The two sub-metal lines 2141 and 2142 extend in the same direction and are spaced apart. The two sub-metal lines 2141 and 2142 are respectively connected to the same first metal line 213 .

[0071] The plurality of first metal wires 213 may be two first metal wires 213 or three or more first metal wires 213. Figure 4 In the illustrated embodiment, the first metal layer 21b21 includes three first metal lines 213 extending along a first direction, and the three first metal lines 213 are spaced apart in a second direction. Similarly, the second metal layer 21b22 includes three second metal lines 214 extending along a second direction, and the three second metal lines 214 are spaced apart in the first direction.

[0072] It can be understood that the first direction and the second direction are two directions perpendicular to each other.

[0073] In this embodiment, one first metal line 213 among the three first metal lines 213 is configured to be used for accessing a DC voltage of a first level, one first metal line 213 is configured to be used for accessing an AC voltage that periodically switches between a first level and a second level, and one first metal line 213 is configured to be used for accessing a DC voltage of a second level.

[0074] It is understandable that the first level and the second level are different. For example, if the first level is a high potential, the second level is a low potential; conversely, if the first level is a low potential, the second level is a high potential.

[0075] Figure 7 The diagram schematically shows the formation of an electric field in an electrostatic protection zone according to an embodiment of the present application.

[0076] To facilitate distinction, Figure 7In the figure, the three first metal wires 213 are labeled as 213a, 213b, and 213c, and the three second metal wires 214 are labeled as 214a, 214b, and 214c. The first metal wire 213a is connected to the second metal wire 214a and is insulated from the second metal wire 214b and the second metal wire 214c. The first metal wire 213b is connected to the second metal wire 214b and is insulated from the second metal wire 214a and the second metal wire 214c. The first metal wire 213c is connected to the second metal wire 214c and is insulated from the second metal wire 214a and the second metal wire 214b.

[0077] like Figure 7 As shown, the three first metal lines 213a, 213b, and 213c are respectively provided with different waveform voltages VGH, CLK, and VGL, wherein VGH is a high-potential DC voltage, VGL is a low-potential DC voltage, and CLK is an AC voltage that periodically switches between high potential VGH and low potential VGL.

[0078] Exemplarily, VGH is a DC voltage of 5V, VGL is a DC voltage of -5V, and CLK is an AC voltage that periodically switches between 5V and -5V.

[0079] The electric field formed between the first metal layer 21b21 and the second metal layer 21b22 is as follows: Figure 7 As shown in the figure, the circuit is constantly changing, and the electrons are constantly moving, making it easier to capture free electrons. The symbol + represents a 5V voltage, and the symbol - represents a -5V voltage. The greater the voltage difference between the first metal layer 21b21 and the second metal layer 21b22, the stronger the electric field force, the stronger the ability to capture free electrons, and the stronger the ability to capture static charges. The electric field formed between the first metal layer 21b21 and the second metal layer 21b22 acts as an electrostatic protection wall that guides static electricity, greatly protecting the internal circuits of the gate drive circuit area 21b1.

[0080] In one embodiment, the overlapping area between the second metal line 214 and the first metal line 213 is greater than or equal to the overlapping area between the metal test line 212 and the signal transmission line 211. That is, the capacitance formed by the second metal line 214 and the first metal line 213 is greater than or equal to the actual capacitance generated between the metal test line 212 and the signal transmission line 211. A larger overlapping area between the second metal line 214 and the first metal line 213 can form a larger capacitance. A larger capacitance can store more static charge and is less susceptible to electrostatic breakdown. The electrostatic protection area 21b2 can better protect the internal circuits of the gate driver circuit area 21b1 from electrostatic damage.

[0081] It should be noted that the overlapping area between the second metal line 214 and the first metal line 213 refers to the area of ​​the part where the second metal line 214 and the first metal line 213 overlap on different planes; similarly, the overlapping area between the metal test line 212 and the signal transmission line 211 refers to the area of ​​the part where the metal test line 212 and the signal transmission line 211 overlap on different planes.

[0082] See also Figure 4 and Figure 6 As shown, the overlapping area between the second metal line 214 and the first metal line 213 is greater than or equal to the overlapping area between the metal test line 212 and the signal transmission line 211, that is, C1*F1≥C2*F2. Here, C1 represents the width of the first metal line 213, F1 represents the width of the second metal line 214, and C1*F1 represents the overlapping area between the second metal line 214 and the first metal line 213. C2 represents the width of the signal transmission line 211, F2 represents the width of the metal test line 212, and C2*F2 represents the overlapping area between the metal test line 212 and the signal transmission line 211.

[0083] Of course, in other embodiments, it may also be configured that the overlapping area between the second metal line 214 and the first metal line 213 is smaller than the overlapping area between the metal test line 212 and the signal transmission line 211 .

[0084] In one embodiment, the width of the first metal line 213 is greater than or equal to the width of the signal transmission line 211. The larger width of the first metal line 213 helps to form a larger capacitor, and the electrostatic protection area 21b2 can better protect the internal circuits of the gate driver circuit area 21b1 from electrostatic damage.

[0085] Likewise, the width of the second metal line 214 is greater than or equal to the width of the metal test line 212 to form a larger capacitor.

[0086] Of course, in other embodiments, the width of the first metal line 213 may be smaller than the width of the signal transmission line 211 , and / or the width of the second metal line 214 may be smaller than the width of the metal test line 212 .

[0087] In one embodiment, the distance between a first metal line 213 adjacent to the gate driver circuit area 21b1 in the electrostatic protection area 21b2 and the gate driver circuit area 21b1 is greater than or equal to the distance between two adjacent first metal lines 213 in the electrostatic protection area 21b2. The first metal lines 213 in the electrostatic protection area 21b2 are positioned farther away from the gate driver circuit area 21b1 to prevent the electrostatic protection area 21b2 from affecting the internal circuit signals of the gate driver circuit area 21b1.

[0088] like Figure 5 and Figure 6As shown, the distance between a first metal line 213 adjacent to the gate driving circuit area 21b1 in the electrostatic protection area 21b2 and the gate driving circuit area 21b1 is represented by A, and the distance between two adjacent first metal lines 213 in the electrostatic protection area 21b2 is represented by B. In this embodiment, A≥B is set.

[0089] Of course, in other embodiments, it can also be configured that the distance between a first metal line 213 adjacent to the gate drive circuit area 21b1 in the electrostatic protection area 21b2 and the gate drive circuit area 21b1 is smaller than the distance between two adjacent first metal lines 213 in the electrostatic protection area 21b2, that is, setting A <B。

[0090] In one embodiment, the distance between two adjacent second metal lines 214 is less than or equal to the distance between two adjacent metal test lines 212. Figure 5 and Figure 6 As shown, D1≤D2, E≤D2.

[0091] Of course, in other embodiments, it may also be configured that the distance between two adjacent second metal lines 214 is greater than the distance between two adjacent metal test lines 212 .

[0092] In one embodiment, the electrostatic protection area 21b2 has a first distance from the edge of the array substrate 21, and the first distance X>cutting accuracy to ensure that the electrostatic protection area 21b2 is not damaged during mid-board cutting.

[0093] Figure 8 The schematic diagram of the electrostatic protection area provided in the second embodiment of the present application is schematically shown.

[0094] like Figure 8 As shown, the first metal layer 21b21 includes four first metal lines 213, which extend along a first direction and are spaced apart in a second direction. Similarly, the second metal layer 21b22 includes four second metal lines 214, which extend along the second direction and are spaced apart in the first direction. The four first metal lines 213 are configured to receive different voltage signals, thereby forming a voltage differential between the first metal layer 21b21 and the second metal layer 21b22.

[0095] exist Figure 8 In the illustrated embodiment, more first metal wires 213 and second metal wires 214 are provided in the electrostatic protection region 21b2, which can further enhance the electrostatic protection capability of the electrostatic protection region 21b2.

[0096] Of course, in other embodiments, the electrostatic protection region 21b2 may further include more first metal lines 213 and second metal lines 214. For example, the first metal layer 21b21 may include five first metal lines 213, and the second metal layer 21b22 may include five second metal lines 214. For another example, the first metal layer 21b21 may include six first metal lines 213, and the second metal layer 21b22 may include six second metal lines 214, and so on.

[0097] Figure 9 The schematic diagram of the electrostatic protection area provided in the third embodiment of the present application is schematically shown.

[0098] like Figure 9 As shown, in this embodiment, Figure 4 and Figure 8 On the basis of the illustrated embodiment, the width of the second metal line 214 and the first metal line 213 is further increased, thereby increasing the overlapping area of ​​the second metal line 214 and the first metal line 213, and then increasing the electric field formed between the first metal layer 21b21 and the second metal layer 21b22, which can further enhance the electrostatic protection capability of the electrostatic protection area 21b2.

[0099] Figure 10 The schematic diagram of the electrostatic protection area provided in the fourth embodiment of the present application is schematically shown.

[0100] like Figure 10 As shown, in this embodiment, Figure 4 、 Figure 8 、 Figure 9 The difference from the illustrated embodiment is that the second metal line 214 is no longer divided into a plurality of sub-metal lines arranged at intervals, but is an integrated metal line.

[0101] In summary, the present application simulates the transmission line layer 21b11 and test line layer 21b12 structures of the gate drive circuit area 21b1, and sets an electrostatic protection area 21b2 including a first metal layer 21b21 and a second metal layer 21b22 on the side of the gate drive circuit area 21b1 away from the display area 21a, and sets the first metal layer 21b21 to include multiple first metal wires 213, and the second metal layer 21b22 to include multiple second metal wires 214 overlapping with the first metal wires 213, and each second metal wire 214 is connected to a corresponding first metal wire 213. By configuring at least two first metal wires 213 to be connected to different voltages, a voltage difference can be formed between the first metal layer 21b21 and the second metal layer 21b22, thereby forming an electric field between the first metal layer 21b21 and the second metal layer 21b22, and utilizing the electric field to capture static electricity to protect the internal circuit of the gate drive circuit area 21b1 and prevent the internal circuit of the gate drive circuit area 21b1 from being damaged by static electricity.

[0102] In the above embodiments, the present application is described by taking a liquid crystal display panel and a liquid crystal display as examples. It can be understood that the display panel and the display of the present application may also be other types of display panels and displays.

[0103] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the appended claims.

Claims

1. An array substrate comprising a display area and a non-display area, characterized in that: The non-display area includes: A gate driving circuit area is arranged on one side of the display area; An electrostatic protection area is arranged on a side of the gate drive circuit area away from the display area, and the electrostatic protection area includes a first metal layer and a second metal layer, the first metal layer includes a plurality of first metal wires, and the second metal layer includes a plurality of second metal wires, the second metal wires are arranged to overlap with the first metal wires, and each second metal wire is connected to a corresponding first metal wire, and at least two first metal wires are configured to be used for connecting to different voltages to form a voltage difference between the first metal layer and the second metal layer.

2. The array substrate according to claim 1, wherein: The gate drive circuit area includes a transmission line layer and a test line layer. The transmission line layer includes multiple signal transmission lines. The signal transmission lines are connected to the scan lines of the display area to transmit gate drive signals to the scan lines. The test line layer includes multiple metal test lines. The metal test lines are overlapped with the signal transmission lines, and each metal test line is connected to a corresponding signal transmission line. The first metal layer and the transmission line layer are located on the same layer, and the second metal layer and the test line layer are located on the same layer.

3. The array substrate according to claim 2, wherein: An overlapping area between the second metal line and the first metal line is greater than or equal to an overlapping area between the metal test line and the signal transmission line; and / or The width of the first metal line is greater than or equal to the width of the signal transmission line.

4. The array substrate according to claim 2, wherein: The distance between a first metal line adjacent to the gate driving circuit area in the electrostatic protection area and the gate driving circuit area is greater than or equal to the distance between two adjacent first metal lines in the electrostatic protection area; and / or The distance between two adjacent second metal lines is less than or equal to the distance between two adjacent metal test lines.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The first metal layer includes three first metal wires extending along a first direction, and the three first metal wires are spaced apart in a second direction; the second metal layer includes three second metal wires extending along the second direction, and the three second metal wires are spaced apart in the first direction.

6. The array substrate according to claim 5, wherein: One of the three first metal wires is configured to be used for accessing a DC voltage of a first level, one of the first metal wires is configured to be used for accessing an AC voltage that periodically switches between the first level and a second level, and one of the first metal wires is configured to be used for accessing a DC voltage of the second level.

7. The array substrate according to any one of claims 1 to 4, characterized in that: The second metal line includes a plurality of sub-metal lines, the plurality of sub-metal lines extend in the same direction and are arranged at intervals, and the plurality of sub-metal lines are respectively connected to the same first metal line.

8. The array substrate according to any one of claims 1 to 4, characterized in that: The electrostatic protection area further includes a first insulating layer, which is arranged between the first metal layer and the second metal layer. The first insulating layer is provided with a plurality of vias, and the second metal wire is connected to the first metal wire through the vias.

9. A display panel, characterized in that: The display panel includes: The array substrate as claimed in any one of claims 1 to 8; The color filter substrate is arranged opposite to the array substrate.

10. A display, characterized in that: The display comprises: The display panel as claimed in claim 9; The backlight module is arranged opposite to the display panel and is used for providing backlight for the display panel.

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