Backside illuminated photodiode structure, preparation method and X-ray detector

Abstract

The invention discloses a backside illuminated photodiode structure, a preparation method and an X-ray detector, and belongs to the field of semiconductor photoelectric sensors in nuclear technology application. The backside illuminated photodiode structure comprises: an epitaxial layer comprising an electrode region located on a non-photosensitive side of the epitaxial layer; the first dielectric layer is located on the non-photosensitive side of the epitaxial layer; the electrode and the lead are located on the side, away from the epitaxial layer, of the first dielectric layer and penetrate through the first dielectric layer to be connected with the electrode region; the bonding layer is positioned on one side, deviating from the first dielectric layer, of the electrode and the lead, and covers the electrode and the lead; the slide glass is bonded with one side, deviating from the electrode and the lead, of the bonding layer; and the silicon through hole structure penetrates through the slide glass and the bonding layer and is connected with the electrode and the lead. According to the invention, the wafer breaking risk can be reduced, the method is suitable for a large-size CMOS process line, the production efficiency is improved, the cost is reduced, and peripheral splicing is realized.

Description

Technical Field

[0001] The present application belongs to the field of photoelectric sensors for nuclear technology applications, and in particular, relates to a back-illuminated photodiode structure and preparation method, and an X-ray detector. Background Art

[0002] Back-illuminated photodiodes used for X-ray detection are generally produced using a 6-inch dedicated production line. After forming the electrode pads of the back-illuminated photodiode, the back of the 6-inch wafer needs to be thinned before continuing with subsequent processes. However, as the wafer size increases (such as 8 inches or 12 inches), the mechanical strength of the thinned wafer becomes increasingly poor, the risk of fragmentation increases significantly, and subsequent processes cannot be performed after the wafer is thinned. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a back-illuminated photodiode structure and preparation method, and an X-ray detector, which can reduce the risk of fragmentation, is suitable for large-size wafer process lines, and can achieve circumferential side splicing.

[0004] In a first aspect, the present application provides a back-illuminated photodiode structure, comprising:

[0005] an epitaxial layer, including an electrode region located on a non-photosensitive side of the epitaxial layer;

[0006] A first dielectric layer, located on the non-photosensitive side of the epitaxial layer;

[0007] An electrode and a lead, located on a side of the first dielectric layer away from the epitaxial layer, and penetrating through the first dielectric layer to connect with the electrode region;

[0008] A bonding layer, located on a side of the electrode lead away from the first dielectric layer, and covering the electrode and the lead;

[0009] A carrier sheet bonded to a side of the bonding layer facing away from the electrode lead;

[0010] The through silicon via structure penetrates the carrier and the bonding layer and is connected to the electrode and the lead.

[0011] According to the back-illuminated photodiode structure of the present application, a bonding layer is formed on the non-photosensitive side of the pixel chip and is permanently bonded to the carrier through the bonding layer to increase the mechanical strength of the epitaxial layer and reduce the risk of breakage, so that the back-illuminated photodiode can be produced on a large-size wafer (for example, 12-inch commercial) process line, that is, it is suitable for large-size wafer process lines. Compared with the 6-inch wafer process line, it improves production efficiency and reduces costs. The electrode of the back-illuminated photodiode is led out from the carrier side through the silicon via structure, so that the surrounding side of the back-illuminated photodiode structure can be spliced, which is suitable for large-area pixel arrays.

[0012] According to one embodiment of the present application, the back-illuminated photodiode structure further includes:

[0013] A deep trench isolation structure extends from the photosensitive side of the epitaxial layer into the epitaxial layer, and the deep trench isolation structure is located on the peripheral side of the electrode region, and the photosensitive side is arranged opposite to the non-photosensitive side.

[0014] According to one embodiment of the present application, the back-illuminated photodiode structure further includes:

[0015] The anti-reflection film is located on the photosensitive side of the epitaxial layer.

[0016] According to one embodiment of the present application, the back-illuminated photodiode structure further includes:

[0017] A second dielectric layer is located on a side of the carrier away from the bonding layer, and the through silicon via structure also penetrates the second dielectric layer;

[0018] The pad is located on a side of the second dielectric layer away from the carrier and is connected to the through silicon via structure.

[0019] According to one embodiment of the present application, the thickness of the first dielectric layer is greater than the target thickness. According to one embodiment of the present application, the electrode region includes a high-doped region having a doping type opposite to that of the epitaxial layer, and the electrode and lead include a lead connected to the high-doped region;

[0020] The epitaxial layer also includes a floating doped region located on the non-photosensitive side of the epitaxial layer. The floating doped region has a different doping type from the epitaxial layer. The floating doped region is located at the bottom of the lead and is laterally spaced apart from the electrode region.

[0021] According to an embodiment of the present application, the peripheral side surface of the back-illuminated photodiode structure is a splicable surface.

[0022] In a second aspect, the present application provides an X-ray detector comprising the back-illuminated photodiode structure as described in the first aspect.

[0023] According to one embodiment of the present application, the X-ray detector includes a plurality of spliced ​​back-illuminated photodiode structures.

[0024] In a third aspect, the present application provides a method for preparing a back-illuminated photodiode structure, comprising:

[0025] Providing a substrate, a first dielectric layer, and electrodes and leads, wherein the substrate includes an epitaxial layer, the epitaxial layer includes an electrode region located on a non-photosensitive side of the epitaxial layer, the first dielectric layer is located on the non-photosensitive side of the epitaxial layer, the electrodes and leads are located on a side of the first dielectric layer away from the epitaxial layer, and penetrate the first dielectric layer to connect with the electrode region;

[0026] Forming a bonding layer on a side of the electrode and the lead away from the first dielectric layer, wherein the bonding layer covers the electrode and the lead;

[0027] Bonding the carrier to the side of the bonding layer away from the electrode and the lead;

[0028] Performing a thinning process on a side of the substrate facing away from the first dielectric layer;

[0029] A through silicon via structure is formed that penetrates the carrier and the bonding layer, and the through silicon via structure is connected to the electrode and the lead.

[0030] According to one embodiment of the present application, the substrate is a wafer having a size greater than 6 inches.

[0031] According to one embodiment of the present application, the base further includes a substrate located on a photosensitive side of the epitaxial layer, the photosensitive side being arranged opposite to the non-photosensitive side;

[0032] The thinning process of the side of the substrate facing away from the first dielectric layer comprises:

[0033] The substrate is removed, and a side of the epitaxial layer facing away from the first dielectric layer is thinned.

[0034] According to an embodiment of the present application, after thinning the side of the substrate facing away from the first dielectric layer, the method further includes:

[0035] A deep trench isolation structure is formed on the peripheral side of the electrode region, and the deep trench isolation structure extends from the photosensitive side of the substrate into the epitaxial layer;

[0036] An antireflection film is formed on the photosensitive side of the substrate.

[0037] According to one embodiment of the present application, before forming a through silicon via structure penetrating the carrier and the bonding layer, the method further includes:

[0038] Performing a thinning process on a side of the carrier facing away from the bonding layer;

[0039] A second dielectric layer is formed on a side of the carrier away from the bonding layer, and the through silicon via structure also penetrates the second dielectric layer;

[0040] After forming the through silicon via structure penetrating the carrier and the bonding layer, the method further comprises:

[0041] A pad is formed on a side of the second dielectric layer facing away from the carrier, and the pad is connected to the through silicon via structure.

[0042] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0043] By forming a bonding layer on the non-photosensitive side of the epitaxial layer and permanently bonding it to the carrier through the bonding layer, the mechanical strength of the epitaxial layer is increased and the risk of breakage is reduced, so that back-illuminated photodiodes can be produced on large-size wafer process lines, that is, they are suitable for large-size wafer process lines. Compared with the 6-inch wafer process line, it improves production efficiency and reduces costs. The electrodes of the back-illuminated photodiodes are led out from the carrier side through the silicon via structure, so that the surrounding sides of the back-illuminated photodiode structure can be spliced, which is suitable for large-area pixel arrays.

[0044] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0046] Figure 1 It is one of the structural schematic diagrams of the back-illuminated photodiode structure provided in the embodiment of the present application;

[0047] Figure 2 This is the second structural schematic diagram of the back-illuminated photodiode structure provided in the embodiment of the present application;

[0048] Figure 3 It is a schematic flow chart of a method for preparing a back-illuminated photodiode structure provided in an embodiment of the present application;

[0049] Figure 4 This is one of the structural schematic diagrams of the method for preparing a back-illuminated photodiode structure provided in an embodiment of the present application;

[0050] Figure 5 This is the second structural schematic diagram of the method for preparing a back-illuminated photodiode structure provided in an embodiment of the present application;

[0051] Figure 6 This is the third structural schematic diagram of the method for preparing a back-illuminated photodiode structure provided in an embodiment of the present application;

[0052] Figure 7This is the fourth structural schematic diagram of the method for preparing a back-illuminated photodiode structure provided in an embodiment of the present application;

[0053] Figure 8 This is the fifth structural schematic diagram of the method for preparing a back-illuminated photodiode structure provided in an embodiment of the present application;

[0054] Fig. 9 This is the sixth structural schematic diagram of the method for preparing a back-illuminated photodiode structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0056] The back-illuminated photodiode structure and preparation method, and X-ray detector provided in the embodiments of the present application are described below with reference to the accompanying drawings.

[0057] Figure 1 A schematic diagram of a back-illuminated photodiode structure provided in an embodiment of the present application, wherein the back-illuminated photodiode structure is a back-illuminated photodiode structure based on a CMOS process, and the back-illuminated photodiode can be applied to an X-ray detector, which is a back-illuminated detector.

[0058] When the back-illuminated photodiode in this embodiment is applied to an X-ray detector, the back-illuminated photodiode is used to convert the visible light signal (the scintillator converts the X-ray signal into a visible light signal) into an electrical signal, which is processed by an ADC (analog-to-digital converter) and then output to a data processing and control circuit.

[0059] Among them, the working principle of the back-illuminated photodiode is: when a certain wavelength of light (visible light signal) is incident on the epitaxial layer (such as silicon), and the photon energy is greater than the band gap Eg of silicon (for silicon, that is, the wavelength is less than 1100nm), the electrons in the valence band will absorb the photon energy and transition to the conduction band to form an electron-hole pair. When the electron-hole pair is generated in the depletion region of the PN junction, the electron and the hole will be separated under the action of the built-in electric field. If the circuit outside the PN junction forms a loop, a photocurrent will be formed. When the electron-hole pair is generated outside the depletion region of the PN junction, if the minority carrier lifetime in the corresponding region is long enough, the minority carrier in the electron-hole pair can diffuse into the depletion region and then be collected to form a photocurrent.

[0060] like Figure 1As shown, the back-illuminated photodiode structure provided in the embodiment of the present application includes an epitaxial layer 1, a first dielectric layer 21, electrodes and leads 3, a bonding layer 4, a carrier 5 and a through silicon via structure 6.

[0061] The epitaxial layer 1 includes an electrode region 11, and the electrode region 11 is located on the non-photosensitive side of the epitaxial layer 1. It should be noted that the back side of the epitaxial layer 1 is the photosensitive side, and the photosensitive side refers to the side where light is incident on the epitaxial layer 1. The non-photosensitive side of the epitaxial layer 1 is arranged opposite to the photosensitive side, that is, the front side of the epitaxial layer 1 is the non-photosensitive side, and the electrode region 11 is located on the front side of the epitaxial layer 1. The photosensitive side of the back-illuminated photodiode has no structure such as metal interconnects, which does not affect light incidence, and there is no highly doped "dead zone" on the photosensitive side. Therefore, the quantum efficiency of the back-illuminated photodiode is higher than that of the front-illuminated photodiode, and the quantum efficiency of the back-illuminated photodiode can theoretically reach 100%.

[0062] The resistance of the epitaxial layer 1 is a target resistance, which can be set according to actual needs. The epitaxial layer 1 can be a semiconductor layer including silicon, or a semiconductor layer including other elements. The epitaxial layer 1 can be a first doping type epitaxial layer, and the first doping type can be N-type. For example, a trace amount of pentavalent elements, such as phosphorus, arsenic, etc., can be doped into the epitaxial layer 1 to form an N-type epitaxial layer. In some embodiments, the epitaxial layer 1 is an N-type low-doped epitaxial layer.

[0063] In some embodiments, the electrode region 11 may include a high-doped region (i.e., a first high-doped region 111) having a different doping type from that of the epitaxial layer 1, that is, the first high-doped region 111 has a second doping type, and the second doping type is different from the first doping type. For example, a trivalent element, such as boron, is doped into the first high-doped region 111 to form a P-type high-doped region. In some embodiments, the epitaxial layer 1 is an N-type low-doped epitaxial layer, and the first high-doped region 111 is a P-type high-doped region. The first high-doped region 111 is an electrode of a back-illuminated photodiode, such as a cathode or an anode. The first high-doped region 111 can be connected to a readout circuit (including a power supply) through conductive structures such as electrodes and leads.

[0064] The electrode region 11 may further include a second highly doped region 112 of the same doping type as the epitaxial layer 1, that is, the second highly doped region 112 has the first doping type. The doping concentration of the second highly doped region 112 is greater than the doping concentration of the epitaxial layer 1. In some embodiments, the epitaxial layer 1 is an N-type low-doped epitaxial layer, the first highly doped region 111 is a P-type highly doped region, and the second highly doped region 112 is an N-type highly doped region. The second highly doped region 112 is an electrode of a back-illuminated photodiode, such as a cathode or an anode. The second highly doped region 112 can be grounded through conductive structures such as electrodes and leads.

[0065] The second highly doped region 112 and the first highly doped region 111 are both located on the non-photosensitive side of the epitaxial layer 1, and the second highly doped region 112 is laterally spaced from the first highly doped region 111, where the lateral direction refers to a direction parallel to the front side of the epitaxial layer 1. The second highly doped region 112 and the first highly doped region 111 are different electrodes of a back-illuminated photodiode. For example, the first highly doped region 111 is a cathode, and the second highly doped region 112 is an anode; or, the first highly doped region 111 is an anode, and the second highly doped region 112 is a cathode.

[0066] The first dielectric layer 21 is located on the non-photosensitive side of the epitaxial layer 1, that is, the first dielectric layer 21 is located on the side of the epitaxial layer 1 close to the electrode region 11 and covers the electrode region 11. The first dielectric layer 21 may include silicon oxide or the like.

[0067] The electrode and lead 3 are located on the side of the first dielectric layer 21 away from the epitaxial layer 1, and the electrode and lead 3 vertically penetrate the first dielectric layer 21 and are connected to the electrode region 11, and the vertical direction refers to the direction perpendicular to the front surface of the epitaxial layer 1. The electrode and lead 3 may include one or more combinations of metals such as copper, aluminum, tungsten, platinum, nickel and titanium.

[0068] In some embodiments, the electrode and lead 3 may include a lead (i.e., a first lead 31) connected to the high-doped region (i.e., the first high-doped region 111). The first lead 31 is located on the side of the first dielectric layer 21 away from the epitaxial layer 1, and the first lead 31 vertically penetrates the first dielectric layer 21 and is connected to the first high-doped region 111. The first lead 31 may extend laterally to increase the connection window and facilitate the connection of the through silicon via structure.

[0069] The electrode and lead 3 may further include a second lead 32 connected to the second highly doped region 112, and the second lead 32 is spaced apart from the first lead 31. The second lead 32 is located on the side of the first dielectric layer 21 away from the epitaxial layer 1, and the second lead 32 vertically penetrates the first dielectric layer 21 and is connected to the second highly doped region 112. The second lead 32 may extend laterally to enlarge the connection window and facilitate the connection of the through silicon via structure.

[0070] The bonding layer 4 is located on the side of the electrode and the lead 3 away from the first dielectric layer 21, and covers the electrode and the lead 3. The bonding layer 4 also covers the first dielectric layer 21. The bonding layer 4 may include silicon oxide or the like.

[0071] The carrier 5 is bonded to the side of the bonding layer 4 away from the electrode and the lead 3, and the bonding is a permanent bond. The bonding of the carrier 5 can increase the mechanical strength of the epitaxial layer 1 and reduce the risk of breakage, so that the back-illuminated photodiode structure can be produced on a large-size (such as 8-inch or 12-inch) wafer process line. Compared with the 6-inch wafer process line, the large-size wafer process line has the advantages of high production efficiency, low production cost, and good process stability. This embodiment is suitable for large-size wafer process lines, which can improve the production efficiency of back-illuminated photodiode structures, reduce costs, and improve product stability.

[0072] The thickness of the carrier 5 cannot be too thin to avoid insufficient mechanical strength reinforcement of the epitaxial layer 1, and the thickness of the carrier 5 cannot be too thick to avoid the through silicon via structure 6 being unable to completely penetrate the carrier 5. The thickness of the carrier 5 can meet the through silicon via (TSV) process, for example, the thickness of the carrier 5 is about 200 μm. The carrier 5 can include a wafer or glass.

[0073] The through silicon via structure 6 vertically penetrates the carrier 5 and the bonding layer 4, and the through silicon via structure 6 is connected to the electrode and the lead 3. The electrode region 11 is connected to the through silicon via structure 6 through the electrode and the lead 3, that is, the electrode region 11 is led out to the side of the carrier 5 away from the epitaxial layer 1 through the electrode and the lead 3 and the through silicon via structure 6.

[0074] In some embodiments, the through silicon via structure 6 may include a first through silicon via substructure 61 and a second through silicon via substructure 62 that are laterally spaced apart. The first through silicon via substructure 61 vertically penetrates the wafer carrier 5 and the bonding layer 4, and is connected to the first lead 31, so as to lead the first highly doped region 111 to the side of the wafer carrier 5 away from the epitaxial layer 1 through the first through silicon via substructure 61 and the first lead 31. The second through silicon via substructure 62 vertically penetrates the wafer carrier 5 and the bonding layer 4, and is connected to the second lead 32, so as to lead the second highly doped region 112 to the side of the wafer carrier 5 away from the epitaxial layer 1 through the second through silicon via substructure 62 and the second lead 32.

[0075] In some embodiments, the first through silicon via substructure 61 and the second through silicon via substructure 62 both include a conductive layer 63 and a spacer layer 64. The conductive layer 63 longitudinally penetrates the carrier 5 and the bonding layer 4, and is connected to the electrode and the lead 3, that is, the conductive layer 63 in the first through silicon via substructure 61 longitudinally penetrates the carrier 5 and the bonding layer 4, and is connected to the first lead 31, and the conductive layer 63 in the second through silicon via substructure 62 longitudinally penetrates the carrier 5 and the bonding layer 4, and is connected to the second lead 32. The spacer layer 64 is arranged around the conductive layer 63 to isolate the conductive layer 63 from other film layers. Among them, the conductive layer 63 may include one or more combinations of metals such as copper, aluminum, tungsten, platinum, nickel and titanium, and the spacer layer 64 may include one or more combinations of silicon nitride and silicon oxide.

[0076] The electrode area 11 is led out from the side of the carrier 5 (non-photosensitive side) through the electrode and lead 3 and the silicon through-hole structure 6, so that the peripheral side surface of the back-illuminated photodiode structure is a splicing surface, that is, the peripheral side surface of the back-illuminated photodiode structure can be spliced ​​with the peripheral side surface of other back-illuminated photodiode structures. When the cross-section of the back-illuminated photodiode structure is rectangular, the four sides of the back-illuminated photodiode structure are all splicing surfaces. Multiple back-illuminated photodiode structures can be spliced ​​to form a pixel array of any size, which is suitable for scenes such as security inspection, industrial inspection, and medical imaging.

[0077] In some embodiments, the back-illuminated photodiode structure further includes a deep trench isolation structure (DTI) 7. The deep trench isolation structure 7 extends longitudinally from the photosensitive side of the epitaxial layer 1 into the epitaxial layer 1. The deep trench isolation structure 7 has a high aspect ratio, and the extension length of the deep trench isolation structure 7 can be adjusted according to the thickness of the epitaxial layer 1, such as the extension length of the deep trench isolation structure 7 can be half the thickness of the epitaxial layer 1, which is not specifically limited here. The deep trench isolation structure 7 is located on the peripheral side of the electrode region 11, such as the deep trench isolation structure 7 can be set along the boundary of the pixel unit.

[0078] The related art improves the problem of crosstalk between pixels by increasing the spacing between the photosensitive areas of adjacent pixels, but the increased spacing will reduce the photosensitive area of ​​the pixel, thereby reducing the external quantum efficiency. In contrast, the present embodiment isolates adjacent pixel units by providing a deep trench isolation structure 7, thereby significantly reducing the crosstalk between pixels without affecting the photosensitive area.

[0079] In some embodiments, the back-illuminated photodiode structure further includes an anti-reflection film 8, which is located on the photosensitive side of the epitaxial layer 1, that is, the anti-reflection film 8 is located on the side of the epitaxial layer 1 away from the electrode and the lead 3. The anti-reflection film 8 may include one or more combinations of silicon oxide and silicon nitride.

[0080] In this embodiment, an anti-reflection film 8 is provided on the photosensitive side of the epitaxial layer 1 to reduce light reflection and increase the intensity of transmitted light, thereby improving the external quantum efficiency.

[0081] In some embodiments, the back-illuminated photodiode structure further includes a second dielectric layer 22 and a pad 9. The second dielectric layer 22 is located on the side of the carrier 5 away from the bonding layer 4, and the through silicon via structure 6 also penetrates the second dielectric layer 22, that is, the through silicon via structure 6 vertically penetrates the second dielectric layer 22, the carrier 5 and the bonding layer 4, and is connected to the electrode and the lead 3. The second dielectric layer 22 may include one or more combinations of silicon nitride and silicon oxide.

[0082] The pad 9 is located on the side of the second dielectric layer 22 away from the carrier 5 and connected to the through silicon via structure 6. The pad 9 is connected to the conductive layer 63 in the through silicon via structure 6. The pad 9 may include one or more combinations of metals such as copper, aluminum, tungsten, platinum, nickel and titanium.

[0083] In some embodiments, the pad 9 may include a first solder joint 91 and a second solder joint 92 that are laterally spaced apart. The first solder joint 91 is located on the side of the second dielectric layer 22 away from the carrier 5, and is connected to the conductive layer 62 in the first through silicon via substructure 61, so that the first highly doped region 111 is led out through the first lead 31, the first through silicon via substructure 61, and the first solder joint 91. The first solder joint 91 may be connected to a power supply or signal line, so that the first highly doped region 111 is connected to a power supply or signal line through the first lead 31, the first through silicon via substructure 61, and the first solder joint 91. The second solder joint 92 is located on the side of the second dielectric layer 22 away from the carrier 5, and is connected to the conductive layer 62 in the first through silicon via substructure 61, so that the second highly doped region 112 is led out through the second lead 32, the second through silicon via substructure 62, and the second solder joint 92. The second solder joint 92 may be a power supply or signal line, so that the second highly doped region 112 is connected to a power supply or signal line through the second lead 32, the second through silicon via substructure 62, and the second solder joint 92.

[0084] In some embodiments, the thickness of the first dielectric layer 21 is greater than the target thickness. For example, the target thickness is greater than 100 nm. A parasitic capacitor is formed between the first lead 31 and the epitaxial layer 1. By increasing the thickness of the first dielectric layer 21 between the first lead 31 and the epitaxial layer 1, the parasitic capacitor can be reduced.

[0085] In some embodiments, Figure 2 As shown, the epitaxial layer 1 also includes a floating doped region 12 located on the non-photosensitive side of the epitaxial layer 1. The floating doped region 12 is located at the bottom of the lead (i.e., the first lead 31), that is, the orthographic projection of the first lead 31 on the epitaxial layer 1 covers the floating doped region 12. The floating doped region 12 is laterally spaced apart from the electrode region 11, that is, the floating doped region 12 is laterally spaced apart from the first high-doped region 111 and the second high-doped region 112, respectively.

[0086] The depth and width of the floating doping region 12 are not specifically limited. The floating doping region 12 has a doping type opposite to that of the epitaxial layer 1, that is, the floating doping region 12 has a second doping type. The doping concentration of the floating doping region 12 is not specifically limited, that is, the floating doping region 12 can be a low-doping region or a high-doping region.

[0087] In some embodiments, the epitaxial layer 1 is an N-type low-doped epitaxial layer, the first high-doped region 111 and the floating doped region 12 are both P-type high-doped regions, and the second high-doped region 112 is an N-type high-doped region. The first high-doped region 111 and the floating doped region 12 can be formed simultaneously without adding additional masks, thereby avoiding increasing process complexity and production costs.

[0088] A parasitic capacitor is formed between the first lead 31 and the epitaxial layer 1 . A floating doped region 12 is added at the bottom of the first lead 31 to form a junction capacitor between the floating doped region 12 and the epitaxial layer 1 . The junction capacitor is connected in series with the parasitic capacitor, thereby reducing the parasitic capacitor.

[0089] To summarize, according to the back-illuminated photodiode structure provided in the embodiment of the present application, a bonding layer 4 is formed on the non-photosensitive side of the epitaxial layer 1, and the bonding layer 4 is permanently bonded to the carrier 5, so as to increase the mechanical strength of the epitaxial layer 1 and reduce the risk of breakage, so that the back-illuminated photodiode can be produced on a large-size (for example, 12-inch commercial) wafer process line, that is, it is suitable for large-size wafer process lines, improves production efficiency, and reduces costs, and the electrode of the back-illuminated photodiode is led out from the side of the carrier 5 through the silicon via structure 6, so that the surrounding side of the back-illuminated photodiode structure can be spliced, which is suitable for large-area pixel arrays.

[0090] Accordingly, an embodiment of the present application also provides an X-ray detector.

[0091] The X-ray detector provided in the embodiment of the present application includes a back-illuminated photodiode structure. The back-illuminated photodiode structure is the back-illuminated photodiode in the above embodiment, which will not be described in detail here.

[0092] Among them, X-ray detectors can be used in security inspection, industrial inspection, and medical imaging. Scintillators are used to convert X-ray signals into visible light signals, and then back-illuminated photodiodes are used to convert visible light signals into electrical signals, which are then processed by ADCs and output to signal processing and control circuits.

[0093] In some embodiments, the X-ray detector may include a plurality of back-illuminated photodiode structures that are spliced ​​together. The back-illuminated photodiode structure is a spliceable structure, that is, the peripheral side of the back-illuminated photodiode structure is a spliceable surface. When the cross-section of the back-illuminated photodiode structure is rectangular, the four sides of the back-illuminated photodiode structure are all spliceable surfaces. Multiple back-illuminated photodiode structures can be spliced ​​together to form a large-area pixel array, which is suitable for scenes such as X-ray CT.

[0094] Correspondingly, an embodiment of the present application also provides a method for preparing a back-illuminated photodiode structure, which can prepare the back-illuminated photodiode structure in the above embodiment.

[0095] like Figure 3 As shown, the method for preparing a back-illuminated photodiode structure provided in the embodiment of the present application includes steps 110 to 150.

[0096] Step 110, provide a substrate, a first dielectric layer, and electrodes and leads, the substrate includes an epitaxial layer, the epitaxial layer includes an electrode area located on the non-photosensitive side of the epitaxial layer, the first dielectric layer is located on the non-photosensitive side of the epitaxial layer, the electrodes and leads are located on the side of the first dielectric layer away from the epitaxial layer, and penetrate the first dielectric layer to connect with the electrode area.

[0097] Combination Figure 4 As shown, a substrate 10 is provided, and the substrate 10 may include an epitaxial layer 1. In some embodiments, the substrate 10 may also include a substrate 13, that is, the epitaxial layer 1 is formed on the substrate 13 by a thin film deposition process. The doping types of the epitaxial layer 1 and the substrate 13 may be the same or different. For example, the epitaxial layer 1 may be an N-type low-doped epitaxial layer, and the substrate 13 may be a P-type high-doped substrate.

[0098] In some embodiments, the substrate 10 is a wafer having a size greater than 6 inches, for example, the substrate 10 may be an 8-inch wafer or a 12-inch wafer, that is, the back-illuminated photodiode in this embodiment may be produced on an 8-inch wafer process line or a 12-inch wafer process line.

[0099] The related art uses a 6-inch wafer dedicated production line to produce back-illuminated photodiodes, that is, a 6-inch wafer is used as a substrate to produce back-illuminated photodiodes. Compared with the 6-inch wafer dedicated production line, the large-size (greater than 6 inches) wafer process line has the advantages of high production efficiency, low production cost, and good process stability. This embodiment uses a large-size wafer process line to produce back-illuminated photodiodes, which can improve the production efficiency of the back-illuminated photodiode structure, reduce costs, and improve process stability.

[0100] Then, the non-photosensitive side of the epitaxial layer 1 is doped by an ion implantation process, and activated by high temperature annealing, to form an electrode region 3 on the non-photosensitive side of the epitaxial layer 1. The electrode region 11 may include a first highly doped region 111 having a different doping type from that of the epitaxial layer 1 and a second highly doped region 112 having the same doping type as that of the epitaxial layer 1. For example, the first highly doped region 111 is a P-type highly doped region, and the second highly doped region 112 is an N-type highly doped region. The second highly doped region 112 and the first highly doped region 111 are both located on the non-photosensitive side of the epitaxial layer 1, and the second highly doped region 112 is laterally spaced from the first highly doped region 111. One of the second highly doped region 112 and the first highly doped region 111 is an anode, and the other is a cathode.

[0101] It should be noted that the first highly doped region 111 and the second highly doped region 112 have different doping types, and two masks are required to form the first highly doped region 111 and the second highly doped region 112 respectively. The order of forming the first highly doped region 111 and the second highly doped region 112 is not specifically limited.

[0102] Then, a first dielectric layer 21 is formed on the non-photosensitive side of the epitaxial layer 1 by a thin film deposition process (such as chemical vapor deposition CVD). Two through holes are formed in the first dielectric layer 21 by an etching process, and the two through holes correspond to the positions of the first high-doped region 111 and the second high-doped region 112, respectively.

[0103] Then, a metal layer is formed on the side of the first dielectric layer 21 away from the epitaxial layer 1 through a thin film deposition process, and the metal layer fills two through holes, respectively contacting the first high-doped region 111 and the second high-doped region 112 to form a low-resistance contact. The metal layer is etched through an etching process to form an electrode and a lead 3. The electrode and the lead 3 include a first lead 31 connected to the first high-doped region 111 and a second lead 32 connected to the second high-doped region 112, and the first lead 31 and the second lead 32 are arranged laterally spaced apart.

[0104] Step 120: forming a bonding layer on a side of the electrode and the lead facing away from the first dielectric layer, and the bonding layer covers the electrode and the lead.

[0105] Combination Figure 5 As shown, a thin film deposition process (such as CVD) is used to form a bonding layer 4 on the side of the electrode and lead 3 away from the first dielectric layer 21, and the bonding layer 4 covers the electrode and lead 3 and also covers the first dielectric layer 21. A CMP (Chemical Mechanical Polishing) process is used to grind the side of the bonding layer 4 away from the electrode and lead 3 to facilitate subsequent bonding with the carrier 5.

[0106] Step 130: Bond the carrier to the side of the bonding layer facing away from the electrodes and leads.

[0107] Combination Figure 6 As shown, the carrier 5 is permanently bonded to the side of the bonding layer 4 facing away from the electrode and the lead 3 to increase the mechanical strength of the wafer, so that this embodiment is suitable for large-size wafer process lines.

[0108] Step 140: Thinning the side of the substrate away from the first dielectric layer.

[0109] In the case where the substrate 10 includes an epitaxial layer 1, the thinning process on the side of the substrate away from the first dielectric layer in step 140 includes: thinning the side of the epitaxial layer 1 away from the first dielectric layer 21. During the thinning process, the resistance of the epitaxial layer 1 is monitored, and when the resistance of the epitaxial layer 1 reaches the target resistance, the thinning of the epitaxial layer 1 is stopped, that is, the resistance of the epitaxial layer 1 after thinning is the target resistance. The target resistance can be set according to actual needs and is not specifically limited here.

[0110] In the case where the base 10 includes the epitaxial layer 1 and the substrate 13 , the step 140 of thinning the side of the base away from the first dielectric layer includes: removing the substrate and thinning the side of the epitaxial layer away from the first dielectric layer.

[0111] Combination Figure 7 As shown, the side of the substrate 10 away from the first dielectric layer 21 is thinned, such as removing the substrate 13, and the side of the epitaxial layer 1 away from the first dielectric layer 21 is thinned. During the thinning process, the resistance of the substrate 10 is monitored, and when the resistance of the substrate 10 reaches the target resistance, the thinning of the substrate 10 is stopped, that is, the resistance of the substrate 10 after thinning is the target resistance.

[0112] After forming electrodes and leads, the related art directly thins the side of the substrate away from the electrodes and leads. The mechanical strength after thinning is weak, which increases the risk of fragmentation. In addition, most current large-size machines cannot transfer thinned wafers, resulting in the inability to continue subsequent processes after wafer thinning. However, this embodiment forms a bonding layer 4 on the electrodes and leads 3 and permanently bonds it to the carrier 5, which increases the mechanical strength of the wafer and reduces the risk of fragmentation. It is suitable for large-size wafer process lines.

[0113] In some embodiments, after thinning the side of the substrate facing away from the first dielectric layer in step 140, the method further includes: forming a deep trench isolation structure on the peripheral side of the electrode region, and the deep trench isolation structure extends from the photosensitive side of the substrate into the epitaxial layer; and forming an anti-reflection film on the photosensitive side of the substrate.

[0114] Combination Figure 8 As shown, an etching process is used to form a deep trench with a high aspect ratio on the photosensitive side of the epitaxial layer 1, the deep trench extends from the photosensitive side of the epitaxial layer 1 to the inside of the epitaxial layer 1, and the deep trench is arranged around the peripheral side of the electrode area 11. A deep trench structure 7 is formed in the deep trench by a surface passivation process and an oxide filling process. The deep trench isolation structure 7 can isolate adjacent pixel units to significantly reduce crosstalk between pixels without affecting the area of ​​the photosensitive area.

[0115] Then, an anti-reflection film 8 is formed on the photosensitive side of the epitaxial layer 1 to reduce light reflection and increase the intensity of transmitted light, thereby improving quantum efficiency.

[0116] It should be noted that the above process is completed based on the CMOS production line, and the subsequent processes are generally completed by the packaging factory. The structure completed by the CMOS production line is a wafer structure, which includes multiple back-illuminated photodiode chips. The wafer structure can be cut later to obtain a single back-illuminated photodiode chip.

[0117] Step 150: forming a through silicon via structure penetrating the carrier and the bonding layer, and the through silicon via structure is connected to the electrode and the lead.

[0118] In some embodiments, before forming a through silicon via structure penetrating the carrier and the bonding layer in step 150, the method further includes: thinning the side of the carrier facing away from the bonding layer; forming a second dielectric layer on the side of the carrier facing away from the bonding layer, and the through silicon via structure also penetrates the second dielectric layer.

[0119] Combination Fig. 9 As shown, the side of the carrier 5 facing away from the bonding layer 4 is thinned to a suitable thickness. The thickness of the carrier 5 after thinning cannot be too thin to avoid that the mechanical strength of the wafer will be insufficient for subsequent processes, and the thickness of the carrier 5 after thinning cannot be too thick to avoid that the subsequent through silicon via process cannot completely penetrate the carrier 5.

[0120] Then, combine Figure 1 As shown, a second dielectric layer 22 is formed on the side of the carrier 5 away from the bonding layer 4 by a thin film deposition process. A plurality of through silicon vias (including a first through silicon via and a second through silicon via) are formed by an etching process. The through silicon vias penetrate the second dielectric layer 22, the carrier 5 and the bonding layer 4 to expose the electrodes and the leads 3. The first through silicon via and the second through silicon via expose the first leads 31 and the second leads 32, respectively. A spacer layer 64 is formed on the sidewalls of the first through silicon via and the second through silicon via by a thin film deposition process, and then a conductive layer 63 is filled in the first through silicon via and the second through silicon via, thereby forming a through silicon via structure 6. The through silicon via structure 6 may include a first through silicon via substructure 61 located in the first through silicon via and a second through silicon via substructure 62 located in the second through silicon via.

[0121] After forming the through silicon via structure penetrating the carrier and the bonding layer in step 150, the method further comprises:

[0122] A pad is formed on the side of the second dielectric layer facing away from the carrier, and the pad is connected to the through silicon via structure.

[0123] Combination Figure 1 As shown, a pad 9 is formed on the side of the second dielectric layer 22 away from the carrier 5 by a thin film deposition process. The pad 9 may include a first solder joint 91 and a second solder joint 92 arranged laterally at intervals. The first solder joint 91 and the second solder joint 92 are respectively connected to the first lead 31 and the second lead 32 through the first silicon through hole structure 61 and the second silicon through hole structure 62, so that the anode and cathode of the back-illuminated photodiode are led out to the side of the carrier 5 (non-photosensitive side), so that the peripheral side surface of the back-illuminated photodiode structure is a splicing surface.

[0124] It should be noted that the order of processing the photosensitive surface and processing the substrate side is not limited. In some embodiments, the substrate side processing is performed first, including substrate thinning, through silicon vias and subsequent processes, and then the photosensitive surface processing is performed, including substrate thinning, deep trench isolation and anti-reflection film growth, etc. In this case, all processes are completed by the foundry.

[0125] In some embodiments, the thickness of the first dielectric layer 21 is greater than a target thickness to reduce the parasitic capacitance between the first lead 31 and the epitaxial layer 1 .

[0126] In some embodiments, the epitaxial layer 1 further includes a floating doped region 12 located on the non-photosensitive side of the epitaxial layer 1. The floating doped region 12 has a doping type opposite to that of the epitaxial layer 1, is located at the bottom of the first lead 31, and is laterally spaced from the electrode region 11.

[0127] Combination Figure 2 As shown, before forming the first dielectric layer 21, the non-photosensitive side of the epitaxial layer 1 is doped by an ion implantation process to form a floating doped region 12. The order in which the floating doped region 12, the first high-doped region 111, and the second high-doped region 112 are formed is not specifically limited. In some embodiments, the floating doped region 12 and the first high-doped region 111 can be formed at the same time, so that the floating doped region 12 and the first high-doped region 111 have the same doping type and doping concentration, thereby avoiding the need to add additional masks and reducing production costs.

[0128] A parasitic capacitor is formed between the first lead 31 and the epitaxial layer 1 . A floating doped region 12 is added at the bottom of the first lead 31 to form a junction capacitor between the floating doped region 12 and the epitaxial layer 1 . The junction capacitor is connected in series with the parasitic capacitor, thereby reducing the parasitic capacitor.

[0129] To summarize, according to the preparation method of the back-illuminated photodiode structure provided in the embodiment of the present application, a bonding layer 4 is formed on the non-photosensitive side of the epitaxial layer 1, and the bonding layer 4 is permanently bonded to the carrier 5, so as to increase the mechanical strength of the epitaxial layer 1 and reduce the risk of breakage, so that the back-illuminated photodiode can be produced on a large-size wafer process line, that is, it is suitable for a large-size wafer process line, improves production efficiency, and reduces costs, and the electrode of the back-illuminated photodiode is led out from the side of the carrier 5 through the silicon via structure 6, so that the surrounding side of the back-illuminated photodiode structure can be spliced, which is suitable for large-area pixel arrays.

[0130] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0131] In the description of the present application, “plurality” means two or more.

[0132] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0133] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A back-illuminated photodiode structure, characterized in that: include: an epitaxial layer, including an electrode region located on a non-photosensitive side of the epitaxial layer; a first dielectric layer, located on the non-photosensitive side of the epitaxial layer; An electrode and a lead, located on a side of the first dielectric layer away from the epitaxial layer, and penetrating the first dielectric layer to connect to the electrode region; a bonding layer, located on a side of the electrodes and leads facing away from the first dielectric layer, and covering the electrodes and leads; a carrier sheet bonded to a side of the bonding layer facing away from the electrodes and the leads; A through silicon via structure penetrates the carrier and the bonding layer and is connected to the electrodes and leads.

2. The back-illuminated photodiode structure according to claim 1, wherein: The back-illuminated photodiode structure further comprises: A deep trench isolation structure extends from the photosensitive side of the epitaxial layer into the epitaxial layer, and the deep trench isolation structure is located on the peripheral side of the electrode region, and the photosensitive side is arranged opposite to the non-photosensitive side.

3. The back-illuminated photodiode structure according to claim 1, wherein: The back-illuminated photodiode structure further comprises: The antireflection film is located on the photosensitive side of the epitaxial layer.

4. The back-illuminated photodiode structure according to claim 1, wherein: The back-illuminated photodiode structure further comprises: a second dielectric layer, located on a side of the carrier away from the bonding layer, wherein the through silicon via structure also penetrates the second dielectric layer; The pad is located on a side of the second dielectric layer facing away from the carrier and is connected to the through silicon via structure.

5. The back-illuminated photodiode structure according to claim 1, wherein: The thickness of the first dielectric layer is greater than a target thickness.

6. The back-illuminated photodiode structure according to claim 1, wherein: The electrode region includes a high-doping region having a doping type different from that of the epitaxial layer, and the electrode and lead include a lead connected to the high-doping region; The epitaxial layer also includes a floating doped region located on the non-photosensitive side of the epitaxial layer. The floating doped region has a doping type opposite to that of the epitaxial layer. The floating doped region is located at the bottom of the lead and is laterally spaced apart from the electrode region.

7. The back-illuminated photodiode structure according to any one of claims 1 to 6, wherein: The peripheral side surface of the back-illuminated photodiode structure is a splicing surface.

8. An X-ray detector, characterized in that: The method comprises the back-illuminated photodiode structure according to any one of claims 1 to 7.

9. The X-ray detector according to claim 8, characterized in that The X-ray detector includes a plurality of spliced ​​back-illuminated photodiode structures.

10. A method for preparing a back-illuminated photodiode structure, characterized in that: include: Providing a substrate, a first dielectric layer, and electrodes and leads, wherein the substrate includes an epitaxial layer, the epitaxial layer includes an electrode region located on a non-photosensitive side of the epitaxial layer, the first dielectric layer is located on the non-photosensitive side of the epitaxial layer, and the electrodes and leads are located on a side of the first dielectric layer away from the epitaxial layer, and penetrate the first dielectric layer to connect to the electrode region; forming a bonding layer on a side of the electrode and the lead facing away from the first dielectric layer, wherein the bonding layer covers the electrode and the lead; bonding the carrier to the side of the bonding layer facing away from the electrodes and the leads; performing a thinning process on a side of the substrate facing away from the first dielectric layer; A through silicon via structure is formed that penetrates the carrier and the bonding layer, and the through silicon via structure is connected to the electrode and the lead.

11. The method for preparing a back-illuminated photodiode structure according to claim 10, wherein: The substrate is a wafer with a size greater than 6 inches.

12. The method for preparing a back-illuminated photodiode structure according to claim 10, wherein: The base also includes a substrate located on the photosensitive side of the epitaxial layer, the photosensitive side being arranged opposite to the non-photosensitive side; The thinning process on the side of the substrate facing away from the first dielectric layer comprises: The substrate is removed, and a side of the epitaxial layer facing away from the first dielectric layer is thinned.

13. The method for preparing a back-illuminated photodiode structure according to claim 10, wherein: After thinning the side of the substrate facing away from the first dielectric layer, the method further includes: forming a deep trench isolation structure on a peripheral side of the electrode region, wherein the deep trench isolation structure extends from the photosensitive side of the substrate into the epitaxial layer; An antireflection film is formed on the photosensitive side of the substrate.

14. The method for preparing a back-illuminated photodiode structure according to claim 10, wherein: Before forming a through silicon via structure penetrating the carrier and the bonding layer, the method further includes: performing a thinning process on a side of the carrier facing away from the bonding layer; forming a second dielectric layer on a side of the carrier away from the bonding layer, wherein the through silicon via structure also penetrates the second dielectric layer; After forming the through silicon via structure penetrating the carrier and the bonding layer, the method further includes: A pad is formed on a side of the second dielectric layer facing away from the carrier, and the pad is connected to the through silicon via structure.

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