Silicon carbide MOSFET device and preparation method thereof

Abstract

According to the silicon carbide MOSFET device and the preparation method thereof, a short-circuit tolerance enhancing region is additionally arranged beside a channel region, so that the effective channel length of the device is increased, the short-circuit current impact resistance of the device is improved, and the short-circuit tolerance time of the device is prolonged; a current diffusion region is arranged between the short-circuit tolerance enhancement regions to balance the influence on the current conduction capability of the device; an electric field modulation region is additionally arranged between the well regions, so that when the device works in a blocking state, the short-circuit tolerance enhancement region is effectively prevented from being threatened by a high electric field, and the blocking capability of the device is ensured; a current diffusion region is additionally arranged between the electric field modulation regions, and a current modulation region is arranged above the electric field modulation regions, so that the conduction capability of the electric field modulation regions to device current is reduced; the device is simple in structure and preparation method, is highly compatible with a traditional silicon carbide MOSFET preparation process, and can realize batch production.

Description

Technical Field

[0001] The invention relates to a switch device, and in particular to a silicon carbide MOSFET device and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) is a third-generation semiconductor material with excellent characteristics such as large bandgap, high critical breakdown electric field strength, and high thermal conductivity. Power devices based on SiC materials have excellent performance such as high breakdown voltage, high power density, and high operating frequency. SiC MOSFET is a voltage-controlled switching device that is competitive in high-temperature, high-frequency, high-voltage, and high-power applications. Using it to replace silicon-based devices can reduce the system volume to 1 / 3 of the original. However, the higher operating junction temperature and power density of SiCMOSFET place strict requirements on its reliability. As a switching tube device, short-circuit conditions are an extreme condition that SiC MOSFET is very likely to experience. While maintaining the gate conduction mode, the device will directly withstand the impact of bus voltage and short-circuit current. How to improve the short-circuit tolerance of the device is an important issue that needs to be solved in device design. Compared with silicon-based devices (short-circuit tolerance time ≥ 10μs), the short-circuit tolerance time of SiC MOSFET is shorter, about 3μs, mainly due to its shorter channel and lower on-resistance. A lower short-circuit withstand time is not conducive to the feedback control of the drive signal and affects the reliability of the system. Directly increasing the channel length will affect the current conduction capability of the device and affect the sensitivity of the device. Summary of the invention

[0003] Purpose of the invention: The purpose of the present invention is to provide a silicon carbide MOSFET device for decoupling the current conduction capability and short-circuit tolerance of the device; another purpose of the present invention is to provide a method for preparing the device.

[0004] Technical solution: The silicon carbide MOSFET device described in the present invention includes a drain electrode, a drain ohmic contact layer, a heavily doped substrate of the first doping type, a lightly doped first epitaxial layer of the first doping type, a gate dielectric layer, a polysilicon layer of the first doping type, a source ohmic contact layer, a passivation layer, a source electrode and a gate electrode, which are arranged in sequence from bottom to top; a pair of well regions of the second doping type and a channel region of the second doping type are arranged on the top of the lightly doped first epitaxial layer of the first doping type, and a source region of the first doping type and a contact region of the second doping type are arranged in the well region of the second doping type; a short-circuit tolerance enhancement region of the second doping type for increasing the channel length and improving resistance to short-circuit current impact is arranged between the well regions of the second doping type and next to the channel region of the second doping type.

[0005] Furthermore, the first doping type is N-type, and the second doping type is P-type.

[0006] Furthermore, the second doping type short-circuit tolerance enhanced region is arranged parallel to the second doping type channel region, and the short-circuit tolerance enhanced region is adjacent to the channel region, and together with the channel region resists the impact of short-circuit current, effectively increasing the length of the channel region and increasing the short-circuit tolerance time of the device.

[0007] Furthermore, a first current diffusion region is provided between the short-circuit tolerance enhanced regions of the second doping type to balance the influence thereof on the current conduction capability of the device, thereby reducing the influence of the short-circuit tolerance enhanced regions on the current conduction capability of the device and ensuring the sensitivity of the device.

[0008] Furthermore, a plurality of groups of the second doping type short-circuit tolerance enhanced regions are arranged perpendicular to the second doping type channel regions, and the second doping type short-circuit tolerance enhanced regions are spaced apart from the first current diffusion regions for balancing their influence on the current conduction capability of the device. This design can increase the area of ​​the short-circuit tolerance enhanced regions and increase the ability of the device to resist short-circuit current shocks. By increasing the doping concentration of the first current diffusion region, its current conduction capability is increased, thereby ensuring the sensitivity of the device.

[0009] Furthermore, the doping concentration of the first current diffusion region is greater than the doping concentration of the lightly doped first epitaxial layer of the first doping type; the depth of the first current diffusion region is less than, equal to or greater than the depth of the short-circuit tolerance enhancement region of the second doping type. A sufficiently large short-circuit tolerance enhancement region of the second doping type is set in a limited space. In order to balance the influence of this region on the current conduction capability of the device, the doping concentration of the first current diffusion region can be increased or its area can be increased by extending downward.

[0010] Furthermore, a group of electric field modulation areas are arranged below the second doping type short circuit tolerance enhanced area and next to the second doping type well area to shield the short circuit tolerance enhanced area from the threat of high electric field and maintain the blocking capability of the device, thereby ensuring the effectiveness of the device.

[0011] Furthermore, a second current diffusion region for balancing the influence of the electric field modulation region on the current conduction capability of the device is arranged between the electric field modulation region, and a current modulation region for regulating the current of the second current diffusion region is arranged between the second current diffusion region and the electric field modulation region and the second doping type short-circuit tolerance enhanced region and the second doping type channel region, thereby improving the sensitivity of the device while ensuring the effectiveness of the device.

[0012] The present invention also provides a method for preparing a silicon carbide MOSFET device, comprising the following steps:

[0013] Step 1, preparing a heavily doped substrate of a first doping type, and forming a lightly doped first epitaxial layer of the first doping type on the upper surface thereof;

[0014] Step 2, forming a well region of a second doping type and a channel region of a second doping type on an upper surface of the first epitaxial layer lightly doped with a first doping type by an ion implantation process;

[0015] Step 3, forming a source region of the first doping type and a contact region of the second doping type in the well region of the second doping type by an ion implantation process;

[0016] Step 4, forming a short circuit tolerance enhancement region of the second doping type in the first epitaxial layer of the first doping type and between the well regions of the second doping type by an ion implantation process;

[0017] Step 5, forming a gate dielectric layer on the upper surface of the first epitaxial layer of the first doping type, and growing a polysilicon layer on the gate dielectric layer;

[0018] Step 6, using photolithography and etching processes to form a passivation layer, and forming a source window in the passivation layer, forming a source ohmic contact layer in the source window, and forming a source electrode on the surface of the source ohmic contact layer; forming a gate window at a position corresponding to the polysilicon layer in the passivation layer, and forming a gate electrode in the gate window;

[0019] Step 7, forming a drain ohmic contact layer on the bottom surface of the heavily doped substrate of the first doping type, and forming a drain electrode on the surface of the drain ohmic contact layer.

[0020] Furthermore, the step 4 also includes injecting a first current diffusion region between the short-circuit tolerance enhancement regions of the second doping type.

[0021] Furthermore, the doping concentration of the first current diffusion region is greater than the doping concentration of the lightly doped first epitaxial layer of the first doping type; the depth of the first current diffusion region is less than, equal to or greater than the depth of the short-circuit tolerance enhancement region of the second doping type.

[0022] Furthermore, the step 1 or 3 or 4 also includes forming an electric field modulation region by epitaxially or by implantation in the lightly doped first epitaxial layer of the first doping type.

[0023] Furthermore, the step 1 or 3 or 4 also includes epitaxially forming or implanting a second current diffusion region and a current modulation region in the lightly doped first epitaxial layer of the first doping type.

[0024] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: 1. A short-circuit tolerance enhancement area is added next to the channel area to increase the effective channel length of the device, improve the device's ability to resist short-circuit current impact, and increase the short-circuit tolerance time of the device; 2. A current diffusion area is set between the short-circuit tolerance enhancement areas to balance their influence on the current conduction capability of the device; 3. An electric field modulation area is added between the well areas. When the device works in a blocking state, the short-circuit tolerance enhancement area is effectively prevented from being threatened by a high electric field, thereby ensuring the blocking capability of the device; 4. A current diffusion area is added between the electric field modulation areas and a current modulation area is set above them to reduce the electric field modulation area's ability to conduct the device current; 5. The device structure and preparation method are simple, highly compatible with the traditional silicon carbide MOSFET preparation process, and can be mass-produced. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural schematic diagram of the present invention;

[0026] Figure 2 It is a top view of the structure of the present invention;

[0027] Figure 3 This is a schematic diagram of the structure of Embodiment 2 of the present invention;

[0028] Figure 4 It is a top view of the structure of Embodiment 2 of the present invention;

[0029] Figure 5 A top view of the structure of Embodiment 3 of the present invention;

[0030] Figure 6 It is a structural front view of embodiment 3 of the present invention;

[0031] Figure 7 This is a rear view of the structure of Embodiment 3 of the present invention;

[0032] Figure 8 This is a schematic diagram of the structure of Example 4 of the present invention. DETAILED DESCRIPTION

[0033] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0034] Example 1

[0035] like Figure 1 and 2A silicon carbide MOSFET device is shown, comprising a drain electrode 115, a drain ohmic contact layer 111, a heavily doped substrate 104 of a first doping type, a lightly doped first epitaxial layer 102 of a first doping type, a gate dielectric layer 108, a polysilicon layer 109 of a first doping type, a source ohmic contact layer 110, a passivation layer 112, a source electrode 113 and a gate electrode 114 arranged in sequence from bottom to top; a pair of well regions 103 of a second doping type and a channel region 106 of a second doping type are arranged on the top of the lightly doped first epitaxial layer 102 of the first doping type, a source region 104 of a first doping type and a contact region 105 of a second doping type are arranged in the well region 103 of the second doping type, and a short-circuit tolerance enhancement region 107 of a second doping type for increasing the channel length and improving the resistance to short-circuit current impact is arranged between the well regions 103 of the second doping type, beside the channel region 106 of the second doping type and parallel to the channel region 106 of the second doping type. The first doping type is N-type, and the second doping type is P-type.

[0036] The method for preparing the above silicon carbide MOSFET device comprises the following steps:

[0037] Step 1, preparing a heavily doped substrate 101 of a first doping type, and forming a lightly doped first epitaxial layer 102 of a first doping type on the upper surface thereof;

[0038] Step 2, forming a well region 103 of a second doping type and a channel region 106 of a second doping type on the upper surface of the lightly doped first epitaxial layer 102 of the first doping type by an ion implantation process;

[0039] Step 3, forming a source region 104 of the first doping type and a contact region 105 of the second doping type in the well region 103 of the second doping type by an ion implantation process;

[0040] Step 4, forming a second doping type short circuit tolerance enhancement region 107 in the first epitaxial layer 102 of the first doping type and between the second doping type well regions 103 by an ion implantation process;

[0041] Step 5, forming a gate dielectric layer 108 on the upper surface of the first epitaxial layer 102 of the first doping type, and growing a polysilicon layer 109 on the gate dielectric layer 108;

[0042] Step 6, using photolithography and etching processes to form a passivation layer 112, and forming a source window in the passivation layer 112, forming a source ohmic contact layer 110 in the source window, and forming a source electrode 113 on the surface of the source ohmic contact layer 110; forming a gate window in the passivation layer 112 at a position corresponding to the polysilicon layer 109, and forming a gate electrode 114 in the gate window;

[0043] Step 7: forming a drain ohmic contact layer 111 on the bottom surface of the heavily doped substrate 101 of the first doping type, and forming a drain electrode 115 on the surface of the drain ohmic contact layer 111 .

[0044] The above-mentioned silicon carbide MOSFET device adds a second doping type short-circuit tolerance enhancement region 107 next to the second doping type channel region 106 to increase the effective channel length of the device, enhance the device's ability to resist short-circuit current impact, and increase the short-circuit tolerance time of the device.

[0045] Example 2

[0046] like Figure 3 and 4 As shown, different from Example 1, a first current diffusion region 116 for balancing the influence of the second doping type short-circuit tolerance enhancement region 107 on the current conduction capability of the device is further provided. The doping concentration of the diffusion region 116 is greater than the doping concentration of the lightly doped first epitaxial layer 102 of the first doping type, and the depth of the first current diffusion region 116 is equal to the depth of the second doping type short-circuit tolerance enhancement region 107 (the depth of the first current diffusion region 116 can also be set to be greater than or less than the depth of the second doping type short-circuit tolerance enhancement region 107 according to the requirements of the current conduction capability).

[0047] The method for preparing a silicon carbide MOSFET device is different from that of Embodiment 1 in that step 4 further includes implanting a first current diffusion region 116 between the short-circuit tolerance enhancement regions 107 of the second doping type.

[0048] The above silicon carbide MOSFET device adds a second doping type short circuit tolerance enhancement region 107 next to the second doping type channel region 106 to increase the effective channel length of the device, improve the device's ability to resist short circuit current impact, and increase the short circuit tolerance time of the device. At the same time, in order to balance the impact of the second doping type short circuit tolerance enhancement region 107 on the current conduction capability of the device, a first current diffusion region 116 is set between the short circuit tolerance enhancement regions.

[0049] Example 3

[0050] like Figure 5 , 6 As shown in Figure 7, different from Example 2, multiple short-circuit tolerance enhanced regions 107 are arranged perpendicular to the second doping type channel region 106 (4 are drawn in the figure for the convenience of display), and multiple first current diffusion regions 116 are arranged at intervals from the second doping type short-circuit tolerance enhanced regions 107 (4 are drawn in the figure for the convenience of display).

[0051] The preparation method of the above silicon carbide MOSFET device is the same as that of Example 2.

[0052] In the above silicon carbide MOSFET device, a plurality of short-circuit tolerance enhancement regions 107 of the second doping type are arranged perpendicular to the second doping type channel region 106, which can increase the effective area of ​​the short-circuit tolerance enhancement region, thereby maximizing the ability of the device to resist short-circuit current impact and increasing the short-circuit tolerance time of the device. At the same time, a first current diffusion region 116 is arranged between the short-circuit tolerance enhancement regions, and the current conduction capability is increased by increasing the depth of the first current diffusion region 116, thereby balancing the influence of the short-circuit tolerance enhancement region 107 of the second doping type on the current conduction capability of the device to the maximum extent.

[0053] Example 4

[0054] like Figure 8 As shown, different from Example 2, a group of electric field modulation regions 117 for shielding the short-circuit tolerance enhanced region 107 from the threat of high electric fields and maintaining the device blocking capability are arranged below the second doping type short-circuit tolerance enhanced region 107 and next to the second doping type well region 103, current diffusion regions 118 for balancing the influence of the electric field modulation regions 117 on the current conduction capability of the device are arranged between the electric field modulation regions 117, and current modulation regions 119 for regulating the current of the current diffusion region 118 are arranged between the current diffusion region 118 and the electric field modulation region 117 and the second doping type short-circuit tolerance enhanced region 107 and the second doping type channel region 106.

[0055] The method for preparing the silicon carbide MOSFET device is different from that of Example 2 in that it also includes the preparation of an electric field modulation region 117, a second current diffusion region 118, and a current modulation region 119. The preparation of the electric field modulation region 117, the second current diffusion region 118, and the current modulation region 119 can be generated by epitaxy or by an ion implantation process, but the electric field modulation region 117 and the second current diffusion region 118 cannot be formed by epitaxy at the same time. Therefore, it is possible to choose to epitaxially form the electric field modulation region 117 in step 1, and to form the second current diffusion region 118 and the current modulation region 119 by ion implantation in step 3 or step 4; or to choose to form the electric field modulation region 117, the second current diffusion region 118, and the current modulation region 119 by ion implantation in step 3 or step 4; or to complete the preparation by epitaxially forming the electric field modulation region 117 and the current modulation region 119 in step 1, and to form the second current diffusion region 118 by ion implantation in step 3 or step 4.

[0056] In addition to setting the second doping type short-circuit tolerance enhanced region 107 and the first current diffusion region 116, the above-mentioned silicon carbide MOSFET device is provided with a group of electric field modulation regions 117 for shielding the short-circuit tolerance enhanced region 107 from the threat of high electric field and maintaining the blocking capability of the device below the second doping type short-circuit tolerance enhanced region 107 and next to the second doping type well region 103. When the device is working in the blocking state, the second doping type short-circuit tolerance enhanced region 107 is effectively prevented from being threatened by high electric field, thereby ensuring the blocking capability of the device; current diffusion regions 118 are provided between the electric field modulation regions 117 to balance the influence of the electric field modulation regions on the current conduction capability of the device; current modulation regions 119 for adjusting the current of the current diffusion region 118 are provided between the current diffusion region 118 and the electric field modulation region 117 and the second doping type short-circuit tolerance enhanced region 107 and the second doping type channel region 106, thereby reducing the conduction capability of the electric field modulation region on the device current.

Claims

1. A silicon carbide MOSFET device, comprising, arranged in sequence from bottom to top, a drain electrode (115), a drain ohmic contact layer (111), a heavily doped substrate (101) of a first doping type, a lightly doped first epitaxial layer (102) of a first doping type, a gate dielectric layer (108), a polysilicon layer (109) of a first doping type, a source ohmic contact layer (110), a passivation layer (112), a source electrode (113) and a gate electrode (114); a pair of well regions (103) of a second doping type and a channel region (106) of a second doping type are arranged on the top of the lightly doped first epitaxial layer (102) of the first doping type, and a source region (104) of a first doping type and a contact region (105) of a second doping type are arranged in the well region (103) of the second doping type; and the characteristic is that: A second doping type short circuit tolerance enhancement region (107) for increasing the channel length and improving the resistance to short circuit current impact is provided between the second doping type well regions (103) and beside the second doping type channel region (106).

2. The silicon carbide MOSFET device according to claim 1, characterized in that: The first doping type is N-type, and the second doping type is P-type.

3. The silicon carbide MOSFET device according to claim 1, characterized in that: The second doping type short circuit tolerance enhancement region (107) is arranged in parallel with the second doping type channel region (106).

4. The silicon carbide MOSFET device according to claim 2, characterized in that: A first current diffusion region (116) is provided between the second doping type short circuit tolerance enhancement regions (107) for balancing the influence of the second doping type on the current conduction capability of the device.

5. The silicon carbide MOSFET device according to claim 1, characterized in that: A plurality of groups of the second doping type short circuit tolerance enhancement regions (107) are arranged perpendicular to the second doping type channel regions (106).

6. The silicon carbide MOSFET device according to claim 5, characterized in that: A first current diffusion region (116) for balancing the influence of the second doping type short-circuit tolerance enhancement region (107) on the current conduction capability of the device is arranged between the second doping type short-circuit tolerance enhancement region (107) and the first current diffusion region (116) for balancing the influence of the second doping type short-circuit tolerance enhancement region (107) on the current conduction capability of the device is arranged at intervals.

7. The silicon carbide MOSFET device according to claim 4 or 6, characterized in that: The doping concentration of the first current diffusion region (116) is greater than the doping concentration of the lightly doped first epitaxial layer (102) of the first doping type.

8. The silicon carbide MOSFET device according to claim 1, characterized in that: A group of electric field modulation regions (117) are provided below the second doping type short circuit tolerance enhancement region (107) and next to the second doping type well region (103) to shield the short circuit tolerance enhancement region (107) from the threat of high electric field and maintain the blocking capability of the device.

9. The silicon carbide MOSFET device according to claim 8, characterized in that: A second current diffusion region (118) is provided between the electric field modulation regions (117) to balance the effect of the electric field modulation region (117) on the current conduction capability of the device.

10. The silicon carbide MOSFET device according to claim 9, characterized in that: A current modulation region (119) for regulating the current of the second current diffusion region (118) is provided between the second current diffusion region (118) and the electric field modulation region (117) and the second doping type short circuit tolerance enhancement region (107) and the second doping type channel region (106).

11. A method for preparing a silicon carbide MOSFET device according to any one of claims 1 to 10, characterized in that: The steps include: A heavily doped substrate (101) of a first doping type is prepared, and a lightly doped first epitaxial layer (102) of the first doping type is formed on the upper surface of the substrate; Forming a well region (103) of a second doping type and a channel region (106) of a second doping type on the upper surface of a lightly doped first epitaxial layer (102) of a first doping type by an ion implantation process; Forming a source region (104) of a first doping type and a contact region (105) of a second doping type in a well region (103) of a second doping type by an ion implantation process; Forming a second doping type short circuit tolerance enhancement region (107) within the first doping type first epitaxial layer (102) and between the second doping type well regions (103) by an ion implantation process; Forming a gate dielectric layer (108) on the upper surface of a first epitaxial layer (102) of a first doping type, and growing a polysilicon layer (109) on the gate dielectric layer (108); Using photolithography and etching processes, a passivation layer (112) is formed, a source window is formed in the passivation layer (112), a source ohmic contact layer (110) is formed in the source window, and a source electrode (113) is formed on the surface of the source ohmic contact layer (110); a gate window is formed in the passivation layer (112) at a position corresponding to the polysilicon layer (109), and a gate electrode (114) is formed in the gate window; A drain ohmic contact layer (111) is formed on the bottom surface of a heavily doped substrate (101) of a first doping type, and a drain electrode (115) is formed on the surface of the drain ohmic contact layer (111).

12. The method for preparing a silicon carbide MOSFET device according to claim 11, characterized in that: The first doping type is N-type, and the second doping type is P-type.

13. The method for preparing a silicon carbide MOSFET device according to claim 11, characterized in that: The step of implanting the second doping type short circuit tolerance enhancement region (107) also includes implanting to form a first current diffusion region (116).

14. The method for preparing a silicon carbide MOSFET device according to claim 13, characterized in that: The doping concentration of the first current diffusion region (116) is greater than the doping concentration of the lightly doped first epitaxial layer (102) of the first doping type.

15. The method for preparing a silicon carbide MOSFET device according to claim 11, characterized in that: An electric field modulation region (117) is formed in the lightly doped first epitaxial layer (102) of the first doping type.

16. The method for preparing a silicon carbide MOSFET device according to claim 15, characterized in that: A second current diffusion region (118) and a current modulation region (119) are formed in the lightly doped first epitaxial layer (102) of the first doping type.

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