Driving circuit and display device

Abstract

A driving circuit and a display device. The driving circuit comprises a pull-up node noise reduction circuit (11), an input circuit (12), a first output noise reduction circuit (13) and a pull-down node noise reduction circuit (14); at least one transistor included in the driving circuit is a floating processing transistor, the floating processing transistor comprises a floating electrode, a gate, a first electrode and a second electrode; the floating electrode is arranged in the same layer as at least one of the first electrode and the second electrode of the floating processing transistor; the floating electrode is arranged between the first electrode and the second electrode of the floating processing transistor, and the floating electrode has no electrical signal input; and the shortest distance between the first electrode of the floating processing transistor and the second electrode of the floating processing transistor is greater than an initial distance. The problems of insufficient high-voltage output and no output of the driving circuit can be solved, and the problems of multiple output and low-voltage floating of the output curve of the driving circuit can be solved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit and a display device. Background Art

[0002] In the related art, there are problems with insufficient high voltage output and no output of the high-mobility GOA (Gate On Array, a gate driving circuit set on the array substrate). There are also problems with multiple outputs of the high-mobility GOA and the output curve floating at low voltage. Summary of the Invention

[0003] In one aspect, an embodiment of the present disclosure provides a driving circuit including a pull-up node noise reduction circuit, an input circuit, a first output noise reduction circuit, and a pull-down node noise reduction circuit;

[0004] The pull-up node noise reduction circuit is electrically connected to the pull-up node, the pull-up node noise reduction control terminal and the first voltage terminal, and under the control of the pull-up node noise reduction control signal provided by the pull-up node noise reduction control terminal, the pull-up node noise reduction circuit controls the connection between the pull-up node and the first voltage terminal;

[0005] The input circuit is electrically connected to the input terminal and the pull-up node respectively, and is used to control the potential of the pull-up node under the control of the input signal provided by the input terminal;

[0006] The first output noise reduction circuit is electrically connected to the pull-down node, the output terminal, and the second voltage terminal, respectively, and is configured to control the connection between the output terminal and the second voltage terminal under the control of the potential of the pull-down node;

[0007] The pull-down node noise reduction circuit is electrically connected to the pull-down node, the pull-down node noise reduction control terminal, and the third voltage terminal, respectively, and is configured to control the connection between the pull-down node and the third voltage terminal under the control of a pull-down node noise reduction control signal provided by the pull-down node noise reduction control terminal;

[0008] At least one transistor included in the driving circuit is a floating process transistor, comprising a floating electrode, a gate, a first electrode, and a second electrode; the floating electrode and at least one of the first electrode and the second electrode of the floating process transistor are arranged on the same layer; the floating electrode is arranged between the first electrode and the second electrode of the floating process transistor, and no electrical signal is input to the floating electrode; and the shortest distance between the first electrode of the floating process transistor and the second electrode of the floating process transistor is greater than an initial distance.

[0009] Optionally, at least one of the pull-up node noise reduction circuit, the input circuit, the first output noise reduction circuit, and the pull-down node noise reduction circuit includes the floating processing transistor, and the floating processing transistor includes A floating electrodes, where A is greater than or equal to 1 and less than or equal to 3.

[0010] Optionally, the floating electrode, the first electrode and the second electrode of the floating process transistor are all located in the first metal layer;

[0011] The shortest distance between the first electrode and the second electrode is greater than or equal to the first distance and less than or equal to the second distance;

[0012] The first distance is the difference between the initial distance and 3um, and the second distance is the sum of the initial distance and 3um.

[0013] Optionally, the output end is a carry signal output end;

[0014] The input end is the adjacent upper M-level carry signal output end, where M is a positive integer.

[0015] Optionally, the output end is a drive signal output end;

[0016] The input end is the adjacent M-level drive signal output end, where M is a positive integer.

[0017] Optionally, the pull-down node includes a first pull-down node and a second pull-down node; the pull-up node noise reduction control terminal includes the first pull-down node, the second pull-down node, a reset terminal, and a frame reset terminal; the reset terminal is an output terminal of an adjacent lower N-level carry signal, where N is a positive integer;

[0018] The pull-up node noise reduction circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0019] The gate of the first transistor is electrically connected to the first pull-down node, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0020] The gate of the second transistor is electrically connected to the second pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0021] The gate of the third transistor is electrically connected to the reset terminal, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the first voltage terminal;

[0022] A gate of the fourth transistor is electrically connected with the frame reset end, a first electrode of the fourth transistor is electrically connected with the pull-up node, and a second electrode of the fourth transistor is electrically connected with the first voltage end;

[0023] At least one of the first transistor, the second transistor, the third transistor and the fourth transistor is a floating processing transistor.

[0024] Optionally, the pull-down node comprises a first pull-down node and a second pull-down node; the pull-up node noise reduction control end comprises the first pull-down node, the second pull-down node, a reset end and a frame reset end; the reset end is an adjacent N-level driving signal output end, and N is a positive integer;

[0025] The pull-up node noise reduction circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor.

[0026] A gate of the first transistor is electrically connected with the first pull-down node, a first electrode of the first transistor is electrically connected with the pull-up node, and a second electrode of the first transistor is electrically connected with the first voltage end;

[0027] A gate of the second transistor is electrically connected with the second pull-down node, a first electrode of the second transistor is electrically connected with the pull-up node, and a second electrode of the second transistor is electrically connected with the first voltage end;

[0028] A gate of the third transistor is electrically connected with the reset end, a first electrode of the third transistor is electrically connected with the pull-up node, and a second electrode of the third transistor is electrically connected with the first voltage end;

[0029] A gate of the fourth transistor is electrically connected with the frame reset end, a first electrode of the fourth transistor is electrically connected with the pull-up node, and a second electrode of the fourth transistor is electrically connected with the first voltage end;

[0030] At least one of the first transistor, the second transistor, the third transistor and the fourth transistor is a floating processing transistor.

[0031] Optionally, the input circuit comprises a fifth transistor;

[0032] A gate of the fifth transistor and a first electrode of the fifth transistor are both electrically connected with the input end, and a second electrode of the fifth transistor is electrically connected with the pull-up node;

[0033] The fifth transistor is a floating processing transistor.

[0034] Optionally, the first output noise reduction circuit comprises a sixth transistor and a seventh transistor;

[0035] a gate of the sixth transistor is electrically connected with a first pull-down node, a first electrode of the sixth transistor is electrically connected with the output terminal, and a second electrode of the sixth transistor is electrically connected with the second voltage terminal;

[0036] a gate of the seventh transistor is electrically connected with a second pull-down node, a first electrode of the seventh transistor is electrically connected with the output terminal, and a second electrode of the seventh transistor is electrically connected with the second voltage terminal;

[0037] At least one of the sixth transistor and the seventh transistor is a floating processing transistor.

[0038] Optionally, the pull-down node noise reduction circuit includes an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor; the pull-down node includes a first pull-down node and a second pull-down node; and the pull-down node noise reduction control terminal includes a pull-up node and an input terminal.

[0039] a gate of the eighth transistor is electrically connected with the pull-up node, a first electrode of the eighth transistor is electrically connected with the first pull-down node, and a second electrode of the eighth transistor is electrically connected with a third voltage terminal;

[0040] a gate of the ninth transistor is electrically connected with the input terminal, a first electrode of the ninth transistor is electrically connected with the first pull-down node, and a second electrode of the ninth transistor is electrically connected with the third voltage terminal;

[0041] a gate of the tenth transistor is electrically connected with the pull-up node, a first electrode of the tenth transistor is electrically connected with the second pull-down node, and a second electrode of the tenth transistor is electrically connected with the third voltage terminal;

[0042] a gate of the eleventh transistor is electrically connected with the input terminal, a first electrode of the eleventh transistor is electrically connected with the second pull-down node, and a second electrode of the eleventh transistor is electrically connected with the third voltage terminal;

[0043] At least one of the eighth transistor, the ninth transistor, the tenth transistor and the eleventh transistor is a floating processing transistor.

[0044] Optionally, the driving circuit further includes a second output noise reduction circuit, an output circuit and a pull-down node control circuit.

[0045] The second output noise reduction circuit is electrically connected to the first pull-down node, the second pull-down node, the drive signal output terminal, and the fourth voltage terminal, respectively, and is configured to control the communication between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the first pull-down node, and control the communication between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the second pull-down node;

[0046] The pull-down node control circuit is electrically connected to the first pull-down node and the second pull-down node, respectively, and is used to control the potential of the first pull-down node and the potential of the second pull-down node;

[0047] The output circuit is electrically connected to the pull-up node, the first clock signal terminal, the carry signal output terminal and the drive signal output terminal, respectively, and is used to control the connection between the carry signal output terminal and the first clock signal terminal, and control the connection between the drive signal output terminal and the first clock signal terminal under the control of the potential of the pull-up node.

[0048] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes an output circuit and a pull-down node control circuit;

[0049] The pull-down node control circuit is electrically connected to the first pull-down node and the second pull-down node, respectively, and is used to control the potential of the first pull-down node and the potential of the second pull-down node;

[0050] The output circuit is electrically connected to the pull-up node, the first clock signal terminal and the drive signal output terminal respectively, and is used to control the connection between the drive signal output terminal and the first clock signal terminal under the control of the potential of the pull-up node.

[0051] Optionally, the pull-down node control circuit is also electrically connected to the first control voltage terminal and the second control voltage terminal, respectively, and is used to control the connection between the first pull-down node and the first control voltage terminal under the control of a first control voltage provided by the first control voltage terminal, and to control the connection between the second pull-down node and the second control voltage terminal under the control of a second control voltage provided by the second control voltage terminal.

[0052] Optionally, the pull-down node control circuit is also electrically connected to the first clock signal terminal and the second clock signal terminal, respectively, and is used to control the connection between the first pull-down node and the second clock signal terminal under the control of the second clock signal provided by the second clock signal terminal, and to control the connection between the second pull-down node and the first clock signal terminal under the control of the first clock signal provided by the first clock signal terminal.

[0053] In a second aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0055] Figure 2 is a structural diagram of at least one embodiment of a floating process transistor;

[0056] Figure 3 is a circuit diagram of at least one embodiment of a pull-up node noise reduction circuit;

[0057] Figure 4 It is a waveform diagram of the voltage of the pull-up node PU and the waveform diagram of the driving signal provided by the driving signal output terminal Gout after the source-drain floating process is performed on the transistor included in the pull-up node noise reduction circuit;

[0058] Figure 5 is a circuit diagram of at least one embodiment of an input circuit;

[0059] Figure 6 is a circuit diagram of at least one embodiment of a first output noise reduction circuit;

[0060] Figure 7 After the transistors included in the first output noise reduction circuit are subjected to source-drain floating processing, a waveform diagram of the voltage at the pull-up node PU1 of the lower-stage driving circuit whose input end is electrically connected to the output end O1 and a waveform diagram of the driving signal provided by the driving signal output end Gout1 of the lower-stage driving circuit whose input end is electrically connected to the output end O1 are shown;

[0061] Figure 8 is a circuit diagram of at least one embodiment of a pull-down node noise reduction circuit;

[0062] Figure 9 It is a waveform diagram of the voltage of the pull-down node PD and the waveform diagram of the driving signal provided by the driving signal output terminal Gout after the source-drain floating process is performed on the transistor included in the pull-down node noise reduction circuit;

[0063] Figure 10 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0064] Figure 11 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0065] Figure 12 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0066] Figure 13 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0067] Figure 14 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0068] Figure 15 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0069] Figure 16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0070] Figure 17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0072] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0073] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain, and the second electrode may be a source; or, the first electrode may be a source, and the second electrode may be a drain.

[0074] like Figure 1 As shown, the driving circuit according to the embodiment of the present disclosure includes a pull-up node noise reduction circuit 11, an input circuit 12, a first output noise reduction circuit 13 and a pull-down node noise reduction circuit 14;

[0075] The pull-up node noise reduction circuit 11 is electrically connected to the pull-up node PU, the pull-up node noise reduction control terminal K1 and the first voltage terminal V1. Under the control of the pull-up node noise reduction control signal provided by the pull-up node noise reduction control terminal K1, the pull-up node noise reduction circuit 11 controls the connection between the pull-up node PU and the first voltage terminal V1;

[0076] The input circuit 12 is electrically connected to the input terminal I1 and the pull-up node PU, respectively, and is used to control the potential of the pull-up node PU under the control of the input signal provided by the input terminal I1;

[0077] The first output noise reduction circuit 13 is electrically connected to the pull-down node PD, the output terminal O1 and the second voltage terminal V2, respectively, and is used to control the connection between the output terminal O1 and the second voltage terminal V2 under the control of the potential of the pull-down node PD;

[0078] The pull-down node noise reduction circuit 14 is electrically connected to the pull-down node PD, the pull-down node noise reduction control terminal K2, and the third voltage terminal V3, respectively, and is configured to control the connection between the pull-down node PD and the third voltage terminal V3 under the control of the pull-down node noise reduction control signal provided by the pull-down node noise reduction control terminal K2;

[0079] At least one transistor included in the driving circuit is a floating process transistor, comprising a floating electrode, a gate, a first electrode, and a second electrode; the floating electrode is disposed in the same layer as at least one of the first electrode and the second electrode of the floating process transistor; the floating electrode is disposed between the first electrode and the second electrode of the floating process transistor, and no electrical signal is input to the floating electrode; and the shortest distance between the first electrode of the floating process transistor and the second electrode of the floating process transistor is greater than an initial distance.

[0080] In at least one embodiment of the present disclosure, the floating electrode having no electrical signal input may mean that the floating electrode is in a floating state, that is, a structurally disconnected and isolated state, or may mean that the floating electrode is structurally connected but has no signal input.

[0081] In at least one embodiment of the present disclosure, the first voltage terminal, the second voltage terminal, and the third voltage terminal may all be low voltage terminals.

[0082] In the driver circuit described in at least one embodiment of the present disclosure, in a floating process transistor, the shortest distance between the first electrode and the second electrode is greater than an initial distance to increase the threshold voltage of the floating process transistor. A floating electrode is provided between the first electrode and the second electrode, and the floating electrode has no signal input, so that the metal density on the first metal layer (the first electrode, the second electrode, and the floating electrode are all located in the first metal layer) does not vary significantly within a unit area.

[0083] In at least one embodiment of the present disclosure, the initial distance may be the shortest distance between the first electrode of the transistor and the second electrode of the transistor when the source and drain of the transistor are not floated; optionally, the first electrode may be the source and the second electrode may be the drain.

[0084] like Figure 2As shown, S1 is the first electrode of the floating process transistor, D1 is the second electrode of the floating process transistor, F1 is the floating electrode of the floating process transistor, and A1 is the active layer pattern of the floating process transistor;

[0085] The floating electrode is not connected to any electrical signal and is in a floating state.

[0086] like Figure 2 As shown, the length of the channel of the floating process transistor is longer, so the threshold voltage of the floating process transistor becomes larger.

[0087] The first metal layer can be a source-drain metal layer. After the source-drain metal layer is completed, a passivation layer needs to be made. Plasma treatment is used when making the passivation layer. In order to make the effect of plasma acting on the active layer roughly consistent with when the source-drain floating treatment is not performed on the transistor, it is necessary to ensure that the metal density on the first metal layer (the first electrode, the second electrode and the floating electrode are all located on the first metal layer) does not change much.

[0088] In at least one embodiment of the present disclosure, at least one of the pull-up node noise reduction circuit, the input circuit, the first output noise reduction circuit, and the pull-down node noise reduction circuit includes the floating process transistor, and the floating process transistor includes A floating electrodes, where A is greater than or equal to 1 and less than or equal to 3.

[0089] In a specific implementation, the number of floating electrodes included in the floating process transistor may be greater than or equal to 1 and less than or equal to 3, but is not limited thereto.

[0090] In at least one embodiment of the present disclosure, the floating electrode, the first electrode and the second electrode of the floating process transistor are all located in a first metal layer;

[0091] The shortest distance between the first electrode and the second electrode is greater than or equal to the first distance and less than or equal to the second distance;

[0092] The first distance is the difference between the initial distance L0 and 3 μm, and the second distance is the sum of the initial distance L0 and 3 μm.

[0093] In a specific implementation, on the first metal layer, the shortest distance between two adjacent electrodes may be greater than or equal to the first distance and less than or equal to the second distance.

[0094] like Figure 2 As shown, the shortest distance between S1 and F1 is L1, the shortest distance between F1 and D1 is L2, L1 is greater than or equal to the first distance and less than or equal to the second distance, and L2 is greater than or equal to the first distance and less than or equal to the second distance.

[0095] In at least one embodiment of the present disclosure, the driving circuit may be provided on a substrate; the shortest distance between two electrodes may refer to: the shortest distance between orthographic projections of two adjacent electrodes on the substrate;

[0096] The shortest distance between S1 and F1 may refer to: the shortest distance between the orthographic projection of S1 on the substrate and the orthographic projection of F1 on the substrate;

[0097] The shortest distance between F1 and D1 may refer to the shortest distance between the orthographic projection of F1 on the substrate and the orthographic projection of D1 on the substrate.

[0098] In a specific implementation, when two floating electrodes are disposed between the first electrode and the second electrode, and the first electrode, the first floating electrode, the second floating electrode, and the second electrode are arranged sequentially from left to right, the shortest distance between the two floating electrodes is greater than or equal to the first distance and less than or equal to the second distance, the shortest distance between the first electrode and the first floating electrode is greater than or equal to the first distance and less than or equal to the second distance, and the shortest distance between the second floating electrode and the second electrode is greater than or equal to the first distance and less than or equal to the second distance.

[0099] Optionally, the output end is a carry signal output end;

[0100] The input end is the adjacent upper M-level carry signal output end, where M is a positive integer.

[0101] In a specific implementation, the output end may be a carry signal output end, and the input end may be a carry signal output end of an adjacent upper M level.

[0102] Optionally, the output end is a drive signal output end;

[0103] The input end is the adjacent M-level drive signal output end, where M is a positive integer.

[0104] In a specific implementation, the output end may be a driving signal output end, and the input end may be an adjacent upper M-level driving signal output end.

[0105] In at least one embodiment of the present disclosure, the pull-down node may include a first pull-down node and a second pull-down node; the pull-up node noise reduction control terminal may include the first pull-down node, the second pull-down node, a reset terminal, and a frame reset terminal; the reset terminal is an adjacent lower N-level carry signal output terminal, where N is a positive integer;

[0106] The pull-up node noise reduction circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0107] The gate of the first transistor is electrically connected to the first pull-down node, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0108] The gate of the second transistor is electrically connected to the second pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0109] The gate of the third transistor is electrically connected to the reset terminal, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the first voltage terminal;

[0110] The gate of the fourth transistor is electrically connected to the frame reset terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first voltage terminal;

[0111] At least one of the first transistor, the second transistor, the third transistor, and the fourth transistor is a floating process transistor.

[0112] In a specific implementation, the pull-up node noise reduction circuit may include a first transistor, a second transistor, a third transistor and a fourth transistor, the reset end may be an adjacent lower N-level carry signal output end, and at least one of the first transistor, the second transistor, the third transistor and the fourth transistor is a floating processing transistor.

[0113] In at least one embodiment of the present disclosure, the pull-down node includes a first pull-down node and a second pull-down node; the pull-up node noise reduction control terminal includes the first pull-down node, the second pull-down node, a reset terminal, and a frame reset terminal; the reset terminal is an output terminal for the adjacent N-level drive signal, where N is a positive integer;

[0114] The pull-up node noise reduction circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0115] The gate of the first transistor is electrically connected to the first pull-down node, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0116] The gate of the second transistor is electrically connected to the second pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0117] The gate of the third transistor is electrically connected to the reset terminal, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the first voltage terminal;

[0118] The gate of the fourth transistor is electrically connected to the frame reset terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first voltage terminal;

[0119] At least one of the first transistor, the second transistor, the third transistor, and the fourth transistor is a floating process transistor.

[0120] In a specific implementation, the pull-up node noise reduction circuit may include a first transistor, a second transistor, a third transistor and a fourth transistor, the reset end may be an adjacent lower N-level drive signal output end, and at least one of the first transistor, the second transistor, the third transistor and the fourth transistor is a floating processing transistor.

[0121] like Figure 3 As shown, the pull-up node noise reduction circuit includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;

[0122] The gate of the first transistor M1 is electrically connected to the first pull-down node PD1, the first electrode of the first transistor M1 is electrically connected to the pull-up node PU, and the second electrode of the first transistor M1 is electrically connected to the first low voltage terminal LVGL;

[0123] The gate of the second transistor M2 is electrically connected to the second pull-down node PD2, the first electrode of the second transistor M2 is electrically connected to the pull-up node PU, and the second electrode of the second transistor M2 is electrically connected to the first low voltage terminal LVGL;

[0124] The gate of the third transistor M3 is electrically connected to the reset terminal R1, the first electrode of the third transistor M3 is electrically connected to the pull-up node PU, and the second electrode of the third transistor M3 is electrically connected to the first low voltage terminal LVGL;

[0125] The gate of the fourth transistor M4 is electrically connected to the frame reset terminal TRST, the first electrode of the fourth transistor M4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor M4 is electrically connected to the first low voltage terminal LVGL;

[0126] At least one of the first transistor M1 , the second transistor M2 , the third transistor M3 , and the fourth transistor M4 may be a floating process transistor.

[0127] Optionally, the first voltage end may be a first low voltage end, but is not limited thereto.

[0128] exist Figure 3 In at least one embodiment shown, the reset terminal may be an adjacent next N-stage carry signal output terminal or an adjacent next N-stage drive signal output terminal, where N is a positive integer.

[0129] Optionally, the transistor included in the pull-up node noise reduction circuit may be a high-mobility oxide TFT (thin film transistor), but is not limited thereto.

[0130] In at least one embodiment of the present disclosure, the transistor included in the pull-up node noise reduction circuit is subjected to source-drain floating processing to solve the problem that the voltage of the pull-up node is pulled down by the first low voltage signal provided by the first low voltage terminal, thereby improving the problem of insufficient high voltage output or no output of the high-mobility GOA (Gate On Array, a gate drive circuit provided on the array substrate). Figure 4 As shown, after the source-drain floating process is performed on the transistor included in the pull-up node noise reduction circuit, the voltage of the pull-up node PU and the driving signal provided by the driving signal output terminal Gout are normal.

[0131] In a specific implementation, when the transistors included in the pull-up node noise reduction circuit are turned off, their gate-source voltages are greater than or equal to 0V. In the related art, the threshold voltage of the high-mobility oxide TFT is about 0V, and the SS (subthreshold swing) is small. When the threshold voltage of the transistors included in the pull-up node noise reduction circuit is negatively offset by 0.5V, the current of the transistors included in the pull-up node noise reduction circuit when the gate-source voltage is equal to 0V will increase by one order of magnitude. Based on this, at least one embodiment of the present disclosure performs source-drain floating processing on the transistors included in the pull-up node noise reduction circuit to increase the threshold voltage of the transistors included in the pull-up node noise reduction circuit, so that the threshold voltage of the transistors included in the pull-up node noise reduction circuit is greater than 0, thereby ensuring a good off state when the gate-source voltage of the transistors included in the pull-up node noise reduction circuit is 0V, and the leakage current is more than 5 orders of magnitude smaller than that of the transistors that are not subjected to source-drain floating processing.

[0132] Optionally, the input circuit includes a fifth transistor;

[0133] The gate of the fifth transistor and the first electrode of the fifth transistor are both electrically connected to the input terminal, and the second electrode of the fifth transistor is electrically connected to the pull-up node;

[0134] The fifth transistor is a floating process transistor.

[0135] like Figure 5 As shown, the input circuit includes a fifth transistor M5;

[0136] The gate of the fifth transistor M5 and the first electrode of the fifth transistor M5 are both electrically connected to the input terminal I1, and the second electrode of the fifth transistor is electrically connected to the pull-up node PU;

[0137] The fifth transistor M5 may be a floating process transistor.

[0138] In at least one embodiment of the present disclosure, the input terminal may be an adjacent M-level carry signal output terminal or an adjacent M-level drive signal output terminal, where M is a positive integer.

[0139] Optionally, the transistor included in the input circuit may be a high-mobility oxide TFT (thin film transistor), but is not limited thereto.

[0140] In at least one embodiment of the present disclosure, the transistors included in the input circuit are subjected to source-drain floating processing to solve the problem that the voltage of the pull-up node is pulled down by the low voltage provided by the input terminal, thereby improving the problem of insufficient high voltage output or no output of the high-mobility GOA (Gate On Array, a gate drive circuit provided on the array substrate). Figure 4 As shown, after the source-drain floating process is performed on the transistor included in the input circuit, the voltage of the pull-up node PU and the driving signal provided by the driving signal output terminal Gout are normal.

[0141] In a specific implementation, when the transistors included in the input circuit are turned off, their gate-source voltages are greater than or equal to 0V. In related technologies, the threshold voltage of high-mobility oxide TFTs is around 0V, and the SS (subthreshold swing) is small. When the threshold voltage of the transistors included in the input circuit is negatively offset by 0.5V, the current of the transistors included in the input circuit will increase by one order of magnitude when the gate-source voltage is equal to 0V. Based on this, at least one embodiment of the present disclosure performs source-drain floating processing on the transistors included in the input circuit to increase the threshold voltage of the transistors included in the input circuit, so that the threshold voltage of the transistors included in the input circuit is greater than 0, thereby ensuring a good off state when the gate-source voltage of the transistors included in the input circuit is 0V, which is more than 5 orders of magnitude smaller than the leakage current of the transistors that have not undergone source-drain floating processing.

[0142] Optionally, the first output noise reduction circuit includes a sixth transistor and a seventh transistor;

[0143] The gate of the sixth transistor is electrically connected to the first pull-down node, the first electrode of the sixth transistor is electrically connected to the output terminal, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal;

[0144] The gate of the seventh transistor is electrically connected to the second pull-down node, the first electrode of the seventh transistor is electrically connected to the output terminal, and the second electrode of the seventh transistor is electrically connected to the second voltage terminal;

[0145] At least one of the sixth transistor and the seventh transistor is a floating process transistor.

[0146] like Figure 6 As shown, at least one embodiment of the first output noise reduction circuit includes a sixth transistor M6 and a seventh transistor M7;

[0147] The gate of the sixth transistor M6 is electrically connected to the first pull-down node PD1, the first electrode of the sixth transistor M6 is electrically connected to the output terminal O1, and the second electrode of the sixth transistor M6 is electrically connected to the first low voltage terminal LVGL;

[0148] The gate of the seventh transistor M7 is electrically connected to the second pull-down node PD2, the first electrode of the seventh transistor M7 is electrically connected to the output terminal O1, and the second electrode of the seventh transistor M7 is electrically connected to the first low voltage terminal LVGL;

[0149] At least one of the sixth transistor M6 and the seventh transistor M7 is a floating process transistor.

[0150] Optionally, the second voltage end may be a first low voltage end or a second low voltage end, but is not limited thereto.

[0151] exist Figure 6 In at least one embodiment shown, when the driving circuit includes a carry signal output terminal and a driving signal output terminal, the output terminal O1 can be the carry signal output terminal; when the driving circuit only includes a driving signal output terminal, the output terminal O1 can be the driving signal output terminal.

[0152] Optionally, the transistor included in the first output noise reduction circuit may be a high-mobility oxide TFT (thin film transistor), but is not limited thereto.

[0153] In at least one embodiment of the present disclosure, the transistors included in the first output noise reduction circuit are subjected to source-drain floating processing, thereby solving the problem that the high voltage of the output signal provided by the output terminal O1 is pulled down by the first low voltage terminal, and solving the problem that the high voltage of the pull-up node of the lower-level driving circuit whose input terminal is electrically connected to the output terminal O1 is insufficiently raised. Figure 7As shown, after the source-drain floating processing is performed on the transistor included in the first output noise reduction circuit, the voltage of the pull-up node PU1 of the lower-level driving circuit whose input end is electrically connected to the output end O1 and the driving signal provided by the driving signal output end Gout1 of the lower-level driving circuit whose input end is electrically connected to the output end O1 are normal.

[0154] In a specific implementation, when the transistors included in the first output noise reduction circuit are turned off, their gate-source voltages are greater than or equal to 0V. In related technologies, the threshold voltage of a high-mobility oxide TFT is approximately 0V, and the SS (subthreshold swing) is relatively small. When the threshold voltage of the transistors included in the first output noise reduction circuit is negatively offset by 0.5V, the current of the transistors included in the first output noise reduction circuit when the gate-source voltage is equal to 0V will increase by one order of magnitude. Based on this, at least one embodiment of the present disclosure performs source-drain floating processing on the transistors included in the first output noise reduction circuit to increase the threshold voltage of the transistors included in the first output noise reduction circuit, so that the threshold voltage of the transistors included in the first output noise reduction circuit is greater than 0, thereby ensuring a good off state when the gate-source voltage of the transistors included in the first output noise reduction circuit is 0V, and the leakage current is more than 5 orders of magnitude smaller than that of the transistors that do not undergo source-drain floating processing.

[0155] In at least one embodiment of the present disclosure, the pull-down node noise reduction circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; the pull-down node includes a first pull-down node and a second pull-down node; the pull-down node noise reduction control terminal includes a pull-up node and an input terminal;

[0156] The gate of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the third voltage terminal;

[0157] The gate of the ninth transistor is electrically connected to the input terminal, the first electrode of the ninth transistor is electrically connected to the first pull-down node, and the second electrode of the ninth transistor is electrically connected to the third voltage terminal;

[0158] The gate of the tenth transistor is electrically connected to the pull-up node, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the third voltage terminal;

[0159] The gate of the eleventh transistor is electrically connected to the input terminal, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the third voltage terminal;

[0160] At least one of the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor is a floating process transistor.

[0161] Optionally, the transistor included in the pull-down node noise reduction circuit may be a high-mobility oxide TFT (thin film transistor), but is not limited thereto.

[0162] Optionally, the third voltage end may be the first low voltage end, but is not limited thereto.

[0163] like Figure 8 As shown, the pull-down node noise reduction circuit includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11; the pull-down node includes a first pull-down node PD1 and a second pull-down node PD2; the pull-down node noise reduction control terminal includes a pull-up node PU and an input terminal I1;

[0164] The gate of the eighth transistor M8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor M8 is electrically connected to the first pull-down node PD1, and the second electrode of the eighth transistor M8 is electrically connected to the first low voltage terminal LVGL;

[0165] The gate of the ninth transistor M9 is electrically connected to the input terminal I1, the first electrode of the ninth transistor M9 is electrically connected to the first pull-down node PD1, and the second electrode of the ninth transistor M9 is electrically connected to the first low voltage terminal LVGL;

[0166] The gate of the tenth transistor M10 is electrically connected to the pull-up node PU, the first electrode of the tenth transistor M10 is electrically connected to the second pull-down node PD2, and the second electrode of the tenth transistor M10 is electrically connected to the first low voltage terminal LVGL;

[0167] The gate of the eleventh transistor M11 is electrically connected to the input terminal I1, the first electrode of the eleventh transistor M11 is electrically connected to the second pull-down node PD2, and the second electrode of the eleventh transistor M11 is electrically connected to the first low voltage terminal LVGL;

[0168] At least one of the eighth transistor M8 , the ninth transistor M9 , the tenth transistor M10 , and the eleventh transistor M11 is a floating process transistor.

[0169] In at least one embodiment of the present disclosure, the transistors included in the pull-down node noise reduction circuit are subjected to source-drain floating processing to solve the problem that the high voltage of the pull-down node is pulled down by the first low voltage terminal, thereby improving the problem of multiple outputs of high-mobility GOA (Gate On Array, a gate drive circuit provided on an array substrate) and the low-voltage floating of the output curve. Figure 9 As shown, after the source-drain floating process is performed on the transistor included in the pull-down node noise reduction circuit, the voltage of the pull-down node PD is normal, and the driving signal provided by the driving signal output terminal Gout is normal.

[0170] In a specific implementation, when the transistors included in the pull-down node noise reduction circuit are turned off, their gate-source voltages are greater than or equal to 0V. In the related art, the threshold voltage of the high-mobility oxide TFT is about 0V, and the SS (subthreshold swing) is small. When the threshold voltage of the transistors included in the pull-down node noise reduction circuit is negatively offset by 0.5V, the current of the transistors included in the pull-down node noise reduction circuit when the gate-source voltage is equal to 0V will increase by one order of magnitude. Based on this, at least one embodiment of the present disclosure performs source-drain floating processing on the transistors included in the pull-down node noise reduction circuit to increase the threshold voltage of the transistors included in the pull-down node noise reduction circuit, so that the threshold voltage of the transistors included in the pull-down node noise reduction circuit is greater than 0, thereby ensuring a good off state when the gate-source voltage of the transistors included in the pull-down node noise reduction circuit is 0V, and the leakage current is more than 5 orders of magnitude smaller than that of the transistors that do not undergo source-drain floating processing.

[0171] In at least one embodiment of the present disclosure, the transistors included in the pull-up node noise reduction circuit, the transistors included in the input circuit, the transistors included in the first output noise reduction circuit, and the transistors included in the pull-down node noise reduction circuit can all be subjected to source-drain floating processing, thereby improving the problem of insufficient high-voltage output and no output of the high-mobility GOA, and also improving the problem of multiple outputs of the high-mobility GOA and low-voltage floating of the output curve.

[0172] The driving circuit according to at least one embodiment of the present disclosure further includes a second output noise reduction circuit, an output circuit, and a pull-down node control circuit;

[0173] The second output noise reduction circuit is electrically connected to the first pull-down node, the second pull-down node, the drive signal output terminal, and the fourth voltage terminal, respectively, and is configured to control the communication between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the first pull-down node, and control the communication between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the second pull-down node;

[0174] The pull-down node control circuit is electrically connected to the first pull-down node and the second pull-down node, respectively, and is used to control the potential of the first pull-down node and the potential of the second pull-down node;

[0175] The output circuit is electrically connected to the pull-up node, the first clock signal terminal, the carry signal output terminal and the drive signal output terminal, respectively, and is used to control the connection between the carry signal output terminal and the first clock signal terminal, and control the connection between the drive signal output terminal and the first clock signal terminal under the control of the potential of the pull-up node.

[0176] In a specific implementation, when the output end is a carry signal output end, the driving circuit may further include a second output noise reduction circuit, an output circuit and a pull-down node control circuit, wherein the second output noise reduction circuit is used to reduce the noise of the driving signal provided by the driving signal output end, the pull-down node control circuit controls the potential of the pull-down node, and the output circuit controls the driving signal output end to provide the driving signal.

[0177] Optionally, the fourth voltage end may be the second low voltage end, but is not limited thereto.

[0178] like Figure 10 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the output terminal is a carry signal output terminal Out_C; at least one embodiment of the driving circuit further includes a second output noise reduction circuit 21, an output circuit 22, and a pull-down node control circuit 23; the pull-down node includes a first pull-down node PD1 and a second pull-down node PD2; the first voltage terminal, the second voltage terminal, and the third voltage terminal are all first low voltage terminals LVGL;

[0179] The pull-up node noise reduction control terminal includes the first pull-down node PD1, the second pull-down node PD2, a reset terminal R1 and a frame reset terminal TRST;

[0180] The pull-down node noise reduction control terminal includes a pull-up node PU and an input terminal I1;

[0181] The second output noise reduction circuit 21 is electrically connected to the first pull-down node PD1, the second pull-down node PD2, the drive signal output terminal Gout, and the second low voltage terminal VGL, respectively, and is configured to control the communication between the drive signal output terminal Gout and the second low voltage terminal VGL under the control of the potential of the first pull-down node PD1, and control the communication between the drive signal output terminal Gout and the second low voltage terminal VGL under the control of the potential of the second pull-down node PD2;

[0182] The pull-down node control circuit 23 is electrically connected to the first pull-down node PD1 and the second pull-down node PD2, respectively, and is used to control the potential of the first pull-down node PD1 and the potential of the second pull-down node PD2;

[0183] The output circuit 22 is electrically connected to the pull-up node PU, the first clock signal terminal CLK, the carry signal output terminal Out_C and the drive signal output terminal Gout, respectively, and is used to control the connection between the carry signal output terminal Out_C and the first clock signal terminal CLK, and control the connection between the drive signal output terminal Gout and the first clock signal terminal CLK under the control of the potential of the pull-up node PU.

[0184] like Figure 11 As shown, in Figure 10 Based on at least one embodiment of the driving circuit shown,

[0185] The pull-down node control circuit 23 may also be electrically connected to the first control voltage terminal VDDo and the second control voltage terminal VDDe, respectively, and configured to control the connection between the first pull-down node PD1 and the first control voltage terminal VDDo under the control of a first control voltage provided by the first control voltage terminal VDDo, and to control the connection between the second pull-down node PD2 and the second control voltage terminal VDDe under the control of a second control voltage provided by the second control voltage terminal VDDe;

[0186] When the first control voltage is a high voltage, the second control voltage is a low voltage;

[0187] When the first control voltage is a low voltage, the second control voltage is a high voltage.

[0188] like Figure 12 As shown, in Figure 10 Based on at least one embodiment of the driving circuit shown,

[0189] The pull-down node control circuit 23 can also be electrically connected to the first clock signal terminal CLK and the second clock signal terminal CLKB, respectively, to control the connection between the first pull-down node PD1 and the second clock signal terminal CLKB under the control of the second clock signal provided by the second clock signal terminal CLKB, and to control the connection between the second pull-down node PD2 and the first clock signal terminal CLK under the control of the first clock signal provided by the first clock signal terminal CLK.

[0190] In at least one embodiment of the present disclosure, the first clock signal may be in opposite phase to the second clock signal.

[0191] The driving circuit according to at least one embodiment of the present disclosure further includes an output circuit and a pull-down node control circuit;

[0192] The pull-down node control circuit is electrically connected to the first pull-down node and the second pull-down node, respectively, and is used to control the potential of the first pull-down node and the potential of the second pull-down node;

[0193] The output circuit is electrically connected to the pull-up node, the first clock signal terminal and the drive signal output terminal respectively, and is used to control the connection between the drive signal output terminal and the first clock signal terminal under the control of the potential of the pull-up node.

[0194] In a specific implementation, when the output end is a drive signal output end, the drive circuit described in at least one embodiment of the present disclosure may further include an output circuit and a pull-down node control circuit, wherein the pull-down node control circuit controls the potential of the first pull-down node and the potential of the second pull-down node, and the output circuit controls the drive signal output end to provide a drive signal.

[0195] like Figure 13 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the output terminal is a driving signal output terminal Gout; the pull-down node includes a first pull-down node PD1 and a second pull-down node PD2; at least one embodiment of the driving circuit further includes an output circuit 22 and a pull-down node control circuit 23; the first voltage terminal and the third voltage terminal are a first low voltage terminal LVGL, and the second voltage terminal is a second low voltage terminal VGL;

[0196] The pull-down node control circuit 23 is electrically connected to the first pull-down node PD1 and the second pull-down node PD2, respectively, and is used to control the potential of the first pull-down node PD1 and the potential of the second pull-down node PD2;

[0197] The output circuit 22 is electrically connected to the pull-up node PU, the first clock signal terminal CLK and the drive signal output terminal Gout respectively, and is used to control the connection between the drive signal output terminal Gout and the first clock signal terminal CLK under the control of the potential of the pull-up node PU.

[0198] like Figure 14 As shown, in Figure 13 Based on at least one embodiment of the driving circuit shown,

[0199] The pull-down node control circuit 23 may also be electrically connected to the first control voltage terminal VDDo and the second control voltage terminal VDDe, respectively, and configured to control the connection between the first pull-down node PD1 and the first control voltage terminal VDDo under the control of a first control voltage provided by the first control voltage terminal VDDo, and to control the connection between the second pull-down node PD2 and the second control voltage terminal VDDe under the control of a second control voltage provided by the second control voltage terminal VDDe;

[0200] When the first control voltage is a high voltage, the second control voltage is a low voltage;

[0201] When the first control voltage is a low voltage, the second control voltage is a high voltage.

[0202] like Figure 15 As shown, in Figure 13 Based on at least one embodiment of the driving circuit shown,

[0203] The pull-down node control circuit 23 can also be electrically connected to the first clock signal terminal CLK and the second clock signal terminal CLKB, respectively, to control the connection between the first pull-down node PD1 and the second clock signal terminal CLKB under the control of the second clock signal provided by the second clock signal terminal CLKB, and to control the connection between the second pull-down node PD2 and the first clock signal terminal CLK under the control of the first clock signal provided by the first clock signal terminal CLK.

[0204] In at least one embodiment of the present disclosure, the first clock signal may be in opposite phase to the second clock signal.

[0205] like Figure 16 As shown, in Figure 11 Based on at least one embodiment of the driving circuit shown,

[0206] The pull-up node noise reduction circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;

[0207] The gate of the first transistor M1 is electrically connected to the first pull-down node PD1, the first electrode of the first transistor M1 is electrically connected to the pull-up node PU, and the second electrode of the first transistor M1 is electrically connected to the first low voltage terminal LVGL;

[0208] The gate of the second transistor M2 is electrically connected to the second pull-down node PD2, the first electrode of the second transistor M2 is electrically connected to the pull-up node PU, and the second electrode of the second transistor M2 is electrically connected to the first low voltage terminal LVGL;

[0209] The gate of the third transistor M3 is electrically connected to the reset terminal R1, the first electrode of the third transistor M3 is electrically connected to the pull-up node PU, and the second electrode of the third transistor M3 is electrically connected to the first low voltage terminal LVGL;

[0210] The gate of the fourth transistor M4 is electrically connected to the frame reset terminal TRST, the first electrode of the fourth transistor M4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor M4 is electrically connected to the first low voltage terminal LVGL;

[0211] The input circuit 12 includes a fifth transistor M5;

[0212] The gate of the fifth transistor M5 and the first electrode of the fifth transistor M5 are both electrically connected to the input terminal I1, and the second electrode of the fifth transistor is electrically connected to the pull-up node PU;

[0213] The first output noise reduction circuit 13 includes a sixth transistor M6 and a seventh transistor M7;

[0214] The gate of the sixth transistor M6 is electrically connected to the first pull-down node PD1, the first electrode of the sixth transistor M6 is electrically connected to the carry signal output terminal Out_C, and the second electrode of the sixth transistor M6 is electrically connected to the first low voltage terminal LVGL;

[0215] The gate of the seventh transistor M7 is electrically connected to the second pull-down node PD2, the first electrode of the seventh transistor M7 is electrically connected to the carry signal output terminal Out_C, and the second electrode of the seventh transistor M7 is electrically connected to the first low voltage terminal LVGL;

[0216] The pull-down node noise reduction circuit 14 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11; the pull-down node includes a first pull-down node PD1 and a second pull-down node PD2; the pull-down node noise reduction control terminal includes a pull-up node PU and an input terminal I1;

[0217] The gate of the eighth transistor M8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor M8 is electrically connected to the first pull-down node PD1, and the second electrode of the eighth transistor M8 is electrically connected to the first low voltage terminal LVGL;

[0218] The gate of the ninth transistor M9 is electrically connected to the input terminal I1, the first electrode of the ninth transistor M9 is electrically connected to the first pull-down node PD1, and the second electrode of the ninth transistor M9 is electrically connected to the first low voltage terminal LVGL;

[0219] The gate of the tenth transistor M10 is electrically connected to the pull-up node PU, the first electrode of the tenth transistor M10 is electrically connected to the second pull-down node PD2, and the second electrode of the tenth transistor M10 is electrically connected to the first low voltage terminal LVGL;

[0220] The gate of the eleventh transistor M11 is electrically connected to the input terminal I1, the first electrode of the eleventh transistor M11 is electrically connected to the second pull-down node PD2, and the second electrode of the eleventh transistor M11 is electrically connected to the first low voltage terminal LVGL;

[0221] The second output noise reduction circuit 21 includes a twelfth transistor M12 and a thirteenth transistor M13;

[0222] The gate of the twelfth transistor M12 is electrically connected to the first pull-down node PD1, the first electrode of the twelfth transistor M12 is electrically connected to the driving signal output terminal Gout, and the second electrode of the twelfth transistor M12 is electrically connected to the second low voltage terminal VGL;

[0223] The gate of the thirteenth transistor M13 is electrically connected to the second pull-down node PD2, the first electrode of the thirteenth transistor M13 is electrically connected to the driving signal output terminal Gout, and the second electrode of the thirteenth transistor M13 is electrically connected to the second low voltage terminal VGL;

[0224] The pull-down node control circuit 23 includes a fourteenth transistor M14 and a fifteenth transistor M15;

[0225] The gate of the fourteenth transistor M14 and the first electrode of the fourteenth transistor M14 are electrically connected to the first control voltage terminal VDDo, and the second electrode of the fourteenth transistor M14 is electrically connected to the pull-up node PU;

[0226] The gate of the fifteenth transistor M15 and the first electrode of the fifteenth transistor M15 are electrically connected to the second control voltage terminal VDDe, and the second electrode of the fifteenth transistor M15 is electrically connected to the pull-up node PU;

[0227] The output circuit 22 includes a sixteenth transistor M16 and a seventeenth transistor M17;

[0228] The gate of the sixteenth transistor M16 is electrically connected to the pull-up node PU, the first electrode of the sixteenth transistor M16 is electrically connected to the first clock signal terminal CLK, and the second electrode of the sixteenth transistor M16 is electrically connected to the carry signal output terminal Out_C;

[0229] A gate of the seventeenth transistor M17 is electrically connected to the pull-up node PU, a first electrode of the seventeenth transistor M17 is electrically connected to the first clock signal terminal CLK, and a second electrode of the seventeenth transistor M17 is electrically connected to the driving signal output terminal Gout.

[0230] exist Figure 16 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0231] exist Figure 16 In at least one embodiment of the driving circuit shown, a source-drain floating process may be performed on at least one of M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, and M11.

[0232] like Figure 17 As shown, in Figure 14 Based on at least one embodiment of the driving circuit shown,

[0233] The pull-up node noise reduction circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;

[0234] The gate of the first transistor M1 is electrically connected to the first pull-down node PD1, the first electrode of the first transistor M1 is electrically connected to the pull-up node PU, and the second electrode of the first transistor M1 is electrically connected to the first low voltage terminal LVGL;

[0235] The gate of the second transistor M2 is electrically connected to the second pull-down node PD2, the first electrode of the second transistor M2 is electrically connected to the pull-up node PU, and the second electrode of the second transistor M2 is electrically connected to the first low voltage terminal LVGL;

[0236] The gate of the third transistor M3 is electrically connected to the reset terminal R1, the first electrode of the third transistor M3 is electrically connected to the pull-up node PU, and the second electrode of the third transistor M3 is electrically connected to the first low voltage terminal LVGL;

[0237] The gate of the fourth transistor M4 is electrically connected to the frame reset terminal TRST, the first electrode of the fourth transistor M4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor M4 is electrically connected to the first low voltage terminal LVGL;

[0238] The input circuit 12 includes a fifth transistor M5;

[0239] The gate of the fifth transistor M5 and the first electrode of the fifth transistor M5 are electrically connected with the input terminal I1, and the second electrode of the fifth transistor is electrically connected with the pull-up node PU;

[0240] The first output noise reduction circuit 13 comprises a sixth transistor M6 and a seventh transistor M7;

[0241] The gate of the sixth transistor M6 is electrically connected with the first pull-down node PD1, the first electrode of the sixth transistor M6 is electrically connected with the driving signal output terminal Gout, and the second electrode of the sixth transistor M6 is electrically connected with the first low voltage terminal LVGL;

[0242] The gate of the seventh transistor M7 is electrically connected with the second pull-down node PD2, the first electrode of the seventh transistor M7 is electrically connected with the driving signal output terminal Gout, and the second electrode of the seventh transistor M7 is electrically connected with the first low voltage terminal LVGL;

[0243] The pull-down node noise reduction circuit 14 comprises an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and an eleventh transistor M11; the pull-down node comprises a first pull-down node PD1 and a second pull-down node PD2; the pull-down node noise reduction control end comprises a pull-up node PU and an input terminal I1;

[0244] The gate of the eighth transistor M8 is electrically connected with the pull-up node PU, the first electrode of the eighth transistor M8 is electrically connected with the first pull-down node PD1, and the second electrode of the eighth transistor M8 is electrically connected with the first low voltage terminal LVGL;

[0245] The gate of the ninth transistor M9 is electrically connected with the input terminal I1, the first electrode of the ninth transistor M9 is electrically connected with the first pull-down node PD1, and the second electrode of the ninth transistor M9 is electrically connected with the first low voltage terminal LVGL;

[0246] The gate of the tenth transistor M10 is electrically connected with the pull-up node PU, the first electrode of the tenth transistor M10 is electrically connected with the second pull-down node PD2, and the second electrode of the tenth transistor M10 is electrically connected with the first low voltage terminal LVGL;

[0247] The gate of the eleventh transistor M11 is electrically connected with the input terminal I1, the first electrode of the eleventh transistor M11 is electrically connected with the second pull-down node PD2, and the second electrode of the eleventh transistor M11 is electrically connected with the first low voltage terminal LVGL;

[0248] The pull-down node control circuit 23 comprises a fourteenth transistor M14 and a fifteenth transistor M15;

[0249] The gate of the fourteenth transistor M14 and the first electrode of the fourteenth transistor M14 are electrically connected with the first control voltage terminal VDDo, and the second electrode of the fourteenth transistor M14 is electrically connected with the pull-up node PU;

[0250] The gate of the fifteenth transistor M15 and the first electrode of the fifteenth transistor M15 are electrically connected with the second control voltage terminal VDDe, and the second electrode of the fifteenth transistor M15 is electrically connected with the pull-up node PU;

[0251] The output circuit 22 includes a seventeenth transistor M17.

[0252] The gate of the seventeenth transistor M17 is electrically connected with the pull-up node PU, the first electrode of the seventeenth transistor M17 is electrically connected with the first clock signal terminal CLK, and the second electrode of the seventeenth transistor M17 is electrically connected with the driving signal output terminal Gout.

[0253] In at least one embodiment of the driving circuit shown in Figure 17 In at least one embodiment of the driving circuit shown in

[0254] In at least one embodiment of the driving circuit shown in Figure 17 In at least one embodiment of the driving circuit shown in

[0255] The display device provided by the embodiments of the present disclosure includes the driving circuit described above.

[0256] The above describes the preferred embodiments of the present disclosure. It should be noted that, for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, which should also be considered within the scope of protection of the present disclosure.

Claims

1. A driving circuit comprising a pull-up node noise reduction circuit, an input circuit, a first output noise reduction circuit, and a pull-down node noise reduction circuit; The pull-up node noise reduction circuit is electrically connected to the pull-up node, the pull-up node noise reduction control terminal and the first voltage terminal, and under the control of the pull-up node noise reduction control signal provided by the pull-up node noise reduction control terminal, the pull-up node noise reduction circuit controls the connection between the pull-up node and the first voltage terminal; The input circuit is electrically connected to the input terminal and the pull-up node respectively, and is used to control the potential of the pull-up node under the control of the input signal provided by the input terminal; The first output noise reduction circuit is electrically connected to the pull-down node, the output terminal, and the second voltage terminal, respectively, and is configured to control the connection between the output terminal and the second voltage terminal under the control of the potential of the pull-down node; The pull-down node noise reduction circuit is electrically connected to the pull-down node, the pull-down node noise reduction control terminal, and the third voltage terminal, respectively, and is configured to control the connection between the pull-down node and the third voltage terminal under the control of a pull-down node noise reduction control signal provided by the pull-down node noise reduction control terminal; At least one transistor included in the driving circuit is a floating process transistor, comprising a floating electrode, a gate, a first electrode, and a second electrode; the floating electrode and at least one of the first electrode and the second electrode of the floating process transistor are arranged on the same layer; the floating electrode is arranged between the first electrode and the second electrode of the floating process transistor, and no electrical signal is input to the floating electrode; and the shortest distance between the first electrode of the floating process transistor and the second electrode of the floating process transistor is greater than an initial distance.

2. The driving circuit according to claim 1, wherein: At least one of the pull-up node noise reduction circuit, the input circuit, the first output noise reduction circuit, and the pull-down node noise reduction circuit includes the floating process transistor, which includes A floating electrodes, where A is greater than or equal to 1 and less than or equal to 3.

3. The driving circuit according to claim 2, wherein: The floating electrode and the first electrode and the second electrode of the floating process transistor are all located in the first metal layer; The shortest distance between the first electrode and the second electrode is greater than or equal to the first distance and less than or equal to the second distance; The first distance is the difference between the initial distance and 3 μm, and the second distance is the sum of the initial distance and 3 μm.

4. The driving circuit according to claim 1, wherein: The output end is a carry signal output end; The input end is the adjacent upper M-level carry signal output end, where M is a positive integer.

5. The driving circuit according to claim 1, wherein: The output end is a driving signal output end; The input end is the adjacent M-level drive signal output end, where M is a positive integer.

6. The driving circuit according to claim 4, wherein: The pull-down node includes a first pull-down node and a second pull-down node; the pull-up node noise reduction control terminal includes the first pull-down node, the second pull-down node, a reset terminal and a frame reset terminal; the reset terminal is an output terminal of an adjacent lower N-level carry signal, where N is a positive integer; The pull-up node noise reduction circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor is electrically connected to the first pull-down node, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first voltage terminal; The gate of the second transistor is electrically connected to the second pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the first voltage terminal; The gate of the third transistor is electrically connected to the reset terminal, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the first voltage terminal; The gate of the fourth transistor is electrically connected to the frame reset terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first voltage terminal; At least one of the first transistor, the second transistor, the third transistor, and the fourth transistor is a floating process transistor.

7. The driving circuit according to claim 5, wherein: The pull-down node includes a first pull-down node and a second pull-down node; the pull-up node noise reduction control terminal includes a first pull-down node, a second pull-down node, a reset terminal and a frame reset terminal; the reset terminal is an output terminal for the adjacent N-level drive signal, where N is a positive integer; The pull-up node noise reduction circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor is electrically connected to the first pull-down node, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first voltage terminal; The gate of the second transistor is electrically connected to the second pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the first voltage terminal; The gate of the third transistor is electrically connected to the reset terminal, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the first voltage terminal; The gate of the fourth transistor is electrically connected to the frame reset terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first voltage terminal; At least one of the first transistor, the second transistor, the third transistor, and the fourth transistor is a floating process transistor.

8. The driving circuit according to claim 4 or 5, wherein: The input circuit includes a fifth transistor; The gate of the fifth transistor and the first electrode of the fifth transistor are both electrically connected to the input terminal, and the second electrode of the fifth transistor is electrically connected to the pull-up node; The fifth transistor is a floating process transistor.

9. The driving circuit according to claim 4 or 5, wherein: The first output noise reduction circuit includes a sixth transistor and a seventh transistor; The gate of the sixth transistor is electrically connected to the first pull-down node, the first electrode of the sixth transistor is electrically connected to the output terminal, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal; The gate of the seventh transistor is electrically connected to the second pull-down node, the first electrode of the seventh transistor is electrically connected to the output terminal, and the second electrode of the seventh transistor is electrically connected to the second voltage terminal; At least one of the sixth transistor and the seventh transistor is a floating process transistor.

10. The driving circuit according to any one of claims 1 to 5, wherein: The pull-down node noise reduction circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; the pull-down node includes a first pull-down node and a second pull-down node; the pull-down node noise reduction control terminal includes a pull-up node and an input terminal; The gate of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the third voltage terminal; The gate of the ninth transistor is electrically connected to the input terminal, the first electrode of the ninth transistor is electrically connected to the first pull-down node, and the second electrode of the ninth transistor is electrically connected to the third voltage terminal; The gate of the tenth transistor is electrically connected to the pull-up node, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the third voltage terminal; The gate of the eleventh transistor is electrically connected to the input terminal, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the third voltage terminal; At least one of the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor is a floating process transistor.

11. The driving circuit according to claim 4, wherein: Also included is a second output noise reduction circuit, an output circuit, and a pull-down node control circuit; The second output noise reduction circuit is electrically connected to the first pull-down node, the second pull-down node, the drive signal output terminal, and the fourth voltage terminal, respectively, and is configured to control the communication between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the first pull-down node, and control the communication between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the second pull-down node; The pull-down node control circuit is electrically connected to the first pull-down node and the second pull-down node, respectively, and is used to control the potential of the first pull-down node and the potential of the second pull-down node; The output circuit is electrically connected to the pull-up node, the first clock signal terminal, the carry signal output terminal and the drive signal output terminal, respectively, and is used to control the connection between the carry signal output terminal and the first clock signal terminal, and control the connection between the drive signal output terminal and the first clock signal terminal under the control of the potential of the pull-up node.

12. The driving circuit according to claim 5, wherein: Also included are output circuitry and a pull-down node control circuit; The pull-down node control circuit is electrically connected to the first pull-down node and the second pull-down node, respectively, and is used to control the potential of the first pull-down node and the potential of the second pull-down node; The output circuit is electrically connected to the pull-up node, the first clock signal terminal and the drive signal output terminal respectively, and is used to control the connection between the drive signal output terminal and the first clock signal terminal under the control of the potential of the pull-up node.

13. The driving circuit according to claim 11 or 12, wherein: The pull-down node control circuit is also electrically connected to the first control voltage terminal and the second control voltage terminal, respectively, and is used to control the connection between the first pull-down node and the first control voltage terminal under the control of a first control voltage provided by the first control voltage terminal, and to control the connection between the second pull-down node and the second control voltage terminal under the control of a second control voltage provided by the second control voltage terminal.

14. The driving circuit according to claim 11 or 12, wherein: The pull-down node control circuit is also electrically connected to the first clock signal terminal and the second clock signal terminal, respectively, and is used to control the connection between the first pull-down node and the second clock signal terminal under the control of the second clock signal provided by the second clock signal terminal, and to control the connection between the second pull-down node and the first clock signal terminal under the control of the first clock signal provided by the first clock signal terminal.

15. A display device comprising the driving circuit according to any one of claims 1 to 14.

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