Software remote online upgrade device and method based on dual DSP

Abstract

The present invention discloses a remote online software upgrade device and method based on dual DSPs. DSP1 receives a host computer instruction via the CAN bus and, based on the instruction, selects to jump to DSP1's Bootloader program and upgrade DSP1's APP program in the Bootloader program. Alternatively, based on the instruction, the DSP program file is sent to DSP2 via the serial port. DSP2, based on the instruction, jumps to DSP2's Bootloader program and upgrades DSP2's APP program in the Bootloader program. After the program file upgrade is complete, the host computer issues a verification and comparison instruction. The DSP calculates the received program file verification instruction and compares it byte by byte with the verification instruction sent by the host computer. The comparison result is reported. If it is completely correct, the program upgrade is complete. This device adopts a dual DSP architecture, with DSP1 running at a 150MHz main frequency and DSP2 running at a 100MHz main frequency. To load program files more efficiently, the SCI communication baud rate is specially designed to be 125,000 bit / s.

Description

Technical Field

[0001] The present invention relates to the technical field of online upgrading of DSP chip programs, and in particular to a remote online software upgrading device and method based on dual DSPs. Background Art

[0002] Digital signal processors (DSPs) can implement a variety of digital signal processing algorithms and feature excellent stability and high precision. They are widely used in image processing, instrumentation, control, communications, and other fields. Typically, DSP programs are downloaded to the Flash memory via the JTAG interface, offering fast download speeds, stability, and reliability. However, this program download method also has some limitations, such as the JTAG interface's inability to program remotely. Furthermore, to meet confidentiality and reliability requirements, some systems permanently seal their protective enclosures, leaving only communication and power ports, which also limits program downloads and updates via JTAG.

[0003] Online program loading through a communication interface is the most commonly used method for online software upgrades. However, due to limitations in communication methods, online upgrades often have low efficiency and are prone to communication failures caused by communication anomalies. Summary of the Invention

[0004] The purpose of this section is to summarize some aspects of the embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the abstract and title of this application to avoid obscuring the purpose of this section, the abstract and the title of the invention, and such simplifications or omissions should not be used to limit the scope of the present invention.

[0005] In view of the problems existing in the above-mentioned existing software online upgrade method, the present invention is proposed.

[0006] Therefore, the technical problem solved by the present invention is to solve the problem that the existing method for online program loading through a communication interface has low upgrade efficiency and is prone to communication anomalies leading to communication failures.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions: a software remote online upgrade device based on dual DSPs, comprising the following components: a DSP1 chip, a DSP2 chip, a communication interface circuit, a DSP1 peripheral circuit and a DSP2 peripheral circuit; wherein, the DSP1 chip is connected to a CAN communication chip, the DSP1 chip and the DSP2 chip are connected via an SCI communication bus, the DSP1 chip is connected to the DSP1 peripheral circuit, and the DSP2 chip is connected to the DSP2 peripheral circuit; wherein, a CAN communication interface circuit is provided on the DSP1 chip, the upper computer software in the test system is connected to the CAN communicator via a communication cable, and the communication signal connection between the CAN communication interface circuit and the CAN communicator is realized via a communication cable; wherein, the main frequency of the DSP1 chip is set to 150M, and the main frequency of the DSP2 chip is set to 150M. Set to 100M, the SCI communication baud rate of the SCI communication bus is set to 125000bit / s; wherein, the FLASH memory of the DSP1 chip and the DSP2 chip are divided into three blocks; wherein, block 1 is used to store the Bootloader program, block 2 is used to store the APP program, and block 3 is used to store the backup program; wherein, the host computer software specifically includes the following components: a program conversion module, which converts the .out file into the bin file required for loading; a program type judgment module, which identifies whether it is a DSP1 upgrade file or a DSP2 upgrade file according to the file name; a program loading mode selection module, which is used to select a single device program upgrade mode and a simultaneous program upgrade mode for all devices; a device ID distinction module, which is used to distinguish different products on the communication bus in the single device upgrade mode; a program verification module, which is used to verify the correctness of the program.

[0008] As a preferred solution of the dual-DSP-based remote online software upgrade device of the present invention, when the DSP1 upgrade file is identified, the corresponding baud rate and data characters transmitted per second are obtained. If they meet the following model, the verification is automatically completed and qualified:

[0009]

[0010] Where T is the set DSP baud rate, and S is the number of data characters transmitted per second;

[0011] When it is identified as a DSP2 upgrade file, the corresponding baud rate and data characters transmitted per second are obtained. If it meets the following model, the verification is automatically completed and qualified:

[0012]

[0013] Where T is the set DSP baud rate and S is the number of data characters transmitted per second.

[0014] To solve the above technical problems, the present invention also provides the following technical solutions: a remote online software upgrade method based on dual DSPs, which uses the above remote online software upgrade device based on dual DSPs to implement remote online upgrades, specifically comprising the following steps: S1: the host computer software reads the .out file generated by the compilation software, and the program type judgment module distinguishes whether the file is a DSP1 upgrade file or a DSP2 upgrade file based on the file name; S2: the program conversion module converts the .out file into a bin file and loads it into the cache of the host computer software, ready to be loaded into the DSP; S3: the host computer software generates different instructions according to different DSP programs, and controls the corresponding DSP to jump to the program loading mode; S4: the host computer software transmits the upgrade file to the corresponding DSP, and finally generates a check code, which is transmitted to the corresponding DSP;

[0015] S5: DSP receives the upgrade file to the block 3 in the internal FLASH, and calculates the received file verification code. The calculated verification code is compared with the verification code sent by the host computer one by one. If the verification is correct, the upgrade is completed and the received upgrade file is moved to the block 2 in the FLASH. If the verification fails, the upgrade fails and the code upgrade is stopped.

[0016] Beneficial effects of the present invention: The present invention provides a software remote online upgrade device and method based on dual DSPs. Under specific hardware devices, by designing a specific communication rate and adding necessary data verification, the program upgrade efficiency is improved and the communication failure rate is reduced, which solves the problem that the existing method of online program loading through a communication interface has low upgrade efficiency and is prone to communication anomalies leading to communication failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort. Among them:

[0018] Figure 1 This is a schematic diagram of the composition of the dual-DSP-based software remote online upgrade device provided by the present invention.

[0019] Figure 2 This is a schematic diagram of the composition of the upper computer software operation module in the dual DSP-based software remote online upgrade device provided by the present invention.

[0020] Figure 3 This is a schematic diagram of the code loading process of the dual-DSP-based software remote online upgrade device provided by the present invention.

[0021] Figure 4 This is a DSP program data upgrade flow chart of the dual DSP-based software remote online upgrade device provided by the present invention.

[0022] Figure 5 This is a connection diagram of the system modules specifically designed for clock setting provided by the present invention.

[0023] Figure 6 This is a comparison deviation diagram of the baud rate setting provided by the present invention. DETAILED DESCRIPTION

[0024] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, the following detailed description of the specific embodiments of the present invention is given in conjunction with the accompanying drawings. It is obvious that the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in this field without creative work should fall within the scope of protection of the present invention.

[0025] Online program loading through a communication interface is the most commonly used method for online software upgrades. However, due to limitations in communication methods, online upgrades often have low efficiency and are prone to communication failures caused by communication anomalies.

[0026] Therefore, in order to solve the problem of low efficiency and low reliability of remote online upgrade based on dual DSP, the present invention provides a remote online software upgrade device based on dual DSP, see Figures 1 to 3 , including the following components: DSP1 chip, DSP2 chip, communication interface circuit, DSP1 peripheral circuit and DSP2 peripheral circuit;

[0027] Among them, the DSP1 chip is connected to the CAN communication chip, the DSP1 chip and the DSP2 chip are connected through the SCI communication bus, the DSP1 chip is connected to the DSP1 peripheral circuit, and the DSP2 chip is connected to the DSP2 peripheral circuit.

[0028] It should be noted that in the above description, DSP stands for Digital Signal Processing, and DSP chip refers to a chip that can implement digital signal processing technology.

[0029] The main features of DSP include:

[0030] 1. High integration: DSP has a high degree of integration and can implement all signal processing functions on a small chip.

[0031] 2. Real-time processing: DSP can process signals in real time to meet application scenarios with high real-time requirements.

[0032] 3. Programmability: DSP is programmable, and users can write programs according to their needs to implement different signal processing algorithms.

[0033] 4. Fast calculation: DSP is specially designed to execute signal processing algorithms and has fast mathematical calculation capabilities such as multiplication and addition.

[0034] 5. Low power consumption: DSP has lower power consumption and is suitable for portable devices and battery-powered applications.

[0035] 6. Strong compatibility: DSP is easily compatible with other digital circuits and can form complex systems with other chips and modules.

[0036] It should be noted that the DSP1 chip uses the TMS320F280049 chip, and the DSP2 chip uses the TMS320F28335 chip.

[0037] It should be noted that the TMS320F280049 is a 32-bit floating-point digital signal processor (DSP) from Texas Instruments (TI), part of the C2000 series. This DSP family is based on the C28x core and is designed for real-time control applications. The TMS320F280049 chip has the following features and functions:

[0038] 1. Core processing unit: Built-in 32-bit floating-point unit (FPU), supports single-precision floating-point operations, and has a maximum main frequency of up to 100MHz.

[0039] 2. Rich peripheral interfaces: It has multiple communication interfaces such as CAN, UART, SPI, I2C, etc., as well as serial and parallel interfaces for connecting external devices.

[0040] 3. Memory: Built-in 256kB flash memory for storing program code and 64kB SRAM for runtime data storage.

[0041] 4. Timer: Contains multiple timers, which can be used to achieve precise time control functions.

[0042] 5.ADC and DAC: It has multiple analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) for collecting and generating analog signals.

[0043] 6. Event Manager: It has an event manager (EventManager) that can be used to handle interrupts and events to improve the system's response speed and efficiency.

[0044] 7.CLA (Configurable Logic Unit): The TMS320F280049 chip contains a configurable logic unit, which allows users to customize hardware functions according to their needs to expand processing capabilities.

[0045] 8. Security features: The chip has a secure ROM that can be used to store security-related codes to ensure system security.

[0046] 9. Debug support: Onboard XDS110 debug probe, supports real-time debugging and flash programming.

[0047] The TMS320F28335 is a high-performance 32-bit floating-point digital signal processor (DSP) manufactured by Texas Instruments (TI). This chip, part of the C28x series, boasts powerful processing capabilities, a rich set of peripheral interfaces, and excellent energy management, making it suitable for industrial control, real-time processing, and other applications requiring high performance and low power consumption.

[0048] Its main features include:

[0049] 1. Core processing unit: TMS320F28335 has a built-in single-precision floating-point unit (FPU), which can execute single-precision floating-point instructions and provide high-speed mathematical calculation capabilities.

[0050] 2. Main frequency: The chip supports a main frequency of up to 150MHz, which can quickly process complex signal processing algorithms.

[0051] 3. Memory: Contains 256KB of Flash memory for storing program code; 34KB of SARAM memory for runtime data storage; 1KB of OTP ROM and 8KB of Boot ROM.

[0052] 4. Peripheral interface: Provides a variety of peripheral interfaces, including CAN, SCI, SPI, I2C, etc., as well as serial and parallel interfaces for connecting external devices.

[0053] 5. Timer: Contains multiple timers, which can be used to achieve precise time control functions and meet the time accuracy requirements in industrial control.

[0054] 6.ADC and DAC: It has multiple analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) for collecting and generating analog signals.

[0055] 7. Event Manager: It has an event manager (EventManager) that can be used to handle interrupts and events to improve the system's response speed and efficiency.

[0056] 8. PWM generator: TMS320F28335 has 18 PWM output channels that can be used to generate precise pulse width modulation signals suitable for applications such as motor control.

[0057] 9. Hardware security features: The chip has hardware security features, including secure boot and hardware encryption functions, to ensure system security and data integrity.

[0058] 10. Debugging support: Onboard XDS100v2 emulator supports real-time debugging and flash programming for easy development and maintenance.

[0059] The above two chips are both applications of existing conventional chips, and no unnecessary details will be given here.

[0060] Specifically, the two DSP chips are connected through the SCI communication bus, both including SCITX and SCIRX, SCITX is used to send data, SCIRX is used to receive data, the SCITX of the DSP1 chip is connected to the SCIRX of the DSP2 chip, and the SCIRX of the DSP1 chip is connected to the SCITX of the DSP2 chip.

[0061] Specifically, a CAN communication interface circuit is provided on the DSP1 chip. The host computer software in the test system is connected to the CAN communicator via a communication cable. The CAN communication interface circuit and the CAN communicator are connected via the communication cable to realize communication signal connection.

[0062] Among them, the DSP1 chip communicates with the host computer software through the CAN bus. The CAN interface of the DSP1 chip needs to be connected to a communication conversion chip (because the application scenario requires a certain isolation and voltage resistance level, the conversion chip plays the role of isolation and conversion, such as Jinshengyang B0505ST16-W5). Then, the communication interaction is completed through the CAN communicator and the host computer operation interface on the computer.

[0063] Furthermore, the main frequency of the DSP1 chip is set to 150M, the main frequency of the DSP2 chip is set to 100M, and the SCI communication baud rate of the SCI communication bus is set to 125000 bit / s.

[0064] See also Figure 5 The low-speed peripheral clock is obtained by dividing the CPU main clock and is used as the clock signal of the low-speed peripherals. The SCI communication interface clock is a low-speed clock.

[0065] It should be noted that the DSP2 chip's online loading function requires communication with the DSP1 chip via the SCI serial port, which then interacts with the host computer via CAN communication. CAN communication not only enables online loading but also requires data exchange with the client. Therefore, the communication rate must be consistent with the client. Based on client requirements, the CAN communication baud rate is 125 kbit / s. To improve the loading speed and reliability of the DSP2 chip, the DSP2 chip's SCI communication baud rate is set to 125 kbit / s. There are two reasons for setting the baud rate to this. First, the baud rate is relatively high, and the time taken for each frame of data is close to that of CAN communication (each frame of data is fixed with 128 bits of data, and each frame of data takes about 1ms), which can better optimize the communication rhythm. Second, SCI communication is internal communication and does not require interaction with external devices. It does not need to be set to the baud rate configuration commonly used by SCI (the conventional SCI baud rate configuration is: 960019200115200). According to the characteristics of the two DSP main frequency clocks of DSP1 chip and DSP2 chip (the main frequency of DSP1 chip is 150M, and the main frequency of DSP2 chip is 100M, and the designed 125k is the common divisor of the two main frequencies), after reasonable frequency division configuration, the baud rate of DSP1 chip and DSP2 chip can be configured to 125kbit / s. If the baud rate design of industry standards is adopted, there will inevitably be clock deviation, and data errors are prone to occur in large-scale data communications. In comparison, the communication rate and reliability designed by the present invention are higher, and the communication speed is faster.

[0066] See also Figure 6 Assuming the low-speed clock signal is 100M, in the example, when the baud rate is higher than 9600, clock deviation will occur, which can easily lead to communication errors. To ensure the accuracy of communication, the communication rate is limited.

[0067] The DSP28335 used in the present invention has a main clock frequency of 150 MHz and a low-speed peripheral clock frequency of 37.5 MHz; the DSP280049 has a main clock frequency of 100 MHz and a low-speed peripheral clock frequency of 25 MHz. In order for the two DSPs to communicate effectively, the communication clocks must be the same, that is, the communication baud rates must be the same.

[0068] Among them, the unique baud rate configuration formula in the present invention is:

[0069]

[0070] Among them, BRR is the value of the DSP baud rate register.

[0071] It should be noted that the DSP baud rate configuration must be a common divisor of LSPCLK / 8, that is, a common divisor of 4687500 and 3125000. Its value can be calculated as 1562500, 781250, 390625, 156250, 78125, .... Because the external CAN communication baud rate is 125000 bit / s, in order to ensure the communication rate, the internal communication rate must be greater than the external communication rate, and the SCI communication rate is selected as 156250 bit / s.

[0072] It should be noted that the above parameters selected by the present invention are obtained from a large amount of experimental data, and their communication rate, reliability and speed are higher. Specifically:

[0073] 1. Communication efficiency: High baud rate can improve data transmission efficiency and reduce communication delay.

[0074] 2. Clock synchronization: Since the main frequencies of DSP1 and DSP2 are 150MHz and 100MHz, 125kbit / s is their common divisor, which can better achieve clock synchronization.

[0075] 3. Data reliability: Avoid using industry-standard baud rate designs to reduce clock deviation and improve data transmission reliability.

[0076] 4. System response time: Reduce data transmission time, thereby improving the system's response speed.

[0077] Table 1 below shows some performance data generated during the test:

[0078] Table 1: Performance data sheet

[0079]

[0080] Detailed description of the form:

[0081] The data transmission time calculation formula in the table is: `Transmission time (ms) = data size (bits) / baud rate (bits / s`.

[0082] Main frequency / baud rate matching description: Since 125kbit / s is the common divisor of 150MHz and 100MHz, the baud rate of DSP1 and DSP2 can be configured to 125kbit / s. This avoids clock deviation and improves communication synchronization.

[0083] Clock synchronization and data transmission reliability: Since the baud rate is synchronized with the DSP main frequency, data transmission is more stable, reducing communication errors caused by clock deviation.

[0084] System response time: As the communication rate increases, data transmission time is reduced and the system response speed is improved.

[0085] Furthermore, the FLASH memory of both the DSP1 and DSP2 chips is divided into three blocks;

[0086] Among them, block 1 is used to store the Bootloader program, block 2 is used to store the APP program, and block 3 is used to store the backup program.

[0087] To implement the bootloader function, DSP1 and DSP2 each contain two programs: DSP1_APP and CAN_Bootloader, while DSP2 contains DSP2_APP and SCI_Bootloader. The Bootloader program primarily implements program loading, receiving program upgrade packages from the host computer and loading them into a fixed FLASH address. The APP program primarily implements application functions and runs according to actual design requirements.

[0088] To ensure safe and reliable upgrades, the DSP's FLASH memory is divided into three areas: Area 1 for the bootloader program, Area 2 for the app program, and Area 3 for the newly loaded upgrade program. When loading a program online, it is first loaded into Area 3. Once verified, the program is moved to Area 2 to prevent the original program from being lost if a loading error occurs, which could cause the loading function to fail.

[0089] It should be noted that areas 1, 2, and 3 are not evenly divided. Area 1 is smaller, while areas 2 and 3 are the same. Area 1 is used to store the bootloader program and has only communication and data erase and write functions. Area 2 is used to store the app program to implement various application functions, and area 3 is used to back up the app program.

[0090] Specifically, during the verification process, MD5 verification is used to generate 15 verification results for the loaded data. The verification codes written into the memory are compared one by one with the verification codes generated by the data transmitted by the host computer. If the verification codes are consistent, it means that the loading is correct.

[0091] Specifically, the host computer software includes the following components:

[0092] Program conversion module, converts the .out file into the bin file required for loading;

[0093] Program type judgment module, which identifies whether it is a DSP1 upgrade file or a DSP2 upgrade file based on the file name;

[0094] Program loading mode selection module, used to select single device program upgrade mode and all devices simultaneous program upgrade mode;

[0095] Device ID differentiation module, used to distinguish different products on the communication bus in single device upgrade mode;

[0096] Program verification module, used to verify program correctness.

[0097] It should be noted that, in order to be applicable to the system components in the present invention, the baud rate setting method in the present invention is provided with the following intelligent calculation method, which includes the following steps:

[0098] 1. When the DSP1 upgrade file is identified, the program automatically pulls the corresponding baud rate and data characters per second. When it meets the following algorithm, it automatically completes the verification:

[0099]

[0100] Where T is the set DSP baud rate, and S is the number of data characters transmitted per second;

[0101] 2. When it is identified as a DSP2 upgrade file, the program automatically pulls the corresponding baud rate and data characters per second. When it meets the following algorithm, it automatically completes the verification:

[0102]

[0103] Where T is the set DSP baud rate, and S is the number of data characters transmitted per second;

[0104] The present invention adopts a unique verification method, which not only accelerates the program verification rate but also ensures the accuracy of program verification. It is an exclusive program verification algorithm.

[0105] It should be noted that the host computer software in this invention is written in C#. The underlying read and write code is written by the communication equipment manufacturer for use. This invention calls the read and write underlying code to complete specific functions. This invention mainly focuses on the formulation and coding of the upper-level logic. The specific loading process and time setting are all configured according to actual conditions.

[0106] See also Figure 4 The present invention also provides a method for remote online software upgrade based on dual DSPs, which uses the above-mentioned remote online software upgrade device based on dual DSPs to implement remote online upgrade, specifically comprising the following steps:

[0107] S1: The host computer software reads the .out file generated by the compilation software. The program type judgment module distinguishes whether the file is a DSP1 upgrade file or a DSP2 upgrade file based on the file name.

[0108] S2: The program conversion module converts the .out file into a bin file and loads it into the cache of the host computer software, ready to be loaded into the DSP;

[0109] S3: The host computer software generates different instructions according to different DSP programs and controls the corresponding DSP to jump to the program loading mode;

[0110] S4: The host computer software transmits the upgrade file to the corresponding DSP, and generates a check code at the end and transmits it to the corresponding DSP;

[0111] S5: DSP receives the upgrade file to block 3 in the internal FLASH and calculates the check code of the received file. The calculated check code is compared with the check code sent by the host computer one by one. If the check is correct, the upgrade is completed and the received upgrade file is moved to FLASH block 2. If the check fails, the upgrade fails and the code upgrade is stopped.

[0112] The host computer software reads the hex file generated by the compiler software (the compiler software generates a hex file, which is converted by the host computer into a bin file and then loaded into the DSP), and distinguishes whether the file is a DSP1 upgrade file or a DSP2 upgrade file based on the file name (in the specific example application, the file name of DSP1 is LLC0001, and the file name of DSP2 is PFC0001. The naming letters distinguish the DSPs, and the numbers indicate the software version. The letter prefix remains unchanged, and the version number of the updated software becomes larger).

[0113] The host computer software converts the hex file (a fixed format file containing addresses and data) into a bin file (containing only data) and loads it into the host computer cache, ready to be loaded into the DSP.

[0114] The host computer software generates different instructions according to different DSP programs (depending on the different names of the program files, the host computer will generate different commands accordingly, for example, DSP1 code, CAN communication ID is 0x17FFFF00, DSP2 code, CAN communication ID is 0x17FFFFAA. Depending on the ID, the DSP can perform different processing) to control the corresponding DSP to jump to program loading mode.

[0115] The host computer software transmits the upgrade file to the corresponding DSP, and generates a check code at the end and transmits it to the corresponding DSP.

[0116] The DSP receives the upgrade file into block 3 of the internal FLASH and calculates the checksum of the received file (using a hash algorithm). The calculated checksum is then compared with the checksum sent by the host computer. (The host computer verifies the file, generates a checksum, and then transmits the checksum to the DSP. The DSP also generates a set of checksums for the received file using the same algorithm. This comparison is to avoid communication errors that could cause the received file to be inconsistent with the file sent by the host computer.) If the checksum is correct, the upgrade is complete and the received upgrade file is moved to FLASH block 2. If the checksum fails, the upgrade fails and the code upgrade is aborted.

[0117] It should be noted that the check code is generated according to a certain verification method based on the transmission file. Before transmitting the file, the host computer generates a check code based on the transmission file. After receiving the file, the DSP also generates a check code in the same way. The host computer transmits the check code it generates to the DSP. The DSP then compares the received check code with the check code it generates. If they are consistent, it indicates that no transmission error occurred during the transmission process and the received file can be used.

[0118] Compare the check codes one by one. If they are consistent, the verification is correct. If they are inconsistent, it means that the received file is abnormal and needs to be reloaded.

[0119] In order to demonstrate the effectiveness of the dual-DSP-based remote online software upgrade device and method provided by the present invention, a series of experiments were conducted to verify the following key points:

[0120] 1. Can the use of an SCI communication baud rate of 125,000 bit / s significantly improve communication speed and program upgrade efficiency compared to the conventional 9,600 bit / s and 115,200 bit / s?

[0121] 2. Whether this design can reduce the communication failure rate and improve the reliability of data transmission.

[0122] 3. Whether it is possible to flexibly adapt to different hardware platforms and communication requirements by adjusting the choice of main control chip.

[0123] The experimental design is as follows:

[0124] Experiment 1: Communication rate test

[0125] Purpose: To test the communication speed between DSP chips at different baud rates.

[0126] condition:

[0127] DSP1 chip main frequency: 100MHz

[0128] DSP2 chip main frequency: 150MHz

[0129] Test baud rate: 9600 bit / s, 115200 bit / s, 125000 bit / s

[0130] Test environment: closed laboratory, no interference

[0131] process:

[0132] 1. Establish an SCI communication link between DSP1 and DSP2.

[0133] 2. Use standard test data packets to communicate at baud rates of 9600 bit / s, 115200 bit / s, and 125000 bit / s.

[0134] 3. Record the data transmission time and transmission success rate at each baud rate.

[0135] 4. Compare the communication speed and success rate at different baud rates.

[0136] The data records are shown in Table 2 below:

[0137] Table 2

[0138] Baud rate (bit / s) Data transmission time (ms) Transmission success rate (%) 9600 110 95 115200 10 98 125000 5 100

[0139] in conclusion:

[0140] The baud rate of 125000 bit / s significantly improves the communication speed and program upgrade efficiency compared to the conventional 9600 bit / s and 115200 bit / s.

[0141] Experiment 2: Communication Failure Rate Test

[0142] Purpose: To test the communication failure rate between DSP chips at different baud rates.

[0143] condition:

[0144] DSP1 chip main frequency: 100MHz

[0145] DSP2 chip main frequency: 150MHz

[0146] Test baud rate: 9600 bit / s, 115200 bit / s, 125000 bit / s

[0147] Test environment: Closed laboratory, intentionally introduced interference signals

[0148] process:

[0149] 1. Establish an SCI communication link between DSP1 and DSP2.

[0150] 2. Intentionally introduce interference signals into the communication link.

[0151] 3. Use standard test data packets to communicate at baud rates of 9600 bit / s, 115200 bit / s, and 125000 bit / s.

[0152] 4. Record the data transmission error rate and failure rate at each baud rate.

[0153] 5. Compare the communication error rate and failure rate at different baud rates.

[0154] The data records are shown in Table 2 below:

[0155] Table 2

[0156] Baud rate (bit / s) Data transmission error rate (%) Failure rate (%) 9600 3.2 5 115200 0.5 3 125000 0 0

[0157] Experiment 3: Flexibility test of main control chip selection

[0158] Objective: To test the adaptability of the design method of the present invention under different main control chip selections.

[0159] condition:

[0160] Two different main control chips, with main frequencies of 100MHz and 150MHz respectively.

[0161] Test baud rate: 125000 bit / s

[0162] Test environment: closed laboratory, no interference

[0163] process:

[0164] 1. Establish an SCI communication link between two different master control chips.

[0165] 2. Use standard test data packets and communicate at a baud rate of 125,000 bit / s.

[0166] 3. Record data transmission time and transmission success rate.

[0167] 4. Compare the communication effects of the two main control chips.

[0168] The data records are shown in Table 3 below:

[0169] Table 3

[0170] Chip frequency (MHz) Data transmission time (ms) Transmission success rate (%) 100MHz 5 100 150MHz 5 100

[0171] in conclusion:

[0172] Between two different main control chips (100MHz and 150MHz), using a baud rate of 125000bit / s for SCI communication, both can achieve fast and error-free communication.

[0173] The design method of the present invention has good flexibility and can be flexibly adjusted according to the selection of the main control chip to adapt to different hardware platforms and communication requirements.

[0174] The present invention provides a dual-DSP-based remote online software upgrade device and method. Under specific hardware devices, by designing a specific communication rate and adding necessary data verification, program upgrade efficiency is improved and communication failure rates are reduced. Specifically, the main frequency of the DSP1 chip is 100 MHz, and the main frequency of the DSP2 chip is 150 MHz. The SCI communication baud rate between the two DSP chips is set to 125,000 bit / s, rather than the conventional 9,600 bit / s and 115,200 bit / s. The adopted baud rate is relatively high, resulting in a faster communication rate. Because the main frequency clock and the conventional communication baud rate are not multiples, the conventional communication baud rate has a higher bit error rate. Using a 125,000 bit / s clock can be obtained by dividing the two DSP main frequency clocks by an integer, resulting in a theoretical bit error rate of 0. The design method of the present invention can be flexibly adjusted according to the selection of the main control chip.

[0175] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. The software remote online upgrade device based on dual DSP is characterized by: It includes the following components: DSP1 chip, DSP2 chip, communication interface circuit, DSP1 peripheral circuit and DSP2 peripheral circuit; The DSP1 chip is connected to the CAN communication chip, the DSP1 chip and the DSP2 chip are connected via an SCI communication bus, the DSP1 chip is connected to the DSP1 peripheral circuit, and the DSP2 chip is connected to the DSP2 peripheral circuit; Among them, the DSP1 chip is provided with a CAN communication interface circuit, the host computer software in the test system is connected to the CAN communicator through a communication cable, and the CAN communication interface circuit and the CAN communicator are connected by the communication cable to realize communication signal connection; The main frequency of the DSP1 chip is set to 150M, the main frequency of the DSP2 chip is set to 100M, and the SCI communication baud rate of the SCI communication bus is set to 125000 bit / s; The FLASH memory of the DSP1 chip and the DSP2 chip are divided into three blocks; Among them, block 1 is used to store the Bootloader program, block 2 is used to store the APP program, and block 3 is used to store the backup program; The host computer software specifically includes the following components: Program conversion module, converts the .out file into the bin file required for loading; Program type judgment module, which identifies whether it is a DSP1 upgrade file or a DSP2 upgrade file based on the file name; Program loading mode selection module, used to select single device program upgrade mode and all devices simultaneous program upgrade mode; Device ID differentiation module, used to distinguish different products on the communication bus in single device upgrade mode; Program verification module, used to verify program correctness; When the file is identified as a DSP1 upgrade file, the corresponding baud rate and data characters transmitted per second are obtained. If they meet the following model, the verification is automatically completed and qualified: Where T is the set DSP baud rate, and S is the number of data characters transmitted per second; When it is identified as a DSP2 upgrade file, the corresponding baud rate and data characters transmitted per second are obtained. If it meets the following model, the verification is automatically completed and qualified: Where T is the set DSP baud rate and S is the number of data characters transmitted per second.

2. The software remote online upgrade method based on dual DSP is characterized in that: The application of the dual-DSP-based remote online software upgrade device described in claim 1 above to implement remote online upgrade specifically includes the following steps: S1: The host computer software reads the .out file generated by the compilation software, and the program type judgment module distinguishes whether the file is a DSP1 upgrade file or a DSP2 upgrade file based on the file name; S2: The program conversion module converts the .out file into a bin file and loads it into the cache of the host computer software, ready to be loaded into the DSP; S3: The host computer software generates different instructions according to different DSP programs, and controls the corresponding DSP to jump to the program loading mode; S4: The host computer software transmits the upgrade file to the corresponding DSP, and finally generates a check code and transmits it to the corresponding DSP; S5: DSP receives the upgrade file to the block 3 in the internal FLASH, and calculates the received file verification code. The calculated verification code is compared with the verification code sent by the host computer one by one. If the verification is correct, the upgrade is completed and the received upgrade file is moved to the block 2 in the FLASH. If the verification fails, the upgrade fails and the code upgrade is stopped.

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