Method for epitaxially growing silicon cap layer on germanium-silicon channel of SOI (Silicon On Insulator) device

Abstract

The invention provides a method for epitaxially growing a silicon cap layer on a germanium-silicon channel of an SOI device, and the method comprises the steps: 1, providing an SOI substrate which comprises a bottom bulk silicon layer, an insulating medium buried layer and a top silicon layer which are stacked from bottom to top; 2, forming a germanium-silicon layer on the top silicon layer; 3, performing thermal oxidation and thermal annealing treatment on the germanium-silicon layer in sequence, and diffusing germanium in the germanium-silicon layer into a top silicon layer of the SOI substrate while forming a top oxide layer on the surface of the germanium-silicon layer; step 4, removing a top oxide layer; 5, epitaxially growing a silicon cap layer on the germanium-silicon layer; and 6, forming a gate oxide layer on the silicon cap layer. The silicon cap layer epitaxially grown on the germanium-silicon channel is continuously distributed, and after the gate oxide layer is grown on the silicon cap layer, a thin silicon cap layer exists between the germanium-silicon channel and the gate oxide layer, so that the interface state between the germanium-silicon channel and the gate oxide layer is improved, and the CV curve of a PMOS (P-channel Metal Oxide Semiconductor) meets the requirement.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for epitaxially growing a silicon cap layer on a germanium silicon channel of an SOI device. Background Art

[0002] Silicon-on-insulator (SOI) devices use silicon germanium (SiGe) as a channel to improve the hole mobility of PMOS. Since the gate oxide layer is directly grown on the SiGe channel, there is an interface state problem between the SiGe channel and the gate oxide layer, resulting in the cyclic voltammetry (CV) curve of PMOS being as follows: Figure 1A The double peaks shown indicate a sharp increase in capacitance when the gate voltage does not exceed the threshold voltage.

[0003] In order to avoid the interface state problem between the SiGe channel and the gate oxide layer, the prior art forms a silicon cap layer on the SiGe before growing the gate oxide layer. However, when forming the silicon cap layer, the temperature of the prior epitaxial process is too high (higher than 650°C), causing the SiGe to migrate and form a surface layer such as Figure 1B The "agglomeration" phenomenon shown exposes the buried oxide layer below, thereby affecting the epitaxial growth of the silicon cap layer. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a method for epitaxially growing a silicon cap layer on a germanium silicon channel of an SOI device, so as to solve the problem in the prior art that the epitaxially grown silicon cap layer on the germanium silicon channel is discontinuous, resulting in the inability to improve the interface state between the germanium silicon channel and the gate oxide layer.

[0005] To achieve the above-mentioned object and other related objects, the present application provides a method for epitaxially growing a silicon cap layer on a silicon germanium channel of an SOI device, comprising:

[0006] Step 1, providing an SOI substrate, wherein the SOI substrate includes a bottom bulk silicon layer, an insulating dielectric buried layer and a top silicon layer stacked from bottom to top;

[0007] Step 2, forming a silicon germanium layer on the top silicon layer;

[0008] Step 3, sequentially performing thermal oxidation and thermal annealing treatments on the silicon germanium layer, forming a top oxide layer on the surface of the silicon germanium layer while diffusing the germanium in the silicon germanium layer into the top silicon layer of the SOI substrate;

[0009] Step 4, removing the top oxide layer;

[0010] Step 5, epitaxially growing a silicon cap layer on the silicon germanium layer;

[0011] Step six, forming a gate oxide layer on the silicon cap layer.

[0012] Preferably, the gases used in the epitaxial process implemented in step five include Si2H6, HCL and H2.

[0013] Preferably, the temperature of the epitaxial process implemented in step five is 400° C.-500° C., and the pressure is 10 torr-100 torr.

[0014] Preferably, in step six, a gate oxide layer is formed by a thermal oxidation process, consuming part of the silicon cap layer.

[0015] Preferably, after step six, the thickness of the silicon cap layer is 3 angstroms to 5 angstroms.

[0016] Preferably, the insulating dielectric buried layer is a silicon dioxide buried layer.

[0017] Preferably, the silicon dioxide buried layer is formed by adopting an oxygen implantation isolation process.

[0018] Preferably, in step 2, a germanium silicon layer is formed by an epitaxial growth process.

[0019] Preferably, in step three, thermal oxidation and thermal annealing are performed in a cycle for multiple times.

[0020] Preferably, in step four, the top oxide layer is removed by a siconi cleaning process.

[0021] As described above, the method for epitaxially growing a silicon cap layer on a germanium silicon channel of an SOI device provided in the present application has the following beneficial effects: the silicon cap layer epitaxially grown on the germanium silicon channel is continuously distributed, and after a gate oxide layer is grown on the silicon cap layer, a very thin silicon cap layer exists between the germanium silicon channel and the gate oxide layer, thereby improving the interface state between the germanium silicon channel and the gate oxide layer, so that the CV curve of the PMOS meets the requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1A The CV curve of PMOS with gate oxide layer directly formed on the silicon germanium channel of SOI device is shown;

[0024] Figure 1B An electron photograph showing the phenomenon of "agglomeration" of germanium silicon migration on the surface layer when epitaxially growing a silicon cap layer using the prior art;

[0025] Figure 2A flow chart showing a method for epitaxially growing a silicon cap layer on a silicon germanium channel of an SOI device provided in an embodiment of the present application;

[0026] Figure 3A-Figure 3F Shown is a schematic diagram of a device cross-sectional structure formed after each step is completed in a method for epitaxially growing a silicon cap layer on a silicon germanium channel of an SOI device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0029] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0030] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0031] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0032] See also Figure 2, which shows a flow chart of a method for epitaxially growing a silicon cap layer on a silicon germanium channel of an SOI device provided in an embodiment of the present application.

[0033] like Figure 2 As shown, the method for epitaxially growing a silicon cap layer on a silicon germanium channel of the SOI device comprises the following steps:

[0034] Step 1, providing an SOI substrate, wherein the SOI substrate includes a bottom bulk silicon layer, an insulating dielectric buried layer and a top silicon layer stacked from bottom to top;

[0035] Step 2, forming a silicon germanium layer on the top silicon layer;

[0036] Step 3, sequentially performing thermal oxidation and thermal annealing treatments on the silicon germanium layer, forming a top oxide layer on the surface of the silicon germanium layer while diffusing the germanium in the silicon germanium layer into the top silicon layer of the SOI substrate;

[0037] Step 4, removing the top oxide layer;

[0038] Step 5, epitaxially growing a silicon cap layer on the silicon germanium layer;

[0039] Step six, forming a gate oxide layer on the silicon cap layer.

[0040] In step 1, the SOI substrate includes a bottom bulk silicon layer 300, an insulating dielectric buried layer 301, and a top silicon layer 302 stacked from bottom to top. As an example, the insulating dielectric buried layer 301 is a silicon dioxide buried layer, which is usually formed by an oxygen implantation isolation process, that is, first providing a silicon substrate; then performing oxygen ion implantation to form a silicon dioxide buried layer in the silicon substrate.

[0041] In step 2, a germanium silicon layer 303 is formed on the top silicon layer 302 by an epitaxial growth process. Exemplarily, the germanium concentration of the germanium silicon layer 303 has a distribution that gradually increases from bottom to top, preferably a gradient distribution that gradually increases from bottom to top.

[0042] In step three, a top oxide layer 305 is formed on the surface of the germanium silicon layer 303 by thermal oxidation, and the thickness of the germanium silicon layer 303 is reduced at the same time; the top oxide layer 305 is made into a silicon dioxide layer by utilizing the characteristic that the Si-O bond bonding ability is stronger than the Ge-O bond, and germanium condensation is formed at the interface between the top oxide layer 305 and the germanium silicon layer 303. Exemplarily, the thermal oxidation is rapid thermal oxidation.

[0043] The germanium condensed at the interface between the top oxide layer 305 and the germanium silicon layer 303 is diffused downward by thermal annealing, so that the germanium in the germanium silicon layer 303 is diffused into the top silicon layer 302. Exemplarily, the thermal annealing is rapid thermal annealing.

[0044] As an example, the thermal oxidation and thermal annealing may be performed multiple times in a cycle.

[0045] After step 3 is completed, the top silicon layer 302 is transformed into a silicon germanium layer, and the germanium concentration of the silicon germanium layer 303 is increased.

[0046] In step four, the top oxide layer 305 is removed by a siconi cleaning process.

[0047] In step five, a silicon cap layer 306 is epitaxially grown on the silicon germanium layer 303. In order to prevent the silicon germanium in the silicon germanium layer 303 from migrating and agglomerating at high temperatures to affect the growth of the silicon cap layer 306, the epitaxial process uses gases such as Si2H6, HCL, and H2 at a temperature of 400°C-500°C and a pressure of 10 torr-100 torr.

[0048] After step five is completed, the formed silicon cap layer 306 is continuously distributed, while the silicon cap layer formed by the prior art has an island structure.

[0049] In step six, a gate oxide layer 307 is formed on the silicon cap layer 306. As an example, the gate oxide layer 307 is formed by a thermal oxidation process, and a portion of the silicon cap layer 306 is consumed.

[0050] After step 6, the thickness of the silicon cap layer 306 is 3 angstroms to 5 angstroms. Too large a thickness of the silicon cap layer 306 may lead to side effects such as a higher EOT (effective gate oxide thickness).

[0051] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0052] In summary, the method for epitaxially growing a silicon cap layer on a germanium silicon channel of an SOI device provided by the present application is adopted, the silicon cap layer epitaxially grown on the germanium silicon channel is continuously distributed, and after the gate oxide layer is grown on the silicon cap layer, a thin silicon cap layer exists between the germanium silicon channel and the gate oxide layer, which improves the interface state between the germanium silicon channel and the gate oxide layer, so that the CV curve of the PMOS meets the requirements. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0053] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.

Claims

1. A method for epitaxially growing a silicon cap layer on a silicon germanium channel of an SOI device, characterized in that: The method comprises: Step 1, providing an SOI substrate, wherein the SOI substrate comprises a bottom bulk silicon layer, an insulating dielectric buried layer and a top silicon layer stacked from bottom to top; Step 2, forming a silicon germanium layer on the top silicon layer; Step 3, sequentially performing thermal oxidation and thermal annealing treatments on the silicon germanium layer, while forming a top oxide layer on the surface of the silicon germanium layer and diffusing the germanium in the silicon germanium layer into the top silicon layer of the SOI substrate; Step 4, removing the top oxide layer; Step 5, epitaxially growing a silicon cap layer on the silicon germanium layer; Step six, forming a gate oxide layer on the silicon cap layer.

2. The method according to claim 1, characterized in that The gases used in the epitaxial process implemented in step five include Si2H6, HCL and H2.

3. The method according to claim 1 or 2, characterized in that: The temperature of the epitaxial process implemented in the step 5 is 400° C.-500° C., and the pressure is 10 torr-100 torr.

4. The method according to claim 1, characterized in that: In step six, a gate oxide layer is formed by a thermal oxidation process, which consumes part of the silicon cap layer.

5. The method according to claim 1 or 4, characterized in that: After step six is ​​completed, the thickness of the silicon cap layer is 3 angstroms to 5 angstroms.

6. The method according to claim 1, characterized in that The insulating dielectric buried layer is a silicon dioxide buried layer.

7. The method according to claim 6, characterized in that The silicon dioxide buried layer is formed by adopting an oxygen implantation isolation process.

8. The method according to claim 1, characterized in that In the step 2, the silicon germanium layer is formed by an epitaxial growth process.

9. The method according to claim 1, characterized in that: In the step three, the thermal oxidation and thermal annealing treatments are performed in a cycle for multiple times.

10. The method according to claim 1, characterized in that In the step 4, the top oxide layer is removed by a siconi cleaning process.

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