Gate driving circuit and display panel

Abstract

The application provides a gate drive circuit and a display panel. The gate drive circuit comprises a signal input module, a low-potential writing module, a high-potential control module and a signal output module. The low-potential writing module is used for directly writing a preset low potential to a first node. The high-potential control module is used for controlling the potential of a second node. The signal output module controls the potential of a signal output end of the current stage under the control of the potentials of the first node and the second node. The gate drive circuit and the display panel provided by the application eliminate the threshold voltage of a transistor in the gate drive circuit, dynamically adjust the output step size, and improve the service life performance and uniformity of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Technology

[0002] Gate Driver On Array (GOA) is a technology that integrates the gate driver circuitry onto the array substrate of the display panel to achieve line-by-line scanning drive. For example... Figure 1 As shown, the threshold voltage (Vth) of the P-type transistor in the gate drive circuit will shift due to factors such as transistor temperature changes, process differences, and aging. This will cause the falling edge step of the drive signal output by the gate drive circuit to change due to the shift in threshold voltage, affecting the output stability of the gate drive circuit. Summary of the Invention

[0003] The embodiments of this application provide a gate driving circuit and a display panel to solve the problem of poor output stability of gate driving circuits in related technologies.

[0004] To solve the above problems, the technical solution provided in this application is as follows:

[0005] In a first aspect, this application provides a gate driving circuit, including a plurality of cascaded gate driving units, wherein the gate driving unit includes:

[0006] The signal input module is used to receive the output signal from the previous stage.

[0007] A low-potential writing module is electrically connected to the signal input terminal and to the first node. The low-potential writing module is used to directly write a preset potential to the first node.

[0008] A high-potential control module is electrically connected to the second node and to the potential writing module. The high-potential control module is used to control the potential of the second node.

[0009] The signal output module is electrically connected to the signal output terminal of this stage, and is also electrically connected to the first node and the second node. The signal output module is used to control the potential of the signal output terminal of this stage under the control of the potential of the first node and the potential of the second node.

[0010] In one embodiment, the signal input module includes:

[0011] The first transistor has a gate connected to a first clock signal, a source electrically connected to the output signal of the previous stage, and a drain electrically connected to the first control module.

[0012] In one embodiment, the low-potential writing module includes:

[0013] The second transistor has a gate connected to a constant low potential signal, a source electrically connected to the drain of the first transistor, and a drain electrically connected to the first node.

[0014] The third transistor has its gate connected to the first node and its source connected to a preset high-potential signal.

[0015] The fourth transistor has its gate electrically connected to the drain of the third transistor, its source connected to a preset low-potential signal, and its drain connected to the first node.

[0016] A fifth transistor, wherein the gate of the fifth transistor is connected to the first node, the source of the fifth transistor is connected to the preset low-potential signal, and the drain of the fifth transistor is electrically connected to the drain of the third transistor; and

[0017] The sixth transistor has a gate connected to a reset control signal, a source connected to a constant high potential signal, and a drain connected to the drain of the first transistor.

[0018] Wherein, the voltage value of the preset high potential signal is less than that of the constant high potential signal, and the voltage value of the preset low potential signal is less than that of the constant low potential signal.

[0019] In one embodiment, the low-potential writing module further includes:

[0020] A seventh transistor, the gate of which is connected to the first node, and the source of which is connected to a second clock signal;

[0021] An eighth transistor, the gate of which is connected to the high-potential control module, the source of which is connected to a constant high-potential signal, and the drain of which is electrically connected to the drain of the seventh transistor; and

[0022] A first capacitor, the first terminal of which is electrically connected to the gate of the seventh transistor, and the second terminal of which is electrically connected to the drain of the third transistor.

[0023] In one embodiment, the low-potential writing module further includes:

[0024] The second capacitor has one end electrically connected to the first node and the other end connected to the constant high-potential signal.

[0025] In one embodiment, the third transistor is a P-type transistor, and the fourth and fifth transistors are both N-type transistors.

[0026] In one embodiment, the high-potential control module includes:

[0027] The ninth transistor has its gate connected to the first clock signal and its source connected to the constant low potential signal.

[0028] The tenth transistor has its gate connected to the constant low-potential signal, and its source is electrically connected to the drain of the ninth transistor.

[0029] The eleventh transistor has its gate electrically connected to the drain of the tenth transistor, and its source is connected to the second clock signal.

[0030] The twelfth transistor has its gate connected to the second clock signal, its source electrically connected to the drain of the eleventh transistor, and its drain electrically connected to the second node.

[0031] The thirteenth transistor has its gate electrically connected to the drain of the first transistor, its source connected to the first clock signal, and its drain electrically connected to the drain of the ninth transistor.

[0032] The fourteenth transistor, wherein the gate of the fourteenth transistor is electrically connected to the source of the second transistor, the source of the fourteenth transistor is connected to the constant high-potential signal, and the drain of the fourteenth transistor is electrically connected to the second node; and

[0033] The third capacitor has its first terminal electrically connected to the gate of the eleventh transistor and its second terminal electrically connected to the drain of the eleventh transistor.

[0034] In one embodiment, the signal output module includes:

[0035] The fifteenth transistor has its gate electrically connected to the first node, its source connected to the constant low-potential signal, and its drain electrically connected to the signal output terminal of this stage.

[0036] The sixteenth transistor, wherein its gate is electrically connected to the second node, its source is connected to the constant high-potential signal, and its drain is electrically connected to the signal output terminal of this stage; and

[0037] The fourth capacitor has its first terminal electrically connected to the second node and its second terminal electrically connected to the source of the sixteenth transistor.

[0038] In one embodiment, the first transistor, the second transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor are all P-type transistors.

[0039] In one embodiment, the first clock signal and the second clock signal are signals with the same period but opposite phase.

[0040] Secondly, this application provides a display panel including the aforementioned gate driving circuit.

[0041] This application provides a gate driving circuit and a display panel. The gate driving circuit includes a signal input module, a low-potential writing module, a high-potential control module, and a signal output module. The low-potential writing module controls the potential of a first node, the high-potential control module controls the potential of a second node, and the signal output module controls the potential of its own signal output terminal under the control of the potentials of the first and second nodes. By setting up a low-potential writing module, this application directly writes a preset low potential to the first node, eliminating the transistor threshold voltage in the gate driving circuit, dynamically adjusting the output step size, and improving the lifespan performance and uniformity of the display panel. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Appendix Figure 1 This is a schematic diagram of the output step of the gate drive circuit in an embodiment of this application;

[0044] Appendix Figure 2 This is a schematic diagram of the gate driving unit in an embodiment of this application;

[0045] Appendix Figure 3 This is a circuit diagram of an optional gate driving unit in an embodiment of this application;

[0046] Appendix Figure 4 This is a circuit diagram of another optional gate driving unit in an embodiment of this application;

[0047] Appendix Figure 5 This is a timing diagram of the gate driving unit in an embodiment of this application;

[0048] Appendix Figure 6 This is another timing diagram of the gate driving unit in an embodiment of this application;

[0049] Appendix Figure 7 This is a schematic diagram illustrating the effect of the gate driving unit in the embodiments of this application in eliminating the output step.

[0050] Appendix Figure 8 This is a schematic diagram of an optional display panel module in an embodiment of this application.

[0051] Explanation of the reference numerals in the figure:

[0052] 1. Display panel; 10. Gate drive circuit;

[0053] 100. Gate driving unit; 110. Signal input module; 120. Low-level writing module; 130. High-level control module; 140. Signal output module. Detailed Implementation

[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0055] According to a first aspect of this application, a gate driving circuit 10 is provided, including a plurality of cascaded gate driving units 100, as shown in the reference. Figure 2 As shown, the gate driving unit 100 includes a signal input module 110, a low-potential writing module 120, a high-potential control module 130, and a signal output module 140.

[0056] The signal input module 110 is used to receive the output signal EM_in from the previous stage. It should be noted that when the gate driving unit 100 is the first-stage driving unit, the signal input module 110 receives the frame start signal STV.

[0057] Specifically, the low-potential writing module 120 is electrically connected to the signal input terminal and to the first node Q. The low-potential writing module 120 is used to directly write a preset potential to the first node Q.

[0058] The high-potential control module 130 is electrically connected to the second node P and to the low-potential writing module. The high-potential control module 130 is used to control the potential of the second node P.

[0059] The signal output module 140 is electrically connected to the signal output terminal of this stage and to the first node Q and the second node P. The signal output module 140 is used to control the potential of the signal output terminal of this stage under the control of the potential of the first node Q and the potential of the second node P.

[0060] Compared to the existing gate driving circuit 10, the gate driving circuit 10 of this application embodiment uses the low-potential writing module 120 to directly write a preset low potential to the first node Q, eliminating the output step of the gate driving circuit 10, which is beneficial to improving the life performance and uniformity of the display panel 1.

[0061] In some specific embodiments of this application, reference is made to Figure 3 As shown, the signal input module 110 includes: a first transistor T1, the gate of the first transistor T1 is connected to the first clock signal XCK, the source of the first transistor T1 is connected to the previous stage output signal EM_in, and the drain of the first transistor T1 is electrically connected to the first control module.

[0062] In some specific embodiments of this application, reference is made to Figure 4 As shown, the low-potential writing module 120 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0063] In this embodiment, the gate of the second transistor T2 is connected to a constant low-potential signal, the source of the second transistor T2 is electrically connected to the drain of the first transistor T1, and the drain of the second transistor T2 is electrically connected to the first node Q. It should be noted that in some embodiments of this application, the constant low-potential signal may be the gate turn-off voltage VGL.

[0064] The gate of the third transistor T3 is connected to the first node Q, and the source of the third transistor T3 is connected to a preset high-level signal VGHL. It should be noted that the third transistor T3 is a low-level trigger module, which is used to trigger the writing of the preset low-level signal VGHL to the first node Q.

[0065] The gate of the fourth transistor T4 is electrically connected to the drain of the third transistor T3, the source of the fourth transistor T4 is connected to a preset low-potential signal VGLL, and the drain of the fourth transistor T4 is connected to the first node Q. It should be noted that the fourth transistor T4 writes the preset low-potential signal VGLL to the first node Q according to the operation of the third transistor T3.

[0066] The gate of the fifth transistor T5 is connected to the first node Q. The source of the fifth transistor T5 is connected to a preset low-potential signal VGLL. The drain of the fifth transistor T5 is electrically connected to the drain of the third transistor T3. It should be noted that the fifth transistor T5 is used to cut off the ultra-low voltage (i.e., the preset low-potential VGLL) flowing to the first node Q, ensuring the voltage of the first node Q remains stable. It should be noted that in this embodiment, the third transistor T3 is a P-type transistor, while the fourth transistor T4 and the fifth transistor T5 are both N-type transistors. Based on this, when the first node Q is at a low potential, the third transistor T3 is turned on, the fifth transistor T5 is turned off, and the gate of the fourth transistor T4 is connected to a preset high-potential signal VGHL, causing the fourth transistor T4 to turn on, thus connecting the first node Q to the preset low-potential VGLL. When the first node Q is at a high potential, the third transistor T3 is turned off, the fifth transistor T5 is turned on, and the gate of the fourth transistor is connected to the preset low-potential signal VGLL, causing the fourth transistor T4 to turn off, thus maintaining the voltage of the first node Q stably at a high potential.

[0067] The gate of the sixth transistor T6 is connected to a reset control signal, the source of the sixth transistor T6 is connected to a constant high potential signal, and the drain of the sixth transistor T6 is electrically connected to the drain of the first transistor T1.

[0068] Among them, the voltage value of the preset high potential signal VGHL is less than that of the constant high potential signal, and the voltage value of the preset low potential signal VGLL is less than that of the constant low potential signal.

[0069] In some embodiments of this application, the low-potential writing module 120 further includes a seventh transistor T7 and an eighth transistor T8.

[0070] In this configuration, the gate of the seventh transistor T7 is connected to the first node Q, and the source of the seventh transistor T7 is connected to the second clock signal CK.

[0071] The eighth transistor T8 has its gate connected to the high-level control module 130, its source connected to a constant high-level signal, and its drain electrically connected to the drain of the seventh transistor T7; and

[0072] The first capacitor C1 has its first terminal electrically connected to the gate of the seventh transistor T7, and its second terminal electrically connected to the drain of the seventh transistor T7.

[0073] In this embodiment, the seventh transistor T7, the eighth transistor T8, and the first capacitor C1 together constitute a coupling pull-low module. It should be noted that since the potential of the first node Q can be directly written by the fourth transistor T4, this coupling pull-low module can also be removed without affecting the output.

[0074] In some specific embodiments of this application, reference is made to Figure 4 As shown, the low-potential writing module 120 also includes a second capacitor C2. One end of the second capacitor C2 is electrically connected to the first node Q, and the other end of the second capacitor C2 is connected to a constant high-potential signal.

[0075] Reference Figure 3 and Figure 4 As shown, in some embodiments of this application, the high-potential control module 130 includes: a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a third capacitor C3.

[0076] In this configuration, the gate of the ninth transistor T9 is connected to the first clock signal XCK, and the source of the ninth transistor T9 is connected to a constant low-potential signal.

[0077] The gate of the tenth transistor T10 is connected to a constant low potential signal, and the source of the tenth transistor T10 is electrically connected to the drain of the ninth transistor T9.

[0078] The gate of the eleventh transistor T11 is electrically connected to the drain of the tenth transistor T10, and the source of the eleventh transistor T11 is connected to the second clock signal CK.

[0079] The gate of the twelfth transistor T12 is connected to the second clock signal CK. The source of the twelfth transistor T12 is electrically connected to the drain of the eleventh transistor T11. The drain of the twelfth transistor T12 is electrically connected to the second node P.

[0080] The gate of the thirteenth transistor T13 is electrically connected to the drain of the first transistor T1, the source of the thirteenth transistor T13 is connected to the first clock signal XCK, and the drain of the thirteenth transistor T13 is electrically connected to the drain of the eighth transistor T8.

[0081] The gate of the fourteenth transistor T14 is electrically connected to the source of the second transistor T2. A constant high potential signal is applied to the source of the fourteenth transistor T14. The drain of the fourteenth transistor T14 is electrically connected to the second node P.

[0082] The first terminal of the third capacitor C3 is electrically connected to the gate of the eleventh transistor T11, and the second terminal of the third capacitor C3 is electrically connected to the drain of the eleventh transistor T11.

[0083] In this embodiment, transistors T9, T11, T12, and T13 constitute a high-potential output sustaining module. Capacitor C3 is used to pull the coupling low. Transistor T10 is used to block ultra-low potentials. Transistor T14 is used to prevent output short circuits.

[0084] In some specific embodiments of this application, reference is made to Figures 3 to 4 As shown, the signal output module 140 includes: a fifteenth transistor T15, a sixteenth transistor T16, and a fourth capacitor C4.

[0085] In this circuit, the gate of the fifteenth transistor T15 is electrically connected to the first node Q, the source of the fifteenth transistor T15 is connected to a constant low-potential signal, and the drain of the fifteenth transistor T15 is electrically connected to the signal output terminal of this stage.

[0086] The gate of the sixteenth transistor T16 is electrically connected to the second node P, the source of the sixteenth transistor T16 is connected to a constant high potential signal, and the drain of the sixteenth transistor T16 is electrically connected to the signal output terminal of this stage.

[0087] The first terminal of the fourth capacitor C4 is electrically connected to the second node P, and the second terminal of the fourth capacitor C4 is electrically connected to the source of the sixteenth transistor T16, that is, a constant high potential signal is applied to achieve voltage regulation of the second node P.

[0088] It should be noted that in the aforementioned embodiments, the first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are all P-type transistors.

[0089] It should be noted that in the aforementioned embodiments, the first clock signal XCK and the second clock signal CK are signals with the same period but opposite phases. Based on this, referring to... Figure 5 and Figure 6 The figure shown is a timing diagram of the gate driving unit 100 of this application. The following is a summary of the timing diagram. Figure 4 The timing diagram is illustrated using the circuit diagram of the gate driving unit 100 shown as an example:

[0090] At time t0, the gate drive unit 100 receives a low-level output signal EM_in from the previous stage, a low-level first clock signal XCK, and a high-level second clock signal CK. At this time, T9 and T1 are turned on under the control of the low-level first clock signal XCK, and T2 and T10 are turned on under the control of a constant low-level signal. The low level of the constant low-level signal is output to nodes C, B, and the first terminal of C3. The low level of the previous stage output signal EM_in is output to nodes D and Q. Since node D is low, T13 and T14 are turned on, the low level of the first clock signal XCK is output to node C, and the high level of the constant high-level signal is output to the second node P. At this time, T11 is turned on, and the high level of the second clock signal CK is output to the second terminal of C3 (node ​​A). At this time, the first node Q remains low, the second node P is high, and the low level of the constant low-level signal is output to the signal output terminal of this stage.

[0091] At time t1, the gate drive unit 100 receives a low-level output signal EM_in from the previous stage, a high-level first clock signal XCK, and a low-level second clock signal CK. The first node Q begins to transition from low to high. At this time, T13 and T14 are turned on, and the high-level first clock signal XCK is output to nodes C and B, as well as the first terminal of capacitor C3. The high-level constant high-potential signal is output to the second node P and the second terminal of capacitor C3. At this point, the first node Q has not yet transitioned to high, the second node P is at high, and the low-level constant low-potential signal VGL is output to the current stage's signal output terminal OUT.

[0092] At time t2, when the gate drive unit 100 receives a high level output signal EM_in from the previous stage, the first clock signal XCK is low, and the second clock signal CK is high, T9 and T1 are turned on. The low level of the constant low-potential signal is output to nodes C, B, and the first terminal of capacitor C3. The high level of the previous stage output signal EM_in is output to nodes D and the first node Q. Since node D is high, T13 and T14 are turned off. Since the second clock signal CK is high, T12 is turned off, and the second node P remains high. Since node B is low, T11 is turned on, and the high level of the second clock signal CK is output to the second terminal of capacitor C3. At this time, the first node Q is high, the second node P is high, and the low level of the constant low-potential signal VGL is output to the signal output terminal of this stage.

[0093] At time t3, when the gate drive unit 100 receives the previous stage output signal EM_in and holds it at a high level, the first clock signal XCK is at a high level, and the second clock signal CK is at a low level. The first node Q remains at a high level, and at this time, T13 and T14 are off. Since the second clock signal CK is at a low level, T12 is turned on. Since node B is at a low level, T11 is turned on, and the low level of the second clock signal CK is output to the second terminal of capacitor C3 and the second node P. At this time, capacitor C3 bootstraps and pulls the potential of node B low. At this time, the first node Q is at a high level, the second node P is at a low level, and the high level of the constant high potential signal is output to the signal output terminal of this stage.

[0094] At time t4, when the gate drive unit 100 receives the output signal EM_in from the previous stage and it changes from high to low, the first clock signal XCK is low and the second clock signal CK is high. T1 and T9 are turned on, and the low level of the constant low-level signal VGL is output to nodes C and B, and the first terminal of capacitor C3. The low level of the previous stage output signal EM_in is output to node D and the first node Q. T14 is turned on. The high level of the second clock signal CK and the high level of the constant high-level signal VGH are output to the second terminal of capacitor C3. At this time, T14 is turned on, T12 is turned off, node P is connected to the constant high-level signal, T16 is turned off, and the low level of the constant low-level signal is output to the signal output terminal of this stage.

[0095] Reference Figure 7 As shown, out1 is the output step of the gate drive circuit 10 in the related art, and out2 is the output step of the gate drive circuit 10 in this application. This application eliminates the output step of the gate drive circuit 10 by setting a low-potential writing module 120, and the output falling edge is not delayed, thereby improving the life performance and uniformity of the display panel 1.

[0096] According to the second aspect of this application, referring to Figure 8 As shown, a display panel 1 is provided, which includes the aforementioned gate driving circuit 10 and can achieve all the effects of the aforementioned gate driving circuit 10, which will not be described in detail here.

[0097] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A gate driving circuit, characterized in that, It includes multiple cascaded gate driving units, each gate driving unit comprising: The signal input module is used to receive the output signal from the previous stage. A low-potential writing module is electrically connected to the signal input module and to the first node. The low-potential writing module is used to directly write a preset low potential to the first node. A high-potential control module is electrically connected to the second node and to the low-potential writing module. The high-potential control module is used to control the potential of the second node. A signal output module is electrically connected to the signal output terminal of this stage and to the first node and the second node. The signal output module is used to control the potential of the signal output terminal of this stage according to the potential of the first node and the potential of the second node. The low-potential writing module includes: The second transistor has a gate connected to a constant low potential signal, the source of the second transistor is electrically connected to the drain of the first transistor, and the drain of the second transistor is electrically connected to the first node. The third transistor has its gate connected to the first node and its source connected to a preset high-potential signal. The fourth transistor has its gate electrically connected to the drain of the third transistor, its source connected to a preset low-potential signal, and its drain connected to the first node. A fifth transistor, wherein the gate of the fifth transistor is connected to the first node, the source of the fifth transistor is connected to the preset low-potential signal, and the drain of the fifth transistor is electrically connected to the drain of the third transistor; and The sixth transistor has a gate connected to a reset control signal, a source connected to a constant high potential signal, and a drain connected to the drain of the first transistor. Wherein, the voltage value of the preset high potential signal is less than that of the constant high potential signal, and the voltage value of the preset low potential signal is less than that of the constant low potential signal.

2. The gate driving circuit according to claim 1, characterized in that, The signal input module includes: The first transistor has its gate connected to a first clock signal, and its source is electrically connected to the output signal of the previous stage.

3. The gate driving circuit according to claim 1, characterized in that, The low-potential writing module also includes: A seventh transistor, the gate of which is connected to the first node, and the source of which is connected to a second clock signal; An eighth transistor, the gate of which is connected to the high-potential control module, the source of which is connected to a constant high-potential signal, and the drain of which is electrically connected to the drain of the seventh transistor; and A first capacitor, the first terminal of which is electrically connected to the gate of the seventh transistor, and the second terminal of which is electrically connected to the drain of the seventh transistor.

4. The gate driving circuit according to claim 1, wherein the low-potential writing module further comprises: The second capacitor has one end electrically connected to the first node and the other end connected to the constant high-potential signal.

5. The gate driving circuit according to claim 1, characterized in that, The third transistor is a P-type transistor, and the fourth and fifth transistors are both N-type transistors.

6. The gate driving circuit according to any one of claims 3 to 5, characterized in that, The high-potential control module includes: The ninth transistor has its gate connected to a first clock signal and its source connected to the constant low potential signal. The tenth transistor has its gate connected to the constant low potential signal, and its source and drain are electrically connected. The eleventh transistor has its gate electrically connected to the drain of the tenth transistor, and its source is connected to a second clock signal. The twelfth transistor has its gate connected to the second clock signal, its source electrically connected to the drain of the eleventh transistor, and its drain electrically connected to the second node. The thirteenth transistor has its gate electrically connected to the drain of the first transistor, its source connected to the first clock signal, and its drain electrically connected to the drain of the ninth transistor. The fourteenth transistor, wherein the gate of the fourteenth transistor is electrically connected to the source of the second transistor, the source of the fourteenth transistor is connected to the constant high-potential signal, and the drain of the fourteenth transistor is electrically connected to the second node; and The third capacitor has its first terminal electrically connected to the gate of the eleventh transistor and its second terminal electrically connected to the drain of the eleventh transistor.

7. The gate driving circuit according to claim 6, characterized in that, The signal output module includes: The fifteenth transistor has its gate electrically connected to the first node, its source connected to the constant low-potential signal, and its drain electrically connected to the signal output terminal of this stage. The sixteenth transistor, wherein its gate is electrically connected to the second node, its source is connected to the constant high-potential signal, and its drain is electrically connected to the signal output terminal of this stage; and The fourth capacitor has its first terminal electrically connected to the second node and its second terminal electrically connected to the source of the sixteenth transistor.

8. The gate driving circuit according to claim 7, characterized in that, The first transistor, the second transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor are all P-type transistors.

9. The gate driving circuit according to claim 8, characterized in that, The first clock signal and the second clock signal are signals with the same period but opposite phase.

10. A display panel, characterized in that, Includes the gate drive circuit according to any one of claims 1 to 9.

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