Light emission control circuit and its control method, gate drive circuit and its control method

Abstract

A light-emitting control circuit includes a first detection control unit electrically connected to a detection control terminal, a first clock signal terminal, a first voltage signal terminal, and a first node, configured to transmit a first voltage signal to the first node under the control of a detection control signal and a first clock signal. A first light-emitting output unit electrically connected to the first node, the first voltage signal terminal, and a first output signal terminal, configured to transmit the first voltage signal to the first output signal terminal under the control of the voltage at the first node. A second detection control unit electrically connected to a detection control terminal, a second clock signal terminal, the first voltage signal terminal, and a second node, configured to transmit the first voltage signal to the second node under the control of a detection control signal and a second clock signal. A second light-emitting output unit electrically connected to the second node, the first voltage signal terminal, and a second output signal terminal, configured to transmit the first voltage signal to the second output signal terminal under the control of the voltage at the second node.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a light-emitting control circuit and its control method, and a gate driving circuit and its control method. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have attracted widespread attention due to their advantages such as active light emission, wide viewing angle, high contrast, fast response speed, low power consumption, and ultra-thin design. A display panel consists of multiple pixels, each comprising a pixel driving circuit and a light-emitting device. Prolonged continuous illumination by pixels can cause aging of the light-emitting devices, thus requiring pixel compensation. Summary of the Invention

[0003] On one hand, a light-emitting control circuit is provided. The light-emitting control circuit includes a first light-emitting control sub-circuit and a second light-emitting control sub-circuit. The first light-emitting control sub-circuit includes a first detection control unit and a first light-emitting output unit. The second light-emitting control sub-circuit includes a second detection control unit and a second light-emitting output unit. The first detection control unit is electrically connected to a detection control terminal, a first clock signal terminal, a first voltage signal terminal, and a first node, and is configured to transmit a first voltage signal from the first voltage signal terminal to the first node under the control of a detection control signal from the detection control terminal and a first clock signal from the first clock signal terminal. The first light-emitting output unit is electrically connected to the first node, the first voltage signal terminal, and a first output signal terminal, and is configured to transmit the first voltage signal to the first output signal terminal under the control of the voltage of the first node. The second detection control unit is electrically connected to the detection control terminal, a second clock signal terminal, the first voltage signal terminal, and the second node, and is configured to transmit the first voltage signal to the second node under the control of the detection control signal and a second clock signal from the second clock signal terminal. The second light-emitting output unit is electrically connected to the second node, the first voltage signal terminal, and the second output signal terminal, and is configured to transmit the first voltage signal to the second output signal terminal under the voltage control of the second node.

[0004] In some embodiments, the first detection control unit includes a first detection input subunit and a first detection output subunit. The first detection input subunit is electrically connected to the detection control terminal, the first clock signal terminal, and the third node, and is configured to transmit the first clock signal to the third node under the control of the detection control signal. The first detection output subunit is electrically connected to the third node, the first voltage signal terminal, and the first node, and is configured to transmit the first voltage signal to the first node under the voltage control of the third node.

[0005] The second detection control unit includes a second detection input subunit and a second detection output subunit. The second detection input subunit is electrically connected to the detection control terminal, the second clock signal terminal, and the fourth node, and is configured to transmit the second clock signal to the fourth node under the control of the detection control signal. The second detection output subunit is electrically connected to the fourth node, the first voltage signal terminal, and the second node, and is configured to transmit the first voltage signal to the second node under the voltage control of the fourth node.

[0006] In some embodiments, the first detection control unit further includes a first energy storage subunit; the first energy storage subunit is electrically connected to the first node and the third node and is configured to maintain the voltage of the third node. The second detection control unit further includes a second energy storage subunit; the second energy storage subunit is electrically connected to the second node and the fourth node and is configured to maintain the voltage of the fourth node.

[0007] In some embodiments, the first detection input subunit includes a first transistor, the control electrode of the first transistor being electrically connected to the detection control terminal, the first electrode being electrically connected to the second clock signal terminal, and the second electrode being electrically connected to the third node. The first detection output subunit includes a second transistor, the control electrode of the second transistor being electrically connected to the third node, the first electrode being electrically connected to the first voltage signal terminal, and the second electrode being electrically connected to the first node. The first energy storage subunit includes a first capacitor, the first plate of the first capacitor being electrically connected to the third node, and the second plate being electrically connected to the first node.

[0008] The second detection input subunit includes a third transistor, whose control electrode is electrically connected to the detection control terminal, first electrode is electrically connected to the fourth clock signal terminal, and second electrode is electrically connected to the fourth node. The second detection output subunit includes a fourth transistor, whose control electrode is electrically connected to the fourth node, first electrode is electrically connected to the first voltage signal terminal, and second electrode is electrically connected to the second node. The second energy storage subunit includes a second capacitor, whose first plate is electrically connected to the fourth node, and second plate is electrically connected to the second node.

[0009] In some embodiments, the first light emission control sub-circuit further includes a first pulse width modulation unit. The first pulse width modulation unit is electrically connected to a first input signal terminal, a third clock signal terminal, and the first node, and is configured to transmit a first input signal from the first input signal terminal to the first node under the control of a third clock signal from the third clock signal terminal.

[0010] The second light emission control sub-circuit further includes a second pulse width modulation unit. The second pulse width modulation unit is electrically connected to the second input signal terminal, the fourth clock signal terminal, and the second node, and is configured to transmit the second input signal from the second input signal terminal to the second node under the control of the fourth clock signal from the fourth clock signal terminal.

[0011] In some embodiments, the first pulse width modulation unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a third capacitor. The control electrode of the fifth transistor is electrically connected to the third clock signal terminal, its first electrode is electrically connected to the first input signal terminal, and its second electrode is electrically connected to the first node. The control electrode of the sixth transistor is electrically connected to the first node, its first electrode is electrically connected to the second voltage signal terminal, and its second electrode is electrically connected to the fifth node. The control electrode of the seventh transistor is electrically connected to the fifth node, its first electrode is electrically connected to the third voltage signal terminal, and its second electrode is electrically connected to the first output signal terminal. The control electrode of the eighth transistor is electrically connected to the fifth clock signal terminal, its first electrode is electrically connected to the first voltage signal terminal, and its second electrode is electrically connected to the sixth node. The control electrode of the ninth transistor is electrically connected to the sixth node, its first electrode is electrically connected to the third clock signal terminal, and its second electrode is electrically connected to the seventh node. The control electrode of the tenth transistor is electrically connected to the first input signal terminal, its first electrode is electrically connected to the seventh node, and its second electrode is electrically connected to the fifth node. The first plate of the third capacitor is electrically connected to the sixth node, and its second plate is electrically connected to the seventh node.

[0012] The second pulse width modulation unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a fourth capacitor. The control electrode of the eleventh transistor is electrically connected to the fourth clock signal terminal, its first electrode is electrically connected to the second input signal terminal, and its second electrode is electrically connected to the second node. The control electrode of the twelfth transistor is electrically connected to the second node, its first electrode is electrically connected to the second voltage signal terminal, and its second electrode is electrically connected to the eighth node. The control electrode of the thirteenth transistor is electrically connected to the eighth node, its first electrode is electrically connected to the third voltage signal terminal, and its second electrode is electrically connected to the second output signal terminal. The control electrode of the fourteenth transistor is electrically connected to the sixth clock signal terminal, its first electrode is electrically connected to the first voltage signal terminal, and its second electrode is electrically connected to the ninth node. The control electrode of the fifteenth transistor is electrically connected to the ninth node, its first electrode is electrically connected to the fourth clock signal terminal, and its second electrode is electrically connected to the tenth node. The control electrode of the sixteenth transistor is electrically connected to the second input signal terminal, its first electrode is electrically connected to the tenth node, and its second electrode is electrically connected to the eighth node. The first plate of the fourth capacitor is electrically connected to the ninth node, and the second plate is electrically connected to the tenth node.

[0013] The first light-emitting output unit includes a seventeenth transistor, the control electrode of which is electrically connected to the first node, the first electrode of which is electrically connected to the first voltage signal terminal, and the second electrode of which is electrically connected to the first output signal terminal. The second light-emitting output unit includes an eighteenth transistor, the control electrode of which is electrically connected to the second node, the first electrode of which is electrically connected to the first voltage signal terminal, and the second electrode of which is electrically connected to the second output signal terminal.

[0014] On the other hand, a gate driving circuit is also provided. The gate driving circuit includes a random detection circuit, a shift register circuit, and the light-emitting control circuit described in any of the above embodiments. The random detection circuit is electrically connected to a random detection signal terminal, a third input signal terminal, a seventh clock signal terminal, and an eleventh node. It is configured to transmit a seventh clock signal from the seventh clock signal terminal to the eleventh node under the control of a random detection signal from the random detection signal terminal and a third input signal from the third input signal terminal, thereby selecting a row of pixels for light-emitting device compensation. The shift register circuit is electrically connected to the eleventh node and is configured to output a scan signal to the corresponding row of pixels under the voltage control of the eleventh node, thereby turning on the corresponding row of pixels. The detection control terminal of the light-emitting control circuit is electrically connected to a circuit node in the random detection circuit or a circuit node in the shift register circuit.

[0015] In some embodiments, the random detection circuit includes a random detection control subcircuit and a detection output subcircuit. The random detection control subcircuit is electrically connected to the random detection signal terminal, the third input signal terminal, and the twelfth node, and is configured to transmit the third input signal to the twelfth node under the control of the random detection signal. The detection output subcircuit is electrically connected to the twelfth node, the seventh clock signal terminal, and the eleventh node, and is configured to transmit the seventh clock signal to the eleventh node under the voltage control of the twelfth node. The detection control terminal is electrically connected to the twelfth node.

[0016] In some embodiments, the random detection circuit further includes a first energy storage sub-circuit and a first leakage protection electronic circuit. The first energy storage sub-circuit is electrically connected to a fourth voltage signal terminal and the twelfth node, and is configured to maintain the voltage of the twelfth node. The first leakage protection electronic circuit is electrically connected to the random detection control sub-circuit, the random detection signal terminal, the twelfth node, and the fourth voltage signal terminal, and is configured to transmit the fourth voltage signal to the eleventh node under the control of the random detection signal and the voltage of the twelfth node. The random detection control sub-circuit is electrically connected to the twelfth node through the first leakage protection electronic circuit.

[0017] In some embodiments, the random detection control subcircuit includes a nineteenth transistor, the control electrode of which is electrically connected to the random detection signal terminal, the first electrode of which is electrically connected to the third input signal terminal, and the second electrode of which is electrically connected to the thirteenth node. The detection output subcircuit includes a twentieth transistor, the control electrode of which is electrically connected to the twelfth node, the first electrode of which is electrically connected to the seventh clock signal terminal, and the second electrode of which is electrically connected to the eleventh node. The first energy storage subcircuit includes a fifth capacitor, the first plate of which is electrically connected to the fourth voltage signal terminal, and the second electrode of which is electrically connected to the twelfth node. The first leakage protection electronic circuit includes a twenty-first transistor and a twenty-second transistor, the control electrode of which is electrically connected to the random detection signal terminal, the first electrode of which is electrically connected to the thirteenth node, and the second electrode of which is electrically connected to the twelfth node; the control electrode of which is electrically connected to the twelfth node, the first electrode of which is electrically connected to the fourth voltage signal terminal, and the second electrode of which is electrically connected to the thirteenth node.

[0018] In some embodiments, the shift register circuit includes a first shift register sub-circuit and a second shift register sub-circuit. The first shift register sub-circuit includes a first compensation input unit and a first scan output unit. The second shift register sub-circuit includes a second compensation input unit and a second scan output unit. The first compensation input unit is electrically connected to the eleventh node, the seventh clock signal terminal, and the fourteenth node, and is configured to transmit the voltage of the eleventh node to the fourteenth node under the control of the seventh clock signal. The first scan output unit is electrically connected to the fourteenth node, an eighth clock signal terminal, and a third output signal terminal, and the third output signal terminal is configured to be electrically connected to odd-numbered row pixels; the first scan output unit is configured to transmit the eighth clock signal from the eighth clock signal terminal to the third output signal terminal under the control of the voltage of the fourteenth node to open the corresponding odd-numbered row pixels. The second compensation input unit is electrically connected to the eleventh node, the seventh clock signal terminal, and the fifteenth node, and is configured to transmit the voltage of the eleventh node to the fifteenth node under the control of the seventh clock signal. The second scan output unit is electrically connected to the fifteenth node, the ninth clock signal terminal, and the fourth output signal terminal. The fourth output signal terminal is configured to be electrically connected to even-numbered rows of pixels. The second scan output unit is configured to, under the control of the voltage of the fifteenth node, transmit the ninth clock signal from the ninth clock signal terminal to the fourth output signal terminal to open the corresponding even-numbered rows of pixels. The detection control terminal is electrically connected to either the fourteenth node or the fifteenth node.

[0019] In some embodiments, the first compensation input unit includes a twenty-third transistor, the control electrode of which is electrically connected to the seventh clock signal terminal, the first electrode of which is electrically connected to the eleventh node, and the second electrode of which is electrically connected to the fourteenth node. The first scan output unit includes a twenty-fourth transistor, the control electrode of which is electrically connected to the fourteenth node, the first electrode of which is electrically connected to the eighth clock signal terminal, and the second electrode of which is electrically connected to the third output signal terminal. The second compensation input unit includes a twenty-fifth transistor, the control electrode of which is electrically connected to the seventh clock signal terminal, the first electrode of which is electrically connected to the eleventh node, and the second electrode of which is electrically connected to the fifteenth node. The second scan output unit includes a twenty-sixth transistor, the control electrode of which is electrically connected to the fifteenth node, the first electrode of which is electrically connected to the ninth clock signal terminal, and the second electrode of which is electrically connected to the fourth output signal terminal.

[0020] In some embodiments, the first shift register sub-circuit further includes a first scan input unit, a first inverter, and a first reset unit. The first scan input unit is electrically connected to the third input signal terminal, the fourth voltage signal terminal, and the fourteenth node, and is configured to transmit the third voltage signal to the fourteenth node under the control of the third input signal. One end of the first inverter is electrically connected to the fourteenth node, and the other end is electrically connected to the sixteenth node. The first reset unit is electrically connected to a first reset signal terminal, the sixteenth node, the fifth voltage signal terminal, the fourteenth node, and a third output signal terminal, and is configured to transmit the fifth voltage signal from the fifth voltage signal terminal to the fourteenth node and the third output signal terminal under the control of a first reset signal from the first reset signal terminal and the voltage of the sixteenth node.

[0021] The second shift register sub-circuit further includes a second scan input unit, a second inverter, and a second reset unit. The second scan input unit is electrically connected to the third input signal terminal, the fourth voltage signal terminal, and the fifteenth node, and is configured to transmit the third voltage signal to the fifteenth node under the control of the third input signal. One end of the second inverter is electrically connected to the fifteenth node, and the other end is electrically connected to the seventeenth node. The second reset unit is electrically connected to a second reset signal terminal, the fifth voltage signal terminal, the fifteenth node, the seventeenth node, and a fourth output signal terminal, and is configured to transmit the fifth voltage signal to the fifteenth node and the fourth output signal terminal under the control of a second reset signal from the second reset signal terminal and the voltage of the seventeenth node.

[0022] In some embodiments, the first scanning input unit includes a twenty-seventh transistor, the control electrode of the twenty-seventh transistor is electrically connected to the third input signal terminal, the first electrode is electrically connected to the fourth voltage signal terminal, and the second electrode is electrically connected to the fourteenth node.

[0023] The first reset unit includes a twenty-eighth transistor, a twenty-ninth transistor, and a thirtieth transistor. The control electrode of the twenty-eighth transistor is electrically connected to the first reset signal terminal, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the fourteenth node. The control electrode of the twenty-ninth transistor is electrically connected to the sixteenth node, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the third output signal terminal. The control electrode of the thirtieth transistor is electrically connected to the sixteenth node, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the fourteenth node.

[0024] The second scan input unit includes a thirty-first transistor, the control electrode of which is electrically connected to the third input signal terminal, the first electrode of which is electrically connected to the fourth voltage signal terminal, and the second electrode of which is electrically connected to the fourteenth node.

[0025] The second reset unit includes a 32nd transistor, a 33rd transistor, and a 34th transistor. The control electrode of the 32nd transistor is electrically connected to the second reset signal terminal, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the 15th node. The control electrode of the 33rd transistor is electrically connected to the 17th node, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the fourth output signal terminal. The control electrode of the 34th transistor is electrically connected to the 17th node, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the 15th node.

[0026] Furthermore, a control method for a light-emitting control circuit is also provided, used to drive the light-emitting control circuit in any of the above embodiments. The first output signal terminal of the light-emitting control circuit is electrically connected to the odd-numbered rows of pixels, and the second output signal terminal of the light-emitting control circuit is electrically connected to the even-numbered rows of pixels. A frame cycle includes a display phase and a blanking phase.

[0027] When a group of adjacent odd-numbered or even-numbered rows of pixels are selected for compensation of the light-emitting devices, the control method includes: during the blanking phase, the first detection control unit of the first light-emitting control sub-circuit of the light-emitting control circuit transmits a first voltage signal to the first node, and the first output unit of the first light-emitting control sub-circuit, under the control of the voltage of the first node, transmits the first voltage signal to the first output signal terminal, so that the operating current flows through the light-emitting devices of the odd-numbered or even-numbered rows of pixels; or, the second detection control unit of the second light-emitting control sub-circuit of the light-emitting control circuit transmits the first voltage signal to the second node, and the second output unit of the second light-emitting control sub-circuit, under the control of the voltage of the second node, transmits the first voltage signal to the second output signal terminal, so that the operating current flows through the light-emitting devices of the odd-numbered or even-numbered rows of pixels.

[0028] In some embodiments, the first light emission control sub-circuit includes a first pulse width modulation unit, and the second light emission control sub-circuit includes a second pulse width modulation unit.

[0029] The control method includes: during the display phase, the first pulse width modulation unit, under the control of a third clock signal, transmits a first input signal to the first node; the first light-emitting output unit, under the control of the voltage of the first node, transmits the first voltage signal to the first output signal terminal to modulate the light-emitting time of the odd-numbered row pixels and the even-numbered row pixels. When a group of adjacent odd-numbered row pixels or even-numbered row pixels are selected for light-emitting device compensation, during the blanking phase, the second detection control unit transmits the first voltage signal to the second node, and the second light-emitting output unit, under the control of the voltage of the second node, transmits the first voltage signal to the second output signal terminal, so that operating current flows through the light-emitting devices of the odd-numbered row pixels or even-numbered row pixels.

[0030] Alternatively, the control method includes: during the display phase, the second pulse width modulation unit, under the control of a fourth clock signal, transmits a second input signal to the second node; the second light-emitting output unit, under the control of the voltage of the second node, transmits the first voltage signal to the second output signal terminal to modulate the light-emitting time of the odd-numbered row pixels and the even-numbered row pixels. When a group of adjacent odd-numbered row pixels or even-numbered row pixels are selected for light-emitting device compensation, during the blanking phase, the first detection control unit transmits the first voltage signal to the first node, and the first light-emitting output unit, under the control of the voltage of the first node, transmits the first voltage signal to the second output signal terminal, so that operating current flows through the light-emitting devices of the odd-numbered row pixels or even-numbered row pixels.

[0031] In some embodiments, the control method includes: during the same frame period, the first clock signal terminal, the second input signal terminal, and the fourth clock signal terminal output pulse signals, while the second clock signal terminal, the first input signal terminal, and the third clock signal terminal do not output voltage signals. Alternatively, during the same frame period, the second clock signal terminal, the first input signal terminal, and the third clock signal terminal output pulse signals, while the first clock signal terminal, the second input signal terminal, and the fourth clock signal terminal do not output voltage signals.

[0032] On another front, a control method for a gate driving circuit is provided, the control method being configured to drive the gate driving circuit described in any of the above embodiments. A first output signal terminal of the light-emitting control circuit of the gate driving circuit is electrically connected to odd-numbered row pixels, and a second output signal terminal of the light-emitting control circuit is electrically connected to even-numbered row pixels. A frame period includes a display phase and a blanking phase. When a group of adjacent odd-numbered or even-numbered row pixels are selected for compensation of the light-emitting device, the control method includes:

[0033] During the display phase, the random detection circuit of the gate drive circuit transmits the third input signal to the circuit node in the random detection circuit under the control of the random detection signal, and maintains the voltage of the corresponding circuit node until the blank phase.

[0034] During the blanking phase, the random detection circuit, under the control of the voltage of the corresponding circuit node, transmits the seventh clock signal to the shift register circuit of the gate driving circuit; the shift register circuit outputs a scan signal to the corresponding row pixel to turn on the corresponding row pixel; the light emission control circuit of the gate driving circuit, under the control of the voltage of the circuit node in the random detection circuit or the voltage of the circuit node in the shift register circuit, transmits the first voltage signal to the first output signal terminal or the second output signal terminal so that the operating current flows through the light emission device of the odd-numbered row pixel or the even-numbered row pixel.

[0035] In some embodiments, the shift register circuit includes a first shift register sub-circuit and a second shift register sub-circuit. The first shift register sub-circuit includes a first scan input unit and a first scan output unit, and the second shift register sub-circuit includes a second scan input unit and a second scan output unit. The first light emission control sub-circuit of the light emission control circuit includes a first pulse width modulation unit, and the second light emission control sub-circuit includes a second pulse width modulation unit. During the display stage, the control method includes:

[0036] Under the control of the third input signal, the first scanning input unit inputs a fourth voltage signal to the fourteenth node; under the control of the voltage at the fourteenth node, the first scanning output unit transmits an eighth clock signal to the third output signal terminal to activate the corresponding odd-numbered row pixels. Under the control of the third input signal, the second scanning input unit inputs the fourth voltage signal to the fifteenth node; under the control of the voltage at the fifteenth node, the second scanning output unit transmits a ninth clock signal to the fourth output signal terminal to activate the corresponding even-numbered row pixels. Under the control of the third clock signal, the first pulse width modulation unit transmits a first input signal to the first node, or under the control of the fourth clock signal, the second pulse width modulation unit transmits a second input signal to the second node to modulate the emission time of the odd-numbered row pixels and the even-numbered row pixels.

[0037] In another aspect, a control method for a display panel is provided. The display panel includes the gate driving circuit, data driving circuit, odd-numbered row pixels, and even-numbered row pixels as described in any of the above embodiments. A first light-emitting control sub-circuit of the gate driving circuit is electrically connected to the odd-numbered row pixels, and a second light-emitting control sub-circuit is electrically connected to the even-numbered row pixels. A frame cycle includes a display phase and a blanking phase, the blanking phase including a first data writing phase, a second data writing phase, and a sensing phase. When a group of adjacent odd-numbered row pixels or even-numbered row pixels are selected for compensation of the light-emitting device, the control method includes:

[0038] In the first data writing phase, the data driving circuit writes zero-grayscale data to the one of the odd-numbered rows of pixels and the even-numbered rows of pixels that was not selected for external compensation. In the second data writing phase, the data driving circuit writes sensed grayscale data to the one of the odd-numbered rows of pixels and the even-numbered rows of pixels that was selected for compensation of the light-emitting device. In the sensing phase, the first light-emitting control sub-circuit or the second light-emitting control sub-circuit outputs a first voltage signal to allow operating current to flow through the light-emitting devices of the odd-numbered rows of pixels and the even-numbered rows of pixels; the pixel circuit of the odd-numbered rows of pixels or the even-numbered rows of pixels detects the voltage of the light-emitting device.

[0039] In some embodiments, the blanking phase further includes a first data write-back phase and a second data write-back phase. The control method further includes: in the first data write-back phase, writing first initial grayscale data to one of the odd-numbered row pixels and the even-numbered row pixels that were not selected for compensation of the light-emitting device; and in the second data write-back phase, writing second initial grayscale data to one of the odd-numbered row pixels and the even-numbered row pixels that were selected for compensation of the light-emitting device. The first initial grayscale data is the grayscale data of the corresponding row pixels written before the first data write phase. The second initial grayscale data is the grayscale data of the corresponding row pixels written before the second data write phase.

[0040] In another aspect, a display device is provided. The display device includes the gate driving circuit described in any of the above embodiments. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0042] Figure 1 This is a structural diagram of a display device according to an embodiment of the present disclosure;

[0043] Figure 2 This is a structural diagram of the display panel according to an embodiment of the present disclosure;

[0044] Figure 3 This is an equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0045] Figure 4 This is a timing control diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0046] Figure 5 This is another equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0047] Figure 6 This is an equivalent circuit diagram of the two-row pixel driving circuit according to an embodiment of the present disclosure;

[0048] Figure 7 This is a cascade diagram of the gate drive circuit according to an embodiment of the present disclosure;

[0049] Figure 8 This is a connection diagram of the gate driving circuit and the pixel driving circuit according to an embodiment of the present disclosure;

[0050] Figure 9 This is a structural diagram of a light-emitting control circuit according to an embodiment of the present disclosure;

[0051] Figure 10 This is another structural diagram of the light-emitting control circuit according to an embodiment of the present disclosure;

[0052] Figure 11 This is another structural diagram of the light-emitting control circuit according to an embodiment of the present disclosure;

[0053] Figure 12 This is an equivalent circuit diagram of the first detection control unit and the second detection control unit according to an embodiment of this disclosure;

[0054] Figure 13 This is another structural diagram of the light-emitting control circuit according to an embodiment of the present disclosure;

[0055] Figure 14A This is an equivalent circuit diagram of the first light-emitting control sub-circuit according to an embodiment of the present disclosure;

[0056] Figure 14B This is an equivalent circuit diagram of the second light-emitting control sub-circuit according to an embodiment of the present disclosure;

[0057] Figure 15 This is another structural diagram of the light-emitting control circuit according to an embodiment of the present disclosure;

[0058] Figure 16A This is another equivalent circuit diagram of the first light-emitting control sub-circuit according to an embodiment of the present disclosure;

[0059] Figure 16B This is another equivalent circuit diagram of the second light-emitting control sub-circuit according to an embodiment of the present disclosure;

[0060] Figure 17A This is another equivalent circuit diagram of the first light-emitting control sub-circuit according to an embodiment of the present disclosure;

[0061] Figure 17B This is another equivalent circuit diagram of the second light-emitting control sub-circuit according to an embodiment of the present disclosure;

[0062] Figure 18 This is a control timing diagram of a light-emitting control circuit according to an embodiment of the present disclosure;

[0063] Figure 19A This is a structural diagram of a gate driving circuit according to an embodiment of the present disclosure;

[0064] Figure 19B This is another structural diagram of the gate driving circuit according to an embodiment of the present disclosure;

[0065] Figure 20 This is a structural diagram of a random detection circuit according to an embodiment of the present disclosure;

[0066] Figure 21 This is an equivalent circuit diagram of a random detection circuit according to an embodiment of the present disclosure;

[0067] Figure 22 This is another structural diagram of the random detection circuit according to an embodiment of the present disclosure;

[0068] Figure 23 This is another equivalent circuit diagram of the random detection circuit in an embodiment of the present disclosure;

[0069] Figure 24A This is a structural diagram of a shift register circuit according to an embodiment of the present disclosure;

[0070] Figure 24B This is an equivalent circuit diagram of a shift register circuit according to an embodiment of the present disclosure;

[0071] Figure 25A This is a structural diagram of the first shift register sub-circuit according to an embodiment of the present disclosure;

[0072] Figure 25B This is a structural diagram of the second shift register sub-circuit according to an embodiment of the present disclosure;

[0073] Figure 26AThis is an equivalent circuit diagram of the first shift register sub-circuit according to an embodiment of the present disclosure;

[0074] Figure 26B This is an equivalent circuit diagram of the second shift register sub-circuit according to an embodiment of the present disclosure;

[0075] Figure 27 This is a timing control diagram of a gate drive circuit according to an embodiment of the present disclosure;

[0076] Figure 28 This is a timing control diagram for a display panel according to an embodiment of the present disclosure. Detailed Implementation

[0077] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0078] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0079] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0080] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0081] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0082] In all embodiments of this disclosure, the transistors used can be thin film transistors (TFTs), metal oscillator transistors (MOSs), or other devices with the same characteristics. This disclosure does not limit the types of transistors used.

[0083] For example, the transistor can be a TFT. The TFT can be fabricated using a-Si technology, oxide semiconductor technology, low-temperature polysilicon (LTPS) technology, or high-temperature polysilicon (HTPS) technology. The embodiments of this disclosure are not limited in this regard.

[0084] The embodiments of this disclosure do not limit the type of transistor. The transistor can be an N-type transistor, a P-type transistor, an enhancement-mode transistor, or a depletion-mode transistor. In the embodiments of this disclosure, all transistors are N-type transistors as an example to illustrate this application. An N-type transistor is turned on under a high-level voltage signal and turned off under a low-level voltage signal; that is, the operating voltage of an N-type transistor is a high-level voltage, and the turn-off voltage is a low-level voltage.

[0085] In the embodiments of this disclosure, the gate of the transistor is the control electrode. To distinguish the two electrodes of the transistor other than the gate, one electrode is directly described as the first electrode, and the other as the second electrode. In this case, the first electrode of the transistor can be either the source or the drain, and the second electrode can be either the source or the drain. Since the source and drain of the transistor can be structurally symmetrical, they can be structurally indistinguishable.

[0086] The capacitor in this embodiment can be a capacitor device manufactured separately through a process, such as by fabricating dedicated capacitor electrodes. The individual capacitor electrodes (first and second plates) can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. The capacitor can also be the parasitic capacitance between transistors, or implemented through the transistor itself and other devices or circuits, or by utilizing the parasitic capacitance between circuit lines themselves.

[0087] Each of the aforementioned transistors may further include at least one switching transistor connected in parallel with each transistor. The embodiments described in this disclosure are merely illustrative examples of pixel driving circuits and gate driving circuits; other structures with the same function as pixel driving circuits and gate driving circuits will not be described in detail, but should all fall within the protection scope of this disclosure.

[0088] In the embodiments of this disclosure, "first node," "second node," etc., do not refer to actual existing components, but rather to the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0089] Some embodiments of this disclosure provide a display device 1000, see reference. Figure 1 , Figure 1 This is a structural diagram of a display device 1000, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether it is text or images.

[0090] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, etc.

[0091] See Figure 2 The display device 1000 includes a display panel 1100, a data driving circuit 1200 disposed on the display panel 1100, and a circuit board 1300 (e.g., a source PCB) electrically connected to the display panel 1100 and the data driving circuit 1200. For example, the data driving circuit 1200 may be a source driver IC, and the circuit board 1300 may be a source PCB.

[0092] The display panel 1100 has a display area AA and a peripheral area BB located at least on one side of the display area AA. For example, see [reference needed]. Figure 2The display panel 1100 has a display area AA and a peripheral area BB surrounding the display area AA. The data driving circuit 1200 is disposed in the peripheral area BB of the display panel 1100.

[0093] The display panel 1100 includes multiple subpixels P, multiple data lines DL, multiple first gate lines GL1, multiple second gate lines GL2, and multiple sensing signal lines SL. Figure 2 (not shown in the image) and multiple gate drive circuits 1120.

[0094] Each pixel P may include a pixel driving circuit 1110 and a light-emitting device EL. The multiple light-emitting devices EL of multiple pixels P can emit at least three primary colors, such as red (R), green (G), and blue (B) light.

[0095] Multiple pixels P are arranged in multiple columns along a first direction X (multiple columns of pixels P arranged along the first direction X) and multiple rows along a second direction Y (multiple rows of pixels P arranged along the second direction Y). Each row of pixels P includes multiple pixels P arranged along the first direction X, and each column of pixels P includes multiple pixels P arranged along the second direction Y. The first direction X and the second direction Y intersect; for example, the second direction Y is perpendicular to the first direction X.

[0096] Along the second direction Y, the multiple rows of pixels P include alternating rows of odd-numbered pixels P1 and even-numbered pixels P2. For example, along the first direction X and away from the data driving circuit 1200, the first, third, fifth, ..., (N-1)th rows are all odd-numbered rows of pixels P1. The second, fourth, sixth, ..., Nth rows are all even-numbered rows of pixels P2. Here, N is a positive integer, and N is even.

[0097] See Figure 2 Gate driving circuit 1120 is disposed in peripheral area BB. Each group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 are electrically connected to a gate driving circuit 1120 through a first gate line GL1 and a second gate line GL2, respectively. Multiple gate driving circuits 1120 are cascaded. Each column of pixels P is electrically connected to data driving circuit 1200 through a data line DL, and each column of pixels P is electrically connected to a sensing signal line SL. Figure 2 The sensing signal line SL is not shown in the image.

[0098] It is understood that in the embodiments of this disclosure, "a set of adjacent odd-numbered rows of pixels and even-numbered rows of pixels" refers to a row of odd-numbered rows of pixels P1 and a row of even-numbered rows of pixels P2 that are electrically connected to the same gate driving circuit 1120 (and electrically connected to the same light-emitting control circuit 100).

[0099] See Figure 3 , Figure 3 This is an equivalent circuit diagram of a pixel driving circuit 1110 provided in an embodiment of the present disclosure. The pixel driving circuit 1110 may include a driving transistor T101, a data writing transistor T102, a sensing transistor T103, and an energy storage capacitor Cst.

[0100] Specifically, the control electrode of the data writing transistor T102 is electrically connected to the first gate line GL1, the first electrode is electrically connected to the data line DL, and the second electrode is electrically connected to the control electrode of the driving transistor T101. The first electrode of the driving transistor T101 is electrically connected to the power supply voltage signal terminal VDD, and the second electrode is electrically connected to the anode of the light-emitting device EL. The control electrode of the sensing transistor T103 is electrically connected to the second gate line GL2, the first electrode is electrically connected to the anode of the light-emitting device EL, and the second electrode is electrically connected to the sensing signal line SL. The first plate of the energy storage capacitor Cst is electrically connected to the control electrode of the driving transistor T101, and the second plate is electrically connected to the anode of the light-emitting device EL.

[0101] Because light-emitting diodes (ELs) age after prolonged operation (emitting light), they need to be compensated to ensure that they can display the required grayscale data.

[0102] See Figure 4 , Figure 4 for Figure 3 The pixel driving circuit 1110 shown is a timing control diagram. A frame period (Frame) F includes a blank phase (Blank) B and a display phase (Display) D. The blank phase B includes a sensing data writing phase B1, a sensing phase B2, and a display data write-back phase B3.

[0103] During the sensing data writing stage B1, the gate driving circuit 1120 controls the data writing transistor T102 to turn on via the first gate line GL1, and the data driving circuit 1200 writes the sensing grayscale data VGm to the control electrode of the driving transistor T101 via the data line DL. The sensing grayscale data VGm turns on the driving transistor T101, and the power supply voltage signal terminal VDD charges the anode of the light-emitting device EL through the driving transistor T101.

[0104] During the sensing phase B2, the data writing transistor T102 is turned off, and the second gate line GL2 controls the sensing transistor T103 to turn on, and the sensing signal line SL senses the voltage of the anode of the light-emitting device EL.

[0105] It is understood that the process of compensating the light-emitting device EL is a conventional technique in the art, and other processes of compensating the light-emitting device EL in the embodiments of this disclosure will not be described in detail.

[0106] During the display stage, the gate driving circuit 1120 can control the data writing transistor T102 to turn on through the first gate line GL1, and the data driving circuit 1200 writes the display grayscale data Dn to the control electrode of the driving transistor T101 through the data line DL; the display grayscale data Dn controls the driving transistor T101 to turn on, the power supply voltage signal terminal CDD is connected to the anode of the light-emitting device EL, the driving current flows through the light-emitting device EL, and the light-emitting device EL works.

[0107] In some embodiments, the light-emitting device (EL) can be an organic light-emitting diode (OLED). In this case, the luminous efficiency of the EL is positively correlated with the magnitude (or current density) of the current flowing through the EL. That is, when the magnitude of the current flowing through the EL is small, the luminous efficiency of the EL is low, and when the magnitude of the current flowing through the EL is large, the luminous efficiency of the EL is high.

[0108] To improve the luminous efficiency of the light-emitting device (EL) when displaying low grayscale, some embodiments of this disclosure also provide a pixel driving circuit 1110, see reference. Figure 5 , Figure 5 In order to be in Figure 3 The equivalent circuit diagram of pixel driving circuit 1110 after adding light-emitting control transistor T104 to the pixel driving circuit shown is as follows. Light-emitting control transistor T104 is used to modulate the emission time of light-emitting device EL (i.e., pulse width modulation; abbreviated as PWM) to change the emission space ratio of light-emitting device EL within a frame, thereby shortening the emission time of light-emitting device EL. By shortening the emission time of light-emitting device EL, the current flowing through light-emitting device EL during emission increases, thereby improving the luminous efficiency of light-emitting device EL.

[0109] See Figure 5 The control electrode of the light-emitting control transistor T104 is electrically connected to the gate drive circuit 1120 through the light-emitting control scan line EM, the first electrode is electrically connected to the power supply voltage signal terminal VDD, and the second electrode is electrically connected to the first electrode of the drive transistor T101.

[0110] In some embodiments, the light-emitting control transistor T104 can be an oxide thin-film transistor (oxide TFT), which has high electron mobility and good turn-off characteristics. This facilitates the complete switching on or off of the light-emitting control transistor T104 during the time-emission modulation of the light-emitting device EL.

[0111] In some embodiments, see Figure 6 , Figure 6The equivalent circuit diagram is shown for a group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2, where only one pixel P is shown as an example in each row. The second terminal of the light-emitting control transistor T104(1) of the odd-numbered row pixel P1 is electrically connected to the second terminal of the light-emitting control transistor T104(2) of the even-numbered row pixel P2 via a connecting line L0. In this way, a group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 share the light-emitting control transistor T104.

[0112] Within the same frame period F, one of the light-emitting control transistors T104(1) for odd-numbered row pixels P1 and T104(2) for even-numbered row pixels P2 modulates the emission time of the two light-emitting devices EL of the corresponding pixels P in the two rows, while the other remains off (always in the off state within the corresponding frame period). In this way, the risk of damage or threshold voltage drift of the light-emitting control transistor T104 due to long-term operation can be reduced, and the reliability of the light-emitting control transistor T104 can be improved.

[0113] Within different frame periods F, the light-emitting control transistor T104(1) of the odd-numbered row pixel P1 and the light-emitting control transistor T104(2) of the even-numbered row pixel P2 alternately modulate the light-emitting time of the two light-emitting devices EL of the corresponding pixels P in the two rows, and alternately rest.

[0114] In related technologies, due to the use of the aforementioned pixel driving circuit (a group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 share a light-emitting control transistor T104), within one frame period, one of the two light-emitting control scan lines EM electrically connected to the group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 continuously outputs a shutdown voltage (low-level voltage signal), and the light-emitting control transistor T104 of the row pixel P electrically connected to the corresponding light-emitting control scan line EM is in a turned-off state; the other light-emitting control scan line EM outputs a pulse signal, and the pulse signal may also be a shutdown voltage during the sensing data writing stage B1, so the light-emitting control transistor T104 of the row pixel P electrically connected to the corresponding light-emitting control scan line EM may also be in a turned-off state. However, during the sensing data writing stage B1, when the light-emitting control transistors T104 of a group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 are both in the off state, and one of the adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 is selected for compensation of the light-emitting device EL, the light-emitting control transistor T104 of the corresponding row pixel P cannot be turned on. The anode of the light-emitting device EL is electrically insulated from the power supply voltage VDD, so the charging of the light-emitting device EL cannot be completed, and therefore the compensation of the light-emitting device EL cannot be performed.

[0115] To address the aforementioned problems, some embodiments of this disclosure also provide a gate drive circuit 1120, see reference. Figure 7The gate driving circuit 1120 includes a light emission control circuit 100, a random detection circuit 200, and a shift register circuit 300.

[0116] The random detection circuit 200 can also be called a random sense unit. The random detection circuit 200 is configured to randomly select a row of pixels P in each frame period F and compensate the light-emitting device EL of the selected row of pixels P.

[0117] Multiple shift register circuits 300 are cascaded sequentially. Each shift register circuit 300 is electrically connected to a first gate line GL1 and a second gate line GL2, and is configured to output a first scan signal to the first gate line GL1 and a second scan signal to the second gate line GL2. A random detection circuit 200 is electrically connected to two shift register circuits 300 (e.g., ...). Figure 8 (As shown).

[0118] For example, see Figure 8 The shift register circuit 300 includes a first shift register sub-circuit GL1 GOA and a second shift register sub-circuit GL2 GOA; multiple first shift register sub-circuits GL1 GOA of multiple shift register circuits 300 are cascaded sequentially, and multiple second shift register sub-circuits GL2 GOA of multiple shift register circuits 300 are cascaded sequentially. It should be noted that... Figure 7 The first shift register subcircuit GL1 GOA is shown only as an example.

[0119] See Figure 9 , Figure 9 This is a structural diagram of a light-emitting control circuit 100. The light-emitting control circuit 100 includes a first light-emitting control sub-circuit 110 and a second light-emitting control sub-circuit 120.

[0120] See Figure 7 and Figure 8 Multiple gate driving circuits 1120 and multiple light-emitting control circuits 100 are cascaded sequentially. Exemplarily, the first light-emitting control sub-circuit 110 of each gate driving circuit 1120 is cascaded with each other, wherein the first cascaded output signal terminal CR1 of the previous stage first light-emitting control sub-circuit 110 is electrically connected to the first input signal terminal IN1 of the next stage first light-emitting control sub-circuit 110. The second light-emitting control sub-circuit 120 of each gate driving circuit 1120 is cascaded sequentially, wherein the second cascaded output signal terminal CR2 of the previous stage second light-emitting control sub-circuit 120 is electrically connected to the second input signal terminal IN2 of the next stage second light-emitting control sub-circuit 120.

[0121] Each light-emitting control circuit 100 is electrically connected to a first light-emitting control scan line EM1 and a second light-emitting control scan line EM2, and is configured to output light-emitting control signals through the first light-emitting control scan line EM1 and the second light-emitting control scan line EM2 to modulate the light-emitting duration of a set of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2 electrically connected thereto.

[0122] For example, see Figure 8 and Figure 9 Each light-emitting control circuit 100 is electrically connected to a group of adjacent odd-numbered row pixels P1 and even-numbered row pixels P2. The first light-emitting control sub-circuit 110 of the light-emitting control circuit 100 is electrically connected to the odd-numbered row pixels P1, and the second light-emitting control sub-circuit 120 is electrically connected to the even-numbered row pixels P2. Thus, the first output signal terminal EM1 is electrically connected to the control electrode of the light-emitting control transistor T104 of the odd-numbered row pixels P1, and the second output signal terminal EM2 is electrically connected to the control electrode of the light-emitting control transistor T104 of the even-numbered row pixels P2.

[0123] In the embodiments of this disclosure, for the sake of simplicity, the first output signal terminal and the first light-emitting control signal line are labeled with the same numeral EM1 to indicate that the first output signal terminal is electrically connected to the first light-emitting control signal line; the second output signal terminal and the second light-emitting control signal line are labeled with the same numeral EM2 to indicate that the second output signal terminal and the second light-emitting control signal line are electrically connected.

[0124] The first light-emitting control sub-circuit 110 includes a first detection and control unit 111 and a first light-emitting output unit 112. The second light-emitting control sub-circuit 120 includes a second detection and control unit 121 and a second light-emitting output unit 122.

[0125] The first detection control unit 111 is electrically connected to the detection control terminal VH, the first clock signal terminal CKA1, the first voltage signal terminal VGH, and the first node N1. It is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the first node N1 under the control of the detection control signal from the detection control terminal VH and the first clock signal from the first clock signal terminal CKA1.

[0126] The first light-emitting output unit 112 is electrically connected to the first node N1, the first voltage signal terminal VGH and the first output signal terminal EM1, and is configured to transmit the first voltage signal to the first output signal terminal EM1 under the control of the voltage of the first node N1.

[0127] The second detection control unit 121 is electrically connected to the detection control terminal VH, the second clock signal terminal CKA2, the first voltage signal terminal VGH, and the second node N2, and is configured to transmit the first voltage signal to the second node N2 under the control of the detection control signal and the second clock signal from the second clock signal terminal CKLB.

[0128] The second light-emitting output unit 122 is electrically connected to the second node N2, the first voltage signal terminal VGH, and the second output signal terminal EM2, and is configured to transmit the first voltage signal to the second output signal terminal EM2 under the voltage control of the second node N2.

[0129] In some embodiments, when a row of pixels P is selected and the light-emitting device EL of that row of pixels P is compensated, the detection control terminal VH can output a working voltage (high-level voltage signal) to the light-emitting control circuit 100 electrically connected to that row of pixels P.

[0130] For example, when the Nth row (N is an even number) pixel P is selected and the light-emitting device EL of the Nth row pixel P is compensated, the detection control terminal VH in the second light-emitting control sub-circuit 120 electrically connected to the Nth row pixel and the detection control terminal VH in the first light-emitting control sub-circuit 110 electrically connected to the (N-1)th row pixel simultaneously generate a working voltage (high-level voltage signal).

[0131] The first voltage signal terminal VGH can be a voltage signal terminal that continuously outputs a high level, thus the first voltage signal is a high-level voltage signal.

[0132] Within the same frame period F, one of the first clock signal terminal CKA1 and the second clock signal terminal CKA2 outputs a pulse signal during the blank phase B, while the other outputs a continuous low-level voltage signal. In different frame periods, the first clock signal terminal CKA1 and the second clock signal terminal CKA2 alternately output pulse signals during the blank phase B (e.g., ...). Figure 18 (As shown). Thus, during the blank phase B of the same frame period F, there is only one output pulse signal in the first clock signal terminal CKA1 and the second clock signal terminal CKA2. In this way, when selecting a group of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 for light-emitting device compensation, one of the two light-emitting control transistors T104 of the odd-numbered row pixels P1 and even-numbered row pixels P2 is turned on, while the other is turned off.

[0133] For example, the output pulse signal is switched between the first clock signal terminal CKA1 and the second clock signal terminal CKA2 every frame period F. That is, during the blank phase B of the odd-numbered frame period (e.g., 1, 3, 5, etc.), one of the first clock signal terminal CKA1 and the second clock signal terminal CKA2 outputs a pulse signal; during the blank phase B of the even-numbered frame period (e.g., 2, 4, 6, etc.), the other of the first clock signal terminal CKA1 and the second clock signal terminal CKA2 outputs a pulse signal.

[0134] For example, every two frame periods (e.g.) Figure 18 As shown, the first clock signal terminal CKA1 and the second clock signal terminal CKA2 switch the output pulse signal once. That is, in the first, third, fifth, ..., N-1th "two-frame cycles", one of the first clock signal terminal CKA1 and the second clock signal terminal CKA2 outputs a pulse signal in the blank phase X2; in the second, fourth, sixth, ..., Nth "two-frame cycles", the other of the first clock signal terminal CKA1 and the second clock signal terminal CKA2 outputs a pulse signal in the blank phase B. Where N is an even number.

[0135] When a row of pixels P is selected for compensation, the light-emitting control transistor T104 turns on one of the adjacent odd-numbered rows of pixels P1 and even-numbered rows of pixels P2. The power supply voltage signal terminal VDD can be transmitted to the first pole of the two driving transistors T101 through the turned-on light-emitting control transistor T104 and the connecting line L0. Depending on the on-state of the two driving transistors T101 (the driving transistor T101 of the selected row of pixels P is turned on under the control of the sensed grayscale data VGm, and the driving transistor T101 of the other row of pixels P is turned off during the sensed data writing stage B1), the anode of the light-emitting device EL of the selected row of pixels P is charged.

[0136] In summary, the light-emitting control circuit 100 provided in the embodiments of this disclosure includes a first detection control unit 111 and a second detection control unit 122. When compensating for the light-emitting device EL of the selected row pixel P, the driving transistor T101 of the selected row pixel P can be electrically connected to the power supply voltage signal terminal VDD through the first detection control unit 111 and the second detection control unit 122. Then, when the driving transistor T101 is turned on, the anode of the light-emitting device EL of the selected row pixel P is charged, thereby achieving compensation for the light-emitting device EL of the selected row pixel P. Here, the selected row pixel P refers to a row of pixels P for which compensation for the light-emitting device EL is performed.

[0137] Some embodiments of this disclosure also provide a control method for a light-emitting control circuit 100, used to drive the light-emitting control circuit 100 in any of the above embodiments. A frame period F includes a display phase D and a blanking phase B. The control method includes:

[0138] When a set of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected for compensation of the light-emitting device EL.

[0139] During blank phase B, the first detection and control unit 111 of the first light-emitting control sub-circuit 110 of the light-emitting control circuit 100 transmits the first voltage signal to the first node N1. Under the control of the voltage of the first node N1, the first output unit 112 of the first light-emitting control sub-circuit 110 transmits the first voltage signal to the first output signal terminal EM1 so that the working current flows through the light-emitting device EL of the odd-numbered row pixel P1 or the even-numbered row pixel P2.

[0140] Alternatively, the second detection and control unit 121 of the second light-emitting control sub-circuit 120 of the light-emitting control circuit 100 transmits the first voltage signal to the second node N2, and the second output unit 122 of the second light-emitting control sub-circuit 120 transmits the first voltage signal to the second output signal terminal EM2 under the control of the voltage of the second node N2, so that the working current flows through the light-emitting device EL of the odd-numbered row pixel P1 or the even-numbered row pixel P2.

[0141] For example, when compensating the light-emitting device EL of the selected row pixel P, the detection control terminal VH outputs a working voltage signal to the light-emitting control circuit 100 that is electrically connected to the selected row pixel P.

[0142] Then, under the control of the detection signal (working voltage signal) from the detection control terminal VH and the first clock signal from the first clock signal terminal CKA1, the first detection control unit 111 transmits the first voltage signal from the first voltage signal terminal VGH to the first node N1.

[0143] Next, under the control of the voltage (first voltage signal) of the first node N1, the first light-emitting output unit 112 transmits the first voltage signal from the first voltage signal terminal VGH to the first output signal terminal EM1.

[0144] Alternatively, for example, the second detection control unit 121, under the control of the detection signal from the detection control terminal VH and the second clock signal from the second clock signal terminal CKA2, transmits the first voltage signal from the first voltage signal terminal VGH to the second node N2.

[0145] Next, under the control of the voltage (first voltage signal) of the second node N2, the second light-emitting output unit 122 transmits the first voltage signal from the first voltage signal terminal VGH to the second output signal terminal EM2.

[0146] That is, when a set of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected for compensation of the light-emitting device EL, one of the first output signal terminal EM1 and the second output signal terminal EM2 of the light-emitting control circuit 100 outputs a first voltage signal to turn on the light-emitting control transistor T104 of the corresponding row pixel P.

[0147] For example, the first output signal terminal EM1 of the light-emitting control circuit 100 outputs a first voltage signal. This first voltage signal is transmitted from the first output signal terminal EM1 along the light-emitting control scan line EM1 to the control electrode of the light-emitting control transistor T104(1) of the odd-numbered row pixel P1. The light-emitting control transistor T104(1) is turned on, and the power supply voltage signal from the power supply voltage signal terminal VDD is transmitted through the light-emitting control transistor T104(1) of the odd-numbered row pixel P1 and the connecting line L0 to the first electrode of the driving transistor T101(1) of the odd-numbered row pixel P1 and the first electrode of the driving transistor T101(2) of the even-numbered row pixel P2. Then, the driving transistor T101 of the selected row pixel P is turned on, and the anode of the light-emitting device 120 of the selected row pixel P is charged, thereby enabling the row pixel P to realize the compensation function of the light-emitting device EL.

[0148] In some embodiments, see Figure 10 The first detection control unit 111 includes a first detection input subunit 1111 and a first detection output subunit 1112.

[0149] The first detection input subunit 1111 is electrically connected to the detection control terminal VH, the first clock signal terminal CKA1, and the third node N3, and is configured to transmit the first clock signal to the third node N3 under the control of the detection control signal.

[0150] The first detection output subunit 1112 is electrically connected to the third node N3, the first voltage signal terminal VGH and the first node N1, and is configured to transmit the first voltage signal to the first node N1 under the control of the voltage (first clock signal) of the third node N3.

[0151] For example, see Figure 12 The first detection input subunit 1111 includes a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the detection control terminal VH, the first electrode is electrically connected to the first clock signal terminal CKA1, and the second electrode is electrically connected to the third node N3.

[0152] For example, see Figure 12 The second detection output subunit 1112 includes a second transistor T2. The control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the first node N1.

[0153] In some embodiments, see Figure 10 The second detection control unit 121 includes a second detection input subunit 1211 and a second detection output subunit 1212.

[0154] The second detection input subunit 1211 is electrically connected to the detection control terminal VH, the second clock signal terminal CKA2, and the fourth node N4, and is configured to transmit the second clock signal to the fourth node N4 under the control of the detection control signal.

[0155] The second detection output subunit 1212 is electrically connected to the fourth node N4, the first voltage signal terminal VGH, and the second node N2, and is configured to transmit the first voltage signal to the second node N2 under the control of the voltage (second clock signal) of the fourth node N4.

[0156] For example, see Figure 12 The second detection input subunit 1211 includes a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the detection control terminal VH, the first electrode is electrically connected to the second clock signal terminal CKA2, and the second electrode is electrically connected to the fourth node N4.

[0157] For example, see Figure 12 The second detection output subunit 1212 includes a fourth transistor T4. The control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the second node N2.

[0158] In some embodiments, see Figure 11 The first detection and control unit 111 further includes a first energy storage subunit 1113. The first energy storage subunit 1113 is electrically connected to the first node N1 and the third node N3 and is configured to maintain the voltage of the third node N3. The first clock signal input to the first clock signal terminal CKA1 of the third node N3 can be a pulse signal. The first energy storage subunit 1113 enables the third node N3 to maintain the voltage value of the first clock signal for a certain period of time, and when the voltage of the first node N1 transitions (increases or decreases), the third node N3 transitions accordingly.

[0159] For example, see Figure 12 The first energy storage sub-unit 1113 includes a first capacitor C1, the first plate of the first capacitor C1 is electrically connected to the third node N3, and the second plate is electrically connected to the first node N1.

[0160] When the pulse width of the first clock signal CKA1 transmitted to the third node N3 is small, and the detection control signal controls the first transistor T1 to turn off, the first energy storage subunit 1113 can make the third transistor T3 continuously input the first voltage signal to the first node N1 for a certain period of time, thereby making the first output signal terminal EM1 output a continuous working voltage signal, which is beneficial to the anode charging of the light-emitting device EL by the power supply voltage signal terminal VDD.

[0161] In some embodiments, see Figure 11 The second detection and control unit 121 further includes a second energy storage subunit 1213, which is electrically connected to the second node N2 and the fourth node N4 and is configured to maintain the voltage of the fourth node N4. The second clock signal input to the second clock signal terminal CKA2 of the fourth node N4 can be a pulse signal. The second energy storage subunit 1213 enables the fourth node N3 to maintain the voltage value of the first clock signal for a certain period of time, and when the voltage of the second node N2 transitions (increases or decreases), the fourth node N4 transitions accordingly.

[0162] For example, see Figure 12 The second energy storage sub-unit 1213 includes a second capacitor C2, the first plate of the second capacitor C2 is electrically connected to the fourth node N4, and the second plate is electrically connected to the second node N2.

[0163] The second energy storage subunit 1213 can achieve the same effect as the first energy storage subunit 1113, and will not be described again here.

[0164] In some embodiments, see Figure 12 The first detection input subunit 1111 includes a first transistor T1; the first detection output subunit 1112 includes a second transistor T2; the first energy storage subunit 1113 includes a first capacitor C1; the second detection input subunit 1211 includes a third transistor T3; the second detection output subunit 1212 includes a fourth transistor T4; and the second energy storage subunit 1213 includes a second capacitor C2.

[0165] In this configuration, the control electrode of the first transistor T1 is electrically connected to the detection control terminal VH, its first terminal is electrically connected to the first clock signal terminal CKA1, and its second terminal is electrically connected to the third node N3. The control electrode of the second transistor T2 is electrically connected to the third node N3, its first terminal is electrically connected to the first voltage signal terminal VGH, and its second terminal is electrically connected to the first node N1. The first plate of the first capacitor C1 is electrically connected to the third node N3, and its second plate is electrically connected to the first node N1. The control electrode of the third transistor T3 is electrically connected to the detection control terminal VH, its first terminal is electrically connected to the second clock signal terminal CKA2, and its second terminal is electrically connected to the fourth node N4. The control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, its first terminal is electrically connected to the first voltage signal terminal VGH, and its second terminal is electrically connected to the second node N2. The first plate of the second capacitor C2 is electrically connected to the fourth node N4, and its second plate is electrically connected to the second node N2.

[0166] In some embodiments, see Figure 13 The first light-emitting output unit 112 may include a first cascaded signal output subunit 1121 and a first light-emitting control signal output subunit 1122.

[0167] The first cascaded signal output subunit 1121 is electrically connected to the first node N1, the first voltage signal terminal VGH and the first cascaded output signal terminal CR1. It is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the first cascaded output signal terminal CR1 under the control of the voltage of the first node N1, and output the first cascaded signal to the first input signal terminal IN1 of the first light-emitting control subcircuit 110 of the next light-emitting control circuit 100.

[0168] For example, see Figure 14A The first cascaded signal output subunit 1121 includes a thirty-fifth transistor T35 and a seventh capacitor C7. The control electrode of the thirty-fifth transistor T35 is electrically connected to the first node N1, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the first cascaded output signal terminal CR1. The first plate of the seventh capacitor C7 is electrically connected to the first node N1, and the second plate is electrically connected to the first cascaded output signal terminal CR1.

[0169] For example, in two cascaded first light-emitting control circuits 110, the first cascaded output signal terminal CR1 of the first light-emitting control circuit 110 of the previous stage is electrically connected to the first input signal terminal IN1 of the first light-emitting control circuit 110 of the next stage.

[0170] The first light emission control signal output subunit 1122 is electrically connected to the first node N1, the first voltage signal terminal VGH and the first output signal terminal EM1. It is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the first output signal terminal EM1 under the control of the voltage of the first node N1, and output the light emission control signal to the first light emission control scan line EM1 of the odd-numbered row pixel P1 to turn on or off the light emission control transistor T104(1) of the odd-numbered row pixel P1.

[0171] See Figure 14A The first light-emitting control signal output subunit 1122 of the first light-emitting output unit 112 includes a seventeenth transistor T17. The control electrode of the seventeenth transistor T17 is electrically connected to the first node N1, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the first output signal terminal EM1.

[0172] See Figure 13 The second light-emitting output unit 122 may include a second cascaded signal output subunit 1221 and a second light-emitting control signal output subunit 1222.

[0173] The second cascaded signal output sub-unit 1221 is electrically connected to the second node N2, the first voltage signal terminal VGH, and the second cascaded output signal terminal CR2. It is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the second cascaded output signal terminal CR2 under the control of the voltage of the second node N2, and output the second cascaded signal to the second light-emitting control sub-circuit 120 of the next light-emitting control circuit 100.

[0174] For example, see Figure 14B The second cascaded signal output subunit 1221 includes a thirty-sixth transistor T36 and an eighth capacitor C8. The control electrode of the thirty-sixth transistor T36 is electrically connected to the second node N2, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the second cascaded output signal terminal CR2. The first plate of the eighth capacitor C8 is electrically connected to the second node N2, and the second plate is electrically connected to the second cascaded output signal terminal CR2.

[0175] For example, in two cascaded second light-emitting control circuits 120, the second cascaded output signal terminal CR2 of the first light-emitting control circuit 120 of the previous stage is electrically connected to the second input signal terminal IN2 of the second light-emitting control circuit 120 of the next stage.

[0176] See Figure 13The second light emission control signal output subunit 1222 is electrically connected to the second node N2, the first voltage signal terminal VGH, and the second output signal terminal EM2. It is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the second output signal terminal EM2 under the control of the voltage of the second node N2, and output the light emission control signal to the second light emission control scan line EM2 of the even-numbered row pixel P2 to turn on or off the light emission control transistor T104 of the even-numbered row pixel.

[0177] For example, see Figure 14B The second light-emitting control signal output subunit 1222 of the second light-emitting output unit 122 includes an eighteenth transistor T18. The control electrode of the eighteenth transistor T18 is electrically connected to the second node N2, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the second output signal terminal EM2.

[0178] In some embodiments, see Figure 15 The first light-emitting control sub-circuit 110 of the light-emitting control circuit 100 further includes a first pulse width modulation unit 113, and the second light-emitting control sub-circuit 120 further includes a second pulse width modulation unit 123.

[0179] The first pulse width modulation unit 113 may include a first input subunit 1131. The first input subunit 1131 of the first pulse width modulation unit 113 is electrically connected to the first input signal terminal IN1, the third clock signal terminal CKB1 and the first node N1, and is configured to transmit the first input signal from the first input signal terminal IN1 to the first node N1 under the control of the third clock signal from the third clock signal terminal CKB1.

[0180] For example, see Figure 14A The first input subunit 1131 may include a fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected to the third clock signal terminal CKB1, the first electrode is electrically connected to the first input signal terminal IN1, and the second electrode is electrically connected to the first node N1.

[0181] The first input signal terminal IN1 can be electrically connected to the first cascaded output signal terminal CR1 in the previous stage light-emitting control circuit 100, and the first input signal is the first cascaded signal output by the previous stage light-emitting control circuit 100. The first input signal terminal IN1 in the first stage light-emitting control circuit 100 can be electrically connected to the first start signal terminal STU1 (e.g., ...). Figure 7 (As shown).

[0182] In some embodiments, see Figure 16A , Figure 16AAn equivalent circuit diagram of the first light-emitting control sub-circuit 110 is provided. The first pulse width modulation unit 113 may also include a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a thirty-seventh transistor T37, and a third capacitor C3.

[0183] In this configuration, the control electrode of the sixth transistor T6 is electrically connected to the first node N1, the first electrode is electrically connected to the second voltage signal terminal LVGL, and the second electrode is electrically connected to the fifth node N5. The sixth transistor T6 is configured to transmit the second voltage signal from the second voltage signal terminal LVGL to the fifth node N5 under the control of the voltage of the first node N1.

[0184] For example, the second voltage signal terminal LVGL can continuously output a shutdown voltage signal.

[0185] The control terminal of the seventh transistor T7 is electrically connected to the fifth node N5, the first terminal is electrically connected to the third voltage signal terminal VGL, and the second terminal is electrically connected to the first output signal terminal EM1. The seventh transistor T7 is configured to transmit the second voltage signal from the third voltage signal terminal VGL to the first output signal terminal EM1 under the control of the voltage of the fifth node N5.

[0186] For example, the third voltage signal terminal VGL can continuously output a shutdown voltage signal.

[0187] It is understood that both the second voltage signal terminal LVGL and the third voltage signal terminal VGL can continuously output a turn-off voltage signal. The voltage levels output by the third voltage signal terminal VGL and the second voltage signal terminal LVGL can be the same, or the voltage of the voltage signal output by the third voltage signal terminal VGL can be higher than the voltage of the voltage signal output by the second voltage signal terminal LVGL. For example, the voltage of the voltage signal output by the third voltage signal terminal VGL is higher than the voltage of the voltage signal output by the second voltage signal terminal LVGL.

[0188] The control terminal of the eighth transistor T8 is electrically connected to the fifth clock signal terminal CKC1, the first terminal is electrically connected to the first voltage signal terminal VGH, and the second terminal is electrically connected to the sixth node N6.

[0189] The control electrode of the ninth transistor T9 is electrically connected to the sixth node N6, the first electrode is electrically connected to the third clock signal terminal CKB1, and the second electrode is electrically connected to the seventh node N7.

[0190] The control electrode of the tenth transistor T10 is electrically connected to the first input signal terminal IN1, the first electrode is electrically connected to the seventh node N7, and the second electrode is electrically connected to the fifth node N7.

[0191] The first plate of the third capacitor C3 is electrically connected to the sixth node N6, and the second plate is electrically connected to the seventh node N7.

[0192] The eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the third capacitor C3 are configured to transmit the first voltage signal to the fifth node N5 under the control of the fifth clock signal from the fifth clock signal terminal CKC1, the third clock signal from the third clock signal terminal CKB1 and the first voltage signal from the first voltage signal terminal VGH.

[0193] The control electrode of the 37th transistor T37 is electrically connected to the fifth node N5, the first electrode is electrically connected to the second voltage signal terminal LVGL, and the second electrode is electrically connected to the first cascaded output signal terminal CR1. It is configured to transmit the second voltage signal from the second voltage signal terminal LVGL to the first cascaded output signal terminal CR1 under the control of the voltage of the fifth node N5.

[0194] The functions and roles of the transistors and the third capacitor C3 in the first pulse width modulation unit 113 will not be described in detail here.

[0195] In some embodiments, see Figure 17A The first pulse width modulation unit 113 may also include the thirty-eighth transistor T38, the thirty-ninth transistor T39, the fortieth transistor T40, the forty-first transistor T41, the forty-second transistor T42, the forty-third transistor T43, and the ninth capacitor C9.

[0196] The control terminal of the 38th transistor T38 is electrically connected to the start-reset control terminal TRS, the first terminal is electrically connected to the first voltage signal terminal VGH, and the second terminal is electrically connected to the first node N1. It is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the first node N1 under the control of the reset signal from the start-reset control terminal TRS.

[0197] Understandably, the start reset control terminal TRS is typically turned on for a few lines before the first frame of power-on to initialize the circuit, and remains constantly low during display.

[0198] The control electrode of the thirty-ninth transistor T39 is electrically connected to the third clock signal segment CKB1, its first terminal is electrically connected to the eighteenth node N18, and its second terminal is electrically connected to the first node N1. The control electrode of the fortieth transistor T40 is electrically connected to the first node N1, its first terminal is electrically connected to the first voltage signal terminal VGH, and its second terminal is electrically connected to the eighteenth node N18.

[0199] It is understandable that, in the case where the first pulse width modulation unit 113 includes the thirty-ninth transistor T39 and the fortieth transistor T40, see [reference]. Figure 17AThe second terminal of the fifth transistor T5 is electrically connected to the eighteenth node N18, and the second terminal of the fifth transistor T5 is electrically connected to the first node N1 through the thirty-ninth transistor T39. The thirty-ninth transistor T39 and the fortieth transistor T40 form the leakage protection circuit of the fifth transistor T5, which is configured to reduce the leakage current of the fifth transistor T5 in the off state.

[0200] The control terminal of the forty-first transistor T41 is electrically connected to the first input signal terminal IN1, the first terminal is electrically connected to the fifth clock signal terminal CKC1, and the second terminal is electrically connected to the nineteenth node N19. The forty-first transistor T41 is configured to transmit the fifth clock signal from the fifth clock signal terminal CKC1 to the nineteenth node N19 under the control of the first input signal from the first input signal terminal IN1.

[0201] The control terminal of the forty-second transistor T42 is electrically connected to the first input signal terminal IN1, the first terminal is electrically connected to the nineteenth node N19, and the second terminal is electrically connected to the seventh node N7. The forty-second transistor T42 is configured to transmit the voltage from the nineteenth node N19 to the seventh node N7 under the control of the first input signal from the first input signal terminal IN1.

[0202] The control electrode of the forty-third transistor T43 is electrically connected to the seventh node N7, the first electrode is electrically connected to the first voltage signal terminal VGH, and the second electrode is electrically connected to the nineteenth node N19. It is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the nineteenth node N19 under the control of the voltage of the seventh node N7.

[0203] The first plate of the ninth capacitor C9 is electrically connected to the second voltage signal terminal LVGL, and the second plate is electrically connected to the fifth node N5.

[0204] It is understood that the first pulse width modulation unit 113 may include only some of the transistors described above, such as the thirty-eighth transistor T38, the thirty-ninth transistor T39, the fortieth transistor T40, the forty-first transistor T41, the forty-second transistor T42, and the forty-third transistor T43. For example, the first pulse width modulation unit 113 may include the thirty-seventh transistor T37, the thirty-eighth transistor T38, and the forty-first transistor T41. Alternatively, the first pulse width modulation unit 113 may also include the thirty-ninth transistor T39 and the fortieth transistor T40. The functions and roles that the thirty-eighth transistor T38, the thirty-ninth transistor T39, the fortieth transistor T40, the forty-first transistor T41, the forty-second transistor T42, and the forty-third transistor T43 can be further described in the embodiments of this disclosure.

[0205] In some embodiments, see Figure 15The second pulse width modulation unit 123 may include a second input subunit 1231. The second input subunit 1231 of the second pulse width modulation unit 123 is electrically connected to the second input signal terminal IN2, the fourth clock signal terminal CKB2 and the second node N2, and is configured to transmit the second input signal from the second input signal terminal IN2 to the second node N2 under the control of the fourth clock signal from the fourth clock signal terminal CKB2.

[0206] For example, see Figure 14B The second input subunit 1231 may include an eleventh transistor T11. The control electrode of the eleventh transistor T11 is electrically connected to the fourth clock signal terminal CKB2, the first electrode is electrically connected to the second input signal terminal IN2, and the second electrode is electrically connected to the second node N2.

[0207] The second input signal terminal IN2 can be electrically connected to the second cascaded output signal terminal CR2 in the previous stage light-emitting control circuit 100. The second input signal is the second cascaded signal output by the previous stage light-emitting control circuit 100. The first input signal terminal IN1 in the first stage light-emitting control circuit 100 can be electrically connected to the second start signal terminal STU2 (e.g., ...). Figure 7 (As shown).

[0208] In some embodiments, see Figure 16B , Figure 16B This is an equivalent circuit diagram of the second light-emitting control sub-circuit 120. The second pulse width modulation unit 123 may also include a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a forty-sixth transistor T46, and a fourth capacitor C4.

[0209] In this configuration, the control electrode of the twelfth transistor T12 is electrically connected to the second node N2, the first electrode is electrically connected to the second voltage signal terminal LVGL, and the second electrode is electrically connected to the eighth node N8. The twelfth transistor T12 is configured to transmit the second voltage signal from the second voltage signal terminal LVGL to the eighth node N8 under the control of the voltage at the second node N2.

[0210] The control terminal of the thirteenth transistor T13 is electrically connected to the eighth node N8, the first terminal is electrically connected to the third voltage signal terminal VGL, and the second terminal is electrically connected to the second output signal terminal EM2. The thirteenth transistor T13 is configured to transmit the third voltage signal from the third voltage signal terminal VGL to the second output signal terminal EM2 under the control of the voltage of the eighth node N8.

[0211] The control terminal of the forty-sixth transistor T46 is electrically connected to the eighth node N8, the first terminal is electrically connected to the second voltage signal terminal LVGL, and the second terminal is electrically connected to the second cascaded output signal terminal CR2. The forty-sixth transistor T46 is configured to transmit the second voltage signal from the second voltage signal terminal LVGL to the second cascaded output signal terminal CR2 under the control of the voltage of the eighth node N8.

[0212] The control terminal of the fourteenth transistor T14 is electrically connected to the sixth clock signal terminal CKC2, the first terminal is electrically connected to the first voltage signal terminal VGH, and the second terminal is electrically connected to the ninth node N9.

[0213] The control electrode of the fifteenth transistor T15 is electrically connected to the ninth node N9, the first electrode is electrically connected to the fourth clock signal terminal CKB2, and the second electrode is electrically connected to the tenth node N10.

[0214] The control electrode of the sixteenth transistor T16 is electrically connected to the second input signal terminal IN2, the first electrode is electrically connected to the tenth node N10, and the second electrode is electrically connected to the eighth node N8.

[0215] The first plate of the fourth capacitor C4 is electrically connected to the ninth node N9, and the second plate is electrically connected to the tenth node N10.

[0216] The fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the fourth capacitor C4 are configured to transmit the first voltage signal to the eighth node N8 under the control of the sixth clock signal from the sixth clock signal terminal CKC2, the fourth clock signal from the fourth clock signal terminal CKB2 and the first voltage signal from the first voltage signal terminal VGH.

[0217] In some embodiments, see Figure 17B The second pulse width modulation unit 123 may also include a forty-fifth transistor T45, a forty-sixth transistor T46, a forty-seventh transistor T47, a forty-eighth transistor T48, a forty-ninth transistor T49, a fiftieth transistor T50, and a tenth capacitor C10.

[0218] The control terminal of transistor T45 is electrically connected to the start-reset control terminal TRS, the first terminal is electrically connected to the first voltage signal terminal VGH, and the second terminal is electrically connected to the second node N2. It is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the second node N2 under the control of the reset signal from the start-reset control terminal TRS.

[0219] The control electrode of transistor T46 is electrically connected to the fourth clock signal terminal CKB2, its first electrode is electrically connected to node N20 (the twentieth node), and its second electrode is electrically connected to node N2 (the second node). The control electrode of transistor T47 is electrically connected to node N2 (the second node), its first electrode is electrically connected to node N20 (the twentieth node), and its second electrode is electrically connected to node N2 (the second node).

[0220] The forty-sixth transistor T46 and the forty-seventh transistor T47 together form the leakage protection circuit of the eleventh transistor T11, which is configured to reduce the leakage current of the eleventh transistor T11 in the off state.

[0221] The control terminal of the forty-eighth transistor T48 is electrically connected to the second input signal terminal IN2, the first terminal is electrically connected to the sixth clock signal terminal CKC2, and the second terminal is electrically connected to the twenty-first node N21. The forty-eighth transistor T48 is configured to transmit the sixth clock signal from the sixth clock signal terminal CKC2 to the twenty-first node N21 under the control of the second input signal from the second input signal terminal IN2.

[0222] The control terminal of the forty-ninth transistor T49 is electrically connected to the second input signal terminal IN2, the first terminal is electrically connected to the twenty-first node N21, and the second terminal is electrically connected to the ninth node N9. The forty-ninth transistor T49 is configured to transmit the voltage of the twenty-first node N21 to the ninth node N9 under the control of the second input signal from the second input signal terminal IN2.

[0223] The control terminal of the fiftieth transistor T50 is electrically connected to the ninth node N9, the first terminal is electrically connected to the first voltage signal terminal VGH, and the second terminal is electrically connected to the twenty-first node N21. The fiftieth transistor T50 is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the twenty-first node N21 under the control of the voltage of the ninth node N9.

[0224] The first plate of the tenth capacitor C10 is electrically connected to the second voltage signal terminal LVGL, and the second plate is electrically connected to the eighth node N8.

[0225] When the light-emitting control circuit 100 includes the first pulse width modulation unit 113 and the second pulse width modulation unit 123 as described in any of the above embodiments, and a group of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected to compensate the light-emitting device EL, within the same frame period F, one of the first light-emitting control sub-circuit 110 and the second light-emitting control sub-circuit 120, which are electrically connected to the corresponding group of odd-numbered row pixels P1 and even-numbered row pixels P, outputs a pulse width modulation signal to modulate the light-emitting time of the odd-numbered row pixels P1 and even-numbered row pixels P2; the other outputs a pulse signal during the blank period B to allow the operating current to flow through the light-emitting device EL of the odd-numbered row pixels P1 or even-numbered row pixels P2 (selected row pixel P).

[0226] In the above-described case, the control method of the light-emitting control circuit 100 further includes:

[0227] During the display phase D, the first pulse width modulation unit 113, under the control of the third clock signal CKB1, transmits the first input signal from the first input signal terminal IN1 to the first node N1. The first light emission output unit 112, under the control of the voltage of the first node N1, transmits the first voltage signal to the first output signal terminal EM1 to modulate the light emission time of the odd-numbered row pixels P1 and the even-numbered row pixels P2.

[0228] When a group of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected for compensation of the light-emitting devices, during the blanking phase B, the second detection control unit 123 transmits a first voltage signal to the second node N2. Under the control of the voltage of the second node N2, the second light-emitting output unit 122 transmits the first voltage signal to the second output signal terminal EM2, so that the operating current flows through the light-emitting devices EL of the odd-numbered row pixels P1 or even-numbered row pixels P2. Here, the operating current flowing through the light-emitting devices EL of the odd-numbered row pixels P1 or even-numbered row pixels P2 means charging the anode of the light-emitting device EL of the selected row of pixels P.

[0229] For example, see Figure 17A and Figure 18 , Figure 18 This is a timing control diagram for the light-emitting control circuit 100. During the first two frame periods F, in the display stage D, the first start signal terminal Stu1 outputs a pulse signal, and the first input signal terminal IN1 of the first light-emitting control sub-circuit 110 receives the pulse signal.

[0230] Under the control of the third clock signal CKB1, the first pulse width modulation unit 113 of the first light emission control sub-circuit 110 turns on the fifth transistor T5 and the thirty-ninth transistor T39, transmitting the first input signal from the first input signal terminal IN1 to the first node N1.

[0231] The first light-emitting output unit 112 (the seventeenth transistor T17) transmits a first voltage signal to the first output signal terminal EM1 under the control of the voltage of the first node N1, so as to modulate the light-emitting time of the odd-numbered row pixel P1 and the even-numbered row pixel P2.

[0232] Furthermore, under the control of the voltage of the first node N1, the thirty-fifth transistor T35 transmits the first voltage signal to the first cascade signal output terminal CR1, and outputs the first cascade signal to the first input signal terminal IN1 of the first light-emitting control sub-circuit 110 of the next light-emitting control circuit 100.

[0233] In blank phase B, see [reference] Figure 17A , Figure 17B and Figure 18 During the blank phase B of the first two frame periods F, when a set of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected for compensation of the light-emitting device EL.

[0234] The detection control terminal VH turns on the first transistor T1 and the third transistor T3. The first clock signal terminal CKA1 continuously outputs a turn-off voltage signal (i.e., no pulse signal is output), and since there is no signal input to the third node N3, the voltage of the third node N3 remains unchanged (at the turn-off voltage). The second clock signal terminal CKA2 outputs a pulse signal, which is written to the fourth node N4 through the third transistor T3, raising the potential of the fourth node N3 to the operating voltage.

[0235] The fourth transistor T4 is turned on under the voltage control of the fourth node N4, and the first voltage signal at the first voltage signal terminal VGH is transmitted to the second node N2. That is, the second detection and control unit 121 transmits the first voltage signal to the second node N2.

[0236] The eighteenth transistor T18 (second light-emitting output unit 122) is turned on under the control of the second node N2, and the first voltage signal of the first voltage signal terminal VGH is transmitted to the second output signal terminal EM2 through the eighteenth transistor T18.

[0237] Alternatively, the control method of the light-emitting control circuit 100 may also include:

[0238] During the display stage D, the second pulse width modulation unit 123 transmits the second input signal to the second node N2 under the control of the fourth clock signal CKB2; the second light emission output unit 122 transmits the first voltage signal to the second output signal terminal EM2 under the control of the voltage of the second node N2, so as to modulate the light emission time of the odd row pixel P1 and the even row pixel P2.

[0239] When a set of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected for compensation of the light-emitting device EL, in blank phase B, the first detection control unit 111 transmits the first voltage signal to the first node N1, and the first light-emitting output unit 112, under the control of the voltage of the first node N1, transmits the first voltage signal to the second output signal terminal EM2, so that the working current flows through the light-emitting device EL of the odd-numbered row pixels P1 or even-numbered row pixels P2.

[0240] For example, see Figure 17B and Figure 18 Within the preceding and following frame periods F, during the display phase D, the second start signal terminal Stu2 outputs a pulse signal, and the second input signal terminal IN2 of the second light-emitting control sub-circuit 110 can receive the pulse signal.

[0241] Under the control of the fourth clock signal CKB2, the eleventh transistor T5 and the forty-sixth transistor T46 of the second pulse width modulation unit 123 of the second light emission control sub-circuit 120 are turned on, transmitting the first input signal from the second input signal terminal IN2 to the second node N2.

[0242] The second light-emitting output unit 122 (the eighteenth transistor T18) transmits the first voltage signal to the second output signal terminal EM2 under the control of the voltage of the second node N2, so as to modulate the light-emitting time of the odd-numbered row pixel P1 and the even-numbered row pixel P2.

[0243] Furthermore, under the control of the voltage of the second node N2, the thirty-sixth transistor T36 transmits the first voltage signal to the second cascaded signal output terminal CR2, and outputs the second cascaded signal to the second input signal terminal IN2 of the second light-emitting control sub-circuit 120 of the next light-emitting control circuit 100.

[0244] In blank phase B, see [reference] Figure 17A , Figure 17B and Figure 18 During the blank phase B of the last two frame periods F, when a set of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected for compensation of the light-emitting device EL.

[0245] The detection control terminal VH turns on the first transistor T1 and the third transistor T3. The first clock signal terminal CKA1 outputs a pulse signal, which is written to the third node N3, raising the potential of the third node N3 to the operating voltage. The second clock signal terminal CKA2 continuously outputs the shutdown voltage, and the potential of the fourth node N3 remains at the shutdown voltage.

[0246] The second transistor T2 is turned on under the voltage control of the third node N3, and the first voltage signal of the first voltage signal terminal VGH is transmitted to the first node N1. That is, the first detection and control unit 111 transmits the first voltage signal to the first node N1.

[0247] The seventeenth transistor T17 (first light-emitting output unit 112) is turned on under the control of the first node N1, and the first voltage signal of the first voltage signal terminal VGH is transmitted to the first output signal terminal EM1 through the seventeenth transistor T17.

[0248] In some embodiments, the control method of the light-emitting control circuit 100 further includes:

[0249] Within the same frame period F, the first clock signal terminal CKA1, the second input signal terminal IN2, and the fourth clock signal terminal CKB2 output pulse signals, while the second clock signal terminal CKA2, the first input signal terminal CR1, and the third clock signal terminal CKB1 do not output voltage signals. For example, as... Figure 18 The last two frame periods F in the middle.

[0250] Alternatively, the control method of the light-emitting control circuit 100 may also include:

[0251] Within the same frame period F, the second clock signal terminal CKA2, the first input signal terminal CR1, and the third clock signal terminal CKB1 output pulse signals, while the first clock signal terminal CKA1, the second input signal terminal IN2, and the fourth clock signal terminal CKB2 do not output voltage signals. For example, as... Figure 18 The first two frame periods F in the middle.

[0252] In some embodiments, see Figure 19A and Figure 19B The random detection circuit (random sense unit) 200 is electrically connected to the random detection signal terminal OE, the third input signal terminal IN3, the seventh clock signal terminal CKD, and the eleventh node N11. It is configured to transmit the seventh clock signal from the seventh clock signal terminal CKD to the eleventh node N11 under the control of the random detection signal from the random detection signal terminal OE and the third input signal from the third input signal terminal IN3, so as to select a row of pixels for compensation of the light-emitting device EL.

[0253] The random detection circuit 200 can generate random detection signals, and then select different rows of pixels in each frame to compensate the light-emitting devices of different rows of pixels P, thereby achieving the purpose of random compensation.

[0254] The shift register circuit 300 is electrically connected to the eleventh node N11 and is configured to output a scan signal to the corresponding row pixel P under the voltage control of the eleventh node N11 to open the corresponding row pixel P.

[0255] In any of the above embodiments, the detection control terminal VH of the light-emitting control circuit 100 is electrically connected to a circuit node in the random detection circuit 200 or a circuit node in the shift register circuit 300. This eliminates the need for an additional signal control terminal to provide a signal to the detection control terminal VH, thereby simplifying the gate drive circuit 1120.

[0256] In some embodiments, see Figure 20 The random detection circuit 200 includes a random detection control sub-circuit 210 and a detection output sub-circuit 220.

[0257] The random detection control sub-circuit 210 is electrically connected to the random detection signal terminal OE, the third input signal terminal IN3, and the twelfth node N12, and is configured to transmit the third input signal from the third input signal terminal IN3 to the twelfth node N12 under the control of the random detection signal from the random detection signal terminal OE.

[0258] The third input signal terminal IN3 can be a cascaded input signal terminal, and the third input signal terminal IN3 is electrically connected to the third or fourth cascaded output signal terminal of the shift register circuit 300 in the upper gate drive circuit 1120.

[0259] See Figure 20 The detection output sub-circuit 220 is electrically connected to the twelfth node N12, the seventh clock signal terminal CKD, and the eleventh node N11, and is configured to transmit the seventh clock signal to the eleventh node N11 under the voltage control of the twelfth node N12. The detection control terminal VH of the light emission control circuit 100 is electrically connected to the twelfth node N12.

[0260] For example, see Figure 21 The random detection control sub-circuit 210 includes a nineteenth transistor T19. The control electrode of the nineteenth transistor T19 is electrically connected to the random detection signal terminal OE, the first electrode is electrically connected to the third input signal terminal IN3, and the second electrode is electrically connected to the twelfth node N12.

[0261] The detection output sub-circuit 220 includes a twentieth transistor T20. The control electrode of the twentieth transistor T20 is electrically connected to the twelfth node N12, the first electrode is electrically connected to the seventh clock signal terminal CKD, and the second electrode is electrically connected to the eleventh node N11.

[0262] In some embodiments, see Figure 22 The random detection circuit 200 also includes a first energy storage sub-circuit 230 and a first leakage prevention electronic circuit 240.

[0263] The first energy storage sub-circuit 230 is electrically connected to the fourth voltage signal terminal VDD and the twelfth node N12, and is configured to maintain the voltage of the twelfth node N12.

[0264] The fourth voltage signal terminal VDD can be the same as the power supply voltage signal terminal VDD in the pixel driving circuit 1110, therefore, they use the same label "VDD". This reduces the number of voltage signal terminals, thereby simplifying the circuit structure of the display panel 1000.

[0265] The first leakage protection electronic circuit 240 is electrically connected to the random detection control sub-circuit 210, the random detection signal terminal OE, the twelfth node N12, and the fourth voltage signal terminal VDD. It is configured to transmit the fourth voltage signal from the fourth voltage signal terminal VDD to the eleventh node N11 under the control of the random detection signal from the random detection signal terminal OE and the voltage of the twelfth node.

[0266] For example, see Figure 23 The first energy storage sub-circuit 230 includes a fifth capacitor C5. The first plate of the fifth capacitor C5 is electrically connected to the fourth voltage signal terminal VDD, and the second plate is electrically connected to the twelfth node N12.

[0267] For example, see Figure 23 The first leakage protection electronic circuit 240 includes a twenty-first transistor T21 and a twenty-second transistor T22. The control electrode of the twenty-first transistor T21 is electrically connected to the random detection signal terminal OE, the first electrode is electrically connected to the thirteenth node N13, and the second electrode is electrically connected to the twelfth node N12. The control electrode of the twenty-second transistor T22 is electrically connected to the twelfth node N12, the first electrode is electrically connected to the fourth voltage signal terminal VDD, and the second electrode is electrically connected to the thirteenth node N13.

[0268] See Figure 23 The random detection control sub-circuit 210 is electrically connected to the twelfth node N12 through the first leakage protection electronic circuit 240. That is, the second terminal of the nineteenth transistor T19 is electrically connected to the twelfth node N12 through the twenty-first transistor T21.

[0269] See Figure 23 The second terminal of the nineteenth transistor T19 is electrically connected to the first terminal of the twenty-first transistor T21, and the control terminals of both the nineteenth transistor T19 and the twenty-first transistor T21 are electrically connected to the random detection signal terminal OE. Thus, when the random detection signal terminal OE outputs the working level, the control terminals of the nineteenth transistor T19 and the twenty-first transistor T21 are simultaneously turned on, and the third input signal from the third input signal terminal IN3 can be transmitted to the twelfth node N12 in sequence through the control terminals of the nineteenth transistor T19 and the twenty-first transistor T21.

[0270] Some embodiments of this disclosure also provide a control method for the above-described gate drive circuit 1120. The control method includes:

[0271] When a set of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected for compensation of the light-emitting device EL.

[0272] During the display phase D, the random detection circuit 200 of the gate drive circuit 1120, under the control of the random detection signal (from the random detection signal terminal OE), transmits the third input signal from the third input signal terminal IN3 to the circuit node NX (twelfth node N12) in the random detection circuit 200, and maintains the voltage of the corresponding circuit node NX until the blank phase B.

[0273] During blank phase B, the random detection circuit 200, under the control of the voltage of circuit node NX, transmits the seventh clock signal from the seventh clock signal terminal CKD to the shift register circuit 300 of the gate drive circuit 1120.

[0274] The shift register circuit outputs a scan signal to the corresponding row pixel P (the row pixel P selected for EL compensation of the light-emitting device) to turn on the corresponding row pixel P (turn on the data writing transistor T102 of the corresponding row pixel P).

[0275] Under the control of the voltage of circuit node NX in random detection circuit 200 or the voltage of circuit node NY (fourteenth node N14 or fifteenth node N15) in shift register circuit 300, the light emission control circuit 1000 of gate drive circuit 1120 transmits the first voltage signal to the first output signal terminal EM1 or the second output signal terminal EM2, so that the working current flows through the light emission device of odd row pixel P1 or even row pixel P2.

[0276] For example, during blank phase B, both circuit node NX of the random detection circuit 200 and circuit node NY of the shift register circuit 300 can output operating voltages to the detection control terminal VH of the light emission control circuit 100. Under the control of the detection control signal from the detection control terminal VH, the light emission control circuit 100 transmits the first voltage signal to the first output signal terminal EM1 or the second output signal terminal EM2. Refer to the control method of the light emission control circuit 100 described above; it will not be repeated here.

[0277] In some embodiments, see Figure 24AThe shift register circuit 300 includes a first shift register sub-circuit 310 and a second shift register sub-circuit 320. The first shift register sub-circuit 310 includes a first compensation input unit 311 and a first scan output unit 312. The second shift register sub-circuit 320 includes a second compensation input unit 321 and a second scan output unit 322.

[0278] The first compensation input unit 311 is electrically connected to the eleventh node N11, the seventh clock signal terminal CKD, and the fourteenth node N14, and is configured to transmit the voltage of the eleventh node N11 to the fourteenth node N14 under the control of the seventh clock signal from the seventh clock signal terminal CKD.

[0279] The first scan output unit 312 is electrically connected to the fourteenth node N14, the eighth clock signal terminal CKE1, and the third output signal terminal GL1. The third output signal terminal GL1 is configured to be electrically connected to the odd-numbered row pixel P1 (electrically connected to the control electrode of the data writing transistor T102(1) of the odd-numbered row pixel P1). The first scan output unit 312 is configured to transmit the eighth clock signal from the eighth clock signal terminal CKE1 to the third output signal terminal GL1 under the control of the voltage of the fourteenth node N14, so as to turn on the corresponding odd-numbered row pixel P1 (turn on the data writing transistor T102(1)).

[0280] It is understood that in the embodiments of this disclosure, the third output signal terminal GL1 is electrically connected to the first gate line GL1, and for the sake of simplicity, both are referred to by the same reference numeral "GL1". The fourth output signal terminal GL2 is electrically connected to the second gate line GL2, and for the sake of simplicity, both are referred to by the same reference numeral "GL2".

[0281] The second compensation input unit 321 is electrically connected to the eleventh node N11, the seventh clock signal terminal CKD, and the fifteenth node N15, and is configured to transmit the voltage of the eleventh node N11 to the fifteenth node N15 under the control of the seventh clock signal CKD.

[0282] The second scan output unit 322 is electrically connected to the fifteenth node N15, the ninth clock signal terminal CKE2, and the fourth output signal terminal GL2. The fourth output signal terminal GL2 is configured to be electrically connected to the even-numbered row pixel P2 (electrically connected to the control electrode of the data writing transistor T102(2) of the even-numbered row pixel P2). The second scan output unit 322 is configured to transmit the ninth clock signal from the ninth clock signal terminal CKE2 to the fourth output signal terminal GL2 under the control of the voltage of the fifteenth node N15, so as to turn on the corresponding even-numbered row pixel P2 (turn on the data writing transistor T102(2)).

[0283] For example, see Figure 24BThe first compensation input unit 311 includes a twenty-third transistor T23. The control terminal of the twenty-third transistor T23 is connected to the seventh clock signal terminal CKD, the first terminal is electrically connected to the eleventh node, and the second terminal is electrically connected to the fourteenth node N14.

[0284] The first scan output unit 312 includes a twenty-fourth transistor T24. The control electrode of the twenty-fourth transistor T24 is electrically connected to the fourteenth node N14, the first electrode is electrically connected to the eighth clock signal terminal CKE1, and the second electrode is electrically connected to the third output signal terminal GL1.

[0285] The second compensation input unit 321 includes a twenty-fifth transistor T25. The control terminal of the twenty-fifth transistor T25 is electrically connected to the seventh clock signal terminal CKD, the first terminal is electrically connected to the eleventh node N11, and the second terminal is electrically connected to the fifteenth node N15.

[0286] The second scan output unit 322 includes a twenty-sixth transistor T26. The control electrode of the twenty-sixth transistor T26 is electrically connected to the fifteenth node N15, the first electrode is electrically connected to the ninth clock signal terminal CKE2, and the second electrode is electrically connected to the fourth output signal terminal GL2.

[0287] In some embodiments, the detection control terminal VH of the light emission control circuit 100 in any of the above embodiments is electrically connected to the fourteenth node N14 or the fifteenth node N15.

[0288] In some embodiments, see Figure 25A The first shift register sub-circuit 310 also includes a first scan input unit 313, a first inverter 314, and a first reset unit 315.

[0289] The first scan input unit 313 is electrically connected to the third input signal terminal IN3, the fourth voltage signal terminal VDD, and the fourteenth node N14, and is configured to transmit the fourth voltage signal from the fourth voltage signal terminal VDD to the fourteenth node N14 under the control of the third input signal from the third input signal terminal IN3.

[0290] One end of the first inverter 314 is electrically connected to the fourteenth node N14, and the other end is electrically connected to the sixteenth node N16.

[0291] It is understood that the structure of the first inverter 314 and the second inverter 324, as well as their functions and roles, are conventional technologies in the field and will not be described in detail here.

[0292] The first reset unit is electrically connected to the first reset signal terminal Std1, the sixteenth node N16, the fifth voltage signal terminal LVGL, the fourteenth node N14, and the third output signal terminal GL1. It is configured to transmit the fifth voltage signal of the fifth voltage signal terminal LVGL to the fourteenth node N14 and the third output signal terminal GL1 under the control of the first reset signal from the first reset signal terminal Std1 and the voltage of the sixteenth node N16.

[0293] It is understood that both the fifth voltage signal LVGL and the second voltage signal terminal LVGL can continuously output low-level voltage signals. They can be the same or different. In the embodiments of this disclosure, the fifth voltage signal terminal LVGL and the second voltage signal terminal LVGL are the same as an example for illustrative purposes.

[0294] For example, see Figure 26A The first scan input unit 313 includes a twenty-seventh transistor T27. The control electrode of the twenty-seventh transistor T27 is electrically connected to the third input signal terminal IN3, the first electrode is electrically connected to the fourth voltage signal terminal VDD, and the second electrode is electrically connected to the fourteenth node N14.

[0295] The first reset unit 315 may include a twenty-eighth transistor T28, a twenty-ninth transistor T29, and a thirtieth transistor T30.

[0296] The control terminal of the 28th transistor T28 is electrically connected to the first reset signal terminal Std1, the first terminal is electrically connected to the fifth voltage signal terminal LVGL, and the second terminal is electrically connected to the fourteenth node N14.

[0297] The control electrode of the 29th transistor T29 is electrically connected to the 16th node N16, the first electrode is electrically connected to the fifth voltage signal terminal LVGL, and the second electrode is electrically connected to the third output signal terminal GL1.

[0298] The control terminal of the 30th transistor T30 is electrically connected to the 16th node N16, the first terminal is electrically connected to the fifth voltage signal terminal LVGL, and the second terminal is electrically connected to the 14th node N14.

[0299] In some embodiments, see Figure 26A The first shift register sub-circuit may also include the fifty-first transistor T51, the fifty-second transistor T52, the fifty-third transistor T53, the fifty-fourth transistor T54, and the eleventh capacitor C11.

[0300] The control terminal of the 51st transistor T51 is electrically connected to the first reset signal terminal Std1, the first terminal is electrically connected to the 22nd node N22 (the second terminal of the 28th transistor T28), and the second terminal is electrically connected to the 14th node. The second terminal of the 28th transistor T28 is electrically connected to the 14th node N14 through the 50th transistor T51.

[0301] The control terminal of the 52nd transistor T52 is electrically connected to the 16th node N16, the first terminal is electrically connected to the 22nd node N22 (the second terminal of the 30th transistor T30), and the second terminal is electrically connected to the 14th node N14. Specifically, the second terminal of the 30th transistor T30 is electrically connected to the 14th node N14 via the 52nd transistor T52.

[0302] The control terminal of the 53rd transistor T53 is electrically connected to the 7th clock signal terminal CKD, the first terminal is electrically connected to the 22nd node N22, and the second terminal is electrically connected to the 14th node N14. The second terminal of the 23rd transistor T23 is electrically connected to the 14th node N14 through the 53rd transistor T53.

[0303] The control electrode of the 54th transistor T54 is electrically connected to the 14th node N14, the first electrode is electrically connected to the fourth voltage signal terminal VDD, and the second electrode is electrically connected to the 22nd node N22.

[0304] In some embodiments, see Figure 25B The second shift register sub-circuit 320 also includes a second scan input unit 323, a second inverter 324, and a second reset unit 325.

[0305] The second scan input unit 323 is electrically connected to the third input signal terminal IN3, the fourth voltage signal terminal VDD, and the fifteenth node N15, and is configured to transmit the third voltage signal to the fifteenth node N15 under the control of the third input signal.

[0306] One end of the second inverter 324 is electrically connected to the fifteenth node N15, and the other end is electrically connected to the seventeenth node N17.

[0307] The second reset unit 325 is electrically connected to the second reset signal terminal Std2, the fifth voltage signal terminal LVGL, the fifteenth node N16, the seventeenth node N17, and the fourth output signal terminal GL2. It is configured to transmit the fifth voltage signal from the fifth voltage signal terminal LVGL to the fifteenth node N15 and the fourth output signal terminal GL2 under the control of the second reset signal from the second reset signal terminal Std2 and the voltage of the seventeenth node N17.

[0308] For example, see Figure 26BThe second scan input unit 323 includes a thirty-first transistor T31. The control electrode of the thirty-first transistor T31 is electrically connected to the third input signal terminal IN3, the first electrode is electrically connected to the fourth voltage signal terminal VDD, and the second electrode is electrically connected to the fifteenth node N15.

[0309] The second reset unit 325 includes the thirty-second transistor T32, the thirty-third transistor T33, and the thirty-fourth transistor T34.

[0310] The control terminal of the 32nd transistor T32 is electrically connected to the second reset signal terminal Std2, the first terminal is electrically connected to the fifth voltage signal terminal LVGL, and the second terminal is electrically connected to the 15th node N15.

[0311] The control terminal of the 33rd transistor T33 is electrically connected to the 17th node N17, the first terminal is electrically connected to the fifth voltage signal terminal VLGL, and the second terminal is electrically connected to the fourth output signal terminal GL2.

[0312] The control terminal of the 34th transistor T34 is electrically connected to the 17th node N17, the first terminal is electrically connected to the fourth voltage signal terminal LVGL, and the second terminal is electrically connected to the 15th node N15.

[0313] In some embodiments, the second shift register sub-circuit 320 further includes a fifty-fifth transistor T55, a fifty-sixth transistor T56, a fifty-seventh transistor T57, and a fifty-eighth transistor T58.

[0314] The control terminal of the 55th transistor T55 is electrically connected to the second reset signal terminal Std2, the first terminal is electrically connected to the 23rd node N23 (the second terminal of the 32nd transistor T32), and the second terminal is electrically connected to the 15th node N15. The second terminal of the 32nd transistor T32 is electrically connected to the 15th transistor through the 55th transistor T55.

[0315] The control terminal of the fifty-sixth transistor T56 is electrically connected to the seventeenth node N17, its first terminal is electrically connected to the twenty-third node N23 (the second terminal of the thirty-fourth transistor T34), and its second terminal is electrically connected to the fifteenth node N15. The second terminal of the thirty-fourth transistor T34 is electrically connected to the fifteenth node N15 through the fifty-sixth transistor T56.

[0316] The control terminal of the 57th transistor T57 is electrically connected to the 7th clock signal terminal CKD. Its first terminal is electrically connected to the 23rd node N23 (the second terminal of the 25th transistor T25), and its second terminal is electrically connected to the 15th node N15. The second terminal of the 25th transistor T25 is electrically connected to the 15th node N15 through the 57th transistor T57.

[0317] The control terminal of transistor T58 is electrically connected to node 15, the first terminal is electrically connected to the fourth voltage signal terminal VDD, and the second terminal is electrically connected to node N23.

[0318] Some embodiments of this disclosure also provide a control method for a gate driving circuit, used to drive the gate driving circuit 1120 in any of the above embodiments. When a group of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected for compensation of the light-emitting device EL, the control method includes:

[0319] During the display phase D, the random detection circuit 200 of the gate drive circuit 1120, under the control of the random detection signal (from the random detection signal terminal OE), transmits the third input signal from the third input signal terminal IN3 to the circuit node NX (twelfth node N12) in the random detection circuit 200, and maintains the voltage of the corresponding circuit node NX until the blank phase B.

[0320] For example, see Figure 26A and Figure 27 During a certain period of display stage D, the random detection signal terminal OE and the third input signal terminal IN3 output high-level signals. The nineteenth transistor T19 and the twenty-first transistor T21 are turned on under the control of the random detection signal from the random detection signal terminal OE. The third input signal (high-level signal) from the third input signal terminal IN3 is transmitted to the twelfth node N12 in the random detection circuit 200. The twentieth transistor T20 is turned on.

[0321] Then, the random detection signal terminal OE and the third input signal terminal IN3 output a low-level signal, the twenty-first transistor T21 is turned off, and the voltage of the twelfth node N12 remains unchanged under the action of the fifth capacitor C5.

[0322] During blank phase B, the random detection circuit 200, under the control of the voltage of circuit node NX (twelfth node), transmits the seventh clock signal from the seventh clock signal terminal CKD to the shift register circuit 300 of the gate drive circuit 1120.

[0323] For example, see Figure 26A and Figure 27 At node 12, the voltage remains constant under the action of capacitor C5, and transistor T20 remains on. During a certain period of blank phase B, the seventh clock signal terminal CKD outputs a high-level seventh clock signal, which is transmitted to node 11 N11 through transistor T20.

[0324] The shift register circuit outputs a scan signal to the corresponding row pixel P (the row pixel P selected for EL compensation of the light-emitting device) to turn on the corresponding row pixel P (turn on the data writing transistor T102 of the corresponding row pixel P).

[0325] For example, see Figure 26A Under the influence of the seventh clock signal at the seventh clock signal terminal CKD, the twenty-third transistor T23 and the fifty-third transistor T53 are simultaneously turned on, and the seventh clock signal at the eleventh node N11 is transmitted to the fourteenth node N14. Under the control of the voltage (seventh clock signal) at the fourteenth node N14, the twenty-fourth transistor T24 is turned on.

[0326] Similarly, see Figure 26B The seventh clock signal at node eleven (N11) can also be transmitted to node fifteen (N15). The voltage at node fifteen (N15) controls the activation of transistor twenty-six (T26).

[0327] One of the seventh clock signal terminal CKE1 and the eighth clock signal terminal CKE2 outputs a high-level voltage signal and transmits it to the third output signal terminal GL1 or the fourth output signal terminal GL2.

[0328] For example, when odd-numbered row pixels P1 are selected for EL compensation of light-emitting devices, the seventh clock signal terminal CKE1 outputs a high-level voltage signal. The high-level voltage signal output by the seventh clock signal terminal CKE1 is transmitted to the third output signal terminal GL1 through the twenty-fourth transistor T24, and a scan signal is output to the odd-numbered row pixels P1. The data writing transistor T102(1) of the odd-numbered row pixels P1 is turned on.

[0329] For example, when even-numbered row pixels P2 are selected for EL compensation of light-emitting devices, the eighth clock signal terminal CKE2 outputs a high-level voltage signal. The high-level voltage signal output by the eighth clock signal terminal CKE2 is transmitted to the fourth output signal terminal GL2 through the twenty-sixth transistor T26, and a scan signal is output to even-numbered row pixels P2. The data writing transistor T102(2) of even-numbered row pixels P2 is turned on.

[0330] Under the control of the voltage of circuit node NX in random detection circuit 200 or the voltage of circuit node NY (fourteenth node N14 or fifteenth node N15) in shift register circuit 300, the light emission control circuit 1000 of gate drive circuit 1120 transmits the first voltage signal to the first output signal terminal EM1 or the second output signal terminal EM2, so that the working current flows through the light emission device EL of odd row pixel P1 or even row pixel P2.

[0331] It is understandable that when the operating current flows through the light-emitting device EL of the odd-numbered row pixel P1 or the even-numbered row pixel P2, it means that the anode of the light-emitting device EL of the selected row pixel P is charged.

[0332] During blank phase B, circuit node NX of random detection circuit 200 and circuit node NY of shift register circuit 300 can both output working voltage signals to the detection control terminal VH of light emission control circuit 100. Under the control of the detection control signal from detection control terminal VH, light emission control circuit 100 transmits the first voltage signal to the first output signal terminal EM1 or the second output signal terminal EM2.

[0333] For example, the detection control terminal VH of the light emission control circuit 100 is electrically connected to the twelfth node in the random detection circuit 200. See also Figure 27 During blank phase B, the twelfth node N12 outputs a high-level voltage signal, which can control the light-emitting control circuit 100 to transmit the first voltage signal to the first output signal terminal EM1 or the second output signal terminal EM2, so as to turn on the odd-numbered row pixel P1 (light-emitting control transistor T104(1)) or the even-numbered row pixel P2 (light-emitting control transistor T104(1)). The working process of the light-emitting control circuit 100 is described above and will not be repeated here.

[0334] For example, the detection control terminal VH of the light-emitting control circuit 100 is electrically connected to the fourteenth or fifteenth node N14 in the shift register circuit 300. See also... Figure 27 During blank phase B, both the fourteenth node N14 and the fifteenth node N152 can output high-level voltage signals, and the first voltage signal of the light-emitting control circuit 100 is transmitted to the first output signal terminal EM1 or the second output signal terminal EM2. The working process of the light-emitting control circuit 100 will not be described in detail here.

[0335] The first output signal terminal EM1 of the light-emitting control circuit 110 of the gate driving circuit 1120 is electrically connected to the odd-numbered row pixel P1, and the second output signal terminal EM2 of the light-emitting control circuit 100 is electrically connected to the even-numbered row pixel P2.

[0336] In some embodiments, see Figure 15 and Figure 25A The shift register circuit 300 includes a first shift register sub-circuit 310 and a second shift register sub-circuit 320. The first shift register sub-circuit 310 includes a first scan input unit 313 and a first scan output unit 312, and the second shift register sub-circuit 320 includes a second scan input unit 323 and a second scan output unit 322. The first light emission control sub-circuit 110 of the light emission control circuit 100 includes a first pulse width modulation unit 113, and the second light emission control sub-circuit 120 includes a second pulse width modulation unit 123.

[0337] During the display phase D, the first scan input unit 313, under the control of the third input signal IN3, inputs the fourth voltage signal to the fourteenth node N14; the first scan output unit 312, under the control of the voltage of the fourteenth node N14, transmits the eighth clock signal to the third output signal terminal GL1 to open the corresponding odd-numbered row pixels.

[0338] For example, see Figure 26A and Figure 27 During display phase D, when a high-level voltage signal is output at the third input signal terminal IN3, the twenty-seventh transistor T27 turns on, and the fourth voltage signal at the fourth voltage signal terminal VDD is transmitted to the fourteenth node N14. The fourth voltage signal can be a high-level voltage signal. Under the control of the fourth voltage signal at the fourteenth node N14, the twenty-fourth transistor T24 turns on, and the eighth clock signal from the eighth clock signal terminal CKE1 is transmitted to the third output signal terminal GL1.

[0339] Under the control of the third input signal IN3, the second scan input unit 323 inputs the fourth voltage signal to the fifteenth node N15; under the control of the voltage of the fifteenth node N15, the second scan output unit 322 transmits the ninth clock signal to the fourth output signal terminal GL2 to open the corresponding even-numbered row pixels.

[0340] For example, see Figure 26B and Figure 27 During the display phase D, when a high-level voltage signal is output at the third input signal terminal IN3, the thirty-first transistor T31 turns on, and the fourth voltage signal at the fourth voltage signal terminal VDD is transmitted to the fifteenth node N15. Under the control of the fourth voltage signal at the fourteenth node N14, the twenty-sixth transistor T26 turns on, and the ninth clock signal from the ninth clock signal terminal CKE2 is transmitted to the third output signal terminal GL1.

[0341] For example, the eighth clock signal terminal CKE1 and the ninth clock signal terminal CKE2 can output high-level voltage signals at different times, so that the third output signal terminal GL1 and the fourth output signal terminal GL2 can output scanning signals at different times, thereby marking the data writing transistor T102 of different rows of pixels P at different times.

[0342] Under the control of the third clock signal CKB1, the first pulse width modulation unit 113 transmits the first input signal to the first node; or, under the control of the fourth clock signal CKB2, the second pulse width modulation unit 123 transmits the second input signal to the second node N2, to modulate the emission time of odd-numbered and even-numbered rows of pixels. That is, within the same frame period, one of the first pulse width modulation unit 113 and the second pulse width modulation unit 123 outputs a pulse width modulation signal; in different frame periods, the first pulse width modulation unit 113 and the second pulse width modulation unit 123 alternately output pulse width modulation signals. The control process of the first pulse width modulation unit 113 and the second pulse width modulation unit 123 can be referred to above and will not be repeated here.

[0343] Some embodiments of this disclosure also provide a method for controlling a display panel, used to control the display panel 1000 in the above embodiments. The display panel 1000 includes a gate driving circuit 1120, a data driving circuit 1200, and a pixel driving circuit 1110.

[0344] In some embodiments, see Figure 28 The blank phase B includes a first data writing phase B11, a second data writing phase B12, and a sensing phase B13.

[0345] When a group of adjacent odd-numbered row pixels P1 or even-numbered row pixels P2 are selected for compensation of the light-emitting device, wherein, Figure 28 The following example demonstrates how to supplement the light-emitting device (EL) by selecting even-numbered row pixels P2. The control methods for the display panel 100 include:

[0346] In the first data writing stage B11, the data driving circuit 1200 writes zero-grayscale data V0 to one of the odd-numbered row pixels P1 and even-numbered row pixels P2 that was not selected for external compensation. This prevents the driving transistor T101 of the row of pixels P that was not selected for external compensation from turning on. When one of the light-emitting control transistors T104 turns on, the anode of the light-emitting device EL of the unselected row of pixels P is not charged, ensuring that only one row of pixels P is selected for light-emitting device EL compensation in each frame.

[0347] For example, see Figure 28 When even-numbered row pixels P2 are selected for compensation of the light-emitting device EL, during the first data writing stage B11, the first gate line GL1(1) and the second gate line GL2(1) electrically connected to odd-numbered row pixels P1 output working voltage signals, and the data line DL outputs zero grayscale data V0. In this way, the control electrode of the driving transistor T101(1) of the odd-numbered row pixels P1 turns off the voltage signal, and the driving transistor T10 of the odd-numbered row pixels P1 is in the off state during the subsequent compensation process.

[0348] In the second data writing stage B12, the data driving circuit 1200 writes the sensed grayscale data VGm to one of the odd-row pixels P1 and even-row pixels P2 selected for compensation of the light-emitting device.

[0349] For example, see Figure 28 In the second data writing stage B12, the first gate line GL1(2) and the second gate line GL2(2) electrically connected to the even-numbered row pixel P2 output working voltage signals, and the data line DL outputs the sensed grayscale data VGm. In this way, the control voltage of the driving transistor T101(2) of the even-numbered row pixel P2 is the working voltage, and the driving transistor T101(2) of the even-numbered row pixel P1 can be turned on in the subsequent compensation process.

[0350] During the sensing phase B13, the first light-emitting control sub-circuit 110 or the second light-emitting control sub-circuit 120 outputs a first voltage signal (operating voltage) to allow the operating current to flow through the light-emitting devices EL of the odd-numbered row pixels and the even-numbered row pixels; the pixel circuits of the odd-numbered row pixels or the even-numbered row pixels detect the voltage of the light-emitting devices.

[0351] For example, the first light-emitting control sub-circuit 110 outputs a first voltage signal to the first light-emitting control signal line EM1. Operating current can flow through the drive control transistor T101 of the selected row pixel P (the row of pixels P selected for EL compensation), thereby causing the operating current to flow through the EL of the selected row pixel P, charging the anode of the corresponding EL. The sensing signal line SL of the pixel driving circuit 1110 senses the voltage at the anode of the corresponding EL.

[0352] In some embodiments, see Figure 28 The blank phase B, following the sensing phase B13, also includes a first data write-back phase B14 and a second data write-back phase B15.

[0353] In the first data write-back stage B14, the pixel in a group of adjacent odd-numbered rows P1 and even-numbered rows P2 that was not selected for compensation of the light-emitting device EL is written with first initial grayscale data DATA1. The first initial grayscale data DATA1 is the grayscale data of the corresponding row pixel P written before the first data write stage B11. In this way, the unselected row pixel P can be displayed with the required grayscale in the next display stage D.

[0354] For example, see Figure 28 In the first data write-back stage B14, the first gate line GL1(1) and the second gate line GL2(1) electrically connected to the odd row pixel P1 output working voltage signals, and the data line DL outputs the first initial grayscale data DATA1.

[0355] In the second data write-back stage B15, the pixel selected for compensation of the light-emitting device EL from either odd-numbered row pixels P1 or even-numbered row pixels P2 is written with second initial grayscale data DATA2. This second initial grayscale data DATA2 is the grayscale data of the corresponding row of pixels written before the second data write stage B12. This ensures that the selected row of pixels P displays the required grayscale in the next display stage D.

[0356] For example, see Figure 28 In the second data write-back stage B15, the first gate line GL1(2) and the second gate line GL2(2) electrically connected to the even-numbered row pixels P2 output working voltage signals, and the data line DL outputs the second initial grayscale data DATA2.

[0357] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A light emission control circuit, characterized by comprising: include: The first light-emitting control sub-circuit includes a first detection and control unit and a first light-emitting output unit; wherein... The first detection control unit is electrically connected to the detection control terminal, the first clock signal terminal, the first voltage signal terminal, and the first node, and is configured to transmit the first voltage signal from the first voltage signal terminal to the first node under the control of the detection control signal from the detection control terminal and the first clock signal from the first clock signal terminal; The first light-emitting output unit is electrically connected to the first node, the first voltage signal terminal, and the first output signal terminal, and is configured to transmit the first voltage signal to the first output signal terminal under the control of the voltage of the first node; The second light-emitting control sub-circuit includes a second detection and control unit and a second light-emitting output unit; wherein... The second detection control unit is electrically connected to the detection control terminal, the second clock signal terminal, the first voltage signal terminal, and the second node, and is configured to transmit the first voltage signal to the second node under the control of the detection control signal and the second clock signal from the second clock signal terminal; The second light-emitting output unit is electrically connected to the second node, the first voltage signal terminal, and the second output signal terminal, and is configured to transmit the first voltage signal to the second output signal terminal under the voltage control of the second node.

2. The light-emitting control circuit according to claim 1, characterized in that, The first detection control unit includes: The first detection input subunit is electrically connected to the detection control terminal, the first clock signal terminal and the third node, and is configured to transmit the first clock signal to the third node under the control of the detection control signal. The first detection output subunit is electrically connected to the third node, the first voltage signal terminal and the first node, and is configured to transmit the first voltage signal to the first node under the voltage control of the third node. The second detection control unit includes: The second detection input subunit is electrically connected to the detection control terminal, the second clock signal terminal and the fourth node, and is configured to transmit the second clock signal to the fourth node under the control of the detection control signal. The second detection output subunit is electrically connected to the fourth node, the first voltage signal terminal, and the second node, and is configured to transmit the first voltage signal to the second node under the voltage control of the fourth node.

3. The light-emitting control circuit according to claim 2, characterized in that, The first detection and control unit further includes a first energy storage subunit; the first energy storage subunit is electrically connected to the first node and the third node, and is configured to maintain the voltage of the third node; The second detection and control unit further includes a second energy storage subunit; the second energy storage subunit is electrically connected to the second node and the fourth node and is configured to maintain the voltage of the fourth node.

4. The light-emitting control circuit according to claim 3, characterized in that, The first detection input subunit includes a first transistor, the control electrode of the first transistor is electrically connected to the detection control terminal, the first electrode is electrically connected to the second clock signal terminal, and the second electrode is electrically connected to the third node; The first detection output subunit includes a second transistor, the control electrode of the second transistor is electrically connected to the third node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the first node; The first energy storage subunit includes a first capacitor, the first plate of the first capacitor being electrically connected to the third node, and the second plate being electrically connected to the first node; The second detection input subunit includes a third transistor, the control electrode of the third transistor is electrically connected to the detection control terminal, the first electrode is electrically connected to the fourth clock signal terminal, and the second electrode is electrically connected to the fourth node; The second detection output subunit includes a fourth transistor, the control electrode of the fourth transistor is electrically connected to the fourth node, the first electrode is electrically connected to the first voltage signal terminal, and the second electrode is electrically connected to the second node; The second energy storage subunit includes a second capacitor, the first plate of which is electrically connected to the fourth node, and the second plate of which is electrically connected to the second node.

5. The light-emitting control circuit according to any one of claims 1 to 4, characterized in that, The first light emission control sub-circuit also includes: The first pulse width modulation unit is electrically connected to the first input signal terminal, the third clock signal terminal and the first node, and is configured to transmit the first input signal from the first input signal terminal to the first node under the control of the third clock signal from the third clock signal terminal. The second light-emitting control sub-circuit also includes: The second pulse width modulation unit is electrically connected to the second input signal terminal, the fourth clock signal terminal, and the second node, and is configured to transmit the second input signal from the second input signal terminal to the second node under the control of the fourth clock signal from the fourth clock signal terminal.

6. The light-emitting control circuit according to claim 5, characterized in that, The first pulse width modulation unit includes: The fifth transistor has its control electrode electrically connected to the third clock signal terminal, its first electrode electrically connected to the first input signal terminal, and its second electrode electrically connected to the first node. The sixth transistor has its control electrode electrically connected to the first node, its first electrode electrically connected to the second voltage signal terminal, and its second electrode electrically connected to the fifth node. The seventh transistor has its control electrode electrically connected to the fifth node, its first electrode electrically connected to the third voltage signal terminal, and its second electrode electrically connected to the first output signal terminal. The eighth transistor has its control electrode electrically connected to the fifth clock signal terminal, its first electrode electrically connected to the first voltage signal terminal, and its second electrode electrically connected to the sixth node. The ninth transistor has its control electrode electrically connected to the sixth node, its first electrode electrically connected to the third clock signal terminal, and its second electrode electrically connected to the seventh node. The tenth transistor has its control electrode electrically connected to the first input signal terminal, its first electrode electrically connected to the seventh node, and its second electrode electrically connected to the fifth node. The third capacitor has its first plate electrically connected to the sixth node and its second plate electrically connected to the seventh node. The second pulse width modulation unit includes: The eleventh transistor has its control electrode electrically connected to the fourth clock signal terminal, its first electrode electrically connected to the second input signal terminal, and its second electrode electrically connected to the second node. The twelfth transistor has its control electrode electrically connected to the second node, its first electrode electrically connected to the second voltage signal terminal, and its second electrode electrically connected to the eighth node. The thirteenth transistor has its control electrode electrically connected to the eighth node, its first electrode electrically connected to the third voltage signal terminal, and its second electrode electrically connected to the second output signal terminal. The fourteenth transistor has its control electrode electrically connected to the sixth clock signal terminal, its first electrode electrically connected to the first voltage signal terminal, and its second electrode electrically connected to the ninth node. The fifteenth transistor has its control electrode electrically connected to the ninth node, its first electrode electrically connected to the fourth clock signal terminal, and its second electrode electrically connected to the tenth node. The sixteenth transistor has its control electrode electrically connected to the second input signal terminal, its first electrode electrically connected to the tenth node, and its second electrode electrically connected to the eighth node. The fourth capacitor has its first plate electrically connected to the ninth node and its second plate electrically connected to the tenth node. The first light-emitting output unit includes: The seventeenth transistor has its control electrode electrically connected to the first node, its first electrode electrically connected to the first voltage signal terminal, and its second electrode electrically connected to the first output signal terminal. The second light-emitting output unit includes: The eighteenth transistor has its control electrode electrically connected to the second node, its first electrode electrically connected to the first voltage signal terminal, and its second electrode electrically connected to the second output signal terminal.

7. A gate drive circuit characterized by comprising: include: A random detection circuit, electrically connected to a random detection signal terminal, a third input signal terminal, a seventh clock signal terminal, and an eleventh node, is configured to transmit a seventh clock signal from the seventh clock signal terminal to the eleventh node under the control of a random detection signal from the random detection signal terminal and a third input signal from the third input signal terminal, so as to select a row of pixels for compensation of the light-emitting device. The shift register circuit, electrically connected to the eleventh node, is configured to output a scan signal to the corresponding row pixel under the voltage control of the eleventh node, so as to open the corresponding row pixel; The light emission control circuit according to any one of claims 1 to 6, wherein the detection control terminal of the light emission control circuit is electrically connected to a circuit node in the random detection circuit or a circuit node in the shift register circuit.

8. The gate drive circuit according to claim 7, characterized by The random detection circuit includes: The random detection control sub-circuit, electrically connected to the random detection signal terminal, the third input signal terminal, and the twelfth node, is configured to transmit the third input signal to the twelfth node under the control of the random detection signal. The detection output sub-circuit is electrically connected to the twelfth node, the seventh clock signal terminal, and the eleventh node, and is configured to transmit the seventh clock signal to the eleventh node under the voltage control of the twelfth node. The detection control terminal is electrically connected to the twelfth node.

9. The gate drive circuit according to claim 8, characterized in that The random detection circuit also includes: The first energy storage sub-circuit, electrically connected to the fourth voltage signal terminal and the twelfth node, is configured to maintain the voltage of the twelfth node; The first leakage prevention electronic circuit is electrically connected to the random detection control sub-circuit, the random detection signal terminal, the twelfth node, and the fourth voltage signal terminal, and is configured to transmit the fourth voltage signal to the eleventh node under the control of the random detection signal and the voltage of the twelfth node. The random detection control sub-circuit is electrically connected to the twelfth node through the first leakage prevention electronic circuit.

10. The gate driving circuit according to claim 9, characterized in that, The random detection control sub-circuit includes a nineteenth transistor, the control electrode of the nineteenth transistor is electrically connected to the random detection signal terminal, the first electrode is electrically connected to the third input signal terminal, and the second electrode is electrically connected to the thirteenth node; The detection output sub-circuit includes a twentieth transistor, the control electrode of which is electrically connected to the twelfth node, the first electrode of which is electrically connected to the seventh clock signal terminal, and the second electrode of which is electrically connected to the eleventh node. The first energy storage sub-circuit includes a fifth capacitor, the first plate of which is electrically connected to the fourth voltage signal terminal, and the second plate is electrically connected to the twelfth node; The first leakage protection electronic circuit includes a twenty-first transistor and a twenty-second transistor. The control electrode of the twenty-first transistor is electrically connected to the random detection signal terminal, the first electrode is electrically connected to the thirteenth node, and the second electrode is electrically connected to the twelfth node. The control electrode of the twenty-second transistor is electrically connected to the twelfth node, the first electrode is electrically connected to the fourth voltage signal terminal, and the second electrode is electrically connected to the thirteenth node.

11. The gate driving circuit according to claim 7, characterized in that, The shift register circuit includes: The first shift register sub-circuit includes a first compensation input unit and a first scan output unit; wherein... The first compensation input unit is electrically connected to the eleventh node, the seventh clock signal terminal and the fourteenth node, and is configured to transmit the voltage of the eleventh node to the fourteenth node under the control of the seventh clock signal; The first scan output unit is electrically connected to the fourteenth node, the eighth clock signal terminal, and the third output signal terminal. The third output signal terminal is configured to be electrically connected to the odd-numbered row pixels. The first scan output unit is configured to transmit the eighth clock signal from the eighth clock signal terminal to the third output signal terminal under the control of the voltage of the fourteenth node, so as to open the corresponding odd-numbered row pixels. The second shift register sub-circuit includes a second compensation input unit and a second scan output unit; wherein... The second compensation input unit is electrically connected to the eleventh node, the seventh clock signal terminal and the fifteenth node, and is configured to transmit the voltage of the eleventh node to the fifteenth node under the control of the seventh clock signal; The second scan output unit is electrically connected to the fifteenth node, the ninth clock signal terminal, and the fourth output signal terminal. The fourth output signal terminal is configured to be electrically connected to the even-numbered row pixels. The second scan output unit is configured to transmit the ninth clock signal from the ninth clock signal terminal to the fourth output signal terminal under the control of the voltage of the fifteenth node, so as to open the corresponding even-numbered row pixels. The detection control terminal is electrically connected to the fourteenth node or the fifteenth node.

12. The gate driving circuit according to claim 11, characterized in that, The first compensation input unit includes a twenty-third transistor, the control electrode of the twenty-third transistor is electrically connected to the seventh clock signal terminal, the first electrode is electrically connected to the eleventh node, and the second electrode is electrically connected to the fourteenth node; The first scan output unit includes a twenty-fourth transistor, the control electrode of the twenty-fourth transistor is electrically connected to the fourteenth node, the first terminal is electrically connected to the eighth clock signal terminal, and the second terminal is electrically connected to the third output signal terminal; The second compensation input unit includes a twenty-fifth transistor, the control electrode of the twenty-fifth transistor is electrically connected to the seventh clock signal terminal, the first electrode is electrically connected to the eleventh node, and the second electrode is electrically connected to the fifteenth node; The second scan output unit includes a twenty-sixth transistor. The control electrode of the twenty-sixth transistor is electrically connected to the fifteenth node, the first electrode is electrically connected to the ninth clock signal terminal, and the second electrode is electrically connected to the fourth output signal terminal.

13. The gate driving circuit according to claim 11 or 12, characterized in that, The first shift register sub-circuit further includes a first scan input unit, a first inverter, and a first reset unit; wherein, The first scanning input unit is electrically connected to the third input signal terminal, the fourth voltage signal terminal and the fourteenth node, and is configured to transmit the fourth voltage signal to the fourteenth node under the control of the third input signal; One end of the first inverter is electrically connected to the fourteenth node, and the other end is electrically connected to the sixteenth node; The first reset unit is electrically connected to the first reset signal terminal, the sixteenth node, the fifth voltage signal terminal, the fourteenth node, and the third output signal terminal, and is configured to transmit the fifth voltage signal from the fifth voltage signal terminal to the fourteenth node and the third output signal terminal under the control of the first reset signal from the first reset signal terminal and the voltage of the sixteenth node. The second shift register sub-circuit also includes a second scan input unit, a second inverter, and a second reset unit; The second scanning input unit is electrically connected to the third input signal terminal, the fourth voltage signal terminal, and the fifteenth node, and is configured to transmit the third voltage signal to the fifteenth node under the control of the third input signal; One end of the second inverter is electrically connected to the fifteenth node, and the other end is electrically connected to the seventeenth node; The second reset unit is electrically connected to the second reset signal terminal, the fifth voltage signal terminal, the fifteenth node, the seventeenth node, and the fourth output signal terminal, and is configured to transmit the fifth voltage signal to the fifteenth node and the fourth output signal terminal under the control of the second reset signal from the second reset signal terminal and the voltage of the seventeenth node.

14. The gate driving circuit according to claim 13, characterized in that, The first scan input unit includes a twenty-seventh transistor, the control electrode of the twenty-seventh transistor is electrically connected to the third input signal terminal, the first electrode is electrically connected to the fourth voltage signal terminal, and the second electrode is electrically connected to the fourteenth node; The first reset unit includes a twenty-eighth transistor, a twenty-ninth transistor, and a thirtieth transistor. The control electrode of the twenty-eighth transistor is electrically connected to the first reset signal terminal, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the fourteenth node. The control electrode of the twenty-ninth transistor is electrically connected to the sixteenth node, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the third output signal terminal. The control electrode of the thirtieth transistor is electrically connected to the sixteenth node, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the fourteenth node. The second scan input unit includes a thirty-first transistor, the control electrode of which is electrically connected to the third input signal terminal, the first electrode of which is electrically connected to the fourth voltage signal terminal, and the second electrode of which is electrically connected to the fourteenth node; The second reset unit includes a 32nd transistor, a 33rd transistor, and a 34th transistor. The control electrode of the 32nd transistor is electrically connected to the second reset signal terminal, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the 15th node. The control electrode of the 33rd transistor is electrically connected to the 17th node, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the fourth output signal terminal. The control electrode of the 34th transistor is electrically connected to the 17th node, the first electrode is electrically connected to the fifth voltage signal terminal, and the second electrode is electrically connected to the 15th node.

15. A control method for a light-emitting control circuit, characterized in that, For driving the light-emitting control circuit as described in any one of claims 1 to 6, wherein the first output signal terminal of the light-emitting control circuit is electrically connected to the odd-numbered row pixels, and the second output signal terminal of the light-emitting control circuit is electrically connected to the even-numbered row pixels; A frame cycle includes a display phase and a blank phase; When a group of adjacent odd-numbered or even-numbered rows of pixels are selected for compensation of the light-emitting devices, during the blanking phase, the first detection control unit of the first light-emitting control sub-circuit of the light-emitting control circuit transmits a first voltage signal to the first node, and the first output unit of the first light-emitting control sub-circuit transmits the first voltage signal to the first output signal terminal under the control of the voltage of the first node, so that the working current flows through the light-emitting devices of the odd-numbered or even-numbered rows of pixels. or, The second detection and control unit of the second light-emitting control sub-circuit of the light-emitting control circuit transmits the first voltage signal to the second node. Under the control of the voltage of the second node, the second output unit of the second light-emitting control sub-circuit transmits the first voltage signal to the second output signal terminal so that the working current flows through the light-emitting device of the odd-numbered row pixels or the even-numbered row pixels.

16. The control method according to claim 15, characterized in that, The first light emission control sub-circuit includes a first pulse width modulation unit, and the second light emission control sub-circuit includes a second pulse width modulation unit; During the display phase, the first pulse width modulation unit transmits the first input signal to the first node under the control of the third clock signal; Under the control of the voltage of the first node, the first light-emitting output unit transmits the first voltage signal to the first output signal terminal to modulate the light-emitting time of the odd-numbered row pixels and the even-numbered row pixels; When a group of adjacent odd-numbered or even-numbered rows of pixels are selected for compensation of the light-emitting devices, during the blanking phase, the second detection control unit transmits the first voltage signal to the second node, and the second light-emitting output unit, under the control of the voltage of the second node, transmits the first voltage signal to the second output signal terminal, so that the operating current flows through the light-emitting devices of the odd-numbered or even-numbered rows of pixels. or, During the display phase, the second pulse width modulation unit transmits the second input signal to the second node under the control of the fourth clock signal; Under the control of the voltage of the second node, the second light-emitting output unit transmits the first voltage signal to the second output signal terminal to modulate the light-emitting time of the odd-numbered row pixels and the even-numbered row pixels; When a set of adjacent odd-numbered or even-numbered rows of pixels are selected for compensation of the light-emitting devices, during the blanking phase, the first detection control unit transmits the first voltage signal to the first node, and the first light-emitting output unit, under the control of the voltage of the first node, transmits the first voltage signal to the second output signal terminal, so that the operating current flows through the light-emitting devices of the odd-numbered or even-numbered rows of pixels.

17. The control method according to claim 16, characterized in that, During the same frame period, the first clock signal terminal, the second input signal terminal, and the fourth clock signal terminal output pulse signals, while the second clock signal terminal, the first input signal terminal, and the third clock signal terminal do not output voltage signals. or, During the same frame period, the second clock signal terminal, the first input signal terminal, and the third clock signal terminal output pulse signals, while the first clock signal terminal, the second input signal terminal, and the fourth clock signal terminal do not output voltage signals.

18. A control method for a gate driving circuit, characterized in that, The device is configured to drive a gate driving circuit as described in any one of claims 7 to 14; the first output signal terminal of the light emission control circuit of the gate driving circuit is electrically connected to the odd-numbered row pixels, and the second output signal terminal of the light emission control circuit is electrically connected to the even-numbered row pixels. A frame cycle includes a display phase and a blank phase; When a group of adjacent odd-numbered or even-numbered rows of pixels are selected for compensation of the light-emitting device, During the display phase, the random detection circuit of the gate drive circuit transmits the third input signal to the circuit node in the random detection circuit under the control of the random detection signal, and maintains the voltage of the corresponding circuit node until the blank phase. During the blanking phase, the random detection circuit, under the control of the voltage of the corresponding circuit node, transmits the seventh clock signal to the shift register circuit of the gate drive circuit; the shift register circuit outputs a scan signal to the corresponding row pixel to open the corresponding row pixel; The light-emitting control circuit of the gate driving circuit transmits a first voltage signal to a first output signal terminal or a second output signal terminal under the control of the voltage of the circuit node in the random detection circuit or the voltage of the circuit node in the shift register circuit, so that the operating current flows through the light-emitting device of the odd-numbered row pixels or the even-numbered row pixels.

19. The control method according to claim 18, characterized in that, The shift register circuit includes a first shift register sub-circuit and a second shift register sub-circuit. The first shift register sub-circuit includes a first scan input unit and a first scan output unit, and the second shift register sub-circuit includes a second scan input unit and a second scan output unit. The first light emission control sub-circuit of the light emission control circuit includes a first pulse width modulation unit, and the second light emission control sub-circuit includes a second pulse width modulation unit. During the display phase, Under the control of the third input signal, the first scanning input unit inputs a fourth voltage signal to the fourteenth node; under the control of the voltage of the fourteenth node, the first scanning output unit transmits an eighth clock signal to the third output signal terminal to open the corresponding odd-numbered row pixels. Under the control of the third input signal, the second scanning input unit inputs the fourth voltage signal to the fifteenth node; under the control of the voltage of the fifteenth node, the second scanning output unit transmits the ninth clock signal to the fourth output signal terminal to open the corresponding even-numbered row pixels. Under the control of the third clock signal, the first pulse width modulation unit transmits the first input signal to the first node, or under the control of the fourth clock signal, the second pulse width modulation unit transmits the second input signal to the second node, so as to modulate the emission time of the odd-numbered row pixels and the even-numbered row pixels.

20. A method for controlling a display panel, characterized in that, The display panel includes a gate driving circuit, a data driving circuit, odd-numbered rows of pixels, and even-numbered rows of pixels as described in any one of claims 7 to 14; the first light-emitting control sub-circuit of the gate driving circuit is electrically connected to the odd-numbered rows of pixels, and the second light-emitting control sub-circuit is electrically connected to the even-numbered rows of pixels; A frame cycle includes a display phase and a blank phase, wherein the blank phase includes a first data writing phase, a second data writing phase, and a sensing phase; When a group of adjacent odd-numbered or even-numbered rows of pixels are selected for compensation of the light-emitting device, During the first data writing stage, the data driving circuit writes zero grayscale data to the one of the odd-numbered row pixels and the even-numbered row pixels that was not selected for external compensation. In the second data writing stage, the data driving circuit writes sensing grayscale data to one of the odd-numbered row pixels and the even-numbered row pixels selected for compensation of the light-emitting device. During the sensing phase, the first light-emitting control sub-circuit or the second light-emitting control sub-circuit outputs a first voltage signal to allow operating current to flow through the light-emitting devices of the odd-numbered rows of pixels and the even-numbered rows of pixels; the pixel circuit of the odd-numbered rows of pixels or the even-numbered rows of pixels detects the voltage of the light-emitting devices.

21. The control method according to claim 20, characterized in that, The blanking phase also includes a first data write-back phase and a second data write-back phase; During the first data write-back phase, the pixel in the odd-numbered row and the pixel in the even-numbered row that was not selected for compensation of the light-emitting device are written with first initial grayscale data; the first initial grayscale data is the grayscale data of the corresponding row of pixels written before the first data write phase; During the second data write-back phase, the pixel selected for compensation of the light-emitting device from the odd-numbered row pixels and the even-numbered row pixels is written with second initial grayscale data; the second initial grayscale data is the grayscale data of the corresponding row pixels written before the second data write phase.

22. A display device, characterized in that, Includes the gate drive circuit as described in any one of claims 7 to 14.

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