Vertical cavity surface emitting laser chip structure and forming method thereof

Abstract

The invention discloses a vertical cavity surface emitting laser chip structure and a forming method thereof. The vertical cavity surface emitting laser chip structure is provided with a point measurement area and a light emitting area. The spot measurement area and the light-emitting area are divided by a first groove. The vertical cavity surface emitting laser chip structure comprises a substrate, an epitaxial layer, a cover layer, a first electrode and a second electrode. The epitaxial layer is formed on the upper surface of the substrate. The cap layer is formed on the epitaxial layer. The first electrode is formed on the cap layer and a bottom and two sidewalls of the first trench. The second electrode is formed on the lower surface of the substrate. The spot measurement area is provided with a plurality of second grooves, and the second grooves divide the spot measurement area into a plurality of sub-areas. The epitaxial layer in the light-emitting region is provided with a first wet oxygen layer which is provided with an aperture. The epitaxial layer of each sub-region in the spot measurement region is provided with a second wet oxygen layer which stretches across the corresponding sub-region.

Description

Technical Field

[0001] The invention relates to a vertical cavity surface emitting laser chip structure, in particular to a vertical cavity surface emitting laser chip structure used for rapid testing. Background Art

[0002] In recent years, vertical cavity surface emitting laser (VCSEL) components have been widely used as light sources in electronic consumer products.

[0003] In order to prevent sidewall leakage and limit the current path to prevent the current from entering the active layer from the point measurement area, the complete vertical cavity surface emitting laser chip process will add an insulating layer to the structure, such as Figure 1 shown. Figure 1 It is a cross-sectional view of an existing vertical cavity surface emitting laser chip structure 1. The vertical cavity surface emitting laser chip structure 1 includes a substrate 11, an epitaxial layer 12 (which includes an N-type epitaxial layer 12N, a multiple quantum well layer 12M and a P-type epitaxial layer 12P), a cap layer 13, an insulating layer 14, a first electrode 15 and a second electrode 16. The epitaxial layer 12 also includes a wet oxygen layer 121. The point measurement area R1 (left side of the dotted line) and the light emitting area R2 (right side of the dotted line) are divided by a groove 102. Since the insulating layer 14 needs to be formed, the complete vertical cavity surface emitting laser chip process usually takes many days, and it is difficult to complete the newly developed epitaxial verification in a short time to provide subsequent development improvement and optimization.

[0004] In view of this, how to shorten the number of days for VCSEL chip manufacturing process and achieve rapid testing of VCSEL chips is an issue that the industry needs to solve urgently. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a vertical cavity surface emitting laser chip structure for rapid testing and a method for forming the same.

[0006] The purpose of the present invention is to provide a vertical cavity surface emitting laser chip structure for rapid testing. By omitting the process of the insulating layer and adding a groove design in the spot measurement area, a wet oxygen layer with a target aperture is formed in the light emitting area, and a complete wet oxygen layer can be formed in the spot measurement area to prevent the current in the spot measurement area from entering the active layer and affecting the electrical properties. Therefore, compared with the complete vertical cavity surface emitting laser chip process, the vertical cavity surface emitting laser chip process of the present invention can be shortened by several days, and the newly developed epitaxial verification can be completed in the shortest time, providing subsequent development improvement and optimization.

[0007] To achieve the above-mentioned purpose, the present invention discloses a vertical cavity surface emitting laser chip structure for rapid testing. The vertical cavity surface emitting laser chip structure has a point measurement area and a light-emitting area. The point measurement area and the light-emitting area are divided by a first groove. The vertical cavity surface emitting laser chip structure includes a substrate, an epitaxial layer, a cap layer, a first electrode and a second electrode. The epitaxial layer is formed on an upper surface of the substrate. The cap layer is formed on the epitaxial layer. The first electrode is formed on the cap layer and on a bottom and two side walls of the first groove. The second electrode is formed on a lower surface of the substrate. The point measurement area has a plurality of second grooves, and the second grooves divide the point measurement area into a plurality of sub-areas. The epitaxial layer in the light-emitting area has a first wet oxygen layer having an aperture. The epitaxial layer of each of the sub-areas in the point measurement area has a second wet oxygen layer that spans the corresponding sub-area.

[0008] In one embodiment, the substrate is a gallium arsenide (GaAs) substrate.

[0009] In one embodiment, the epitaxial layer includes: an N-type epitaxial layer formed on the upper surface of the substrate; a multi-quantum well layer formed on the N-type epitaxial layer; and a P-type epitaxial layer formed on the multi-quantum well layer. The first wet oxygen layer is formed in the P-type epitaxial layer of the light-emitting area, and each of the second wet oxygen layers is formed in the P-type epitaxial layer of the corresponding sub-area of ​​the spot measurement area. The first wet oxygen layer and each of the second wet oxygen layers are formed simultaneously in a wet oxidation process.

[0010] In one embodiment, the epitaxial layer is grown by using Group III-V semiconductor material or Group II-VI semiconductor material by an organic metal chemical vapor deposition method or a molecular beam epitaxy method.

[0011] In one embodiment, the first trench and the second trench are formed simultaneously in a wet etching process or a dry etching process.

[0012] In addition, the present invention also discloses a method for forming a vertical cavity surface emitting laser chip structure for rapid testing. The method includes: providing a substrate; forming an epitaxial layer on an upper surface of the substrate; forming a cap layer on the epitaxial layer; forming a first groove to divide the vertical cavity surface emitting laser chip structure into a point measurement area and a light emitting area, and forming a plurality of second grooves to divide the point measurement area into a plurality of sub-areas; forming a first wet oxygen layer in the epitaxial layer of the light emitting area, and forming a second wet oxygen layer in the epitaxial layer of each of the sub-areas of the point measurement area, wherein the first wet oxygen layer has an aperture, and the second wet oxygen layer of each of the sub-areas spans the corresponding sub-area; forming a first electrode on the cap layer and on a bottom and two side walls of the first groove; and forming a second electrode on a lower surface of the substrate.

[0013] In one embodiment, the substrate is a gallium arsenide (GaAs) substrate.

[0014] In one embodiment, forming the epitaxial layer includes: forming an N-type epitaxial layer on the upper surface of the substrate; forming a multi-quantum well layer on the N-type epitaxial layer; and forming a P-type epitaxial layer on the multi-quantum well layer. The first wet oxygen layer is formed in the P-type epitaxial layer of the light-emitting area, and each of the second wet oxygen layers is formed in the P-type epitaxial layer of the corresponding sub-area of ​​the spot measurement area. The first wet oxygen layer and each of the second wet oxygen layers are formed simultaneously in a wet oxidation process.

[0015] In one embodiment, the epitaxial layer is grown by using Group III-V semiconductor material or Group II-VI semiconductor material by an organic metal chemical vapor deposition method or a molecular beam epitaxy method.

[0016] In one embodiment, the first trench and the second trench are formed simultaneously in a wet etching process or a dry etching process.

[0017] After referring to the accompanying drawings and the embodiments described below, a person skilled in the art will be able to understand other objects, technical means and embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a cross-sectional schematic diagram of the existing vertical cavity surface emitting laser chip structure;

[0019] Figure 2 A cross-sectional schematic diagram of a vertical cavity surface emitting laser chip structure according to an embodiment of the present invention;

[0020] Figure 3 To form Figure 2 A flowchart of a method for vertical cavity surface emitting laser chip structure; and

[0021] Figure 4A to Figure 4G To correspond to Figure 3 Schematic diagram of the structure of the flowchart.

[0022] Description of Reference Numerals

[0023] 1: Vertical Cavity Surface Emitting Laser Chip Structure

[0024] 11: Substrate

[0025] 12: Epitaxial layer

[0026] 12N: N-type epitaxial layer

[0027] 12M: Multiple quantum well layers

[0028] 12P: P-type epitaxial layer

[0029] 13: Covering layer

[0030] 14: Insulation layer

[0031] 15: First electrode

[0032] 16: Second electrode

[0033] 102: Groove

[0034] 121: Wet oxygen layer

[0035] 2: Vertical Cavity Surface Emitting Laser Chip Structure

[0036] 21: Substrate

[0037] 22: Epitaxial layer

[0038] 22A: Aperture

[0039] 22N: N-type epitaxial layer

[0040] 22M: Multiple quantum well layers

[0041] 22P: P-type epitaxial layer

[0042] 23: Covering layer

[0043] 24: First electrode

[0044] 25: Second electrode

[0045] 202: First Groove

[0046] 204: Second groove

[0047] 221: First wet oxygen layer

[0048] 222: Second wet oxygen layer

[0049] R1: Point measurement area

[0050] R2: Luminous area

[0051] SR1: Sub-region

[0052] S301~S313: steps. DETAILED DESCRIPTION

[0053] The present invention will be explained below by way of examples, and the examples of the present invention are not intended to limit the present invention to any specific environment, application or special method as described in the examples. Therefore, the description of the examples is only for the purpose of explaining the present invention, and is not intended to limit the present invention. It should be noted that in the following examples and drawings, elements that are not directly related to the present invention have been omitted and are not shown, and the dimensional relationship between the elements in the drawings is only for easy understanding, and is not intended to limit the actual proportion.

[0054] Figure 2 The vertical cavity surface emitting laser chip structure 2 for rapid testing of the present invention is shown. The vertical cavity surface emitting laser chip structure 2 has a point measurement area R1 and a light emitting area R2. The point measurement area R1 and the light emitting area R2 are divided by a first groove 202. The vertical cavity surface emitting laser chip structure 2 includes a substrate 21, an epitaxial layer 22, a cap layer 23, a first electrode 24 and a second electrode 25.

[0055] The substrate 21 may be a gallium arsenide (GaAs) substrate, but is not limited thereto. The epitaxial layer 22 is formed on an upper surface of the substrate 21. The epitaxial layer 22 may be grown by a metal-organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method using a III-V semiconductor material or a II-VI semiconductor material. For example, the epitaxial layer 22 may be formed by alternating stacks of gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs) and aluminum arsenide (AlAs). The band gap of the epitaxial layer 22 may be between 1.3 and 2.5 eV.

[0056] The epitaxial layer 22 may include an N-type epitaxial layer 22N, a multi-quantum well layer 22M, and a P-type epitaxial layer 22P. The N-type epitaxial layer 22N is formed on the upper surface of the substrate 21. The multi-quantum well layer 22M is formed on the N-type epitaxial layer 22N. The P-type epitaxial layer 22P is formed on the multi-quantum well layer 22M.

[0057] The cap layer 23 is formed on the epitaxial layer 22. The first electrode 24 is formed on the cap layer 23 and on a bottom and two side walls of a first trench 202. The second electrode 25 is formed on a lower surface of the substrate 21. The first electrode 24 is a P-electrode (P-pad), and the second electrode 25 is an N-electrode (N-pad). The first electrode 24 and the second electrode 25 are made of metal materials, such as gold (Au), titanium (Ti) or platinum (Pt).

[0058] The spot region R1 has a plurality of second trenches 204. The second trenches 204 divide the spot region R1 into a plurality of sub-regions SR1. The first trench 202 and the second trenches 204 are simultaneously formed in a wet etching process or a dry etching process, that is, formed in the same etching process through a specific mask pattern.

[0059] The epitaxial layer 22 in the light emitting region R2 has a first wet oxide layer 221 having an aperture 22A. The epitaxial layer 22 in each sub-region SR1 in the spot measuring region R1 has a second wet oxide layer 222 that spans the corresponding sub-region SR1. Figure 2As shown, during the process, the present invention forms a first wet oxide layer 221 with an aperture 22A in the light emitting region R2, and also forms a complete second wet oxide layer 222 in the sub-regions SR1 of the spot measurement region R1 to serve as an insulating layer to block the current, so as to prevent the spot measurement region R1 from generating a current that enters the active layer (i.e., the multi-quantum well layer 22M) and affects the electrical properties. Therefore, compared with the complete vertical cavity surface emitting laser chip process, the vertical cavity surface emitting laser chip process of the present invention can omit the formation of an insulating layer, so the number of days for the vertical cavity surface emitting laser chip process can be shortened, and the newly developed epitaxial verification can be completed in the shortest time, providing subsequent development improvement and optimization.

[0060] Further, if Figure 1 As shown, the first wet oxide layer 221 is formed in the P-type epitaxial layer 22P of the light emitting region R2. Each second wet oxide layer 222 is formed in the P-type epitaxial layer 22P of the corresponding sub-region SR1 of the spot measurement region R1. The first wet oxide layer 221 and each second wet oxide layer 222 are formed simultaneously in a wet oxidation process.

[0061] The second embodiment of the present invention, please also refer to Figure 3 and Figure 4A to Figure 4G . Figure 3 A flow chart of a method for forming a VCSEL chip structure 2 for rapid testing. Figure 4A to Figure 4G To correspond to Figure 3 Schematic diagram of the structure of the flowchart.

[0062] First, in step S301, a substrate 21 (such as Figure 4A Then, in step S303, an epitaxial layer 22 is formed on the upper surface of the substrate 21 (as shown in FIG. Figure 4B In step S305, a cap layer 23 is formed on the epitaxial layer 22 (as shown in FIG. Figure 4C shown).

[0063] Then, in step S307, a first groove 202 is formed to divide the VCSEL chip structure 2 into a spot measurement region R1 and a light emitting region R2, and a plurality of second grooves 204 are formed to divide the spot measurement region R1 into a plurality of sub-regions SR1 (such as Figure 4D shown).

[0064] Next, in step S309, a first wet oxide layer 221 is formed in the epitaxial layer 22 of the light emitting region R2, and a second wet oxide layer 222 (eg, Figure 4E shown).

[0065] In step S311, a first electrode 24 is formed on the cap layer 23 and the bottom and two side walls of the first trench 202 (eg, Figure 4FThen, in step S313, a second electrode 25 is formed on the lower surface of the substrate 21 (as shown in FIG. Figure 4G shown).

[0066] Further, in step S303, forming the epitaxial layer 22 includes: forming an N-type epitaxial layer 22N on the upper surface of the substrate 21; forming a multi-quantum well layer 22M on the N-type epitaxial layer 22N; and forming a P-type epitaxial layer 22P on the multi-quantum well layer 22M. In addition, in step S309, a first wet oxide layer 221 is formed in the P-type epitaxial layer 22P of the light emitting region R2, and each second wet oxide layer 222 is formed in the P-type epitaxial layer 22P of the corresponding sub-region SR1 of the spot measurement region R1.

[0067] It should be noted that Figure 3 The order of the steps in the flowchart shown is for illustration only and is not intended to limit the present invention. Figure 3 The disclosure understands any possible changes in the order of these steps, and can also form Figure 2 Vertical cavity surface emitting laser chip structure.

[0068] In summary, the present invention provides a VCSEL chip structure for rapid testing, by omitting the insulating layer process. Therefore, compared with the complete VCSEL chip process, the VCSEL chip process of the present invention can be shortened by several days, and the newly developed epitaxial verification can be completed in the shortest time, providing subsequent development improvement and optimization.

[0069] The above embodiments are only used to illustrate the implementation methods of the present invention and to explain the technical features of the present invention, and are not used to limit the protection scope of the present invention. Any changes or equivalent arrangements that can be easily completed by a person skilled in the art belong to the scope claimed by the present invention, and the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A vertical cavity surface emitting laser chip structure, comprising a point measuring area and a light emitting area, wherein the point measuring area and the light emitting area are divided by a first groove, the vertical cavity surface emitting laser chip structure comprising: a substrate; an epitaxial layer formed on an upper surface of the substrate; a capping layer formed on the epitaxial layer; a first electrode formed on the cap layer and on a bottom and two sidewalls of the first trench; and a second electrode formed on a lower surface of the substrate; in, The point measurement area has a plurality of second grooves, and the second grooves divide the point measurement area into a plurality of sub-areas; The epitaxial layer in the light-emitting region has a first wet oxygen layer having an aperture; The epitaxial layer of each of the sub-regions in the spot measurement area has a second wet oxygen layer which spans across the corresponding sub-region.

2. The vertical cavity surface emitting laser chip structure according to claim 1, wherein: The substrate is a gallium arsenide substrate.

3. The vertical cavity surface emitting laser chip structure according to claim 1, wherein: The epitaxial layer comprises: An N-type epitaxial layer formed on the upper surface of the substrate; a multi-quantum well layer formed on the N-type epitaxial layer; as well as a P-type epitaxial layer formed on the multi-quantum well layer; The first wet oxygen layer is formed in the P-type epitaxial layer of the light-emitting area, and each of the second wet oxygen layers is formed in the P-type epitaxial layer of the corresponding sub-area of ​​the spot measurement area; The first wet oxygen layer and each of the second wet oxygen layers are formed simultaneously in a wet oxidation process.

4. The vertical cavity surface emitting laser chip structure according to claim 1, wherein: The epitaxial layer is grown by using III-V semiconductor material or II-VI semiconductor material in an organic metal chemical vapor deposition method or a molecular beam epitaxial method.

5. The vertical cavity surface emitting laser chip structure according to claim 1, wherein: The first trench and the second trench are formed simultaneously in a wet etching process or a dry etching process.

6. A method for forming a vertical cavity surface emitting laser chip structure, comprising: Provide a substrate; forming an epitaxial layer on an upper surface of the substrate; forming a cap layer on the epitaxial layer; Forming a first groove to divide the VCSEL chip structure into a point measurement area and a light emitting area, and forming a plurality of second grooves to divide the point measurement area into a plurality of sub-areas; A first wet oxygen layer is formed in the epitaxial layer of the light emitting area, and a second wet oxygen layer is formed in the epitaxial layer of each of the sub-areas of the spot measuring area, wherein: The first wet oxygen layer has an aperture, and the second wet oxygen layer of each sub-region spans the corresponding sub-region; forming a first electrode on the cap layer and on a bottom and two side walls of the first trench; as well as A second electrode is formed on a lower surface of the substrate.

7. The method of claim 6, wherein: The substrate is a gallium arsenide substrate.

8. The method of claim 6, wherein: Forming the epitaxial layer includes: forming an N-type epitaxial layer on the upper surface of the substrate; forming a multi-quantum well layer on the N-type epitaxial layer; and forming a P-type epitaxial layer on the multi-quantum well layer; The first wet oxygen layer is formed in the P-type epitaxial layer of the light-emitting area, and each of the second wet oxygen layers is formed in the P-type epitaxial layer of the corresponding sub-area of ​​the spot measurement area; The first wet oxygen layer and each of the second wet oxygen layers are formed simultaneously in a wet oxidation process.

9. The method of claim 6, wherein: The epitaxial layer is grown by using III-V semiconductor material or II-VI semiconductor material in an organic metal chemical vapor deposition method or a molecular beam epitaxial method.

10. The method of claim 6, wherein: The first trench and the second trench are formed simultaneously in a wet etching process or a dry etching process.

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